#include "sh2.h"
#include "util.h"
#include <stdlib.h>
#include "sh2_util.c"

typedef void (*impl_fun)(sh2_context *context, uint32_t target_cycle);
static impl_fun impl_main[65536];
static void stc_sr_rn_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->sr = 240 & context->sr;
	if (context->t) {
	context->sr = 1 | context->sr;
	}
	if (context->s) {
	context->sr = 2 | context->sr;
	}
	if (context->q) {
	context->sr = 256 | context->sr;
	}
	if (context->m) {
	context->sr = 512 | context->sr;
	}
	context->gpr[0] = context->sr;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void bsrf_M_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->pr = context->pc + 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = context->gpr[0] + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
}
static void store_rm_r0_rn_indexed_b_M_0000_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[0];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_0000_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[0];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_0000_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[0];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_0000_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[0] & 4294967295)) * ((uint64_t)(context->gpr[0] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void clrt(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->t = 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void nop(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sts_mach_rn_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[0] = context->mach;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void sh2_rts(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = context->pr - 2;
	context->cycles += context->opts->gen.clock_divider * 1;
}
static void load_r0_rm_indexed_rn_b_M_0000_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[0];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_0000_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[0];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_0000_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[0];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_0000_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[0] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[0], context);
	context->gpr[0] = 4 + context->gpr[0];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[0] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[0], context);
	context->gpr[0] = 4 + context->gpr[0];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void stc_gbr_rn_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[0] = context->gbr;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void store_rm_r0_rn_indexed_b_M_0001_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[0];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_0001_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[0];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_0001_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[0];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_0001_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[0] & 4294967295)) * ((uint64_t)(context->gpr[1] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sett(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->t = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0u(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = 0;
	context->m = 0;
	context->t = 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sts_macl_rn_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[0] = context->macl;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void sleep(sh2_context *context, uint32_t target_cycle)
{
	if (context->sleeping) {
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->cycles += context->opts->gen.clock_divider * 3;
	context->sleeping = 1;
	context->pc = 2 + context->pc;
	}
}
static void load_r0_rm_indexed_rn_b_M_0001_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[1];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_0001_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[1];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_0001_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[1];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_0001_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[0] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[0], context);
	context->gpr[0] = 4 + context->gpr[0];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[1] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[1], context);
	context->gpr[1] = 4 + context->gpr[1];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void stc_vbr_rn_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[0] = context->vbr;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void braf_M_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = context->gpr[0] + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
}
static void store_rm_r0_rn_indexed_b_M_0010_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[0];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_0010_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[0];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_0010_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[0];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_0010_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[0] & 4294967295)) * ((uint64_t)(context->gpr[2] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void clrmac(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->mach = 0;
	context->macl = 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void movt_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->t = !context->t;
	context->t = !context->t;
	context->gpr[0] = context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sts_pr_rn_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[0] = context->pr;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void rte(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[15] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[15], context);
	context->pc = context->scratch1 - 2;
	context->gpr[15] = 4 + context->gpr[15];
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[15] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[15], context);
	context->sr = context->scratch1 & 1011;
	context->sr = 1011 & context->sr;
	context->t = context->sr & 1;
	context->s = context->sr >> 1;
	context->s = 1 & context->s;
	context->q = context->sr >> 8;
	context->q = 1 & context->q;
	context->m = context->sr >> 9;
	context->m = 1 & context->m;
	sh2_sync_cycle(context, target_cycle);
	context->gpr[15] = 4 + context->gpr[15];
	context->cycles += context->opts->gen.clock_divider * 1;
}
static void load_r0_rm_indexed_rn_b_M_0010_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[2];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_0010_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[2];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_0010_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[2];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_0010_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[0] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[0], context);
	context->gpr[0] = 4 + context->gpr[0];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[2] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[2], context);
	context->gpr[2] = 4 + context->gpr[2];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_b_M_0011_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[0];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_0011_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[0];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_0011_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[0];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_0011_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[0] & 4294967295)) * ((uint64_t)(context->gpr[3] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_b_M_0011_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[3];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_0011_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[3];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_0011_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[3];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_0011_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[0] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[0], context);
	context->gpr[0] = 4 + context->gpr[0];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[3] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[3], context);
	context->gpr[3] = 4 + context->gpr[3];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_b_M_0100_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[0];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_0100_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[0];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_0100_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[0];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_0100_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[0] & 4294967295)) * ((uint64_t)(context->gpr[4] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_b_M_0100_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[4];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_0100_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[4];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_0100_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[4];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_0100_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[0] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[0], context);
	context->gpr[0] = 4 + context->gpr[0];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[4] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[4], context);
	context->gpr[4] = 4 + context->gpr[4];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_b_M_0101_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[0];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_0101_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[0];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_0101_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[0];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_0101_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[0] & 4294967295)) * ((uint64_t)(context->gpr[5] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_b_M_0101_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[5];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_0101_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[5];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_0101_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[5];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_0101_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[0] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[0], context);
	context->gpr[0] = 4 + context->gpr[0];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[5] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[5], context);
	context->gpr[5] = 4 + context->gpr[5];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_b_M_0110_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[0];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_0110_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[0];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_0110_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[0];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_0110_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[0] & 4294967295)) * ((uint64_t)(context->gpr[6] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_b_M_0110_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[6];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_0110_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[6];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_0110_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[6];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_0110_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[0] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[0], context);
	context->gpr[0] = 4 + context->gpr[0];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[6] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[6], context);
	context->gpr[6] = 4 + context->gpr[6];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_b_M_0111_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[0];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_0111_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[0];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_0111_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[0];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_0111_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[0] & 4294967295)) * ((uint64_t)(context->gpr[7] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_b_M_0111_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[7];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_0111_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[7];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_0111_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[7];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_0111_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[0] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[0], context);
	context->gpr[0] = 4 + context->gpr[0];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[7] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[7], context);
	context->gpr[7] = 4 + context->gpr[7];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_b_M_1000_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[0];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_1000_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[0];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_1000_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[0];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_1000_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[0] & 4294967295)) * ((uint64_t)(context->gpr[8] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_b_M_1000_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[8];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_1000_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[8];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_1000_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[8];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_1000_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[0] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[0], context);
	context->gpr[0] = 4 + context->gpr[0];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[8] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[8], context);
	context->gpr[8] = 4 + context->gpr[8];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_b_M_1001_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[0];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_1001_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[0];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_1001_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[0];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_1001_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[0] & 4294967295)) * ((uint64_t)(context->gpr[9] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_b_M_1001_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[9];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_1001_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[9];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_1001_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[9];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_1001_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[0] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[0], context);
	context->gpr[0] = 4 + context->gpr[0];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[9] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[9], context);
	context->gpr[9] = 4 + context->gpr[9];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_b_M_1010_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[0];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_1010_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[0];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_1010_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[0];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_1010_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[0] & 4294967295)) * ((uint64_t)(context->gpr[10] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_b_M_1010_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[10];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_1010_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[10];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_1010_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[10];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_1010_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[0] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[0], context);
	context->gpr[0] = 4 + context->gpr[0];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[10] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[10], context);
	context->gpr[10] = 4 + context->gpr[10];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_b_M_1011_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[0];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_1011_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[0];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_1011_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[0];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_1011_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[0] & 4294967295)) * ((uint64_t)(context->gpr[11] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_b_M_1011_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[11];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_1011_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[11];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_1011_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[11];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_1011_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[0] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[0], context);
	context->gpr[0] = 4 + context->gpr[0];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[11] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[11], context);
	context->gpr[11] = 4 + context->gpr[11];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_b_M_1100_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[0];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_1100_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[0];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_1100_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[0];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_1100_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[0] & 4294967295)) * ((uint64_t)(context->gpr[12] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_b_M_1100_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[12];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_1100_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[12];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_1100_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[12];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_1100_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[0] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[0], context);
	context->gpr[0] = 4 + context->gpr[0];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[12] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[12], context);
	context->gpr[12] = 4 + context->gpr[12];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_b_M_1101_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[0];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_1101_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[0];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_1101_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[0];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_1101_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[0] & 4294967295)) * ((uint64_t)(context->gpr[13] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_b_M_1101_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[13];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_1101_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[13];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_1101_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[13];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_1101_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[0] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[0], context);
	context->gpr[0] = 4 + context->gpr[0];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[13] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[13], context);
	context->gpr[13] = 4 + context->gpr[13];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_b_M_1110_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[0];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_1110_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[0];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_1110_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[0];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_1110_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[0] & 4294967295)) * ((uint64_t)(context->gpr[14] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_b_M_1110_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[14];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_1110_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[14];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_1110_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[14];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_1110_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[0] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[0], context);
	context->gpr[0] = 4 + context->gpr[0];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[14] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[14], context);
	context->gpr[14] = 4 + context->gpr[14];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_b_M_1111_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[0];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_1111_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[0];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_1111_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[0];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_1111_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[0] & 4294967295)) * ((uint64_t)(context->gpr[15] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_b_M_1111_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[15];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_1111_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[15];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_1111_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[15];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_1111_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[0] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[0], context);
	context->gpr[0] = 4 + context->gpr[0];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[15] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[15], context);
	context->gpr[15] = 4 + context->gpr[15];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void stc_sr_rn_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->sr = 240 & context->sr;
	if (context->t) {
	context->sr = 1 | context->sr;
	}
	if (context->s) {
	context->sr = 2 | context->sr;
	}
	if (context->q) {
	context->sr = 256 | context->sr;
	}
	if (context->m) {
	context->sr = 512 | context->sr;
	}
	context->gpr[1] = context->sr;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void bsrf_M_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->pr = context->pc + 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = context->gpr[1] + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
}
static void store_rm_r0_rn_indexed_b_M_0000_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[1];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_0000_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[1];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_0000_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[1];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_0000_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[1] & 4294967295)) * ((uint64_t)(context->gpr[0] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sts_mach_rn_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[1] = context->mach;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void load_r0_rm_indexed_rn_b_M_0000_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[0];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[1] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_0000_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[0];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[1] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_0000_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[0];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_0000_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[1] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[1], context);
	context->gpr[1] = 4 + context->gpr[1];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[0] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[0], context);
	context->gpr[0] = 4 + context->gpr[0];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void stc_gbr_rn_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[1] = context->gbr;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void store_rm_r0_rn_indexed_b_M_0001_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[1];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_0001_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[1];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_0001_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[1];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_0001_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[1] & 4294967295)) * ((uint64_t)(context->gpr[1] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sts_macl_rn_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[1] = context->macl;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void load_r0_rm_indexed_rn_b_M_0001_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[1];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[1] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_0001_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[1];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[1] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_0001_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[1];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_0001_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[1] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[1], context);
	context->gpr[1] = 4 + context->gpr[1];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[1] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[1], context);
	context->gpr[1] = 4 + context->gpr[1];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void stc_vbr_rn_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[1] = context->vbr;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void braf_M_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = context->gpr[1] + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
}
static void store_rm_r0_rn_indexed_b_M_0010_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[1];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_0010_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[1];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_0010_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[1];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_0010_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[1] & 4294967295)) * ((uint64_t)(context->gpr[2] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void movt_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->t = !context->t;
	context->t = !context->t;
	context->gpr[1] = context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sts_pr_rn_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[1] = context->pr;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void load_r0_rm_indexed_rn_b_M_0010_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[2];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[1] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_0010_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[2];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[1] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_0010_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[2];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_0010_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[1] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[1], context);
	context->gpr[1] = 4 + context->gpr[1];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[2] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[2], context);
	context->gpr[2] = 4 + context->gpr[2];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_b_M_0011_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[1];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_0011_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[1];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_0011_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[1];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_0011_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[1] & 4294967295)) * ((uint64_t)(context->gpr[3] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_b_M_0011_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[3];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[1] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_0011_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[3];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[1] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_0011_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[3];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_0011_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[1] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[1], context);
	context->gpr[1] = 4 + context->gpr[1];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[3] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[3], context);
	context->gpr[3] = 4 + context->gpr[3];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_b_M_0100_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[1];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_0100_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[1];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_0100_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[1];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_0100_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[1] & 4294967295)) * ((uint64_t)(context->gpr[4] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_b_M_0100_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[4];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[1] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_0100_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[4];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[1] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_0100_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[4];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_0100_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[1] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[1], context);
	context->gpr[1] = 4 + context->gpr[1];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[4] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[4], context);
	context->gpr[4] = 4 + context->gpr[4];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_b_M_0101_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[1];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_0101_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[1];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_0101_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[1];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_0101_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[1] & 4294967295)) * ((uint64_t)(context->gpr[5] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_b_M_0101_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[5];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[1] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_0101_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[5];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[1] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_0101_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[5];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_0101_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[1] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[1], context);
	context->gpr[1] = 4 + context->gpr[1];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[5] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[5], context);
	context->gpr[5] = 4 + context->gpr[5];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_b_M_0110_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[1];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_0110_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[1];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_0110_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[1];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_0110_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[1] & 4294967295)) * ((uint64_t)(context->gpr[6] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_b_M_0110_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[6];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[1] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_0110_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[6];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[1] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_0110_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[6];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_0110_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[1] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[1], context);
	context->gpr[1] = 4 + context->gpr[1];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[6] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[6], context);
	context->gpr[6] = 4 + context->gpr[6];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_b_M_0111_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[1];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_0111_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[1];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_0111_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[1];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_0111_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[1] & 4294967295)) * ((uint64_t)(context->gpr[7] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_b_M_0111_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[7];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[1] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_0111_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[7];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[1] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_0111_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[7];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_0111_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[1] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[1], context);
	context->gpr[1] = 4 + context->gpr[1];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[7] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[7], context);
	context->gpr[7] = 4 + context->gpr[7];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_b_M_1000_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[1];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_1000_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[1];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_1000_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[1];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_1000_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[1] & 4294967295)) * ((uint64_t)(context->gpr[8] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_b_M_1000_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[8];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[1] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_1000_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[8];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[1] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_1000_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[8];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_1000_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[1] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[1], context);
	context->gpr[1] = 4 + context->gpr[1];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[8] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[8], context);
	context->gpr[8] = 4 + context->gpr[8];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_b_M_1001_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[1];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_1001_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[1];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_1001_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[1];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_1001_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[1] & 4294967295)) * ((uint64_t)(context->gpr[9] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_b_M_1001_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[9];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[1] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_1001_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[9];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[1] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_1001_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[9];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_1001_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[1] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[1], context);
	context->gpr[1] = 4 + context->gpr[1];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[9] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[9], context);
	context->gpr[9] = 4 + context->gpr[9];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_b_M_1010_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[1];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_1010_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[1];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_1010_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[1];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_1010_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[1] & 4294967295)) * ((uint64_t)(context->gpr[10] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_b_M_1010_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[10];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[1] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_1010_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[10];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[1] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_1010_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[10];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_1010_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[1] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[1], context);
	context->gpr[1] = 4 + context->gpr[1];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[10] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[10], context);
	context->gpr[10] = 4 + context->gpr[10];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_b_M_1011_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[1];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_1011_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[1];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_1011_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[1];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_1011_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[1] & 4294967295)) * ((uint64_t)(context->gpr[11] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_b_M_1011_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[11];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[1] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_1011_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[11];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[1] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_1011_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[11];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_1011_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[1] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[1], context);
	context->gpr[1] = 4 + context->gpr[1];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[11] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[11], context);
	context->gpr[11] = 4 + context->gpr[11];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_b_M_1100_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[1];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_1100_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[1];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_1100_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[1];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_1100_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[1] & 4294967295)) * ((uint64_t)(context->gpr[12] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_b_M_1100_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[12];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[1] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_1100_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[12];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[1] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_1100_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[12];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_1100_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[1] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[1], context);
	context->gpr[1] = 4 + context->gpr[1];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[12] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[12], context);
	context->gpr[12] = 4 + context->gpr[12];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_b_M_1101_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[1];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_1101_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[1];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_1101_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[1];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_1101_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[1] & 4294967295)) * ((uint64_t)(context->gpr[13] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_b_M_1101_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[13];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[1] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_1101_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[13];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[1] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_1101_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[13];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_1101_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[1] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[1], context);
	context->gpr[1] = 4 + context->gpr[1];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[13] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[13], context);
	context->gpr[13] = 4 + context->gpr[13];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_b_M_1110_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[1];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_1110_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[1];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_1110_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[1];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_1110_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[1] & 4294967295)) * ((uint64_t)(context->gpr[14] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_b_M_1110_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[14];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[1] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_1110_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[14];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[1] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_1110_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[14];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_1110_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[1] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[1], context);
	context->gpr[1] = 4 + context->gpr[1];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[14] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[14], context);
	context->gpr[14] = 4 + context->gpr[14];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_b_M_1111_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[1];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_1111_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[1];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_1111_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[1];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_1111_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[1] & 4294967295)) * ((uint64_t)(context->gpr[15] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_b_M_1111_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[15];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[1] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_1111_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[15];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[1] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_1111_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[15];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_1111_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[1] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[1], context);
	context->gpr[1] = 4 + context->gpr[1];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[15] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[15], context);
	context->gpr[15] = 4 + context->gpr[15];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void stc_sr_rn_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->sr = 240 & context->sr;
	if (context->t) {
	context->sr = 1 | context->sr;
	}
	if (context->s) {
	context->sr = 2 | context->sr;
	}
	if (context->q) {
	context->sr = 256 | context->sr;
	}
	if (context->m) {
	context->sr = 512 | context->sr;
	}
	context->gpr[2] = context->sr;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void bsrf_M_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->pr = context->pc + 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = context->gpr[2] + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
}
static void store_rm_r0_rn_indexed_b_M_0000_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[2];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_0000_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[2];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_0000_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[2];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_0000_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[2] & 4294967295)) * ((uint64_t)(context->gpr[0] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sts_mach_rn_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[2] = context->mach;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void load_r0_rm_indexed_rn_b_M_0000_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[0];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[2] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_0000_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[0];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[2] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_0000_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[0];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_0000_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[2] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[2], context);
	context->gpr[2] = 4 + context->gpr[2];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[0] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[0], context);
	context->gpr[0] = 4 + context->gpr[0];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void stc_gbr_rn_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[2] = context->gbr;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void store_rm_r0_rn_indexed_b_M_0001_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[2];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_0001_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[2];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_0001_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[2];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_0001_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[2] & 4294967295)) * ((uint64_t)(context->gpr[1] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sts_macl_rn_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[2] = context->macl;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void load_r0_rm_indexed_rn_b_M_0001_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[1];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[2] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_0001_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[1];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[2] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_0001_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[1];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_0001_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[2] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[2], context);
	context->gpr[2] = 4 + context->gpr[2];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[1] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[1], context);
	context->gpr[1] = 4 + context->gpr[1];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void stc_vbr_rn_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[2] = context->vbr;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void braf_M_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = context->gpr[2] + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
}
static void store_rm_r0_rn_indexed_b_M_0010_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[2];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_0010_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[2];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_0010_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[2];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_0010_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[2] & 4294967295)) * ((uint64_t)(context->gpr[2] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void movt_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->t = !context->t;
	context->t = !context->t;
	context->gpr[2] = context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sts_pr_rn_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[2] = context->pr;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void load_r0_rm_indexed_rn_b_M_0010_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[2];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[2] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_0010_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[2];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[2] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_0010_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[2];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_0010_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[2] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[2], context);
	context->gpr[2] = 4 + context->gpr[2];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[2] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[2], context);
	context->gpr[2] = 4 + context->gpr[2];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_b_M_0011_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[2];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_0011_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[2];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_0011_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[2];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_0011_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[2] & 4294967295)) * ((uint64_t)(context->gpr[3] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_b_M_0011_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[3];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[2] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_0011_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[3];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[2] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_0011_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[3];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_0011_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[2] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[2], context);
	context->gpr[2] = 4 + context->gpr[2];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[3] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[3], context);
	context->gpr[3] = 4 + context->gpr[3];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_b_M_0100_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[2];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_0100_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[2];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_0100_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[2];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_0100_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[2] & 4294967295)) * ((uint64_t)(context->gpr[4] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_b_M_0100_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[4];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[2] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_0100_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[4];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[2] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_0100_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[4];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_0100_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[2] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[2], context);
	context->gpr[2] = 4 + context->gpr[2];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[4] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[4], context);
	context->gpr[4] = 4 + context->gpr[4];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_b_M_0101_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[2];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_0101_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[2];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_0101_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[2];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_0101_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[2] & 4294967295)) * ((uint64_t)(context->gpr[5] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_b_M_0101_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[5];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[2] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_0101_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[5];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[2] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_0101_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[5];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_0101_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[2] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[2], context);
	context->gpr[2] = 4 + context->gpr[2];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[5] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[5], context);
	context->gpr[5] = 4 + context->gpr[5];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_b_M_0110_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[2];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_0110_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[2];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_0110_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[2];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_0110_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[2] & 4294967295)) * ((uint64_t)(context->gpr[6] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_b_M_0110_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[6];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[2] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_0110_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[6];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[2] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_0110_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[6];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_0110_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[2] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[2], context);
	context->gpr[2] = 4 + context->gpr[2];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[6] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[6], context);
	context->gpr[6] = 4 + context->gpr[6];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_b_M_0111_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[2];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_0111_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[2];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_0111_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[2];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_0111_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[2] & 4294967295)) * ((uint64_t)(context->gpr[7] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_b_M_0111_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[7];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[2] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_0111_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[7];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[2] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_0111_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[7];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_0111_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[2] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[2], context);
	context->gpr[2] = 4 + context->gpr[2];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[7] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[7], context);
	context->gpr[7] = 4 + context->gpr[7];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_b_M_1000_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[2];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_1000_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[2];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_1000_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[2];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_1000_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[2] & 4294967295)) * ((uint64_t)(context->gpr[8] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_b_M_1000_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[8];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[2] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_1000_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[8];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[2] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_1000_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[8];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_1000_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[2] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[2], context);
	context->gpr[2] = 4 + context->gpr[2];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[8] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[8], context);
	context->gpr[8] = 4 + context->gpr[8];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_b_M_1001_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[2];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_1001_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[2];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_1001_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[2];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_1001_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[2] & 4294967295)) * ((uint64_t)(context->gpr[9] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_b_M_1001_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[9];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[2] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_1001_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[9];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[2] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_1001_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[9];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_1001_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[2] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[2], context);
	context->gpr[2] = 4 + context->gpr[2];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[9] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[9], context);
	context->gpr[9] = 4 + context->gpr[9];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_b_M_1010_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[2];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_1010_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[2];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_1010_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[2];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_1010_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[2] & 4294967295)) * ((uint64_t)(context->gpr[10] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_b_M_1010_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[10];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[2] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_1010_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[10];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[2] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_1010_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[10];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_1010_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[2] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[2], context);
	context->gpr[2] = 4 + context->gpr[2];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[10] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[10], context);
	context->gpr[10] = 4 + context->gpr[10];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_b_M_1011_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[2];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_1011_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[2];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_1011_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[2];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_1011_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[2] & 4294967295)) * ((uint64_t)(context->gpr[11] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_b_M_1011_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[11];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[2] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_1011_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[11];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[2] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_1011_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[11];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_1011_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[2] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[2], context);
	context->gpr[2] = 4 + context->gpr[2];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[11] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[11], context);
	context->gpr[11] = 4 + context->gpr[11];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_b_M_1100_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[2];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_1100_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[2];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_1100_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[2];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_1100_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[2] & 4294967295)) * ((uint64_t)(context->gpr[12] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_b_M_1100_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[12];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[2] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_1100_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[12];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[2] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_1100_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[12];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_1100_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[2] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[2], context);
	context->gpr[2] = 4 + context->gpr[2];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[12] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[12], context);
	context->gpr[12] = 4 + context->gpr[12];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_b_M_1101_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[2];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_1101_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[2];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_1101_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[2];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_1101_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[2] & 4294967295)) * ((uint64_t)(context->gpr[13] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_b_M_1101_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[13];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[2] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_1101_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[13];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[2] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_1101_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[13];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_1101_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[2] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[2], context);
	context->gpr[2] = 4 + context->gpr[2];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[13] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[13], context);
	context->gpr[13] = 4 + context->gpr[13];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_b_M_1110_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[2];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_1110_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[2];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_1110_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[2];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_1110_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[2] & 4294967295)) * ((uint64_t)(context->gpr[14] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_b_M_1110_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[14];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[2] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_1110_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[14];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[2] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_1110_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[14];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_1110_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[2] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[2], context);
	context->gpr[2] = 4 + context->gpr[2];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[14] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[14], context);
	context->gpr[14] = 4 + context->gpr[14];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_b_M_1111_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[2];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_1111_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[2];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_1111_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[2];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_1111_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[2] & 4294967295)) * ((uint64_t)(context->gpr[15] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_b_M_1111_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[15];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[2] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_1111_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[15];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[2] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_1111_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[15];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_1111_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[2] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[2], context);
	context->gpr[2] = 4 + context->gpr[2];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[15] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[15], context);
	context->gpr[15] = 4 + context->gpr[15];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void stc_sr_rn_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->sr = 240 & context->sr;
	if (context->t) {
	context->sr = 1 | context->sr;
	}
	if (context->s) {
	context->sr = 2 | context->sr;
	}
	if (context->q) {
	context->sr = 256 | context->sr;
	}
	if (context->m) {
	context->sr = 512 | context->sr;
	}
	context->gpr[3] = context->sr;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void bsrf_M_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->pr = context->pc + 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = context->gpr[3] + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
}
static void store_rm_r0_rn_indexed_b_M_0000_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[3];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_0000_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[3];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_0000_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[3];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_0000_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[3] & 4294967295)) * ((uint64_t)(context->gpr[0] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sts_mach_rn_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[3] = context->mach;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void load_r0_rm_indexed_rn_b_M_0000_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[0];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[3] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_0000_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[0];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[3] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_0000_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[0];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_0000_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[3] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[3], context);
	context->gpr[3] = 4 + context->gpr[3];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[0] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[0], context);
	context->gpr[0] = 4 + context->gpr[0];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void stc_gbr_rn_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[3] = context->gbr;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void store_rm_r0_rn_indexed_b_M_0001_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[3];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_0001_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[3];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_0001_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[3];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_0001_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[3] & 4294967295)) * ((uint64_t)(context->gpr[1] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sts_macl_rn_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[3] = context->macl;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void load_r0_rm_indexed_rn_b_M_0001_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[1];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[3] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_0001_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[1];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[3] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_0001_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[1];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_0001_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[3] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[3], context);
	context->gpr[3] = 4 + context->gpr[3];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[1] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[1], context);
	context->gpr[1] = 4 + context->gpr[1];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void stc_vbr_rn_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[3] = context->vbr;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void braf_M_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = context->gpr[3] + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
}
static void store_rm_r0_rn_indexed_b_M_0010_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[3];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_0010_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[3];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_0010_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[3];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_0010_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[3] & 4294967295)) * ((uint64_t)(context->gpr[2] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void movt_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->t = !context->t;
	context->t = !context->t;
	context->gpr[3] = context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sts_pr_rn_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[3] = context->pr;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void load_r0_rm_indexed_rn_b_M_0010_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[2];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[3] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_0010_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[2];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[3] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_0010_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[2];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_0010_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[3] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[3], context);
	context->gpr[3] = 4 + context->gpr[3];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[2] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[2], context);
	context->gpr[2] = 4 + context->gpr[2];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_b_M_0011_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[3];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_0011_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[3];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_0011_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[3];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_0011_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[3] & 4294967295)) * ((uint64_t)(context->gpr[3] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_b_M_0011_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[3];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[3] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_0011_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[3];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[3] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_0011_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[3];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_0011_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[3] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[3], context);
	context->gpr[3] = 4 + context->gpr[3];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[3] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[3], context);
	context->gpr[3] = 4 + context->gpr[3];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_b_M_0100_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[3];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_0100_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[3];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_0100_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[3];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_0100_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[3] & 4294967295)) * ((uint64_t)(context->gpr[4] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_b_M_0100_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[4];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[3] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_0100_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[4];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[3] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_0100_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[4];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_0100_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[3] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[3], context);
	context->gpr[3] = 4 + context->gpr[3];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[4] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[4], context);
	context->gpr[4] = 4 + context->gpr[4];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_b_M_0101_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[3];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_0101_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[3];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_0101_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[3];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_0101_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[3] & 4294967295)) * ((uint64_t)(context->gpr[5] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_b_M_0101_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[5];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[3] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_0101_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[5];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[3] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_0101_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[5];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_0101_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[3] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[3], context);
	context->gpr[3] = 4 + context->gpr[3];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[5] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[5], context);
	context->gpr[5] = 4 + context->gpr[5];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_b_M_0110_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[3];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_0110_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[3];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_0110_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[3];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_0110_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[3] & 4294967295)) * ((uint64_t)(context->gpr[6] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_b_M_0110_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[6];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[3] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_0110_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[6];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[3] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_0110_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[6];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_0110_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[3] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[3], context);
	context->gpr[3] = 4 + context->gpr[3];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[6] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[6], context);
	context->gpr[6] = 4 + context->gpr[6];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_b_M_0111_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[3];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_0111_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[3];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_0111_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[3];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_0111_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[3] & 4294967295)) * ((uint64_t)(context->gpr[7] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_b_M_0111_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[7];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[3] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_0111_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[7];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[3] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_0111_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[7];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_0111_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[3] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[3], context);
	context->gpr[3] = 4 + context->gpr[3];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[7] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[7], context);
	context->gpr[7] = 4 + context->gpr[7];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_b_M_1000_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[3];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_1000_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[3];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_1000_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[3];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_1000_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[3] & 4294967295)) * ((uint64_t)(context->gpr[8] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_b_M_1000_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[8];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[3] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_1000_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[8];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[3] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_1000_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[8];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_1000_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[3] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[3], context);
	context->gpr[3] = 4 + context->gpr[3];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[8] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[8], context);
	context->gpr[8] = 4 + context->gpr[8];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_b_M_1001_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[3];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_1001_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[3];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_1001_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[3];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_1001_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[3] & 4294967295)) * ((uint64_t)(context->gpr[9] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_b_M_1001_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[9];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[3] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_1001_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[9];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[3] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_1001_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[9];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_1001_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[3] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[3], context);
	context->gpr[3] = 4 + context->gpr[3];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[9] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[9], context);
	context->gpr[9] = 4 + context->gpr[9];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_b_M_1010_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[3];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_1010_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[3];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_1010_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[3];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_1010_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[3] & 4294967295)) * ((uint64_t)(context->gpr[10] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_b_M_1010_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[10];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[3] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_1010_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[10];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[3] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_1010_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[10];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_1010_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[3] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[3], context);
	context->gpr[3] = 4 + context->gpr[3];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[10] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[10], context);
	context->gpr[10] = 4 + context->gpr[10];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_b_M_1011_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[3];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_1011_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[3];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_1011_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[3];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_1011_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[3] & 4294967295)) * ((uint64_t)(context->gpr[11] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_b_M_1011_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[11];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[3] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_1011_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[11];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[3] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_1011_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[11];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_1011_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[3] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[3], context);
	context->gpr[3] = 4 + context->gpr[3];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[11] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[11], context);
	context->gpr[11] = 4 + context->gpr[11];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_b_M_1100_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[3];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_1100_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[3];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_1100_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[3];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_1100_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[3] & 4294967295)) * ((uint64_t)(context->gpr[12] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_b_M_1100_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[12];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[3] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_1100_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[12];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[3] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_1100_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[12];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_1100_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[3] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[3], context);
	context->gpr[3] = 4 + context->gpr[3];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[12] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[12], context);
	context->gpr[12] = 4 + context->gpr[12];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_b_M_1101_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[3];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_1101_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[3];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_1101_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[3];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_1101_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[3] & 4294967295)) * ((uint64_t)(context->gpr[13] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_b_M_1101_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[13];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[3] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_1101_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[13];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[3] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_1101_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[13];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_1101_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[3] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[3], context);
	context->gpr[3] = 4 + context->gpr[3];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[13] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[13], context);
	context->gpr[13] = 4 + context->gpr[13];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_b_M_1110_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[3];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_1110_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[3];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_1110_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[3];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_1110_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[3] & 4294967295)) * ((uint64_t)(context->gpr[14] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_b_M_1110_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[14];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[3] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_1110_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[14];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[3] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_1110_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[14];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_1110_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[3] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[3], context);
	context->gpr[3] = 4 + context->gpr[3];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[14] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[14], context);
	context->gpr[14] = 4 + context->gpr[14];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_b_M_1111_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[3];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_1111_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[3];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_1111_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[3];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_1111_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[3] & 4294967295)) * ((uint64_t)(context->gpr[15] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_b_M_1111_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[15];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[3] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_1111_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[15];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[3] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_1111_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[15];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_1111_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[3] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[3], context);
	context->gpr[3] = 4 + context->gpr[3];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[15] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[15], context);
	context->gpr[15] = 4 + context->gpr[15];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void stc_sr_rn_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->sr = 240 & context->sr;
	if (context->t) {
	context->sr = 1 | context->sr;
	}
	if (context->s) {
	context->sr = 2 | context->sr;
	}
	if (context->q) {
	context->sr = 256 | context->sr;
	}
	if (context->m) {
	context->sr = 512 | context->sr;
	}
	context->gpr[4] = context->sr;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void bsrf_M_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->pr = context->pc + 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = context->gpr[4] + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
}
static void store_rm_r0_rn_indexed_b_M_0000_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[4];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_0000_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[4];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_0000_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[4];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_0000_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[4] & 4294967295)) * ((uint64_t)(context->gpr[0] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sts_mach_rn_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[4] = context->mach;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void load_r0_rm_indexed_rn_b_M_0000_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[0];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[4] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_0000_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[0];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[4] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_0000_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[0];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_0000_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[4] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[4], context);
	context->gpr[4] = 4 + context->gpr[4];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[0] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[0], context);
	context->gpr[0] = 4 + context->gpr[0];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void stc_gbr_rn_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[4] = context->gbr;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void store_rm_r0_rn_indexed_b_M_0001_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[4];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_0001_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[4];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_0001_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[4];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_0001_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[4] & 4294967295)) * ((uint64_t)(context->gpr[1] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sts_macl_rn_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[4] = context->macl;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void load_r0_rm_indexed_rn_b_M_0001_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[1];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[4] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_0001_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[1];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[4] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_0001_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[1];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_0001_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[4] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[4], context);
	context->gpr[4] = 4 + context->gpr[4];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[1] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[1], context);
	context->gpr[1] = 4 + context->gpr[1];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void stc_vbr_rn_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[4] = context->vbr;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void braf_M_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = context->gpr[4] + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
}
static void store_rm_r0_rn_indexed_b_M_0010_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[4];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_0010_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[4];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_0010_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[4];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_0010_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[4] & 4294967295)) * ((uint64_t)(context->gpr[2] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void movt_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->t = !context->t;
	context->t = !context->t;
	context->gpr[4] = context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sts_pr_rn_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[4] = context->pr;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void load_r0_rm_indexed_rn_b_M_0010_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[2];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[4] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_0010_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[2];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[4] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_0010_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[2];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_0010_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[4] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[4], context);
	context->gpr[4] = 4 + context->gpr[4];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[2] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[2], context);
	context->gpr[2] = 4 + context->gpr[2];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_b_M_0011_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[4];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_0011_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[4];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_0011_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[4];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_0011_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[4] & 4294967295)) * ((uint64_t)(context->gpr[3] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_b_M_0011_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[3];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[4] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_0011_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[3];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[4] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_0011_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[3];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_0011_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[4] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[4], context);
	context->gpr[4] = 4 + context->gpr[4];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[3] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[3], context);
	context->gpr[3] = 4 + context->gpr[3];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_b_M_0100_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[4];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_0100_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[4];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_0100_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[4];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_0100_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[4] & 4294967295)) * ((uint64_t)(context->gpr[4] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_b_M_0100_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[4];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[4] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_0100_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[4];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[4] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_0100_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[4];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_0100_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[4] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[4], context);
	context->gpr[4] = 4 + context->gpr[4];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[4] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[4], context);
	context->gpr[4] = 4 + context->gpr[4];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_b_M_0101_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[4];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_0101_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[4];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_0101_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[4];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_0101_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[4] & 4294967295)) * ((uint64_t)(context->gpr[5] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_b_M_0101_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[5];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[4] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_0101_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[5];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[4] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_0101_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[5];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_0101_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[4] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[4], context);
	context->gpr[4] = 4 + context->gpr[4];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[5] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[5], context);
	context->gpr[5] = 4 + context->gpr[5];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_b_M_0110_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[4];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_0110_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[4];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_0110_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[4];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_0110_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[4] & 4294967295)) * ((uint64_t)(context->gpr[6] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_b_M_0110_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[6];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[4] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_0110_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[6];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[4] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_0110_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[6];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_0110_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[4] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[4], context);
	context->gpr[4] = 4 + context->gpr[4];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[6] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[6], context);
	context->gpr[6] = 4 + context->gpr[6];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_b_M_0111_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[4];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_0111_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[4];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_0111_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[4];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_0111_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[4] & 4294967295)) * ((uint64_t)(context->gpr[7] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_b_M_0111_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[7];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[4] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_0111_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[7];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[4] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_0111_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[7];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_0111_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[4] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[4], context);
	context->gpr[4] = 4 + context->gpr[4];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[7] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[7], context);
	context->gpr[7] = 4 + context->gpr[7];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_b_M_1000_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[4];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_1000_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[4];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_1000_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[4];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_1000_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[4] & 4294967295)) * ((uint64_t)(context->gpr[8] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_b_M_1000_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[8];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[4] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_1000_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[8];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[4] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_1000_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[8];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_1000_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[4] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[4], context);
	context->gpr[4] = 4 + context->gpr[4];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[8] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[8], context);
	context->gpr[8] = 4 + context->gpr[8];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_b_M_1001_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[4];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_1001_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[4];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_1001_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[4];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_1001_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[4] & 4294967295)) * ((uint64_t)(context->gpr[9] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_b_M_1001_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[9];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[4] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_1001_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[9];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[4] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_1001_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[9];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_1001_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[4] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[4], context);
	context->gpr[4] = 4 + context->gpr[4];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[9] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[9], context);
	context->gpr[9] = 4 + context->gpr[9];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_b_M_1010_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[4];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_1010_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[4];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_1010_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[4];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_1010_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[4] & 4294967295)) * ((uint64_t)(context->gpr[10] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_b_M_1010_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[10];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[4] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_1010_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[10];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[4] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_1010_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[10];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_1010_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[4] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[4], context);
	context->gpr[4] = 4 + context->gpr[4];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[10] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[10], context);
	context->gpr[10] = 4 + context->gpr[10];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_b_M_1011_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[4];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_1011_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[4];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_1011_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[4];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_1011_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[4] & 4294967295)) * ((uint64_t)(context->gpr[11] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_b_M_1011_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[11];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[4] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_1011_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[11];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[4] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_1011_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[11];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_1011_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[4] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[4], context);
	context->gpr[4] = 4 + context->gpr[4];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[11] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[11], context);
	context->gpr[11] = 4 + context->gpr[11];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_b_M_1100_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[4];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_1100_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[4];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_1100_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[4];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_1100_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[4] & 4294967295)) * ((uint64_t)(context->gpr[12] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_b_M_1100_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[12];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[4] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_1100_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[12];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[4] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_1100_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[12];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_1100_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[4] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[4], context);
	context->gpr[4] = 4 + context->gpr[4];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[12] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[12], context);
	context->gpr[12] = 4 + context->gpr[12];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_b_M_1101_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[4];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_1101_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[4];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_1101_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[4];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_1101_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[4] & 4294967295)) * ((uint64_t)(context->gpr[13] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_b_M_1101_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[13];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[4] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_1101_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[13];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[4] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_1101_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[13];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_1101_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[4] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[4], context);
	context->gpr[4] = 4 + context->gpr[4];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[13] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[13], context);
	context->gpr[13] = 4 + context->gpr[13];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_b_M_1110_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[4];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_1110_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[4];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_1110_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[4];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_1110_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[4] & 4294967295)) * ((uint64_t)(context->gpr[14] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_b_M_1110_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[14];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[4] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_1110_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[14];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[4] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_1110_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[14];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_1110_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[4] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[4], context);
	context->gpr[4] = 4 + context->gpr[4];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[14] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[14], context);
	context->gpr[14] = 4 + context->gpr[14];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_b_M_1111_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[4];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_1111_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[4];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_1111_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[4];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_1111_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[4] & 4294967295)) * ((uint64_t)(context->gpr[15] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_b_M_1111_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[15];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[4] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_1111_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[15];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[4] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_1111_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[15];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_1111_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[4] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[4], context);
	context->gpr[4] = 4 + context->gpr[4];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[15] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[15], context);
	context->gpr[15] = 4 + context->gpr[15];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void stc_sr_rn_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->sr = 240 & context->sr;
	if (context->t) {
	context->sr = 1 | context->sr;
	}
	if (context->s) {
	context->sr = 2 | context->sr;
	}
	if (context->q) {
	context->sr = 256 | context->sr;
	}
	if (context->m) {
	context->sr = 512 | context->sr;
	}
	context->gpr[5] = context->sr;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void bsrf_M_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->pr = context->pc + 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = context->gpr[5] + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
}
static void store_rm_r0_rn_indexed_b_M_0000_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[5];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_0000_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[5];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_0000_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[5];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_0000_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[5] & 4294967295)) * ((uint64_t)(context->gpr[0] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sts_mach_rn_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[5] = context->mach;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void load_r0_rm_indexed_rn_b_M_0000_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[0];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[5] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_0000_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[0];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[5] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_0000_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[0];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_0000_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[5] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[5], context);
	context->gpr[5] = 4 + context->gpr[5];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[0] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[0], context);
	context->gpr[0] = 4 + context->gpr[0];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void stc_gbr_rn_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[5] = context->gbr;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void store_rm_r0_rn_indexed_b_M_0001_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[5];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_0001_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[5];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_0001_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[5];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_0001_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[5] & 4294967295)) * ((uint64_t)(context->gpr[1] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sts_macl_rn_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[5] = context->macl;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void load_r0_rm_indexed_rn_b_M_0001_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[1];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[5] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_0001_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[1];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[5] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_0001_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[1];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_0001_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[5] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[5], context);
	context->gpr[5] = 4 + context->gpr[5];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[1] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[1], context);
	context->gpr[1] = 4 + context->gpr[1];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void stc_vbr_rn_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[5] = context->vbr;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void braf_M_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = context->gpr[5] + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
}
static void store_rm_r0_rn_indexed_b_M_0010_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[5];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_0010_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[5];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_0010_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[5];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_0010_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[5] & 4294967295)) * ((uint64_t)(context->gpr[2] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void movt_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->t = !context->t;
	context->t = !context->t;
	context->gpr[5] = context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sts_pr_rn_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[5] = context->pr;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void load_r0_rm_indexed_rn_b_M_0010_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[2];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[5] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_0010_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[2];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[5] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_0010_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[2];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_0010_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[5] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[5], context);
	context->gpr[5] = 4 + context->gpr[5];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[2] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[2], context);
	context->gpr[2] = 4 + context->gpr[2];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_b_M_0011_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[5];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_0011_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[5];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_0011_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[5];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_0011_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[5] & 4294967295)) * ((uint64_t)(context->gpr[3] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_b_M_0011_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[3];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[5] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_0011_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[3];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[5] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_0011_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[3];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_0011_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[5] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[5], context);
	context->gpr[5] = 4 + context->gpr[5];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[3] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[3], context);
	context->gpr[3] = 4 + context->gpr[3];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_b_M_0100_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[5];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_0100_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[5];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_0100_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[5];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_0100_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[5] & 4294967295)) * ((uint64_t)(context->gpr[4] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_b_M_0100_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[4];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[5] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_0100_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[4];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[5] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_0100_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[4];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_0100_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[5] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[5], context);
	context->gpr[5] = 4 + context->gpr[5];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[4] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[4], context);
	context->gpr[4] = 4 + context->gpr[4];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_b_M_0101_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[5];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_0101_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[5];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_0101_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[5];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_0101_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[5] & 4294967295)) * ((uint64_t)(context->gpr[5] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_b_M_0101_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[5];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[5] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_0101_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[5];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[5] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_0101_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[5];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_0101_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[5] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[5], context);
	context->gpr[5] = 4 + context->gpr[5];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[5] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[5], context);
	context->gpr[5] = 4 + context->gpr[5];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_b_M_0110_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[5];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_0110_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[5];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_0110_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[5];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_0110_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[5] & 4294967295)) * ((uint64_t)(context->gpr[6] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_b_M_0110_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[6];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[5] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_0110_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[6];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[5] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_0110_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[6];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_0110_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[5] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[5], context);
	context->gpr[5] = 4 + context->gpr[5];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[6] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[6], context);
	context->gpr[6] = 4 + context->gpr[6];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_b_M_0111_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[5];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_0111_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[5];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_0111_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[5];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_0111_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[5] & 4294967295)) * ((uint64_t)(context->gpr[7] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_b_M_0111_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[7];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[5] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_0111_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[7];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[5] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_0111_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[7];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_0111_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[5] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[5], context);
	context->gpr[5] = 4 + context->gpr[5];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[7] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[7], context);
	context->gpr[7] = 4 + context->gpr[7];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_b_M_1000_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[5];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_1000_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[5];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_1000_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[5];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_1000_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[5] & 4294967295)) * ((uint64_t)(context->gpr[8] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_b_M_1000_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[8];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[5] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_1000_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[8];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[5] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_1000_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[8];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_1000_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[5] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[5], context);
	context->gpr[5] = 4 + context->gpr[5];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[8] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[8], context);
	context->gpr[8] = 4 + context->gpr[8];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_b_M_1001_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[5];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_1001_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[5];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_1001_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[5];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_1001_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[5] & 4294967295)) * ((uint64_t)(context->gpr[9] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_b_M_1001_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[9];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[5] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_1001_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[9];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[5] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_1001_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[9];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_1001_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[5] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[5], context);
	context->gpr[5] = 4 + context->gpr[5];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[9] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[9], context);
	context->gpr[9] = 4 + context->gpr[9];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_b_M_1010_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[5];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_1010_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[5];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_1010_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[5];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_1010_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[5] & 4294967295)) * ((uint64_t)(context->gpr[10] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_b_M_1010_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[10];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[5] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_1010_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[10];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[5] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_1010_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[10];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_1010_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[5] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[5], context);
	context->gpr[5] = 4 + context->gpr[5];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[10] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[10], context);
	context->gpr[10] = 4 + context->gpr[10];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_b_M_1011_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[5];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_1011_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[5];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_1011_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[5];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_1011_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[5] & 4294967295)) * ((uint64_t)(context->gpr[11] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_b_M_1011_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[11];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[5] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_1011_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[11];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[5] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_1011_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[11];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_1011_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[5] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[5], context);
	context->gpr[5] = 4 + context->gpr[5];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[11] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[11], context);
	context->gpr[11] = 4 + context->gpr[11];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_b_M_1100_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[5];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_1100_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[5];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_1100_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[5];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_1100_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[5] & 4294967295)) * ((uint64_t)(context->gpr[12] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_b_M_1100_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[12];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[5] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_1100_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[12];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[5] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_1100_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[12];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_1100_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[5] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[5], context);
	context->gpr[5] = 4 + context->gpr[5];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[12] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[12], context);
	context->gpr[12] = 4 + context->gpr[12];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_b_M_1101_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[5];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_1101_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[5];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_1101_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[5];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_1101_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[5] & 4294967295)) * ((uint64_t)(context->gpr[13] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_b_M_1101_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[13];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[5] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_1101_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[13];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[5] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_1101_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[13];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_1101_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[5] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[5], context);
	context->gpr[5] = 4 + context->gpr[5];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[13] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[13], context);
	context->gpr[13] = 4 + context->gpr[13];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_b_M_1110_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[5];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_1110_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[5];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_1110_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[5];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_1110_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[5] & 4294967295)) * ((uint64_t)(context->gpr[14] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_b_M_1110_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[14];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[5] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_1110_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[14];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[5] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_1110_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[14];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_1110_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[5] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[5], context);
	context->gpr[5] = 4 + context->gpr[5];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[14] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[14], context);
	context->gpr[14] = 4 + context->gpr[14];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_b_M_1111_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[5];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_1111_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[5];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_1111_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[5];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_1111_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[5] & 4294967295)) * ((uint64_t)(context->gpr[15] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_b_M_1111_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[15];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[5] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_1111_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[15];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[5] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_1111_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[15];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_1111_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[5] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[5], context);
	context->gpr[5] = 4 + context->gpr[5];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[15] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[15], context);
	context->gpr[15] = 4 + context->gpr[15];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void stc_sr_rn_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->sr = 240 & context->sr;
	if (context->t) {
	context->sr = 1 | context->sr;
	}
	if (context->s) {
	context->sr = 2 | context->sr;
	}
	if (context->q) {
	context->sr = 256 | context->sr;
	}
	if (context->m) {
	context->sr = 512 | context->sr;
	}
	context->gpr[6] = context->sr;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void bsrf_M_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->pr = context->pc + 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = context->gpr[6] + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
}
static void store_rm_r0_rn_indexed_b_M_0000_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[6];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_0000_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[6];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_0000_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[6];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_0000_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[6] & 4294967295)) * ((uint64_t)(context->gpr[0] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sts_mach_rn_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[6] = context->mach;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void load_r0_rm_indexed_rn_b_M_0000_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[0];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[6] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_0000_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[0];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[6] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_0000_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[0];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_0000_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[6] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[6], context);
	context->gpr[6] = 4 + context->gpr[6];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[0] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[0], context);
	context->gpr[0] = 4 + context->gpr[0];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void stc_gbr_rn_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[6] = context->gbr;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void store_rm_r0_rn_indexed_b_M_0001_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[6];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_0001_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[6];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_0001_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[6];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_0001_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[6] & 4294967295)) * ((uint64_t)(context->gpr[1] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sts_macl_rn_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[6] = context->macl;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void load_r0_rm_indexed_rn_b_M_0001_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[1];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[6] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_0001_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[1];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[6] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_0001_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[1];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_0001_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[6] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[6], context);
	context->gpr[6] = 4 + context->gpr[6];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[1] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[1], context);
	context->gpr[1] = 4 + context->gpr[1];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void stc_vbr_rn_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[6] = context->vbr;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void braf_M_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = context->gpr[6] + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
}
static void store_rm_r0_rn_indexed_b_M_0010_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[6];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_0010_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[6];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_0010_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[6];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_0010_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[6] & 4294967295)) * ((uint64_t)(context->gpr[2] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void movt_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->t = !context->t;
	context->t = !context->t;
	context->gpr[6] = context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sts_pr_rn_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[6] = context->pr;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void load_r0_rm_indexed_rn_b_M_0010_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[2];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[6] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_0010_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[2];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[6] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_0010_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[2];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_0010_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[6] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[6], context);
	context->gpr[6] = 4 + context->gpr[6];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[2] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[2], context);
	context->gpr[2] = 4 + context->gpr[2];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_b_M_0011_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[6];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_0011_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[6];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_0011_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[6];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_0011_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[6] & 4294967295)) * ((uint64_t)(context->gpr[3] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_b_M_0011_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[3];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[6] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_0011_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[3];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[6] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_0011_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[3];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_0011_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[6] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[6], context);
	context->gpr[6] = 4 + context->gpr[6];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[3] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[3], context);
	context->gpr[3] = 4 + context->gpr[3];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_b_M_0100_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[6];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_0100_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[6];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_0100_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[6];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_0100_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[6] & 4294967295)) * ((uint64_t)(context->gpr[4] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_b_M_0100_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[4];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[6] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_0100_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[4];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[6] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_0100_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[4];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_0100_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[6] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[6], context);
	context->gpr[6] = 4 + context->gpr[6];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[4] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[4], context);
	context->gpr[4] = 4 + context->gpr[4];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_b_M_0101_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[6];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_0101_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[6];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_0101_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[6];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_0101_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[6] & 4294967295)) * ((uint64_t)(context->gpr[5] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_b_M_0101_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[5];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[6] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_0101_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[5];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[6] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_0101_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[5];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_0101_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[6] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[6], context);
	context->gpr[6] = 4 + context->gpr[6];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[5] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[5], context);
	context->gpr[5] = 4 + context->gpr[5];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_b_M_0110_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[6];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_0110_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[6];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_0110_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[6];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_0110_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[6] & 4294967295)) * ((uint64_t)(context->gpr[6] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_b_M_0110_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[6];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[6] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_0110_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[6];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[6] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_0110_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[6];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_0110_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[6] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[6], context);
	context->gpr[6] = 4 + context->gpr[6];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[6] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[6], context);
	context->gpr[6] = 4 + context->gpr[6];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_b_M_0111_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[6];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_0111_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[6];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_0111_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[6];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_0111_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[6] & 4294967295)) * ((uint64_t)(context->gpr[7] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_b_M_0111_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[7];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[6] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_0111_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[7];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[6] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_0111_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[7];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_0111_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[6] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[6], context);
	context->gpr[6] = 4 + context->gpr[6];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[7] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[7], context);
	context->gpr[7] = 4 + context->gpr[7];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_b_M_1000_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[6];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_1000_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[6];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_1000_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[6];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_1000_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[6] & 4294967295)) * ((uint64_t)(context->gpr[8] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_b_M_1000_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[8];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[6] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_1000_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[8];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[6] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_1000_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[8];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_1000_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[6] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[6], context);
	context->gpr[6] = 4 + context->gpr[6];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[8] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[8], context);
	context->gpr[8] = 4 + context->gpr[8];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_b_M_1001_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[6];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_1001_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[6];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_1001_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[6];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_1001_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[6] & 4294967295)) * ((uint64_t)(context->gpr[9] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_b_M_1001_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[9];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[6] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_1001_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[9];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[6] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_1001_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[9];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_1001_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[6] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[6], context);
	context->gpr[6] = 4 + context->gpr[6];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[9] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[9], context);
	context->gpr[9] = 4 + context->gpr[9];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_b_M_1010_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[6];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_1010_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[6];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_1010_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[6];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_1010_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[6] & 4294967295)) * ((uint64_t)(context->gpr[10] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_b_M_1010_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[10];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[6] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_1010_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[10];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[6] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_1010_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[10];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_1010_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[6] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[6], context);
	context->gpr[6] = 4 + context->gpr[6];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[10] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[10], context);
	context->gpr[10] = 4 + context->gpr[10];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_b_M_1011_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[6];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_1011_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[6];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_1011_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[6];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_1011_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[6] & 4294967295)) * ((uint64_t)(context->gpr[11] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_b_M_1011_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[11];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[6] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_1011_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[11];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[6] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_1011_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[11];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_1011_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[6] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[6], context);
	context->gpr[6] = 4 + context->gpr[6];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[11] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[11], context);
	context->gpr[11] = 4 + context->gpr[11];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_b_M_1100_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[6];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_1100_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[6];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_1100_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[6];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_1100_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[6] & 4294967295)) * ((uint64_t)(context->gpr[12] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_b_M_1100_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[12];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[6] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_1100_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[12];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[6] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_1100_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[12];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_1100_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[6] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[6], context);
	context->gpr[6] = 4 + context->gpr[6];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[12] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[12], context);
	context->gpr[12] = 4 + context->gpr[12];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_b_M_1101_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[6];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_1101_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[6];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_1101_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[6];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_1101_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[6] & 4294967295)) * ((uint64_t)(context->gpr[13] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_b_M_1101_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[13];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[6] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_1101_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[13];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[6] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_1101_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[13];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_1101_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[6] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[6], context);
	context->gpr[6] = 4 + context->gpr[6];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[13] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[13], context);
	context->gpr[13] = 4 + context->gpr[13];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_b_M_1110_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[6];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_1110_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[6];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_1110_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[6];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_1110_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[6] & 4294967295)) * ((uint64_t)(context->gpr[14] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_b_M_1110_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[14];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[6] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_1110_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[14];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[6] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_1110_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[14];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_1110_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[6] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[6], context);
	context->gpr[6] = 4 + context->gpr[6];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[14] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[14], context);
	context->gpr[14] = 4 + context->gpr[14];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_b_M_1111_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[6];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_1111_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[6];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_1111_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[6];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_1111_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[6] & 4294967295)) * ((uint64_t)(context->gpr[15] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_b_M_1111_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[15];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[6] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_1111_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[15];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[6] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_1111_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[15];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_1111_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[6] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[6], context);
	context->gpr[6] = 4 + context->gpr[6];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[15] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[15], context);
	context->gpr[15] = 4 + context->gpr[15];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void stc_sr_rn_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->sr = 240 & context->sr;
	if (context->t) {
	context->sr = 1 | context->sr;
	}
	if (context->s) {
	context->sr = 2 | context->sr;
	}
	if (context->q) {
	context->sr = 256 | context->sr;
	}
	if (context->m) {
	context->sr = 512 | context->sr;
	}
	context->gpr[7] = context->sr;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void bsrf_M_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->pr = context->pc + 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = context->gpr[7] + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
}
static void store_rm_r0_rn_indexed_b_M_0000_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[7];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_0000_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[7];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_0000_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[7];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_0000_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[7] & 4294967295)) * ((uint64_t)(context->gpr[0] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sts_mach_rn_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[7] = context->mach;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void load_r0_rm_indexed_rn_b_M_0000_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[0];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[7] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_0000_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[0];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[7] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_0000_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[0];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_0000_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[7] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[7], context);
	context->gpr[7] = 4 + context->gpr[7];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[0] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[0], context);
	context->gpr[0] = 4 + context->gpr[0];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void stc_gbr_rn_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[7] = context->gbr;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void store_rm_r0_rn_indexed_b_M_0001_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[7];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_0001_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[7];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_0001_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[7];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_0001_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[7] & 4294967295)) * ((uint64_t)(context->gpr[1] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sts_macl_rn_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[7] = context->macl;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void load_r0_rm_indexed_rn_b_M_0001_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[1];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[7] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_0001_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[1];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[7] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_0001_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[1];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_0001_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[7] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[7], context);
	context->gpr[7] = 4 + context->gpr[7];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[1] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[1], context);
	context->gpr[1] = 4 + context->gpr[1];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void stc_vbr_rn_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[7] = context->vbr;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void braf_M_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = context->gpr[7] + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
}
static void store_rm_r0_rn_indexed_b_M_0010_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[7];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_0010_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[7];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_0010_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[7];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_0010_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[7] & 4294967295)) * ((uint64_t)(context->gpr[2] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void movt_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->t = !context->t;
	context->t = !context->t;
	context->gpr[7] = context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sts_pr_rn_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[7] = context->pr;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void load_r0_rm_indexed_rn_b_M_0010_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[2];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[7] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_0010_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[2];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[7] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_0010_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[2];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_0010_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[7] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[7], context);
	context->gpr[7] = 4 + context->gpr[7];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[2] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[2], context);
	context->gpr[2] = 4 + context->gpr[2];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_b_M_0011_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[7];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_0011_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[7];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_0011_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[7];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_0011_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[7] & 4294967295)) * ((uint64_t)(context->gpr[3] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_b_M_0011_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[3];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[7] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_0011_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[3];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[7] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_0011_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[3];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_0011_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[7] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[7], context);
	context->gpr[7] = 4 + context->gpr[7];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[3] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[3], context);
	context->gpr[3] = 4 + context->gpr[3];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_b_M_0100_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[7];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_0100_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[7];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_0100_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[7];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_0100_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[7] & 4294967295)) * ((uint64_t)(context->gpr[4] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_b_M_0100_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[4];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[7] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_0100_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[4];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[7] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_0100_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[4];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_0100_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[7] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[7], context);
	context->gpr[7] = 4 + context->gpr[7];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[4] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[4], context);
	context->gpr[4] = 4 + context->gpr[4];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_b_M_0101_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[7];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_0101_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[7];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_0101_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[7];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_0101_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[7] & 4294967295)) * ((uint64_t)(context->gpr[5] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_b_M_0101_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[5];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[7] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_0101_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[5];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[7] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_0101_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[5];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_0101_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[7] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[7], context);
	context->gpr[7] = 4 + context->gpr[7];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[5] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[5], context);
	context->gpr[5] = 4 + context->gpr[5];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_b_M_0110_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[7];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_0110_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[7];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_0110_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[7];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_0110_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[7] & 4294967295)) * ((uint64_t)(context->gpr[6] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_b_M_0110_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[6];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[7] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_0110_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[6];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[7] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_0110_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[6];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_0110_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[7] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[7], context);
	context->gpr[7] = 4 + context->gpr[7];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[6] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[6], context);
	context->gpr[6] = 4 + context->gpr[6];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_b_M_0111_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[7];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_0111_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[7];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_0111_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[7];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_0111_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[7] & 4294967295)) * ((uint64_t)(context->gpr[7] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_b_M_0111_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[7];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[7] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_0111_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[7];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[7] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_0111_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[7];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_0111_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[7] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[7], context);
	context->gpr[7] = 4 + context->gpr[7];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[7] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[7], context);
	context->gpr[7] = 4 + context->gpr[7];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_b_M_1000_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[7];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_1000_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[7];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_1000_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[7];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_1000_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[7] & 4294967295)) * ((uint64_t)(context->gpr[8] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_b_M_1000_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[8];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[7] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_1000_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[8];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[7] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_1000_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[8];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_1000_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[7] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[7], context);
	context->gpr[7] = 4 + context->gpr[7];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[8] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[8], context);
	context->gpr[8] = 4 + context->gpr[8];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_b_M_1001_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[7];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_1001_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[7];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_1001_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[7];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_1001_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[7] & 4294967295)) * ((uint64_t)(context->gpr[9] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_b_M_1001_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[9];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[7] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_1001_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[9];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[7] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_1001_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[9];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_1001_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[7] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[7], context);
	context->gpr[7] = 4 + context->gpr[7];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[9] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[9], context);
	context->gpr[9] = 4 + context->gpr[9];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_b_M_1010_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[7];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_1010_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[7];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_1010_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[7];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_1010_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[7] & 4294967295)) * ((uint64_t)(context->gpr[10] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_b_M_1010_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[10];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[7] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_1010_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[10];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[7] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_1010_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[10];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_1010_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[7] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[7], context);
	context->gpr[7] = 4 + context->gpr[7];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[10] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[10], context);
	context->gpr[10] = 4 + context->gpr[10];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_b_M_1011_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[7];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_1011_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[7];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_1011_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[7];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_1011_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[7] & 4294967295)) * ((uint64_t)(context->gpr[11] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_b_M_1011_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[11];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[7] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_1011_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[11];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[7] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_1011_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[11];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_1011_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[7] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[7], context);
	context->gpr[7] = 4 + context->gpr[7];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[11] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[11], context);
	context->gpr[11] = 4 + context->gpr[11];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_b_M_1100_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[7];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_1100_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[7];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_1100_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[7];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_1100_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[7] & 4294967295)) * ((uint64_t)(context->gpr[12] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_b_M_1100_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[12];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[7] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_1100_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[12];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[7] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_1100_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[12];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_1100_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[7] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[7], context);
	context->gpr[7] = 4 + context->gpr[7];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[12] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[12], context);
	context->gpr[12] = 4 + context->gpr[12];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_b_M_1101_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[7];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_1101_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[7];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_1101_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[7];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_1101_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[7] & 4294967295)) * ((uint64_t)(context->gpr[13] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_b_M_1101_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[13];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[7] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_1101_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[13];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[7] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_1101_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[13];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_1101_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[7] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[7], context);
	context->gpr[7] = 4 + context->gpr[7];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[13] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[13], context);
	context->gpr[13] = 4 + context->gpr[13];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_b_M_1110_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[7];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_1110_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[7];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_1110_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[7];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_1110_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[7] & 4294967295)) * ((uint64_t)(context->gpr[14] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_b_M_1110_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[14];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[7] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_1110_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[14];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[7] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_1110_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[14];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_1110_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[7] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[7], context);
	context->gpr[7] = 4 + context->gpr[7];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[14] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[14], context);
	context->gpr[14] = 4 + context->gpr[14];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_b_M_1111_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[7];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_1111_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[7];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_1111_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[7];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_1111_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[7] & 4294967295)) * ((uint64_t)(context->gpr[15] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_b_M_1111_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[15];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[7] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_1111_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[15];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[7] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_1111_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[15];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_1111_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[7] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[7], context);
	context->gpr[7] = 4 + context->gpr[7];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[15] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[15], context);
	context->gpr[15] = 4 + context->gpr[15];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void stc_sr_rn_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->sr = 240 & context->sr;
	if (context->t) {
	context->sr = 1 | context->sr;
	}
	if (context->s) {
	context->sr = 2 | context->sr;
	}
	if (context->q) {
	context->sr = 256 | context->sr;
	}
	if (context->m) {
	context->sr = 512 | context->sr;
	}
	context->gpr[8] = context->sr;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void bsrf_M_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->pr = context->pc + 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = context->gpr[8] + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
}
static void store_rm_r0_rn_indexed_b_M_0000_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[8];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_0000_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[8];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_0000_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[8];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_0000_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[8] & 4294967295)) * ((uint64_t)(context->gpr[0] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sts_mach_rn_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[8] = context->mach;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void load_r0_rm_indexed_rn_b_M_0000_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[0];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[8] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_0000_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[0];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[8] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_0000_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[0];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_0000_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[8] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[8], context);
	context->gpr[8] = 4 + context->gpr[8];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[0] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[0], context);
	context->gpr[0] = 4 + context->gpr[0];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void stc_gbr_rn_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[8] = context->gbr;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void store_rm_r0_rn_indexed_b_M_0001_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[8];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_0001_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[8];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_0001_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[8];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_0001_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[8] & 4294967295)) * ((uint64_t)(context->gpr[1] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sts_macl_rn_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[8] = context->macl;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void load_r0_rm_indexed_rn_b_M_0001_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[1];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[8] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_0001_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[1];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[8] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_0001_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[1];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_0001_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[8] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[8], context);
	context->gpr[8] = 4 + context->gpr[8];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[1] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[1], context);
	context->gpr[1] = 4 + context->gpr[1];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void stc_vbr_rn_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[8] = context->vbr;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void braf_M_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = context->gpr[8] + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
}
static void store_rm_r0_rn_indexed_b_M_0010_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[8];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_0010_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[8];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_0010_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[8];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_0010_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[8] & 4294967295)) * ((uint64_t)(context->gpr[2] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void movt_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->t = !context->t;
	context->t = !context->t;
	context->gpr[8] = context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sts_pr_rn_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[8] = context->pr;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void load_r0_rm_indexed_rn_b_M_0010_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[2];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[8] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_0010_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[2];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[8] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_0010_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[2];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_0010_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[8] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[8], context);
	context->gpr[8] = 4 + context->gpr[8];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[2] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[2], context);
	context->gpr[2] = 4 + context->gpr[2];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_b_M_0011_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[8];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_0011_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[8];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_0011_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[8];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_0011_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[8] & 4294967295)) * ((uint64_t)(context->gpr[3] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_b_M_0011_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[3];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[8] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_0011_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[3];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[8] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_0011_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[3];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_0011_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[8] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[8], context);
	context->gpr[8] = 4 + context->gpr[8];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[3] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[3], context);
	context->gpr[3] = 4 + context->gpr[3];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_b_M_0100_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[8];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_0100_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[8];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_0100_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[8];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_0100_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[8] & 4294967295)) * ((uint64_t)(context->gpr[4] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_b_M_0100_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[4];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[8] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_0100_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[4];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[8] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_0100_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[4];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_0100_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[8] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[8], context);
	context->gpr[8] = 4 + context->gpr[8];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[4] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[4], context);
	context->gpr[4] = 4 + context->gpr[4];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_b_M_0101_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[8];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_0101_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[8];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_0101_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[8];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_0101_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[8] & 4294967295)) * ((uint64_t)(context->gpr[5] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_b_M_0101_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[5];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[8] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_0101_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[5];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[8] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_0101_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[5];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_0101_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[8] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[8], context);
	context->gpr[8] = 4 + context->gpr[8];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[5] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[5], context);
	context->gpr[5] = 4 + context->gpr[5];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_b_M_0110_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[8];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_0110_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[8];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_0110_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[8];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_0110_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[8] & 4294967295)) * ((uint64_t)(context->gpr[6] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_b_M_0110_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[6];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[8] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_0110_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[6];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[8] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_0110_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[6];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_0110_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[8] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[8], context);
	context->gpr[8] = 4 + context->gpr[8];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[6] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[6], context);
	context->gpr[6] = 4 + context->gpr[6];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_b_M_0111_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[8];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_0111_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[8];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_0111_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[8];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_0111_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[8] & 4294967295)) * ((uint64_t)(context->gpr[7] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_b_M_0111_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[7];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[8] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_0111_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[7];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[8] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_0111_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[7];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_0111_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[8] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[8], context);
	context->gpr[8] = 4 + context->gpr[8];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[7] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[7], context);
	context->gpr[7] = 4 + context->gpr[7];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_b_M_1000_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[8];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_1000_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[8];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_1000_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[8];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_1000_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[8] & 4294967295)) * ((uint64_t)(context->gpr[8] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_b_M_1000_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[8];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[8] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_1000_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[8];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[8] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_1000_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[8];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_1000_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[8] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[8], context);
	context->gpr[8] = 4 + context->gpr[8];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[8] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[8], context);
	context->gpr[8] = 4 + context->gpr[8];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_b_M_1001_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[8];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_1001_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[8];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_1001_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[8];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_1001_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[8] & 4294967295)) * ((uint64_t)(context->gpr[9] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_b_M_1001_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[9];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[8] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_1001_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[9];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[8] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_1001_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[9];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_1001_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[8] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[8], context);
	context->gpr[8] = 4 + context->gpr[8];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[9] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[9], context);
	context->gpr[9] = 4 + context->gpr[9];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_b_M_1010_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[8];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_1010_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[8];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_1010_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[8];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_1010_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[8] & 4294967295)) * ((uint64_t)(context->gpr[10] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_b_M_1010_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[10];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[8] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_1010_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[10];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[8] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_1010_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[10];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_1010_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[8] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[8], context);
	context->gpr[8] = 4 + context->gpr[8];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[10] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[10], context);
	context->gpr[10] = 4 + context->gpr[10];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_b_M_1011_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[8];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_1011_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[8];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_1011_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[8];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_1011_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[8] & 4294967295)) * ((uint64_t)(context->gpr[11] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_b_M_1011_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[11];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[8] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_1011_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[11];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[8] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_1011_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[11];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_1011_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[8] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[8], context);
	context->gpr[8] = 4 + context->gpr[8];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[11] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[11], context);
	context->gpr[11] = 4 + context->gpr[11];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_b_M_1100_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[8];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_1100_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[8];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_1100_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[8];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_1100_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[8] & 4294967295)) * ((uint64_t)(context->gpr[12] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_b_M_1100_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[12];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[8] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_1100_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[12];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[8] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_1100_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[12];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_1100_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[8] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[8], context);
	context->gpr[8] = 4 + context->gpr[8];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[12] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[12], context);
	context->gpr[12] = 4 + context->gpr[12];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_b_M_1101_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[8];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_1101_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[8];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_1101_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[8];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_1101_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[8] & 4294967295)) * ((uint64_t)(context->gpr[13] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_b_M_1101_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[13];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[8] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_1101_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[13];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[8] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_1101_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[13];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_1101_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[8] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[8], context);
	context->gpr[8] = 4 + context->gpr[8];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[13] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[13], context);
	context->gpr[13] = 4 + context->gpr[13];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_b_M_1110_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[8];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_1110_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[8];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_1110_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[8];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_1110_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[8] & 4294967295)) * ((uint64_t)(context->gpr[14] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_b_M_1110_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[14];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[8] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_1110_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[14];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[8] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_1110_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[14];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_1110_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[8] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[8], context);
	context->gpr[8] = 4 + context->gpr[8];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[14] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[14], context);
	context->gpr[14] = 4 + context->gpr[14];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_b_M_1111_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[8];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_1111_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[8];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_1111_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[8];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_1111_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[8] & 4294967295)) * ((uint64_t)(context->gpr[15] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_b_M_1111_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[15];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[8] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_1111_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[15];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[8] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_1111_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[15];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_1111_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[8] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[8], context);
	context->gpr[8] = 4 + context->gpr[8];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[15] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[15], context);
	context->gpr[15] = 4 + context->gpr[15];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void stc_sr_rn_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->sr = 240 & context->sr;
	if (context->t) {
	context->sr = 1 | context->sr;
	}
	if (context->s) {
	context->sr = 2 | context->sr;
	}
	if (context->q) {
	context->sr = 256 | context->sr;
	}
	if (context->m) {
	context->sr = 512 | context->sr;
	}
	context->gpr[9] = context->sr;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void bsrf_M_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->pr = context->pc + 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = context->gpr[9] + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
}
static void store_rm_r0_rn_indexed_b_M_0000_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[9];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_0000_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[9];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_0000_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[9];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_0000_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[9] & 4294967295)) * ((uint64_t)(context->gpr[0] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sts_mach_rn_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[9] = context->mach;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void load_r0_rm_indexed_rn_b_M_0000_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[0];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[9] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_0000_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[0];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[9] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_0000_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[0];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_0000_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[9] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[9], context);
	context->gpr[9] = 4 + context->gpr[9];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[0] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[0], context);
	context->gpr[0] = 4 + context->gpr[0];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void stc_gbr_rn_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[9] = context->gbr;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void store_rm_r0_rn_indexed_b_M_0001_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[9];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_0001_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[9];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_0001_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[9];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_0001_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[9] & 4294967295)) * ((uint64_t)(context->gpr[1] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sts_macl_rn_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[9] = context->macl;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void load_r0_rm_indexed_rn_b_M_0001_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[1];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[9] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_0001_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[1];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[9] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_0001_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[1];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_0001_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[9] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[9], context);
	context->gpr[9] = 4 + context->gpr[9];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[1] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[1], context);
	context->gpr[1] = 4 + context->gpr[1];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void stc_vbr_rn_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[9] = context->vbr;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void braf_M_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = context->gpr[9] + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
}
static void store_rm_r0_rn_indexed_b_M_0010_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[9];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_0010_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[9];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_0010_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[9];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_0010_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[9] & 4294967295)) * ((uint64_t)(context->gpr[2] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void movt_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->t = !context->t;
	context->t = !context->t;
	context->gpr[9] = context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sts_pr_rn_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[9] = context->pr;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void load_r0_rm_indexed_rn_b_M_0010_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[2];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[9] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_0010_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[2];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[9] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_0010_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[2];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_0010_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[9] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[9], context);
	context->gpr[9] = 4 + context->gpr[9];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[2] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[2], context);
	context->gpr[2] = 4 + context->gpr[2];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_b_M_0011_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[9];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_0011_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[9];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_0011_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[9];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_0011_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[9] & 4294967295)) * ((uint64_t)(context->gpr[3] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_b_M_0011_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[3];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[9] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_0011_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[3];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[9] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_0011_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[3];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_0011_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[9] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[9], context);
	context->gpr[9] = 4 + context->gpr[9];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[3] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[3], context);
	context->gpr[3] = 4 + context->gpr[3];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_b_M_0100_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[9];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_0100_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[9];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_0100_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[9];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_0100_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[9] & 4294967295)) * ((uint64_t)(context->gpr[4] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_b_M_0100_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[4];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[9] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_0100_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[4];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[9] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_0100_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[4];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_0100_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[9] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[9], context);
	context->gpr[9] = 4 + context->gpr[9];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[4] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[4], context);
	context->gpr[4] = 4 + context->gpr[4];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_b_M_0101_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[9];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_0101_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[9];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_0101_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[9];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_0101_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[9] & 4294967295)) * ((uint64_t)(context->gpr[5] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_b_M_0101_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[5];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[9] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_0101_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[5];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[9] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_0101_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[5];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_0101_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[9] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[9], context);
	context->gpr[9] = 4 + context->gpr[9];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[5] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[5], context);
	context->gpr[5] = 4 + context->gpr[5];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_b_M_0110_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[9];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_0110_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[9];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_0110_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[9];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_0110_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[9] & 4294967295)) * ((uint64_t)(context->gpr[6] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_b_M_0110_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[6];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[9] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_0110_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[6];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[9] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_0110_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[6];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_0110_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[9] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[9], context);
	context->gpr[9] = 4 + context->gpr[9];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[6] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[6], context);
	context->gpr[6] = 4 + context->gpr[6];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_b_M_0111_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[9];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_0111_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[9];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_0111_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[9];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_0111_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[9] & 4294967295)) * ((uint64_t)(context->gpr[7] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_b_M_0111_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[7];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[9] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_0111_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[7];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[9] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_0111_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[7];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_0111_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[9] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[9], context);
	context->gpr[9] = 4 + context->gpr[9];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[7] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[7], context);
	context->gpr[7] = 4 + context->gpr[7];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_b_M_1000_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[9];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_1000_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[9];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_1000_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[9];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_1000_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[9] & 4294967295)) * ((uint64_t)(context->gpr[8] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_b_M_1000_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[8];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[9] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_1000_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[8];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[9] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_1000_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[8];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_1000_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[9] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[9], context);
	context->gpr[9] = 4 + context->gpr[9];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[8] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[8], context);
	context->gpr[8] = 4 + context->gpr[8];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_b_M_1001_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[9];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_1001_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[9];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_1001_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[9];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_1001_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[9] & 4294967295)) * ((uint64_t)(context->gpr[9] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_b_M_1001_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[9];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[9] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_1001_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[9];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[9] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_1001_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[9];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_1001_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[9] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[9], context);
	context->gpr[9] = 4 + context->gpr[9];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[9] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[9], context);
	context->gpr[9] = 4 + context->gpr[9];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_b_M_1010_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[9];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_1010_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[9];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_1010_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[9];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_1010_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[9] & 4294967295)) * ((uint64_t)(context->gpr[10] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_b_M_1010_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[10];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[9] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_1010_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[10];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[9] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_1010_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[10];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_1010_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[9] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[9], context);
	context->gpr[9] = 4 + context->gpr[9];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[10] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[10], context);
	context->gpr[10] = 4 + context->gpr[10];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_b_M_1011_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[9];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_1011_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[9];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_1011_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[9];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_1011_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[9] & 4294967295)) * ((uint64_t)(context->gpr[11] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_b_M_1011_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[11];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[9] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_1011_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[11];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[9] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_1011_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[11];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_1011_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[9] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[9], context);
	context->gpr[9] = 4 + context->gpr[9];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[11] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[11], context);
	context->gpr[11] = 4 + context->gpr[11];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_b_M_1100_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[9];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_1100_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[9];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_1100_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[9];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_1100_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[9] & 4294967295)) * ((uint64_t)(context->gpr[12] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_b_M_1100_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[12];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[9] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_1100_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[12];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[9] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_1100_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[12];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_1100_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[9] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[9], context);
	context->gpr[9] = 4 + context->gpr[9];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[12] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[12], context);
	context->gpr[12] = 4 + context->gpr[12];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_b_M_1101_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[9];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_1101_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[9];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_1101_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[9];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_1101_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[9] & 4294967295)) * ((uint64_t)(context->gpr[13] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_b_M_1101_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[13];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[9] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_1101_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[13];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[9] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_1101_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[13];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_1101_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[9] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[9], context);
	context->gpr[9] = 4 + context->gpr[9];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[13] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[13], context);
	context->gpr[13] = 4 + context->gpr[13];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_b_M_1110_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[9];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_1110_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[9];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_1110_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[9];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_1110_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[9] & 4294967295)) * ((uint64_t)(context->gpr[14] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_b_M_1110_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[14];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[9] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_1110_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[14];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[9] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_1110_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[14];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_1110_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[9] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[9], context);
	context->gpr[9] = 4 + context->gpr[9];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[14] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[14], context);
	context->gpr[14] = 4 + context->gpr[14];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_b_M_1111_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[9];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_1111_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[9];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_1111_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[9];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_1111_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[9] & 4294967295)) * ((uint64_t)(context->gpr[15] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_b_M_1111_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[15];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[9] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_1111_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[15];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[9] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_1111_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[15];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_1111_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[9] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[9], context);
	context->gpr[9] = 4 + context->gpr[9];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[15] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[15], context);
	context->gpr[15] = 4 + context->gpr[15];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void stc_sr_rn_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->sr = 240 & context->sr;
	if (context->t) {
	context->sr = 1 | context->sr;
	}
	if (context->s) {
	context->sr = 2 | context->sr;
	}
	if (context->q) {
	context->sr = 256 | context->sr;
	}
	if (context->m) {
	context->sr = 512 | context->sr;
	}
	context->gpr[10] = context->sr;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void bsrf_M_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->pr = context->pc + 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = context->gpr[10] + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
}
static void store_rm_r0_rn_indexed_b_M_0000_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[10];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_0000_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[10];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_0000_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[10];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_0000_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[10] & 4294967295)) * ((uint64_t)(context->gpr[0] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sts_mach_rn_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[10] = context->mach;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void load_r0_rm_indexed_rn_b_M_0000_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[0];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[10] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_0000_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[0];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[10] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_0000_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[0];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_0000_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[10] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[10], context);
	context->gpr[10] = 4 + context->gpr[10];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[0] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[0], context);
	context->gpr[0] = 4 + context->gpr[0];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void stc_gbr_rn_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[10] = context->gbr;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void store_rm_r0_rn_indexed_b_M_0001_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[10];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_0001_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[10];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_0001_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[10];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_0001_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[10] & 4294967295)) * ((uint64_t)(context->gpr[1] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sts_macl_rn_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[10] = context->macl;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void load_r0_rm_indexed_rn_b_M_0001_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[1];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[10] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_0001_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[1];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[10] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_0001_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[1];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_0001_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[10] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[10], context);
	context->gpr[10] = 4 + context->gpr[10];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[1] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[1], context);
	context->gpr[1] = 4 + context->gpr[1];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void stc_vbr_rn_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[10] = context->vbr;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void braf_M_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = context->gpr[10] + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
}
static void store_rm_r0_rn_indexed_b_M_0010_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[10];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_0010_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[10];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_0010_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[10];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_0010_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[10] & 4294967295)) * ((uint64_t)(context->gpr[2] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void movt_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->t = !context->t;
	context->t = !context->t;
	context->gpr[10] = context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sts_pr_rn_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[10] = context->pr;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void load_r0_rm_indexed_rn_b_M_0010_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[2];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[10] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_0010_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[2];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[10] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_0010_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[2];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_0010_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[10] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[10], context);
	context->gpr[10] = 4 + context->gpr[10];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[2] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[2], context);
	context->gpr[2] = 4 + context->gpr[2];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_b_M_0011_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[10];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_0011_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[10];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_0011_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[10];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_0011_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[10] & 4294967295)) * ((uint64_t)(context->gpr[3] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_b_M_0011_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[3];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[10] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_0011_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[3];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[10] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_0011_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[3];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_0011_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[10] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[10], context);
	context->gpr[10] = 4 + context->gpr[10];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[3] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[3], context);
	context->gpr[3] = 4 + context->gpr[3];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_b_M_0100_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[10];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_0100_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[10];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_0100_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[10];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_0100_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[10] & 4294967295)) * ((uint64_t)(context->gpr[4] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_b_M_0100_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[4];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[10] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_0100_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[4];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[10] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_0100_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[4];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_0100_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[10] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[10], context);
	context->gpr[10] = 4 + context->gpr[10];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[4] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[4], context);
	context->gpr[4] = 4 + context->gpr[4];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_b_M_0101_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[10];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_0101_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[10];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_0101_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[10];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_0101_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[10] & 4294967295)) * ((uint64_t)(context->gpr[5] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_b_M_0101_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[5];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[10] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_0101_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[5];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[10] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_0101_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[5];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_0101_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[10] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[10], context);
	context->gpr[10] = 4 + context->gpr[10];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[5] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[5], context);
	context->gpr[5] = 4 + context->gpr[5];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_b_M_0110_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[10];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_0110_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[10];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_0110_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[10];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_0110_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[10] & 4294967295)) * ((uint64_t)(context->gpr[6] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_b_M_0110_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[6];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[10] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_0110_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[6];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[10] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_0110_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[6];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_0110_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[10] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[10], context);
	context->gpr[10] = 4 + context->gpr[10];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[6] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[6], context);
	context->gpr[6] = 4 + context->gpr[6];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_b_M_0111_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[10];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_0111_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[10];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_0111_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[10];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_0111_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[10] & 4294967295)) * ((uint64_t)(context->gpr[7] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_b_M_0111_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[7];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[10] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_0111_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[7];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[10] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_0111_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[7];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_0111_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[10] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[10], context);
	context->gpr[10] = 4 + context->gpr[10];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[7] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[7], context);
	context->gpr[7] = 4 + context->gpr[7];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_b_M_1000_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[10];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_1000_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[10];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_1000_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[10];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_1000_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[10] & 4294967295)) * ((uint64_t)(context->gpr[8] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_b_M_1000_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[8];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[10] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_1000_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[8];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[10] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_1000_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[8];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_1000_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[10] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[10], context);
	context->gpr[10] = 4 + context->gpr[10];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[8] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[8], context);
	context->gpr[8] = 4 + context->gpr[8];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_b_M_1001_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[10];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_1001_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[10];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_1001_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[10];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_1001_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[10] & 4294967295)) * ((uint64_t)(context->gpr[9] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_b_M_1001_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[9];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[10] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_1001_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[9];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[10] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_1001_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[9];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_1001_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[10] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[10], context);
	context->gpr[10] = 4 + context->gpr[10];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[9] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[9], context);
	context->gpr[9] = 4 + context->gpr[9];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_b_M_1010_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[10];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_1010_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[10];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_1010_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[10];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_1010_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[10] & 4294967295)) * ((uint64_t)(context->gpr[10] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_b_M_1010_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[10];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[10] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_1010_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[10];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[10] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_1010_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[10];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_1010_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[10] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[10], context);
	context->gpr[10] = 4 + context->gpr[10];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[10] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[10], context);
	context->gpr[10] = 4 + context->gpr[10];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_b_M_1011_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[10];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_1011_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[10];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_1011_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[10];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_1011_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[10] & 4294967295)) * ((uint64_t)(context->gpr[11] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_b_M_1011_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[11];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[10] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_1011_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[11];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[10] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_1011_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[11];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_1011_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[10] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[10], context);
	context->gpr[10] = 4 + context->gpr[10];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[11] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[11], context);
	context->gpr[11] = 4 + context->gpr[11];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_b_M_1100_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[10];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_1100_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[10];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_1100_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[10];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_1100_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[10] & 4294967295)) * ((uint64_t)(context->gpr[12] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_b_M_1100_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[12];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[10] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_1100_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[12];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[10] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_1100_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[12];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_1100_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[10] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[10], context);
	context->gpr[10] = 4 + context->gpr[10];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[12] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[12], context);
	context->gpr[12] = 4 + context->gpr[12];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_b_M_1101_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[10];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_1101_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[10];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_1101_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[10];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_1101_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[10] & 4294967295)) * ((uint64_t)(context->gpr[13] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_b_M_1101_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[13];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[10] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_1101_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[13];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[10] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_1101_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[13];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_1101_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[10] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[10], context);
	context->gpr[10] = 4 + context->gpr[10];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[13] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[13], context);
	context->gpr[13] = 4 + context->gpr[13];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_b_M_1110_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[10];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_1110_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[10];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_1110_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[10];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_1110_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[10] & 4294967295)) * ((uint64_t)(context->gpr[14] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_b_M_1110_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[14];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[10] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_1110_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[14];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[10] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_1110_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[14];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_1110_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[10] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[10], context);
	context->gpr[10] = 4 + context->gpr[10];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[14] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[14], context);
	context->gpr[14] = 4 + context->gpr[14];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_b_M_1111_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[10];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_1111_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[10];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_1111_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[10];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_1111_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[10] & 4294967295)) * ((uint64_t)(context->gpr[15] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_b_M_1111_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[15];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[10] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_1111_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[15];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[10] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_1111_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[15];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_1111_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[10] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[10], context);
	context->gpr[10] = 4 + context->gpr[10];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[15] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[15], context);
	context->gpr[15] = 4 + context->gpr[15];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void stc_sr_rn_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->sr = 240 & context->sr;
	if (context->t) {
	context->sr = 1 | context->sr;
	}
	if (context->s) {
	context->sr = 2 | context->sr;
	}
	if (context->q) {
	context->sr = 256 | context->sr;
	}
	if (context->m) {
	context->sr = 512 | context->sr;
	}
	context->gpr[11] = context->sr;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void bsrf_M_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->pr = context->pc + 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = context->gpr[11] + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
}
static void store_rm_r0_rn_indexed_b_M_0000_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[11];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_0000_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[11];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_0000_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[11];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_0000_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[11] & 4294967295)) * ((uint64_t)(context->gpr[0] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sts_mach_rn_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[11] = context->mach;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void load_r0_rm_indexed_rn_b_M_0000_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[0];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[11] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_0000_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[0];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[11] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_0000_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[0];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_0000_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[11] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[11], context);
	context->gpr[11] = 4 + context->gpr[11];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[0] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[0], context);
	context->gpr[0] = 4 + context->gpr[0];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void stc_gbr_rn_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[11] = context->gbr;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void store_rm_r0_rn_indexed_b_M_0001_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[11];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_0001_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[11];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_0001_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[11];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_0001_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[11] & 4294967295)) * ((uint64_t)(context->gpr[1] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sts_macl_rn_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[11] = context->macl;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void load_r0_rm_indexed_rn_b_M_0001_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[1];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[11] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_0001_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[1];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[11] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_0001_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[1];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_0001_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[11] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[11], context);
	context->gpr[11] = 4 + context->gpr[11];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[1] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[1], context);
	context->gpr[1] = 4 + context->gpr[1];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void stc_vbr_rn_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[11] = context->vbr;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void braf_M_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = context->gpr[11] + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
}
static void store_rm_r0_rn_indexed_b_M_0010_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[11];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_0010_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[11];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_0010_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[11];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_0010_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[11] & 4294967295)) * ((uint64_t)(context->gpr[2] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void movt_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->t = !context->t;
	context->t = !context->t;
	context->gpr[11] = context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sts_pr_rn_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[11] = context->pr;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void load_r0_rm_indexed_rn_b_M_0010_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[2];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[11] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_0010_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[2];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[11] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_0010_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[2];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_0010_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[11] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[11], context);
	context->gpr[11] = 4 + context->gpr[11];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[2] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[2], context);
	context->gpr[2] = 4 + context->gpr[2];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_b_M_0011_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[11];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_0011_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[11];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_0011_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[11];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_0011_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[11] & 4294967295)) * ((uint64_t)(context->gpr[3] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_b_M_0011_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[3];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[11] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_0011_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[3];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[11] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_0011_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[3];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_0011_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[11] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[11], context);
	context->gpr[11] = 4 + context->gpr[11];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[3] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[3], context);
	context->gpr[3] = 4 + context->gpr[3];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_b_M_0100_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[11];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_0100_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[11];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_0100_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[11];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_0100_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[11] & 4294967295)) * ((uint64_t)(context->gpr[4] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_b_M_0100_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[4];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[11] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_0100_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[4];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[11] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_0100_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[4];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_0100_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[11] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[11], context);
	context->gpr[11] = 4 + context->gpr[11];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[4] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[4], context);
	context->gpr[4] = 4 + context->gpr[4];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_b_M_0101_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[11];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_0101_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[11];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_0101_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[11];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_0101_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[11] & 4294967295)) * ((uint64_t)(context->gpr[5] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_b_M_0101_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[5];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[11] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_0101_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[5];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[11] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_0101_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[5];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_0101_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[11] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[11], context);
	context->gpr[11] = 4 + context->gpr[11];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[5] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[5], context);
	context->gpr[5] = 4 + context->gpr[5];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_b_M_0110_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[11];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_0110_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[11];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_0110_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[11];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_0110_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[11] & 4294967295)) * ((uint64_t)(context->gpr[6] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_b_M_0110_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[6];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[11] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_0110_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[6];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[11] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_0110_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[6];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_0110_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[11] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[11], context);
	context->gpr[11] = 4 + context->gpr[11];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[6] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[6], context);
	context->gpr[6] = 4 + context->gpr[6];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_b_M_0111_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[11];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_0111_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[11];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_0111_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[11];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_0111_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[11] & 4294967295)) * ((uint64_t)(context->gpr[7] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_b_M_0111_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[7];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[11] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_0111_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[7];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[11] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_0111_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[7];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_0111_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[11] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[11], context);
	context->gpr[11] = 4 + context->gpr[11];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[7] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[7], context);
	context->gpr[7] = 4 + context->gpr[7];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_b_M_1000_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[11];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_1000_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[11];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_1000_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[11];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_1000_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[11] & 4294967295)) * ((uint64_t)(context->gpr[8] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_b_M_1000_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[8];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[11] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_1000_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[8];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[11] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_1000_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[8];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_1000_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[11] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[11], context);
	context->gpr[11] = 4 + context->gpr[11];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[8] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[8], context);
	context->gpr[8] = 4 + context->gpr[8];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_b_M_1001_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[11];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_1001_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[11];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_1001_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[11];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_1001_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[11] & 4294967295)) * ((uint64_t)(context->gpr[9] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_b_M_1001_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[9];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[11] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_1001_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[9];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[11] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_1001_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[9];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_1001_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[11] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[11], context);
	context->gpr[11] = 4 + context->gpr[11];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[9] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[9], context);
	context->gpr[9] = 4 + context->gpr[9];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_b_M_1010_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[11];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_1010_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[11];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_1010_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[11];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_1010_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[11] & 4294967295)) * ((uint64_t)(context->gpr[10] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_b_M_1010_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[10];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[11] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_1010_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[10];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[11] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_1010_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[10];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_1010_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[11] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[11], context);
	context->gpr[11] = 4 + context->gpr[11];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[10] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[10], context);
	context->gpr[10] = 4 + context->gpr[10];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_b_M_1011_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[11];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_1011_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[11];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_1011_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[11];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_1011_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[11] & 4294967295)) * ((uint64_t)(context->gpr[11] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_b_M_1011_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[11];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[11] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_1011_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[11];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[11] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_1011_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[11];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_1011_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[11] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[11], context);
	context->gpr[11] = 4 + context->gpr[11];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[11] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[11], context);
	context->gpr[11] = 4 + context->gpr[11];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_b_M_1100_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[11];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_1100_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[11];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_1100_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[11];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_1100_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[11] & 4294967295)) * ((uint64_t)(context->gpr[12] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_b_M_1100_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[12];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[11] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_1100_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[12];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[11] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_1100_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[12];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_1100_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[11] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[11], context);
	context->gpr[11] = 4 + context->gpr[11];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[12] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[12], context);
	context->gpr[12] = 4 + context->gpr[12];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_b_M_1101_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[11];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_1101_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[11];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_1101_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[11];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_1101_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[11] & 4294967295)) * ((uint64_t)(context->gpr[13] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_b_M_1101_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[13];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[11] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_1101_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[13];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[11] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_1101_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[13];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_1101_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[11] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[11], context);
	context->gpr[11] = 4 + context->gpr[11];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[13] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[13], context);
	context->gpr[13] = 4 + context->gpr[13];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_b_M_1110_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[11];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_1110_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[11];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_1110_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[11];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_1110_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[11] & 4294967295)) * ((uint64_t)(context->gpr[14] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_b_M_1110_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[14];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[11] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_1110_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[14];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[11] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_1110_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[14];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_1110_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[11] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[11], context);
	context->gpr[11] = 4 + context->gpr[11];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[14] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[14], context);
	context->gpr[14] = 4 + context->gpr[14];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_b_M_1111_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[11];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_1111_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[11];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_1111_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[11];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_1111_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[11] & 4294967295)) * ((uint64_t)(context->gpr[15] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_b_M_1111_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[15];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[11] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_1111_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[15];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[11] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_1111_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[15];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_1111_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[11] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[11], context);
	context->gpr[11] = 4 + context->gpr[11];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[15] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[15], context);
	context->gpr[15] = 4 + context->gpr[15];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void stc_sr_rn_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->sr = 240 & context->sr;
	if (context->t) {
	context->sr = 1 | context->sr;
	}
	if (context->s) {
	context->sr = 2 | context->sr;
	}
	if (context->q) {
	context->sr = 256 | context->sr;
	}
	if (context->m) {
	context->sr = 512 | context->sr;
	}
	context->gpr[12] = context->sr;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void bsrf_M_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->pr = context->pc + 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = context->gpr[12] + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
}
static void store_rm_r0_rn_indexed_b_M_0000_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[12];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_0000_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[12];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_0000_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[12];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_0000_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[12] & 4294967295)) * ((uint64_t)(context->gpr[0] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sts_mach_rn_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[12] = context->mach;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void load_r0_rm_indexed_rn_b_M_0000_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[0];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[12] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_0000_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[0];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[12] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_0000_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[0];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_0000_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[12] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[12], context);
	context->gpr[12] = 4 + context->gpr[12];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[0] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[0], context);
	context->gpr[0] = 4 + context->gpr[0];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void stc_gbr_rn_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[12] = context->gbr;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void store_rm_r0_rn_indexed_b_M_0001_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[12];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_0001_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[12];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_0001_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[12];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_0001_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[12] & 4294967295)) * ((uint64_t)(context->gpr[1] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sts_macl_rn_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[12] = context->macl;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void load_r0_rm_indexed_rn_b_M_0001_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[1];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[12] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_0001_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[1];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[12] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_0001_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[1];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_0001_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[12] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[12], context);
	context->gpr[12] = 4 + context->gpr[12];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[1] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[1], context);
	context->gpr[1] = 4 + context->gpr[1];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void stc_vbr_rn_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[12] = context->vbr;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void braf_M_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = context->gpr[12] + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
}
static void store_rm_r0_rn_indexed_b_M_0010_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[12];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_0010_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[12];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_0010_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[12];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_0010_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[12] & 4294967295)) * ((uint64_t)(context->gpr[2] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void movt_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->t = !context->t;
	context->t = !context->t;
	context->gpr[12] = context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sts_pr_rn_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[12] = context->pr;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void load_r0_rm_indexed_rn_b_M_0010_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[2];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[12] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_0010_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[2];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[12] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_0010_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[2];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_0010_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[12] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[12], context);
	context->gpr[12] = 4 + context->gpr[12];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[2] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[2], context);
	context->gpr[2] = 4 + context->gpr[2];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_b_M_0011_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[12];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_0011_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[12];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_0011_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[12];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_0011_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[12] & 4294967295)) * ((uint64_t)(context->gpr[3] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_b_M_0011_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[3];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[12] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_0011_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[3];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[12] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_0011_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[3];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_0011_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[12] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[12], context);
	context->gpr[12] = 4 + context->gpr[12];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[3] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[3], context);
	context->gpr[3] = 4 + context->gpr[3];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_b_M_0100_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[12];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_0100_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[12];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_0100_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[12];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_0100_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[12] & 4294967295)) * ((uint64_t)(context->gpr[4] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_b_M_0100_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[4];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[12] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_0100_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[4];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[12] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_0100_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[4];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_0100_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[12] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[12], context);
	context->gpr[12] = 4 + context->gpr[12];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[4] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[4], context);
	context->gpr[4] = 4 + context->gpr[4];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_b_M_0101_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[12];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_0101_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[12];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_0101_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[12];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_0101_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[12] & 4294967295)) * ((uint64_t)(context->gpr[5] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_b_M_0101_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[5];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[12] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_0101_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[5];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[12] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_0101_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[5];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_0101_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[12] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[12], context);
	context->gpr[12] = 4 + context->gpr[12];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[5] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[5], context);
	context->gpr[5] = 4 + context->gpr[5];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_b_M_0110_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[12];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_0110_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[12];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_0110_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[12];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_0110_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[12] & 4294967295)) * ((uint64_t)(context->gpr[6] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_b_M_0110_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[6];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[12] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_0110_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[6];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[12] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_0110_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[6];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_0110_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[12] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[12], context);
	context->gpr[12] = 4 + context->gpr[12];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[6] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[6], context);
	context->gpr[6] = 4 + context->gpr[6];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_b_M_0111_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[12];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_0111_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[12];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_0111_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[12];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_0111_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[12] & 4294967295)) * ((uint64_t)(context->gpr[7] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_b_M_0111_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[7];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[12] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_0111_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[7];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[12] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_0111_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[7];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_0111_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[12] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[12], context);
	context->gpr[12] = 4 + context->gpr[12];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[7] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[7], context);
	context->gpr[7] = 4 + context->gpr[7];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_b_M_1000_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[12];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_1000_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[12];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_1000_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[12];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_1000_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[12] & 4294967295)) * ((uint64_t)(context->gpr[8] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_b_M_1000_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[8];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[12] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_1000_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[8];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[12] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_1000_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[8];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_1000_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[12] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[12], context);
	context->gpr[12] = 4 + context->gpr[12];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[8] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[8], context);
	context->gpr[8] = 4 + context->gpr[8];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_b_M_1001_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[12];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_1001_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[12];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_1001_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[12];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_1001_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[12] & 4294967295)) * ((uint64_t)(context->gpr[9] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_b_M_1001_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[9];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[12] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_1001_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[9];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[12] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_1001_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[9];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_1001_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[12] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[12], context);
	context->gpr[12] = 4 + context->gpr[12];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[9] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[9], context);
	context->gpr[9] = 4 + context->gpr[9];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_b_M_1010_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[12];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_1010_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[12];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_1010_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[12];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_1010_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[12] & 4294967295)) * ((uint64_t)(context->gpr[10] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_b_M_1010_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[10];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[12] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_1010_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[10];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[12] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_1010_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[10];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_1010_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[12] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[12], context);
	context->gpr[12] = 4 + context->gpr[12];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[10] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[10], context);
	context->gpr[10] = 4 + context->gpr[10];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_b_M_1011_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[12];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_1011_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[12];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_1011_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[12];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_1011_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[12] & 4294967295)) * ((uint64_t)(context->gpr[11] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_b_M_1011_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[11];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[12] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_1011_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[11];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[12] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_1011_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[11];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_1011_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[12] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[12], context);
	context->gpr[12] = 4 + context->gpr[12];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[11] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[11], context);
	context->gpr[11] = 4 + context->gpr[11];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_b_M_1100_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[12];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_1100_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[12];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_1100_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[12];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_1100_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[12] & 4294967295)) * ((uint64_t)(context->gpr[12] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_b_M_1100_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[12];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[12] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_1100_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[12];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[12] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_1100_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[12];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_1100_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[12] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[12], context);
	context->gpr[12] = 4 + context->gpr[12];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[12] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[12], context);
	context->gpr[12] = 4 + context->gpr[12];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_b_M_1101_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[12];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_1101_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[12];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_1101_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[12];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_1101_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[12] & 4294967295)) * ((uint64_t)(context->gpr[13] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_b_M_1101_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[13];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[12] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_1101_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[13];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[12] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_1101_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[13];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_1101_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[12] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[12], context);
	context->gpr[12] = 4 + context->gpr[12];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[13] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[13], context);
	context->gpr[13] = 4 + context->gpr[13];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_b_M_1110_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[12];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_1110_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[12];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_1110_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[12];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_1110_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[12] & 4294967295)) * ((uint64_t)(context->gpr[14] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_b_M_1110_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[14];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[12] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_1110_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[14];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[12] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_1110_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[14];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_1110_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[12] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[12], context);
	context->gpr[12] = 4 + context->gpr[12];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[14] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[14], context);
	context->gpr[14] = 4 + context->gpr[14];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_b_M_1111_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[12];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_1111_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[12];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_1111_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[12];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_1111_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[12] & 4294967295)) * ((uint64_t)(context->gpr[15] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_b_M_1111_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[15];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[12] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_1111_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[15];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[12] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_1111_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[15];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_1111_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[12] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[12], context);
	context->gpr[12] = 4 + context->gpr[12];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[15] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[15], context);
	context->gpr[15] = 4 + context->gpr[15];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void stc_sr_rn_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->sr = 240 & context->sr;
	if (context->t) {
	context->sr = 1 | context->sr;
	}
	if (context->s) {
	context->sr = 2 | context->sr;
	}
	if (context->q) {
	context->sr = 256 | context->sr;
	}
	if (context->m) {
	context->sr = 512 | context->sr;
	}
	context->gpr[13] = context->sr;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void bsrf_M_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->pr = context->pc + 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = context->gpr[13] + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
}
static void store_rm_r0_rn_indexed_b_M_0000_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[13];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_0000_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[13];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_0000_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[13];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_0000_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[13] & 4294967295)) * ((uint64_t)(context->gpr[0] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sts_mach_rn_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[13] = context->mach;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void load_r0_rm_indexed_rn_b_M_0000_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[0];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[13] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_0000_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[0];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[13] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_0000_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[0];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_0000_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[13] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[13], context);
	context->gpr[13] = 4 + context->gpr[13];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[0] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[0], context);
	context->gpr[0] = 4 + context->gpr[0];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void stc_gbr_rn_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[13] = context->gbr;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void store_rm_r0_rn_indexed_b_M_0001_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[13];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_0001_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[13];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_0001_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[13];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_0001_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[13] & 4294967295)) * ((uint64_t)(context->gpr[1] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sts_macl_rn_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[13] = context->macl;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void load_r0_rm_indexed_rn_b_M_0001_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[1];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[13] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_0001_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[1];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[13] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_0001_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[1];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_0001_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[13] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[13], context);
	context->gpr[13] = 4 + context->gpr[13];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[1] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[1], context);
	context->gpr[1] = 4 + context->gpr[1];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void stc_vbr_rn_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[13] = context->vbr;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void braf_M_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = context->gpr[13] + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
}
static void store_rm_r0_rn_indexed_b_M_0010_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[13];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_0010_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[13];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_0010_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[13];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_0010_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[13] & 4294967295)) * ((uint64_t)(context->gpr[2] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void movt_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->t = !context->t;
	context->t = !context->t;
	context->gpr[13] = context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sts_pr_rn_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[13] = context->pr;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void load_r0_rm_indexed_rn_b_M_0010_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[2];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[13] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_0010_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[2];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[13] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_0010_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[2];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_0010_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[13] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[13], context);
	context->gpr[13] = 4 + context->gpr[13];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[2] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[2], context);
	context->gpr[2] = 4 + context->gpr[2];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_b_M_0011_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[13];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_0011_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[13];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_0011_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[13];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_0011_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[13] & 4294967295)) * ((uint64_t)(context->gpr[3] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_b_M_0011_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[3];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[13] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_0011_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[3];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[13] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_0011_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[3];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_0011_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[13] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[13], context);
	context->gpr[13] = 4 + context->gpr[13];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[3] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[3], context);
	context->gpr[3] = 4 + context->gpr[3];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_b_M_0100_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[13];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_0100_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[13];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_0100_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[13];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_0100_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[13] & 4294967295)) * ((uint64_t)(context->gpr[4] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_b_M_0100_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[4];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[13] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_0100_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[4];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[13] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_0100_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[4];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_0100_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[13] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[13], context);
	context->gpr[13] = 4 + context->gpr[13];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[4] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[4], context);
	context->gpr[4] = 4 + context->gpr[4];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_b_M_0101_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[13];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_0101_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[13];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_0101_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[13];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_0101_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[13] & 4294967295)) * ((uint64_t)(context->gpr[5] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_b_M_0101_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[5];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[13] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_0101_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[5];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[13] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_0101_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[5];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_0101_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[13] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[13], context);
	context->gpr[13] = 4 + context->gpr[13];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[5] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[5], context);
	context->gpr[5] = 4 + context->gpr[5];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_b_M_0110_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[13];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_0110_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[13];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_0110_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[13];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_0110_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[13] & 4294967295)) * ((uint64_t)(context->gpr[6] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_b_M_0110_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[6];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[13] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_0110_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[6];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[13] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_0110_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[6];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_0110_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[13] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[13], context);
	context->gpr[13] = 4 + context->gpr[13];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[6] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[6], context);
	context->gpr[6] = 4 + context->gpr[6];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_b_M_0111_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[13];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_0111_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[13];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_0111_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[13];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_0111_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[13] & 4294967295)) * ((uint64_t)(context->gpr[7] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_b_M_0111_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[7];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[13] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_0111_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[7];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[13] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_0111_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[7];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_0111_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[13] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[13], context);
	context->gpr[13] = 4 + context->gpr[13];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[7] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[7], context);
	context->gpr[7] = 4 + context->gpr[7];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_b_M_1000_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[13];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_1000_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[13];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_1000_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[13];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_1000_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[13] & 4294967295)) * ((uint64_t)(context->gpr[8] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_b_M_1000_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[8];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[13] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_1000_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[8];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[13] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_1000_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[8];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_1000_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[13] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[13], context);
	context->gpr[13] = 4 + context->gpr[13];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[8] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[8], context);
	context->gpr[8] = 4 + context->gpr[8];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_b_M_1001_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[13];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_1001_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[13];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_1001_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[13];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_1001_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[13] & 4294967295)) * ((uint64_t)(context->gpr[9] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_b_M_1001_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[9];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[13] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_1001_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[9];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[13] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_1001_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[9];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_1001_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[13] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[13], context);
	context->gpr[13] = 4 + context->gpr[13];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[9] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[9], context);
	context->gpr[9] = 4 + context->gpr[9];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_b_M_1010_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[13];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_1010_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[13];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_1010_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[13];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_1010_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[13] & 4294967295)) * ((uint64_t)(context->gpr[10] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_b_M_1010_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[10];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[13] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_1010_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[10];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[13] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_1010_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[10];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_1010_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[13] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[13], context);
	context->gpr[13] = 4 + context->gpr[13];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[10] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[10], context);
	context->gpr[10] = 4 + context->gpr[10];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_b_M_1011_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[13];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_1011_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[13];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_1011_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[13];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_1011_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[13] & 4294967295)) * ((uint64_t)(context->gpr[11] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_b_M_1011_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[11];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[13] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_1011_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[11];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[13] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_1011_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[11];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_1011_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[13] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[13], context);
	context->gpr[13] = 4 + context->gpr[13];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[11] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[11], context);
	context->gpr[11] = 4 + context->gpr[11];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_b_M_1100_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[13];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_1100_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[13];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_1100_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[13];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_1100_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[13] & 4294967295)) * ((uint64_t)(context->gpr[12] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_b_M_1100_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[12];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[13] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_1100_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[12];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[13] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_1100_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[12];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_1100_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[13] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[13], context);
	context->gpr[13] = 4 + context->gpr[13];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[12] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[12], context);
	context->gpr[12] = 4 + context->gpr[12];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_b_M_1101_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[13];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_1101_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[13];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_1101_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[13];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_1101_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[13] & 4294967295)) * ((uint64_t)(context->gpr[13] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_b_M_1101_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[13];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[13] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_1101_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[13];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[13] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_1101_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[13];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_1101_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[13] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[13], context);
	context->gpr[13] = 4 + context->gpr[13];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[13] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[13], context);
	context->gpr[13] = 4 + context->gpr[13];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_b_M_1110_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[13];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_1110_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[13];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_1110_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[13];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_1110_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[13] & 4294967295)) * ((uint64_t)(context->gpr[14] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_b_M_1110_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[14];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[13] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_1110_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[14];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[13] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_1110_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[14];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_1110_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[13] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[13], context);
	context->gpr[13] = 4 + context->gpr[13];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[14] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[14], context);
	context->gpr[14] = 4 + context->gpr[14];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_b_M_1111_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[13];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_1111_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[13];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_1111_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[13];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_1111_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[13] & 4294967295)) * ((uint64_t)(context->gpr[15] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_b_M_1111_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[15];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[13] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_1111_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[15];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[13] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_1111_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[15];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_1111_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[13] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[13], context);
	context->gpr[13] = 4 + context->gpr[13];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[15] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[15], context);
	context->gpr[15] = 4 + context->gpr[15];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void stc_sr_rn_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->sr = 240 & context->sr;
	if (context->t) {
	context->sr = 1 | context->sr;
	}
	if (context->s) {
	context->sr = 2 | context->sr;
	}
	if (context->q) {
	context->sr = 256 | context->sr;
	}
	if (context->m) {
	context->sr = 512 | context->sr;
	}
	context->gpr[14] = context->sr;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void bsrf_M_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->pr = context->pc + 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = context->gpr[14] + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
}
static void store_rm_r0_rn_indexed_b_M_0000_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[14];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_0000_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[14];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_0000_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[14];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_0000_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[14] & 4294967295)) * ((uint64_t)(context->gpr[0] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sts_mach_rn_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[14] = context->mach;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void load_r0_rm_indexed_rn_b_M_0000_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[0];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[14] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_0000_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[0];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[14] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_0000_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[0];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_0000_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[14] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[14], context);
	context->gpr[14] = 4 + context->gpr[14];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[0] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[0], context);
	context->gpr[0] = 4 + context->gpr[0];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void stc_gbr_rn_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[14] = context->gbr;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void store_rm_r0_rn_indexed_b_M_0001_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[14];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_0001_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[14];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_0001_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[14];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_0001_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[14] & 4294967295)) * ((uint64_t)(context->gpr[1] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sts_macl_rn_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[14] = context->macl;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void load_r0_rm_indexed_rn_b_M_0001_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[1];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[14] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_0001_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[1];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[14] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_0001_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[1];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_0001_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[14] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[14], context);
	context->gpr[14] = 4 + context->gpr[14];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[1] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[1], context);
	context->gpr[1] = 4 + context->gpr[1];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void stc_vbr_rn_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[14] = context->vbr;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void braf_M_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = context->gpr[14] + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
}
static void store_rm_r0_rn_indexed_b_M_0010_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[14];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_0010_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[14];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_0010_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[14];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_0010_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[14] & 4294967295)) * ((uint64_t)(context->gpr[2] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void movt_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->t = !context->t;
	context->t = !context->t;
	context->gpr[14] = context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sts_pr_rn_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[14] = context->pr;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void load_r0_rm_indexed_rn_b_M_0010_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[2];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[14] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_0010_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[2];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[14] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_0010_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[2];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_0010_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[14] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[14], context);
	context->gpr[14] = 4 + context->gpr[14];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[2] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[2], context);
	context->gpr[2] = 4 + context->gpr[2];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_b_M_0011_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[14];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_0011_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[14];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_0011_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[14];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_0011_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[14] & 4294967295)) * ((uint64_t)(context->gpr[3] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_b_M_0011_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[3];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[14] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_0011_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[3];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[14] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_0011_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[3];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_0011_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[14] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[14], context);
	context->gpr[14] = 4 + context->gpr[14];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[3] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[3], context);
	context->gpr[3] = 4 + context->gpr[3];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_b_M_0100_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[14];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_0100_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[14];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_0100_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[14];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_0100_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[14] & 4294967295)) * ((uint64_t)(context->gpr[4] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_b_M_0100_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[4];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[14] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_0100_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[4];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[14] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_0100_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[4];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_0100_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[14] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[14], context);
	context->gpr[14] = 4 + context->gpr[14];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[4] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[4], context);
	context->gpr[4] = 4 + context->gpr[4];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_b_M_0101_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[14];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_0101_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[14];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_0101_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[14];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_0101_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[14] & 4294967295)) * ((uint64_t)(context->gpr[5] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_b_M_0101_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[5];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[14] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_0101_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[5];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[14] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_0101_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[5];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_0101_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[14] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[14], context);
	context->gpr[14] = 4 + context->gpr[14];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[5] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[5], context);
	context->gpr[5] = 4 + context->gpr[5];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_b_M_0110_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[14];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_0110_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[14];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_0110_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[14];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_0110_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[14] & 4294967295)) * ((uint64_t)(context->gpr[6] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_b_M_0110_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[6];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[14] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_0110_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[6];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[14] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_0110_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[6];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_0110_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[14] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[14], context);
	context->gpr[14] = 4 + context->gpr[14];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[6] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[6], context);
	context->gpr[6] = 4 + context->gpr[6];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_b_M_0111_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[14];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_0111_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[14];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_0111_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[14];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_0111_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[14] & 4294967295)) * ((uint64_t)(context->gpr[7] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_b_M_0111_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[7];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[14] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_0111_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[7];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[14] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_0111_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[7];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_0111_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[14] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[14], context);
	context->gpr[14] = 4 + context->gpr[14];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[7] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[7], context);
	context->gpr[7] = 4 + context->gpr[7];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_b_M_1000_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[14];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_1000_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[14];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_1000_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[14];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_1000_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[14] & 4294967295)) * ((uint64_t)(context->gpr[8] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_b_M_1000_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[8];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[14] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_1000_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[8];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[14] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_1000_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[8];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_1000_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[14] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[14], context);
	context->gpr[14] = 4 + context->gpr[14];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[8] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[8], context);
	context->gpr[8] = 4 + context->gpr[8];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_b_M_1001_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[14];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_1001_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[14];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_1001_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[14];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_1001_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[14] & 4294967295)) * ((uint64_t)(context->gpr[9] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_b_M_1001_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[9];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[14] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_1001_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[9];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[14] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_1001_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[9];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_1001_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[14] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[14], context);
	context->gpr[14] = 4 + context->gpr[14];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[9] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[9], context);
	context->gpr[9] = 4 + context->gpr[9];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_b_M_1010_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[14];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_1010_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[14];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_1010_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[14];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_1010_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[14] & 4294967295)) * ((uint64_t)(context->gpr[10] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_b_M_1010_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[10];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[14] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_1010_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[10];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[14] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_1010_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[10];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_1010_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[14] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[14], context);
	context->gpr[14] = 4 + context->gpr[14];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[10] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[10], context);
	context->gpr[10] = 4 + context->gpr[10];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_b_M_1011_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[14];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_1011_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[14];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_1011_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[14];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_1011_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[14] & 4294967295)) * ((uint64_t)(context->gpr[11] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_b_M_1011_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[11];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[14] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_1011_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[11];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[14] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_1011_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[11];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_1011_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[14] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[14], context);
	context->gpr[14] = 4 + context->gpr[14];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[11] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[11], context);
	context->gpr[11] = 4 + context->gpr[11];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_b_M_1100_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[14];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_1100_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[14];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_1100_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[14];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_1100_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[14] & 4294967295)) * ((uint64_t)(context->gpr[12] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_b_M_1100_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[12];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[14] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_1100_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[12];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[14] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_1100_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[12];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_1100_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[14] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[14], context);
	context->gpr[14] = 4 + context->gpr[14];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[12] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[12], context);
	context->gpr[12] = 4 + context->gpr[12];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_b_M_1101_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[14];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_1101_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[14];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_1101_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[14];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_1101_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[14] & 4294967295)) * ((uint64_t)(context->gpr[13] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_b_M_1101_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[13];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[14] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_1101_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[13];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[14] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_1101_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[13];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_1101_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[14] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[14], context);
	context->gpr[14] = 4 + context->gpr[14];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[13] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[13], context);
	context->gpr[13] = 4 + context->gpr[13];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_b_M_1110_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[14];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_1110_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[14];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_1110_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[14];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_1110_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[14] & 4294967295)) * ((uint64_t)(context->gpr[14] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_b_M_1110_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[14];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[14] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_1110_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[14];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[14] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_1110_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[14];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_1110_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[14] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[14], context);
	context->gpr[14] = 4 + context->gpr[14];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[14] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[14], context);
	context->gpr[14] = 4 + context->gpr[14];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_b_M_1111_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[14];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_1111_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[14];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_1111_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[14];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_1111_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[14] & 4294967295)) * ((uint64_t)(context->gpr[15] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_b_M_1111_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[15];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[14] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_1111_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[15];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[14] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_1111_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[15];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_1111_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[14] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[14], context);
	context->gpr[14] = 4 + context->gpr[14];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[15] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[15], context);
	context->gpr[15] = 4 + context->gpr[15];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void stc_sr_rn_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->sr = 240 & context->sr;
	if (context->t) {
	context->sr = 1 | context->sr;
	}
	if (context->s) {
	context->sr = 2 | context->sr;
	}
	if (context->q) {
	context->sr = 256 | context->sr;
	}
	if (context->m) {
	context->sr = 512 | context->sr;
	}
	context->gpr[15] = context->sr;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void bsrf_M_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->pr = context->pc + 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = context->gpr[15] + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
}
static void store_rm_r0_rn_indexed_b_M_0000_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[15];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_0000_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[15];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_0000_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[15];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_0000_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[15] & 4294967295)) * ((uint64_t)(context->gpr[0] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sts_mach_rn_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[15] = context->mach;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void load_r0_rm_indexed_rn_b_M_0000_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[0];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[15] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_0000_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[0];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[15] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_0000_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[0];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_0000_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[15] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[15], context);
	context->gpr[15] = 4 + context->gpr[15];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[0] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[0], context);
	context->gpr[0] = 4 + context->gpr[0];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void stc_gbr_rn_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[15] = context->gbr;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void store_rm_r0_rn_indexed_b_M_0001_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[15];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_0001_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[15];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_0001_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[15];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_0001_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[15] & 4294967295)) * ((uint64_t)(context->gpr[1] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sts_macl_rn_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[15] = context->macl;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void load_r0_rm_indexed_rn_b_M_0001_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[1];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[15] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_0001_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[1];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[15] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_0001_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[1];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_0001_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[15] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[15], context);
	context->gpr[15] = 4 + context->gpr[15];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[1] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[1], context);
	context->gpr[1] = 4 + context->gpr[1];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void stc_vbr_rn_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[15] = context->vbr;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void braf_M_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = context->gpr[15] + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
}
static void store_rm_r0_rn_indexed_b_M_0010_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[15];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_0010_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[15];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_0010_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[15];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_0010_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[15] & 4294967295)) * ((uint64_t)(context->gpr[2] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void movt_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->t = !context->t;
	context->t = !context->t;
	context->gpr[15] = context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sts_pr_rn_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[15] = context->pr;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void load_r0_rm_indexed_rn_b_M_0010_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[2];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[15] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_0010_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[2];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[15] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_0010_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[2];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_0010_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[15] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[15], context);
	context->gpr[15] = 4 + context->gpr[15];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[2] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[2], context);
	context->gpr[2] = 4 + context->gpr[2];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_b_M_0011_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[15];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_0011_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[15];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_0011_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[15];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_0011_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[15] & 4294967295)) * ((uint64_t)(context->gpr[3] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_b_M_0011_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[3];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[15] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_0011_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[3];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[15] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_0011_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[3];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_0011_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[15] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[15], context);
	context->gpr[15] = 4 + context->gpr[15];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[3] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[3], context);
	context->gpr[3] = 4 + context->gpr[3];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_b_M_0100_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[15];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_0100_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[15];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_0100_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[15];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_0100_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[15] & 4294967295)) * ((uint64_t)(context->gpr[4] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_b_M_0100_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[4];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[15] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_0100_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[4];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[15] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_0100_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[4];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_0100_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[15] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[15], context);
	context->gpr[15] = 4 + context->gpr[15];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[4] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[4], context);
	context->gpr[4] = 4 + context->gpr[4];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_b_M_0101_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[15];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_0101_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[15];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_0101_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[15];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_0101_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[15] & 4294967295)) * ((uint64_t)(context->gpr[5] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_b_M_0101_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[5];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[15] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_0101_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[5];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[15] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_0101_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[5];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_0101_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[15] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[15], context);
	context->gpr[15] = 4 + context->gpr[15];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[5] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[5], context);
	context->gpr[5] = 4 + context->gpr[5];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_b_M_0110_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[15];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_0110_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[15];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_0110_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[15];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_0110_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[15] & 4294967295)) * ((uint64_t)(context->gpr[6] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_b_M_0110_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[6];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[15] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_0110_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[6];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[15] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_0110_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[6];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_0110_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[15] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[15], context);
	context->gpr[15] = 4 + context->gpr[15];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[6] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[6], context);
	context->gpr[6] = 4 + context->gpr[6];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_b_M_0111_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[15];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_0111_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[15];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_0111_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[15];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_0111_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[15] & 4294967295)) * ((uint64_t)(context->gpr[7] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_b_M_0111_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[7];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[15] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_0111_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[7];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[15] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_0111_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[7];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_0111_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[15] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[15], context);
	context->gpr[15] = 4 + context->gpr[15];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[7] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[7], context);
	context->gpr[7] = 4 + context->gpr[7];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_b_M_1000_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[15];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_1000_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[15];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_1000_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[15];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_1000_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[15] & 4294967295)) * ((uint64_t)(context->gpr[8] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_b_M_1000_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[8];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[15] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_1000_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[8];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[15] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_1000_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[8];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_1000_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[15] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[15], context);
	context->gpr[15] = 4 + context->gpr[15];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[8] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[8], context);
	context->gpr[8] = 4 + context->gpr[8];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_b_M_1001_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[15];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_1001_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[15];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_1001_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[15];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_1001_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[15] & 4294967295)) * ((uint64_t)(context->gpr[9] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_b_M_1001_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[9];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[15] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_1001_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[9];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[15] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_1001_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[9];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_1001_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[15] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[15], context);
	context->gpr[15] = 4 + context->gpr[15];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[9] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[9], context);
	context->gpr[9] = 4 + context->gpr[9];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_b_M_1010_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[15];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_1010_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[15];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_1010_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[15];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_1010_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[15] & 4294967295)) * ((uint64_t)(context->gpr[10] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_b_M_1010_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[10];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[15] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_1010_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[10];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[15] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_1010_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[10];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_1010_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[15] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[15], context);
	context->gpr[15] = 4 + context->gpr[15];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[10] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[10], context);
	context->gpr[10] = 4 + context->gpr[10];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_b_M_1011_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[15];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_1011_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[15];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_1011_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[15];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_1011_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[15] & 4294967295)) * ((uint64_t)(context->gpr[11] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_b_M_1011_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[11];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[15] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_1011_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[11];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[15] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_1011_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[11];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_1011_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[15] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[15], context);
	context->gpr[15] = 4 + context->gpr[15];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[11] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[11], context);
	context->gpr[11] = 4 + context->gpr[11];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_b_M_1100_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[15];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_1100_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[15];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_1100_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[15];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_1100_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[15] & 4294967295)) * ((uint64_t)(context->gpr[12] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_b_M_1100_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[12];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[15] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_1100_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[12];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[15] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_1100_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[12];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_1100_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[15] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[15], context);
	context->gpr[15] = 4 + context->gpr[15];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[12] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[12], context);
	context->gpr[12] = 4 + context->gpr[12];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_b_M_1101_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[15];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_1101_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[15];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_1101_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[15];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_1101_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[15] & 4294967295)) * ((uint64_t)(context->gpr[13] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_b_M_1101_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[13];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[15] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_1101_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[13];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[15] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_1101_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[13];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_1101_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[15] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[15], context);
	context->gpr[15] = 4 + context->gpr[15];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[13] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[13], context);
	context->gpr[13] = 4 + context->gpr[13];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_b_M_1110_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[15];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_1110_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[15];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_1110_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[15];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_1110_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[15] & 4294967295)) * ((uint64_t)(context->gpr[14] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_b_M_1110_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[14];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[15] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_1110_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[14];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[15] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_1110_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[14];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_1110_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[15] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[15], context);
	context->gpr[15] = 4 + context->gpr[15];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[14] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[14], context);
	context->gpr[14] = 4 + context->gpr[14];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_b_M_1111_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[15];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_w_M_1111_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[15];
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_r0_rn_indexed_l_M_1111_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] + context->gpr[15];
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mul_l_M_1111_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp;
	context->cycles += context->opts->gen.clock_divider * 3;
	tmp = ((uint64_t)(context->gpr[15] & 4294967295)) * ((uint64_t)(context->gpr[15] & 4294967295));
	context->macl = tmp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_b_M_1111_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[15];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[15] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_w_M_1111_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[15];
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[15] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_r0_rm_indexed_rn_l_M_1111_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gpr[15];
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_l_M_1111_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[15] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[15], context);
	context->gpr[15] = 4 + context->gpr[15];
	tmp1 = context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[15] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[15], context);
	context->gpr[15] = 4 + context->gpr[15];
	tmp1 = (int64_t)(((int64_t)((int32_t)tmp1)) * ((int64_t)((int32_t)context->scratch1)));
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (context->s) {
	if (((int64_t)tmp1) >= ((int64_t)140737488355328)) {
	tmp1 = 140737488355327ULL;
	} else {
	if (((int64_t)-140737488355329) >= ((int64_t)tmp1)) {
	tmp1 = 18446603336221196288ULL;
	}
	}
	}
	context->macl = tmp1;
	context->mach = tmp1 >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_0000_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[0] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_0000_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[0] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_0000_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[0] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_0000_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[0] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_0000_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[0] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_0000_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[0] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_0000_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[0] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_0000_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[0] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_0000_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[0] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_0000_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[0] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_0000_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[0] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_0000_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[0] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_0000_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[0] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_0000_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[0] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_0000_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[0] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_0000_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[0] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_0001_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[0] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_0001_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[0] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_0001_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[0] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_0001_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[0] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_0001_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[0] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_0001_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[0] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_0001_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[0] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_0001_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[0] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_0001_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[0] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_0001_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[0] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_0001_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[0] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_0001_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[0] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_0001_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[0] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_0001_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[0] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_0001_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[0] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_0001_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[0] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_0010_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[0] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_0010_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[0] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_0010_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[0] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_0010_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[0] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_0010_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[0] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_0010_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[0] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_0010_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[0] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_0010_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[0] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_0010_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[0] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_0010_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[0] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_0010_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[0] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_0010_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[0] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_0010_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[0] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_0010_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[0] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_0010_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[0] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_0010_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[0] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_0011_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[0] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_0011_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[0] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_0011_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[0] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_0011_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[0] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_0011_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[0] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_0011_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[0] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_0011_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[0] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_0011_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[0] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_0011_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[0] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_0011_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[0] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_0011_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[0] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_0011_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[0] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_0011_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[0] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_0011_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[0] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_0011_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[0] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_0011_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[0] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_0100_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[0] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_0100_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[0] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_0100_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[0] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_0100_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[0] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_0100_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[0] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_0100_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[0] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_0100_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[0] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_0100_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[0] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_0100_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[0] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_0100_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[0] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_0100_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[0] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_0100_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[0] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_0100_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[0] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_0100_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[0] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_0100_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[0] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_0100_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[0] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_0101_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[0] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_0101_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[0] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_0101_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[0] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_0101_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[0] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_0101_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[0] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_0101_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[0] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_0101_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[0] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_0101_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[0] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_0101_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[0] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_0101_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[0] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_0101_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[0] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_0101_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[0] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_0101_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[0] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_0101_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[0] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_0101_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[0] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_0101_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[0] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_0110_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[0] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_0110_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[0] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_0110_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[0] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_0110_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[0] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_0110_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[0] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_0110_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[0] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_0110_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[0] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_0110_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[0] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_0110_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[0] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_0110_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[0] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_0110_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[0] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_0110_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[0] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_0110_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[0] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_0110_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[0] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_0110_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[0] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_0110_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[0] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_0111_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[0] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_0111_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[0] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_0111_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[0] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_0111_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[0] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_0111_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[0] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_0111_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[0] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_0111_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[0] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_0111_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[0] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_0111_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[0] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_0111_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[0] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_0111_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[0] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_0111_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[0] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_0111_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[0] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_0111_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[0] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_0111_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[0] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_0111_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[0] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_1000_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[0] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_1000_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[0] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_1000_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[0] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_1000_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[0] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_1000_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[0] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_1000_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[0] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_1000_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[0] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_1000_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[0] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_1000_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[0] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_1000_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[0] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_1000_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[0] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_1000_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[0] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_1000_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[0] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_1000_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[0] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_1000_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[0] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_1000_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[0] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_1001_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[0] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_1001_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[0] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_1001_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[0] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_1001_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[0] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_1001_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[0] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_1001_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[0] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_1001_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[0] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_1001_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[0] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_1001_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[0] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_1001_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[0] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_1001_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[0] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_1001_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[0] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_1001_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[0] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_1001_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[0] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_1001_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[0] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_1001_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[0] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_1010_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[0] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_1010_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[0] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_1010_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[0] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_1010_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[0] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_1010_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[0] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_1010_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[0] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_1010_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[0] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_1010_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[0] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_1010_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[0] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_1010_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[0] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_1010_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[0] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_1010_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[0] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_1010_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[0] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_1010_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[0] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_1010_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[0] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_1010_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[0] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_1011_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[0] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_1011_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[0] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_1011_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[0] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_1011_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[0] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_1011_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[0] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_1011_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[0] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_1011_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[0] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_1011_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[0] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_1011_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[0] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_1011_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[0] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_1011_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[0] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_1011_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[0] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_1011_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[0] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_1011_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[0] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_1011_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[0] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_1011_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[0] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_1100_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[0] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_1100_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[0] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_1100_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[0] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_1100_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[0] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_1100_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[0] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_1100_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[0] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_1100_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[0] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_1100_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[0] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_1100_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[0] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_1100_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[0] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_1100_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[0] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_1100_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[0] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_1100_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[0] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_1100_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[0] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_1100_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[0] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_1100_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[0] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_1101_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[0] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_1101_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[0] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_1101_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[0] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_1101_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[0] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_1101_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[0] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_1101_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[0] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_1101_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[0] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_1101_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[0] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_1101_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[0] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_1101_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[0] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_1101_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[0] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_1101_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[0] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_1101_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[0] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_1101_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[0] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_1101_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[0] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_1101_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[0] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_1110_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[0] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_1110_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[0] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_1110_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[0] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_1110_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[0] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_1110_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[0] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_1110_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[0] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_1110_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[0] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_1110_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[0] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_1110_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[0] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_1110_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[0] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_1110_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[0] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_1110_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[0] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_1110_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[0] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_1110_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[0] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_1110_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[0] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_1110_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[0] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_1111_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[0] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_1111_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[0] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_1111_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[0] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_1111_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[0] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_1111_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[0] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_1111_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[0] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_1111_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[0] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_1111_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[0] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_1111_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[0] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_1111_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[0] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_1111_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[0] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_1111_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[0] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_1111_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[0] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_1111_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[0] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_1111_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[0] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_1111_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[0] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_0000_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[1] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_0000_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[1] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_0000_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[1] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_0000_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[1] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_0000_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[1] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_0000_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[1] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_0000_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[1] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_0000_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[1] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_0000_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[1] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_0000_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[1] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_0000_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[1] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_0000_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[1] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_0000_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[1] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_0000_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[1] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_0000_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[1] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_0000_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[1] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_0001_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[1] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_0001_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[1] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_0001_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[1] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_0001_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[1] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_0001_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[1] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_0001_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[1] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_0001_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[1] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_0001_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[1] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_0001_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[1] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_0001_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[1] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_0001_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[1] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_0001_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[1] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_0001_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[1] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_0001_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[1] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_0001_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[1] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_0001_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[1] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_0010_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[1] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_0010_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[1] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_0010_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[1] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_0010_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[1] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_0010_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[1] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_0010_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[1] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_0010_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[1] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_0010_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[1] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_0010_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[1] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_0010_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[1] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_0010_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[1] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_0010_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[1] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_0010_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[1] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_0010_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[1] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_0010_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[1] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_0010_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[1] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_0011_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[1] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_0011_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[1] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_0011_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[1] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_0011_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[1] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_0011_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[1] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_0011_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[1] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_0011_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[1] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_0011_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[1] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_0011_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[1] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_0011_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[1] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_0011_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[1] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_0011_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[1] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_0011_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[1] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_0011_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[1] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_0011_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[1] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_0011_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[1] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_0100_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[1] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_0100_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[1] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_0100_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[1] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_0100_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[1] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_0100_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[1] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_0100_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[1] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_0100_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[1] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_0100_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[1] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_0100_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[1] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_0100_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[1] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_0100_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[1] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_0100_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[1] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_0100_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[1] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_0100_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[1] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_0100_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[1] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_0100_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[1] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_0101_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[1] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_0101_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[1] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_0101_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[1] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_0101_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[1] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_0101_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[1] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_0101_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[1] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_0101_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[1] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_0101_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[1] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_0101_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[1] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_0101_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[1] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_0101_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[1] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_0101_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[1] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_0101_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[1] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_0101_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[1] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_0101_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[1] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_0101_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[1] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_0110_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[1] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_0110_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[1] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_0110_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[1] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_0110_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[1] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_0110_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[1] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_0110_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[1] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_0110_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[1] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_0110_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[1] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_0110_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[1] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_0110_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[1] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_0110_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[1] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_0110_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[1] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_0110_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[1] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_0110_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[1] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_0110_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[1] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_0110_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[1] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_0111_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[1] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_0111_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[1] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_0111_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[1] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_0111_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[1] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_0111_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[1] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_0111_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[1] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_0111_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[1] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_0111_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[1] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_0111_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[1] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_0111_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[1] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_0111_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[1] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_0111_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[1] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_0111_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[1] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_0111_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[1] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_0111_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[1] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_0111_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[1] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_1000_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[1] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_1000_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[1] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_1000_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[1] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_1000_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[1] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_1000_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[1] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_1000_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[1] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_1000_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[1] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_1000_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[1] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_1000_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[1] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_1000_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[1] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_1000_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[1] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_1000_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[1] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_1000_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[1] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_1000_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[1] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_1000_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[1] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_1000_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[1] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_1001_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[1] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_1001_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[1] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_1001_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[1] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_1001_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[1] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_1001_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[1] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_1001_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[1] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_1001_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[1] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_1001_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[1] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_1001_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[1] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_1001_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[1] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_1001_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[1] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_1001_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[1] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_1001_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[1] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_1001_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[1] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_1001_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[1] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_1001_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[1] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_1010_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[1] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_1010_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[1] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_1010_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[1] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_1010_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[1] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_1010_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[1] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_1010_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[1] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_1010_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[1] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_1010_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[1] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_1010_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[1] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_1010_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[1] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_1010_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[1] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_1010_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[1] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_1010_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[1] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_1010_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[1] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_1010_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[1] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_1010_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[1] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_1011_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[1] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_1011_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[1] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_1011_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[1] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_1011_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[1] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_1011_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[1] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_1011_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[1] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_1011_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[1] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_1011_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[1] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_1011_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[1] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_1011_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[1] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_1011_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[1] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_1011_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[1] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_1011_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[1] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_1011_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[1] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_1011_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[1] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_1011_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[1] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_1100_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[1] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_1100_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[1] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_1100_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[1] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_1100_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[1] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_1100_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[1] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_1100_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[1] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_1100_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[1] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_1100_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[1] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_1100_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[1] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_1100_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[1] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_1100_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[1] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_1100_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[1] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_1100_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[1] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_1100_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[1] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_1100_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[1] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_1100_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[1] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_1101_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[1] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_1101_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[1] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_1101_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[1] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_1101_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[1] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_1101_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[1] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_1101_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[1] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_1101_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[1] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_1101_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[1] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_1101_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[1] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_1101_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[1] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_1101_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[1] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_1101_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[1] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_1101_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[1] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_1101_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[1] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_1101_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[1] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_1101_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[1] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_1110_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[1] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_1110_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[1] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_1110_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[1] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_1110_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[1] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_1110_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[1] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_1110_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[1] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_1110_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[1] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_1110_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[1] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_1110_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[1] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_1110_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[1] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_1110_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[1] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_1110_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[1] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_1110_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[1] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_1110_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[1] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_1110_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[1] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_1110_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[1] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_1111_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[1] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_1111_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[1] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_1111_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[1] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_1111_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[1] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_1111_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[1] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_1111_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[1] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_1111_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[1] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_1111_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[1] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_1111_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[1] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_1111_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[1] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_1111_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[1] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_1111_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[1] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_1111_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[1] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_1111_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[1] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_1111_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[1] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_1111_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[1] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_0000_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[2] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_0000_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[2] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_0000_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[2] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_0000_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[2] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_0000_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[2] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_0000_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[2] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_0000_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[2] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_0000_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[2] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_0000_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[2] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_0000_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[2] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_0000_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[2] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_0000_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[2] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_0000_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[2] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_0000_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[2] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_0000_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[2] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_0000_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[2] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_0001_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[2] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_0001_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[2] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_0001_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[2] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_0001_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[2] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_0001_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[2] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_0001_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[2] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_0001_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[2] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_0001_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[2] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_0001_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[2] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_0001_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[2] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_0001_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[2] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_0001_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[2] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_0001_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[2] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_0001_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[2] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_0001_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[2] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_0001_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[2] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_0010_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[2] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_0010_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[2] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_0010_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[2] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_0010_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[2] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_0010_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[2] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_0010_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[2] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_0010_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[2] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_0010_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[2] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_0010_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[2] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_0010_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[2] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_0010_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[2] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_0010_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[2] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_0010_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[2] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_0010_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[2] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_0010_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[2] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_0010_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[2] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_0011_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[2] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_0011_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[2] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_0011_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[2] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_0011_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[2] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_0011_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[2] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_0011_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[2] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_0011_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[2] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_0011_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[2] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_0011_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[2] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_0011_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[2] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_0011_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[2] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_0011_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[2] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_0011_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[2] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_0011_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[2] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_0011_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[2] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_0011_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[2] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_0100_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[2] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_0100_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[2] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_0100_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[2] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_0100_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[2] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_0100_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[2] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_0100_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[2] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_0100_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[2] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_0100_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[2] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_0100_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[2] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_0100_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[2] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_0100_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[2] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_0100_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[2] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_0100_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[2] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_0100_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[2] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_0100_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[2] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_0100_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[2] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_0101_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[2] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_0101_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[2] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_0101_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[2] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_0101_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[2] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_0101_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[2] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_0101_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[2] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_0101_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[2] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_0101_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[2] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_0101_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[2] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_0101_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[2] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_0101_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[2] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_0101_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[2] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_0101_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[2] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_0101_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[2] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_0101_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[2] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_0101_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[2] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_0110_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[2] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_0110_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[2] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_0110_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[2] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_0110_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[2] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_0110_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[2] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_0110_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[2] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_0110_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[2] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_0110_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[2] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_0110_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[2] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_0110_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[2] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_0110_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[2] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_0110_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[2] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_0110_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[2] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_0110_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[2] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_0110_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[2] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_0110_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[2] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_0111_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[2] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_0111_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[2] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_0111_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[2] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_0111_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[2] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_0111_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[2] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_0111_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[2] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_0111_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[2] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_0111_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[2] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_0111_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[2] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_0111_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[2] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_0111_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[2] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_0111_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[2] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_0111_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[2] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_0111_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[2] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_0111_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[2] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_0111_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[2] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_1000_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[2] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_1000_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[2] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_1000_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[2] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_1000_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[2] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_1000_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[2] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_1000_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[2] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_1000_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[2] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_1000_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[2] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_1000_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[2] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_1000_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[2] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_1000_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[2] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_1000_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[2] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_1000_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[2] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_1000_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[2] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_1000_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[2] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_1000_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[2] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_1001_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[2] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_1001_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[2] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_1001_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[2] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_1001_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[2] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_1001_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[2] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_1001_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[2] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_1001_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[2] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_1001_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[2] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_1001_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[2] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_1001_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[2] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_1001_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[2] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_1001_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[2] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_1001_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[2] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_1001_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[2] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_1001_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[2] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_1001_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[2] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_1010_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[2] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_1010_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[2] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_1010_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[2] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_1010_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[2] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_1010_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[2] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_1010_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[2] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_1010_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[2] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_1010_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[2] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_1010_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[2] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_1010_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[2] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_1010_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[2] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_1010_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[2] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_1010_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[2] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_1010_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[2] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_1010_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[2] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_1010_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[2] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_1011_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[2] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_1011_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[2] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_1011_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[2] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_1011_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[2] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_1011_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[2] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_1011_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[2] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_1011_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[2] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_1011_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[2] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_1011_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[2] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_1011_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[2] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_1011_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[2] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_1011_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[2] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_1011_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[2] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_1011_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[2] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_1011_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[2] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_1011_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[2] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_1100_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[2] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_1100_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[2] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_1100_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[2] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_1100_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[2] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_1100_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[2] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_1100_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[2] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_1100_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[2] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_1100_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[2] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_1100_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[2] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_1100_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[2] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_1100_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[2] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_1100_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[2] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_1100_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[2] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_1100_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[2] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_1100_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[2] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_1100_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[2] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_1101_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[2] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_1101_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[2] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_1101_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[2] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_1101_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[2] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_1101_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[2] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_1101_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[2] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_1101_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[2] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_1101_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[2] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_1101_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[2] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_1101_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[2] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_1101_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[2] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_1101_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[2] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_1101_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[2] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_1101_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[2] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_1101_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[2] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_1101_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[2] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_1110_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[2] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_1110_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[2] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_1110_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[2] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_1110_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[2] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_1110_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[2] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_1110_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[2] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_1110_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[2] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_1110_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[2] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_1110_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[2] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_1110_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[2] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_1110_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[2] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_1110_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[2] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_1110_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[2] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_1110_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[2] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_1110_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[2] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_1110_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[2] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_1111_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[2] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_1111_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[2] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_1111_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[2] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_1111_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[2] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_1111_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[2] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_1111_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[2] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_1111_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[2] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_1111_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[2] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_1111_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[2] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_1111_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[2] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_1111_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[2] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_1111_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[2] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_1111_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[2] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_1111_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[2] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_1111_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[2] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_1111_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[2] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_0000_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[3] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_0000_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[3] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_0000_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[3] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_0000_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[3] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_0000_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[3] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_0000_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[3] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_0000_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[3] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_0000_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[3] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_0000_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[3] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_0000_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[3] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_0000_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[3] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_0000_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[3] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_0000_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[3] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_0000_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[3] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_0000_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[3] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_0000_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[3] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_0001_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[3] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_0001_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[3] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_0001_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[3] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_0001_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[3] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_0001_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[3] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_0001_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[3] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_0001_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[3] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_0001_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[3] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_0001_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[3] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_0001_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[3] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_0001_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[3] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_0001_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[3] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_0001_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[3] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_0001_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[3] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_0001_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[3] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_0001_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[3] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_0010_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[3] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_0010_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[3] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_0010_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[3] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_0010_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[3] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_0010_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[3] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_0010_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[3] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_0010_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[3] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_0010_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[3] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_0010_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[3] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_0010_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[3] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_0010_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[3] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_0010_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[3] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_0010_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[3] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_0010_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[3] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_0010_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[3] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_0010_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[3] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_0011_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[3] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_0011_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[3] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_0011_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[3] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_0011_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[3] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_0011_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[3] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_0011_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[3] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_0011_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[3] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_0011_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[3] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_0011_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[3] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_0011_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[3] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_0011_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[3] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_0011_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[3] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_0011_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[3] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_0011_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[3] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_0011_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[3] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_0011_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[3] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_0100_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[3] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_0100_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[3] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_0100_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[3] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_0100_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[3] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_0100_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[3] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_0100_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[3] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_0100_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[3] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_0100_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[3] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_0100_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[3] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_0100_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[3] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_0100_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[3] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_0100_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[3] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_0100_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[3] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_0100_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[3] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_0100_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[3] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_0100_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[3] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_0101_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[3] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_0101_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[3] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_0101_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[3] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_0101_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[3] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_0101_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[3] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_0101_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[3] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_0101_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[3] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_0101_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[3] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_0101_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[3] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_0101_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[3] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_0101_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[3] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_0101_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[3] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_0101_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[3] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_0101_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[3] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_0101_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[3] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_0101_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[3] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_0110_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[3] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_0110_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[3] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_0110_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[3] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_0110_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[3] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_0110_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[3] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_0110_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[3] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_0110_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[3] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_0110_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[3] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_0110_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[3] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_0110_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[3] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_0110_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[3] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_0110_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[3] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_0110_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[3] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_0110_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[3] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_0110_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[3] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_0110_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[3] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_0111_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[3] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_0111_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[3] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_0111_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[3] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_0111_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[3] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_0111_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[3] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_0111_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[3] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_0111_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[3] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_0111_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[3] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_0111_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[3] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_0111_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[3] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_0111_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[3] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_0111_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[3] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_0111_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[3] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_0111_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[3] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_0111_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[3] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_0111_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[3] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_1000_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[3] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_1000_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[3] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_1000_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[3] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_1000_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[3] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_1000_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[3] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_1000_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[3] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_1000_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[3] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_1000_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[3] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_1000_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[3] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_1000_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[3] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_1000_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[3] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_1000_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[3] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_1000_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[3] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_1000_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[3] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_1000_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[3] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_1000_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[3] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_1001_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[3] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_1001_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[3] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_1001_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[3] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_1001_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[3] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_1001_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[3] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_1001_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[3] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_1001_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[3] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_1001_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[3] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_1001_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[3] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_1001_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[3] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_1001_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[3] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_1001_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[3] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_1001_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[3] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_1001_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[3] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_1001_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[3] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_1001_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[3] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_1010_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[3] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_1010_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[3] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_1010_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[3] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_1010_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[3] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_1010_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[3] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_1010_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[3] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_1010_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[3] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_1010_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[3] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_1010_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[3] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_1010_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[3] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_1010_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[3] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_1010_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[3] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_1010_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[3] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_1010_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[3] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_1010_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[3] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_1010_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[3] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_1011_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[3] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_1011_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[3] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_1011_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[3] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_1011_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[3] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_1011_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[3] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_1011_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[3] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_1011_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[3] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_1011_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[3] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_1011_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[3] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_1011_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[3] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_1011_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[3] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_1011_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[3] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_1011_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[3] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_1011_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[3] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_1011_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[3] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_1011_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[3] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_1100_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[3] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_1100_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[3] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_1100_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[3] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_1100_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[3] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_1100_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[3] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_1100_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[3] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_1100_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[3] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_1100_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[3] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_1100_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[3] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_1100_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[3] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_1100_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[3] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_1100_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[3] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_1100_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[3] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_1100_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[3] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_1100_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[3] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_1100_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[3] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_1101_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[3] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_1101_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[3] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_1101_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[3] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_1101_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[3] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_1101_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[3] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_1101_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[3] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_1101_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[3] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_1101_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[3] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_1101_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[3] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_1101_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[3] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_1101_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[3] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_1101_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[3] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_1101_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[3] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_1101_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[3] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_1101_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[3] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_1101_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[3] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_1110_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[3] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_1110_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[3] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_1110_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[3] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_1110_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[3] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_1110_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[3] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_1110_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[3] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_1110_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[3] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_1110_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[3] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_1110_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[3] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_1110_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[3] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_1110_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[3] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_1110_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[3] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_1110_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[3] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_1110_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[3] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_1110_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[3] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_1110_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[3] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_1111_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[3] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_1111_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[3] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_1111_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[3] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_1111_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[3] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_1111_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[3] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_1111_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[3] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_1111_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[3] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_1111_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[3] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_1111_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[3] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_1111_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[3] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_1111_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[3] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_1111_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[3] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_1111_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[3] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_1111_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[3] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_1111_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[3] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_1111_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[3] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_0000_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[4] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_0000_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[4] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_0000_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[4] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_0000_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[4] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_0000_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[4] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_0000_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[4] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_0000_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[4] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_0000_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[4] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_0000_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[4] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_0000_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[4] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_0000_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[4] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_0000_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[4] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_0000_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[4] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_0000_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[4] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_0000_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[4] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_0000_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[4] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_0001_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[4] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_0001_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[4] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_0001_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[4] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_0001_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[4] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_0001_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[4] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_0001_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[4] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_0001_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[4] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_0001_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[4] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_0001_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[4] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_0001_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[4] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_0001_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[4] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_0001_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[4] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_0001_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[4] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_0001_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[4] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_0001_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[4] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_0001_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[4] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_0010_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[4] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_0010_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[4] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_0010_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[4] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_0010_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[4] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_0010_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[4] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_0010_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[4] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_0010_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[4] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_0010_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[4] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_0010_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[4] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_0010_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[4] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_0010_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[4] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_0010_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[4] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_0010_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[4] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_0010_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[4] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_0010_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[4] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_0010_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[4] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_0011_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[4] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_0011_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[4] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_0011_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[4] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_0011_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[4] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_0011_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[4] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_0011_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[4] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_0011_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[4] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_0011_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[4] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_0011_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[4] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_0011_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[4] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_0011_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[4] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_0011_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[4] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_0011_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[4] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_0011_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[4] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_0011_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[4] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_0011_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[4] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_0100_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[4] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_0100_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[4] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_0100_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[4] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_0100_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[4] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_0100_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[4] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_0100_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[4] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_0100_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[4] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_0100_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[4] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_0100_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[4] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_0100_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[4] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_0100_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[4] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_0100_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[4] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_0100_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[4] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_0100_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[4] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_0100_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[4] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_0100_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[4] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_0101_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[4] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_0101_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[4] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_0101_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[4] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_0101_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[4] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_0101_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[4] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_0101_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[4] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_0101_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[4] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_0101_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[4] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_0101_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[4] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_0101_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[4] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_0101_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[4] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_0101_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[4] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_0101_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[4] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_0101_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[4] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_0101_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[4] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_0101_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[4] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_0110_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[4] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_0110_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[4] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_0110_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[4] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_0110_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[4] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_0110_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[4] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_0110_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[4] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_0110_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[4] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_0110_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[4] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_0110_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[4] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_0110_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[4] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_0110_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[4] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_0110_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[4] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_0110_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[4] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_0110_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[4] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_0110_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[4] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_0110_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[4] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_0111_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[4] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_0111_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[4] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_0111_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[4] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_0111_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[4] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_0111_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[4] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_0111_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[4] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_0111_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[4] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_0111_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[4] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_0111_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[4] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_0111_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[4] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_0111_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[4] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_0111_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[4] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_0111_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[4] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_0111_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[4] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_0111_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[4] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_0111_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[4] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_1000_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[4] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_1000_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[4] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_1000_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[4] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_1000_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[4] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_1000_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[4] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_1000_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[4] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_1000_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[4] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_1000_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[4] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_1000_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[4] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_1000_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[4] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_1000_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[4] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_1000_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[4] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_1000_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[4] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_1000_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[4] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_1000_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[4] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_1000_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[4] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_1001_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[4] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_1001_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[4] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_1001_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[4] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_1001_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[4] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_1001_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[4] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_1001_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[4] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_1001_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[4] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_1001_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[4] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_1001_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[4] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_1001_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[4] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_1001_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[4] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_1001_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[4] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_1001_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[4] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_1001_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[4] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_1001_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[4] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_1001_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[4] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_1010_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[4] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_1010_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[4] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_1010_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[4] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_1010_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[4] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_1010_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[4] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_1010_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[4] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_1010_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[4] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_1010_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[4] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_1010_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[4] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_1010_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[4] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_1010_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[4] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_1010_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[4] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_1010_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[4] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_1010_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[4] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_1010_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[4] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_1010_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[4] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_1011_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[4] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_1011_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[4] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_1011_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[4] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_1011_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[4] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_1011_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[4] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_1011_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[4] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_1011_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[4] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_1011_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[4] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_1011_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[4] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_1011_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[4] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_1011_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[4] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_1011_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[4] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_1011_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[4] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_1011_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[4] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_1011_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[4] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_1011_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[4] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_1100_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[4] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_1100_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[4] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_1100_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[4] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_1100_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[4] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_1100_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[4] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_1100_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[4] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_1100_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[4] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_1100_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[4] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_1100_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[4] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_1100_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[4] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_1100_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[4] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_1100_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[4] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_1100_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[4] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_1100_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[4] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_1100_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[4] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_1100_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[4] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_1101_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[4] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_1101_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[4] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_1101_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[4] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_1101_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[4] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_1101_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[4] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_1101_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[4] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_1101_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[4] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_1101_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[4] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_1101_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[4] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_1101_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[4] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_1101_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[4] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_1101_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[4] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_1101_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[4] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_1101_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[4] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_1101_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[4] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_1101_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[4] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_1110_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[4] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_1110_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[4] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_1110_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[4] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_1110_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[4] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_1110_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[4] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_1110_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[4] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_1110_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[4] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_1110_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[4] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_1110_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[4] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_1110_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[4] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_1110_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[4] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_1110_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[4] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_1110_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[4] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_1110_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[4] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_1110_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[4] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_1110_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[4] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_1111_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[4] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_1111_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[4] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_1111_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[4] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_1111_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[4] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_1111_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[4] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_1111_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[4] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_1111_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[4] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_1111_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[4] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_1111_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[4] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_1111_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[4] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_1111_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[4] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_1111_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[4] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_1111_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[4] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_1111_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[4] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_1111_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[4] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_1111_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[4] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_0000_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[5] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_0000_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[5] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_0000_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[5] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_0000_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[5] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_0000_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[5] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_0000_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[5] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_0000_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[5] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_0000_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[5] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_0000_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[5] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_0000_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[5] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_0000_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[5] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_0000_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[5] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_0000_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[5] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_0000_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[5] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_0000_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[5] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_0000_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[5] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_0001_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[5] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_0001_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[5] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_0001_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[5] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_0001_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[5] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_0001_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[5] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_0001_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[5] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_0001_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[5] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_0001_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[5] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_0001_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[5] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_0001_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[5] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_0001_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[5] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_0001_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[5] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_0001_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[5] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_0001_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[5] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_0001_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[5] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_0001_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[5] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_0010_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[5] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_0010_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[5] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_0010_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[5] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_0010_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[5] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_0010_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[5] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_0010_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[5] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_0010_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[5] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_0010_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[5] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_0010_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[5] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_0010_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[5] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_0010_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[5] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_0010_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[5] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_0010_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[5] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_0010_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[5] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_0010_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[5] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_0010_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[5] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_0011_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[5] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_0011_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[5] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_0011_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[5] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_0011_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[5] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_0011_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[5] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_0011_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[5] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_0011_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[5] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_0011_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[5] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_0011_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[5] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_0011_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[5] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_0011_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[5] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_0011_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[5] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_0011_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[5] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_0011_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[5] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_0011_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[5] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_0011_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[5] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_0100_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[5] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_0100_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[5] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_0100_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[5] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_0100_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[5] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_0100_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[5] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_0100_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[5] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_0100_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[5] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_0100_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[5] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_0100_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[5] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_0100_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[5] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_0100_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[5] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_0100_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[5] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_0100_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[5] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_0100_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[5] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_0100_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[5] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_0100_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[5] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_0101_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[5] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_0101_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[5] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_0101_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[5] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_0101_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[5] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_0101_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[5] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_0101_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[5] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_0101_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[5] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_0101_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[5] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_0101_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[5] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_0101_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[5] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_0101_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[5] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_0101_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[5] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_0101_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[5] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_0101_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[5] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_0101_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[5] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_0101_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[5] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_0110_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[5] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_0110_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[5] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_0110_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[5] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_0110_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[5] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_0110_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[5] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_0110_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[5] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_0110_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[5] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_0110_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[5] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_0110_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[5] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_0110_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[5] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_0110_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[5] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_0110_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[5] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_0110_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[5] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_0110_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[5] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_0110_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[5] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_0110_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[5] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_0111_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[5] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_0111_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[5] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_0111_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[5] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_0111_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[5] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_0111_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[5] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_0111_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[5] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_0111_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[5] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_0111_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[5] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_0111_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[5] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_0111_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[5] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_0111_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[5] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_0111_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[5] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_0111_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[5] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_0111_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[5] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_0111_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[5] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_0111_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[5] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_1000_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[5] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_1000_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[5] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_1000_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[5] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_1000_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[5] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_1000_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[5] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_1000_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[5] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_1000_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[5] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_1000_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[5] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_1000_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[5] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_1000_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[5] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_1000_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[5] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_1000_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[5] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_1000_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[5] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_1000_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[5] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_1000_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[5] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_1000_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[5] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_1001_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[5] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_1001_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[5] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_1001_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[5] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_1001_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[5] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_1001_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[5] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_1001_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[5] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_1001_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[5] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_1001_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[5] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_1001_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[5] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_1001_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[5] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_1001_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[5] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_1001_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[5] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_1001_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[5] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_1001_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[5] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_1001_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[5] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_1001_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[5] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_1010_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[5] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_1010_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[5] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_1010_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[5] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_1010_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[5] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_1010_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[5] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_1010_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[5] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_1010_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[5] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_1010_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[5] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_1010_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[5] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_1010_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[5] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_1010_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[5] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_1010_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[5] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_1010_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[5] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_1010_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[5] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_1010_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[5] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_1010_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[5] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_1011_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[5] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_1011_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[5] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_1011_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[5] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_1011_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[5] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_1011_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[5] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_1011_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[5] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_1011_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[5] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_1011_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[5] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_1011_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[5] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_1011_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[5] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_1011_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[5] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_1011_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[5] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_1011_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[5] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_1011_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[5] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_1011_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[5] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_1011_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[5] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_1100_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[5] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_1100_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[5] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_1100_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[5] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_1100_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[5] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_1100_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[5] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_1100_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[5] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_1100_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[5] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_1100_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[5] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_1100_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[5] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_1100_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[5] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_1100_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[5] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_1100_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[5] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_1100_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[5] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_1100_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[5] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_1100_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[5] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_1100_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[5] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_1101_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[5] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_1101_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[5] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_1101_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[5] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_1101_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[5] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_1101_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[5] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_1101_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[5] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_1101_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[5] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_1101_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[5] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_1101_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[5] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_1101_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[5] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_1101_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[5] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_1101_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[5] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_1101_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[5] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_1101_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[5] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_1101_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[5] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_1101_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[5] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_1110_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[5] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_1110_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[5] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_1110_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[5] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_1110_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[5] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_1110_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[5] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_1110_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[5] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_1110_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[5] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_1110_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[5] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_1110_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[5] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_1110_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[5] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_1110_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[5] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_1110_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[5] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_1110_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[5] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_1110_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[5] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_1110_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[5] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_1110_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[5] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_1111_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[5] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_1111_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[5] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_1111_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[5] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_1111_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[5] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_1111_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[5] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_1111_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[5] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_1111_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[5] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_1111_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[5] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_1111_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[5] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_1111_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[5] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_1111_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[5] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_1111_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[5] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_1111_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[5] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_1111_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[5] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_1111_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[5] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_1111_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[5] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_0000_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[6] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_0000_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[6] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_0000_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[6] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_0000_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[6] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_0000_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[6] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_0000_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[6] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_0000_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[6] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_0000_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[6] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_0000_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[6] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_0000_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[6] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_0000_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[6] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_0000_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[6] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_0000_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[6] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_0000_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[6] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_0000_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[6] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_0000_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[6] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_0001_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[6] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_0001_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[6] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_0001_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[6] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_0001_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[6] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_0001_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[6] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_0001_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[6] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_0001_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[6] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_0001_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[6] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_0001_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[6] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_0001_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[6] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_0001_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[6] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_0001_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[6] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_0001_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[6] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_0001_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[6] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_0001_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[6] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_0001_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[6] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_0010_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[6] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_0010_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[6] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_0010_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[6] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_0010_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[6] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_0010_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[6] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_0010_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[6] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_0010_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[6] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_0010_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[6] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_0010_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[6] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_0010_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[6] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_0010_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[6] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_0010_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[6] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_0010_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[6] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_0010_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[6] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_0010_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[6] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_0010_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[6] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_0011_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[6] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_0011_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[6] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_0011_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[6] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_0011_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[6] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_0011_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[6] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_0011_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[6] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_0011_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[6] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_0011_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[6] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_0011_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[6] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_0011_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[6] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_0011_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[6] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_0011_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[6] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_0011_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[6] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_0011_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[6] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_0011_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[6] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_0011_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[6] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_0100_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[6] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_0100_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[6] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_0100_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[6] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_0100_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[6] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_0100_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[6] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_0100_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[6] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_0100_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[6] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_0100_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[6] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_0100_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[6] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_0100_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[6] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_0100_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[6] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_0100_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[6] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_0100_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[6] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_0100_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[6] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_0100_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[6] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_0100_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[6] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_0101_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[6] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_0101_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[6] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_0101_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[6] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_0101_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[6] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_0101_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[6] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_0101_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[6] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_0101_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[6] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_0101_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[6] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_0101_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[6] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_0101_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[6] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_0101_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[6] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_0101_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[6] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_0101_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[6] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_0101_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[6] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_0101_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[6] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_0101_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[6] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_0110_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[6] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_0110_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[6] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_0110_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[6] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_0110_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[6] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_0110_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[6] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_0110_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[6] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_0110_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[6] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_0110_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[6] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_0110_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[6] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_0110_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[6] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_0110_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[6] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_0110_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[6] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_0110_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[6] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_0110_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[6] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_0110_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[6] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_0110_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[6] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_0111_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[6] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_0111_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[6] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_0111_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[6] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_0111_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[6] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_0111_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[6] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_0111_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[6] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_0111_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[6] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_0111_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[6] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_0111_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[6] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_0111_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[6] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_0111_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[6] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_0111_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[6] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_0111_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[6] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_0111_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[6] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_0111_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[6] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_0111_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[6] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_1000_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[6] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_1000_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[6] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_1000_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[6] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_1000_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[6] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_1000_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[6] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_1000_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[6] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_1000_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[6] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_1000_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[6] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_1000_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[6] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_1000_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[6] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_1000_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[6] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_1000_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[6] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_1000_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[6] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_1000_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[6] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_1000_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[6] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_1000_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[6] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_1001_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[6] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_1001_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[6] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_1001_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[6] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_1001_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[6] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_1001_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[6] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_1001_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[6] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_1001_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[6] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_1001_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[6] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_1001_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[6] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_1001_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[6] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_1001_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[6] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_1001_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[6] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_1001_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[6] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_1001_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[6] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_1001_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[6] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_1001_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[6] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_1010_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[6] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_1010_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[6] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_1010_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[6] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_1010_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[6] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_1010_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[6] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_1010_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[6] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_1010_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[6] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_1010_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[6] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_1010_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[6] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_1010_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[6] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_1010_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[6] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_1010_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[6] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_1010_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[6] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_1010_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[6] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_1010_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[6] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_1010_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[6] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_1011_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[6] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_1011_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[6] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_1011_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[6] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_1011_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[6] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_1011_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[6] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_1011_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[6] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_1011_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[6] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_1011_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[6] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_1011_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[6] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_1011_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[6] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_1011_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[6] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_1011_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[6] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_1011_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[6] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_1011_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[6] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_1011_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[6] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_1011_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[6] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_1100_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[6] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_1100_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[6] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_1100_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[6] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_1100_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[6] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_1100_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[6] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_1100_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[6] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_1100_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[6] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_1100_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[6] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_1100_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[6] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_1100_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[6] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_1100_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[6] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_1100_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[6] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_1100_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[6] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_1100_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[6] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_1100_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[6] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_1100_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[6] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_1101_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[6] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_1101_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[6] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_1101_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[6] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_1101_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[6] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_1101_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[6] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_1101_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[6] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_1101_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[6] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_1101_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[6] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_1101_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[6] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_1101_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[6] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_1101_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[6] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_1101_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[6] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_1101_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[6] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_1101_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[6] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_1101_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[6] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_1101_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[6] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_1110_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[6] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_1110_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[6] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_1110_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[6] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_1110_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[6] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_1110_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[6] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_1110_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[6] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_1110_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[6] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_1110_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[6] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_1110_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[6] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_1110_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[6] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_1110_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[6] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_1110_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[6] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_1110_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[6] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_1110_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[6] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_1110_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[6] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_1110_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[6] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_1111_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[6] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_1111_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[6] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_1111_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[6] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_1111_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[6] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_1111_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[6] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_1111_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[6] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_1111_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[6] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_1111_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[6] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_1111_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[6] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_1111_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[6] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_1111_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[6] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_1111_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[6] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_1111_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[6] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_1111_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[6] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_1111_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[6] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_1111_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[6] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_0000_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[7] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_0000_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[7] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_0000_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[7] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_0000_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[7] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_0000_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[7] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_0000_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[7] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_0000_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[7] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_0000_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[7] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_0000_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[7] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_0000_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[7] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_0000_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[7] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_0000_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[7] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_0000_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[7] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_0000_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[7] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_0000_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[7] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_0000_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[7] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_0001_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[7] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_0001_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[7] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_0001_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[7] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_0001_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[7] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_0001_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[7] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_0001_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[7] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_0001_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[7] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_0001_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[7] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_0001_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[7] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_0001_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[7] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_0001_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[7] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_0001_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[7] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_0001_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[7] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_0001_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[7] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_0001_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[7] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_0001_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[7] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_0010_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[7] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_0010_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[7] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_0010_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[7] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_0010_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[7] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_0010_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[7] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_0010_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[7] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_0010_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[7] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_0010_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[7] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_0010_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[7] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_0010_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[7] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_0010_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[7] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_0010_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[7] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_0010_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[7] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_0010_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[7] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_0010_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[7] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_0010_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[7] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_0011_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[7] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_0011_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[7] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_0011_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[7] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_0011_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[7] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_0011_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[7] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_0011_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[7] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_0011_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[7] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_0011_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[7] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_0011_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[7] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_0011_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[7] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_0011_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[7] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_0011_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[7] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_0011_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[7] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_0011_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[7] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_0011_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[7] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_0011_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[7] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_0100_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[7] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_0100_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[7] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_0100_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[7] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_0100_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[7] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_0100_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[7] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_0100_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[7] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_0100_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[7] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_0100_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[7] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_0100_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[7] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_0100_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[7] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_0100_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[7] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_0100_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[7] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_0100_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[7] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_0100_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[7] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_0100_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[7] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_0100_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[7] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_0101_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[7] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_0101_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[7] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_0101_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[7] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_0101_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[7] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_0101_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[7] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_0101_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[7] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_0101_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[7] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_0101_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[7] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_0101_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[7] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_0101_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[7] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_0101_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[7] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_0101_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[7] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_0101_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[7] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_0101_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[7] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_0101_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[7] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_0101_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[7] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_0110_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[7] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_0110_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[7] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_0110_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[7] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_0110_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[7] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_0110_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[7] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_0110_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[7] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_0110_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[7] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_0110_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[7] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_0110_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[7] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_0110_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[7] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_0110_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[7] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_0110_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[7] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_0110_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[7] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_0110_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[7] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_0110_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[7] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_0110_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[7] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_0111_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[7] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_0111_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[7] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_0111_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[7] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_0111_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[7] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_0111_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[7] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_0111_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[7] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_0111_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[7] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_0111_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[7] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_0111_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[7] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_0111_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[7] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_0111_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[7] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_0111_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[7] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_0111_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[7] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_0111_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[7] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_0111_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[7] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_0111_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[7] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_1000_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[7] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_1000_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[7] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_1000_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[7] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_1000_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[7] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_1000_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[7] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_1000_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[7] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_1000_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[7] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_1000_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[7] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_1000_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[7] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_1000_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[7] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_1000_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[7] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_1000_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[7] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_1000_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[7] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_1000_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[7] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_1000_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[7] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_1000_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[7] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_1001_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[7] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_1001_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[7] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_1001_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[7] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_1001_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[7] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_1001_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[7] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_1001_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[7] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_1001_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[7] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_1001_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[7] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_1001_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[7] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_1001_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[7] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_1001_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[7] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_1001_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[7] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_1001_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[7] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_1001_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[7] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_1001_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[7] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_1001_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[7] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_1010_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[7] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_1010_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[7] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_1010_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[7] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_1010_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[7] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_1010_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[7] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_1010_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[7] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_1010_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[7] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_1010_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[7] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_1010_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[7] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_1010_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[7] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_1010_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[7] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_1010_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[7] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_1010_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[7] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_1010_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[7] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_1010_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[7] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_1010_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[7] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_1011_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[7] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_1011_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[7] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_1011_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[7] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_1011_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[7] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_1011_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[7] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_1011_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[7] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_1011_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[7] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_1011_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[7] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_1011_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[7] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_1011_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[7] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_1011_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[7] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_1011_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[7] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_1011_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[7] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_1011_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[7] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_1011_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[7] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_1011_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[7] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_1100_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[7] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_1100_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[7] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_1100_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[7] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_1100_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[7] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_1100_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[7] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_1100_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[7] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_1100_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[7] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_1100_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[7] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_1100_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[7] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_1100_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[7] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_1100_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[7] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_1100_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[7] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_1100_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[7] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_1100_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[7] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_1100_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[7] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_1100_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[7] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_1101_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[7] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_1101_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[7] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_1101_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[7] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_1101_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[7] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_1101_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[7] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_1101_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[7] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_1101_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[7] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_1101_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[7] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_1101_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[7] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_1101_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[7] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_1101_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[7] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_1101_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[7] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_1101_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[7] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_1101_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[7] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_1101_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[7] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_1101_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[7] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_1110_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[7] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_1110_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[7] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_1110_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[7] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_1110_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[7] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_1110_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[7] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_1110_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[7] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_1110_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[7] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_1110_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[7] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_1110_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[7] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_1110_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[7] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_1110_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[7] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_1110_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[7] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_1110_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[7] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_1110_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[7] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_1110_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[7] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_1110_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[7] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_1111_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[7] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_1111_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[7] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_1111_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[7] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_1111_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[7] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_1111_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[7] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_1111_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[7] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_1111_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[7] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_1111_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[7] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_1111_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[7] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_1111_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[7] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_1111_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[7] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_1111_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[7] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_1111_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[7] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_1111_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[7] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_1111_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[7] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_1111_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[7] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_0000_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[8] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_0000_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[8] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_0000_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[8] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_0000_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[8] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_0000_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[8] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_0000_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[8] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_0000_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[8] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_0000_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[8] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_0000_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[8] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_0000_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[8] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_0000_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[8] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_0000_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[8] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_0000_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[8] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_0000_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[8] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_0000_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[8] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_0000_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[8] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_0001_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[8] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_0001_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[8] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_0001_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[8] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_0001_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[8] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_0001_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[8] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_0001_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[8] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_0001_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[8] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_0001_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[8] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_0001_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[8] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_0001_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[8] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_0001_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[8] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_0001_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[8] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_0001_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[8] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_0001_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[8] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_0001_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[8] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_0001_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[8] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_0010_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[8] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_0010_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[8] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_0010_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[8] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_0010_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[8] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_0010_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[8] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_0010_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[8] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_0010_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[8] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_0010_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[8] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_0010_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[8] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_0010_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[8] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_0010_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[8] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_0010_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[8] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_0010_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[8] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_0010_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[8] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_0010_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[8] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_0010_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[8] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_0011_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[8] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_0011_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[8] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_0011_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[8] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_0011_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[8] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_0011_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[8] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_0011_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[8] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_0011_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[8] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_0011_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[8] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_0011_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[8] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_0011_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[8] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_0011_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[8] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_0011_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[8] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_0011_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[8] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_0011_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[8] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_0011_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[8] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_0011_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[8] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_0100_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[8] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_0100_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[8] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_0100_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[8] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_0100_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[8] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_0100_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[8] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_0100_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[8] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_0100_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[8] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_0100_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[8] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_0100_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[8] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_0100_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[8] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_0100_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[8] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_0100_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[8] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_0100_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[8] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_0100_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[8] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_0100_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[8] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_0100_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[8] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_0101_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[8] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_0101_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[8] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_0101_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[8] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_0101_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[8] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_0101_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[8] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_0101_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[8] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_0101_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[8] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_0101_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[8] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_0101_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[8] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_0101_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[8] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_0101_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[8] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_0101_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[8] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_0101_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[8] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_0101_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[8] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_0101_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[8] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_0101_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[8] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_0110_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[8] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_0110_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[8] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_0110_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[8] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_0110_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[8] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_0110_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[8] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_0110_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[8] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_0110_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[8] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_0110_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[8] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_0110_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[8] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_0110_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[8] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_0110_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[8] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_0110_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[8] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_0110_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[8] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_0110_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[8] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_0110_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[8] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_0110_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[8] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_0111_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[8] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_0111_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[8] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_0111_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[8] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_0111_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[8] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_0111_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[8] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_0111_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[8] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_0111_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[8] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_0111_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[8] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_0111_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[8] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_0111_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[8] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_0111_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[8] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_0111_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[8] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_0111_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[8] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_0111_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[8] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_0111_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[8] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_0111_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[8] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_1000_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[8] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_1000_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[8] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_1000_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[8] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_1000_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[8] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_1000_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[8] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_1000_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[8] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_1000_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[8] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_1000_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[8] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_1000_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[8] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_1000_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[8] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_1000_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[8] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_1000_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[8] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_1000_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[8] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_1000_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[8] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_1000_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[8] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_1000_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[8] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_1001_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[8] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_1001_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[8] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_1001_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[8] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_1001_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[8] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_1001_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[8] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_1001_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[8] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_1001_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[8] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_1001_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[8] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_1001_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[8] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_1001_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[8] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_1001_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[8] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_1001_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[8] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_1001_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[8] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_1001_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[8] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_1001_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[8] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_1001_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[8] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_1010_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[8] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_1010_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[8] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_1010_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[8] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_1010_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[8] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_1010_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[8] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_1010_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[8] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_1010_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[8] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_1010_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[8] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_1010_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[8] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_1010_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[8] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_1010_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[8] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_1010_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[8] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_1010_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[8] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_1010_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[8] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_1010_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[8] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_1010_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[8] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_1011_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[8] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_1011_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[8] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_1011_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[8] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_1011_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[8] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_1011_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[8] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_1011_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[8] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_1011_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[8] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_1011_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[8] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_1011_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[8] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_1011_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[8] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_1011_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[8] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_1011_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[8] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_1011_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[8] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_1011_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[8] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_1011_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[8] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_1011_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[8] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_1100_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[8] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_1100_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[8] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_1100_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[8] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_1100_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[8] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_1100_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[8] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_1100_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[8] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_1100_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[8] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_1100_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[8] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_1100_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[8] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_1100_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[8] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_1100_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[8] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_1100_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[8] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_1100_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[8] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_1100_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[8] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_1100_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[8] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_1100_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[8] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_1101_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[8] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_1101_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[8] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_1101_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[8] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_1101_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[8] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_1101_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[8] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_1101_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[8] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_1101_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[8] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_1101_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[8] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_1101_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[8] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_1101_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[8] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_1101_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[8] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_1101_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[8] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_1101_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[8] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_1101_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[8] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_1101_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[8] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_1101_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[8] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_1110_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[8] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_1110_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[8] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_1110_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[8] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_1110_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[8] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_1110_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[8] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_1110_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[8] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_1110_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[8] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_1110_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[8] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_1110_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[8] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_1110_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[8] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_1110_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[8] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_1110_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[8] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_1110_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[8] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_1110_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[8] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_1110_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[8] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_1110_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[8] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_1111_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[8] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_1111_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[8] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_1111_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[8] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_1111_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[8] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_1111_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[8] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_1111_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[8] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_1111_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[8] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_1111_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[8] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_1111_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[8] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_1111_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[8] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_1111_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[8] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_1111_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[8] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_1111_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[8] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_1111_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[8] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_1111_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[8] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_1111_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[8] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_0000_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[9] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_0000_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[9] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_0000_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[9] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_0000_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[9] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_0000_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[9] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_0000_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[9] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_0000_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[9] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_0000_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[9] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_0000_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[9] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_0000_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[9] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_0000_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[9] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_0000_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[9] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_0000_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[9] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_0000_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[9] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_0000_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[9] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_0000_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[9] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_0001_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[9] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_0001_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[9] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_0001_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[9] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_0001_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[9] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_0001_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[9] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_0001_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[9] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_0001_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[9] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_0001_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[9] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_0001_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[9] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_0001_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[9] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_0001_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[9] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_0001_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[9] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_0001_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[9] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_0001_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[9] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_0001_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[9] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_0001_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[9] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_0010_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[9] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_0010_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[9] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_0010_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[9] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_0010_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[9] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_0010_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[9] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_0010_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[9] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_0010_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[9] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_0010_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[9] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_0010_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[9] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_0010_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[9] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_0010_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[9] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_0010_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[9] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_0010_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[9] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_0010_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[9] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_0010_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[9] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_0010_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[9] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_0011_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[9] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_0011_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[9] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_0011_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[9] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_0011_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[9] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_0011_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[9] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_0011_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[9] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_0011_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[9] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_0011_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[9] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_0011_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[9] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_0011_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[9] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_0011_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[9] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_0011_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[9] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_0011_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[9] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_0011_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[9] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_0011_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[9] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_0011_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[9] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_0100_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[9] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_0100_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[9] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_0100_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[9] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_0100_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[9] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_0100_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[9] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_0100_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[9] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_0100_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[9] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_0100_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[9] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_0100_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[9] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_0100_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[9] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_0100_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[9] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_0100_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[9] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_0100_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[9] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_0100_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[9] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_0100_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[9] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_0100_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[9] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_0101_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[9] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_0101_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[9] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_0101_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[9] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_0101_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[9] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_0101_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[9] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_0101_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[9] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_0101_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[9] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_0101_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[9] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_0101_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[9] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_0101_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[9] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_0101_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[9] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_0101_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[9] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_0101_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[9] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_0101_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[9] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_0101_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[9] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_0101_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[9] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_0110_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[9] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_0110_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[9] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_0110_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[9] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_0110_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[9] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_0110_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[9] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_0110_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[9] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_0110_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[9] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_0110_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[9] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_0110_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[9] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_0110_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[9] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_0110_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[9] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_0110_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[9] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_0110_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[9] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_0110_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[9] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_0110_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[9] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_0110_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[9] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_0111_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[9] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_0111_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[9] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_0111_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[9] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_0111_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[9] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_0111_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[9] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_0111_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[9] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_0111_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[9] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_0111_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[9] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_0111_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[9] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_0111_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[9] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_0111_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[9] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_0111_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[9] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_0111_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[9] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_0111_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[9] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_0111_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[9] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_0111_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[9] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_1000_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[9] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_1000_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[9] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_1000_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[9] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_1000_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[9] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_1000_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[9] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_1000_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[9] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_1000_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[9] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_1000_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[9] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_1000_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[9] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_1000_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[9] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_1000_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[9] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_1000_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[9] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_1000_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[9] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_1000_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[9] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_1000_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[9] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_1000_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[9] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_1001_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[9] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_1001_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[9] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_1001_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[9] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_1001_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[9] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_1001_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[9] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_1001_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[9] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_1001_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[9] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_1001_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[9] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_1001_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[9] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_1001_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[9] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_1001_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[9] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_1001_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[9] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_1001_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[9] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_1001_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[9] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_1001_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[9] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_1001_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[9] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_1010_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[9] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_1010_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[9] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_1010_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[9] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_1010_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[9] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_1010_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[9] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_1010_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[9] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_1010_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[9] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_1010_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[9] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_1010_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[9] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_1010_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[9] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_1010_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[9] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_1010_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[9] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_1010_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[9] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_1010_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[9] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_1010_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[9] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_1010_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[9] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_1011_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[9] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_1011_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[9] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_1011_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[9] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_1011_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[9] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_1011_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[9] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_1011_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[9] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_1011_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[9] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_1011_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[9] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_1011_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[9] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_1011_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[9] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_1011_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[9] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_1011_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[9] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_1011_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[9] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_1011_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[9] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_1011_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[9] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_1011_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[9] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_1100_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[9] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_1100_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[9] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_1100_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[9] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_1100_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[9] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_1100_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[9] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_1100_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[9] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_1100_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[9] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_1100_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[9] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_1100_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[9] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_1100_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[9] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_1100_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[9] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_1100_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[9] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_1100_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[9] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_1100_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[9] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_1100_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[9] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_1100_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[9] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_1101_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[9] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_1101_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[9] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_1101_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[9] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_1101_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[9] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_1101_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[9] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_1101_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[9] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_1101_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[9] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_1101_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[9] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_1101_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[9] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_1101_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[9] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_1101_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[9] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_1101_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[9] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_1101_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[9] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_1101_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[9] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_1101_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[9] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_1101_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[9] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_1110_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[9] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_1110_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[9] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_1110_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[9] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_1110_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[9] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_1110_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[9] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_1110_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[9] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_1110_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[9] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_1110_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[9] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_1110_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[9] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_1110_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[9] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_1110_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[9] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_1110_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[9] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_1110_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[9] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_1110_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[9] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_1110_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[9] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_1110_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[9] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_1111_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[9] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_1111_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[9] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_1111_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[9] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_1111_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[9] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_1111_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[9] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_1111_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[9] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_1111_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[9] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_1111_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[9] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_1111_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[9] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_1111_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[9] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_1111_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[9] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_1111_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[9] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_1111_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[9] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_1111_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[9] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_1111_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[9] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_1111_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[9] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_0000_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[10] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_0000_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[10] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_0000_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[10] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_0000_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[10] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_0000_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[10] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_0000_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[10] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_0000_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[10] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_0000_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[10] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_0000_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[10] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_0000_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[10] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_0000_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[10] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_0000_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[10] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_0000_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[10] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_0000_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[10] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_0000_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[10] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_0000_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[10] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_0001_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[10] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_0001_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[10] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_0001_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[10] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_0001_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[10] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_0001_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[10] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_0001_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[10] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_0001_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[10] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_0001_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[10] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_0001_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[10] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_0001_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[10] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_0001_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[10] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_0001_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[10] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_0001_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[10] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_0001_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[10] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_0001_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[10] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_0001_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[10] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_0010_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[10] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_0010_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[10] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_0010_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[10] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_0010_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[10] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_0010_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[10] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_0010_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[10] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_0010_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[10] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_0010_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[10] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_0010_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[10] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_0010_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[10] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_0010_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[10] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_0010_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[10] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_0010_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[10] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_0010_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[10] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_0010_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[10] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_0010_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[10] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_0011_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[10] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_0011_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[10] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_0011_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[10] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_0011_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[10] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_0011_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[10] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_0011_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[10] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_0011_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[10] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_0011_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[10] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_0011_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[10] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_0011_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[10] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_0011_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[10] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_0011_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[10] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_0011_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[10] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_0011_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[10] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_0011_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[10] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_0011_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[10] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_0100_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[10] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_0100_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[10] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_0100_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[10] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_0100_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[10] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_0100_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[10] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_0100_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[10] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_0100_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[10] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_0100_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[10] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_0100_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[10] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_0100_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[10] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_0100_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[10] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_0100_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[10] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_0100_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[10] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_0100_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[10] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_0100_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[10] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_0100_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[10] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_0101_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[10] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_0101_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[10] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_0101_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[10] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_0101_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[10] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_0101_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[10] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_0101_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[10] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_0101_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[10] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_0101_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[10] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_0101_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[10] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_0101_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[10] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_0101_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[10] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_0101_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[10] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_0101_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[10] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_0101_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[10] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_0101_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[10] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_0101_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[10] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_0110_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[10] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_0110_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[10] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_0110_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[10] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_0110_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[10] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_0110_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[10] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_0110_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[10] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_0110_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[10] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_0110_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[10] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_0110_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[10] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_0110_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[10] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_0110_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[10] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_0110_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[10] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_0110_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[10] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_0110_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[10] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_0110_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[10] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_0110_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[10] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_0111_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[10] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_0111_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[10] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_0111_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[10] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_0111_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[10] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_0111_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[10] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_0111_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[10] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_0111_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[10] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_0111_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[10] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_0111_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[10] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_0111_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[10] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_0111_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[10] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_0111_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[10] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_0111_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[10] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_0111_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[10] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_0111_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[10] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_0111_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[10] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_1000_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[10] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_1000_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[10] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_1000_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[10] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_1000_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[10] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_1000_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[10] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_1000_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[10] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_1000_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[10] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_1000_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[10] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_1000_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[10] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_1000_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[10] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_1000_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[10] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_1000_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[10] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_1000_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[10] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_1000_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[10] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_1000_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[10] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_1000_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[10] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_1001_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[10] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_1001_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[10] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_1001_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[10] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_1001_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[10] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_1001_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[10] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_1001_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[10] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_1001_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[10] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_1001_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[10] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_1001_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[10] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_1001_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[10] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_1001_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[10] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_1001_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[10] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_1001_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[10] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_1001_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[10] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_1001_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[10] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_1001_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[10] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_1010_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[10] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_1010_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[10] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_1010_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[10] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_1010_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[10] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_1010_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[10] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_1010_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[10] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_1010_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[10] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_1010_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[10] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_1010_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[10] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_1010_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[10] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_1010_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[10] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_1010_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[10] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_1010_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[10] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_1010_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[10] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_1010_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[10] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_1010_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[10] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_1011_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[10] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_1011_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[10] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_1011_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[10] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_1011_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[10] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_1011_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[10] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_1011_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[10] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_1011_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[10] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_1011_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[10] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_1011_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[10] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_1011_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[10] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_1011_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[10] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_1011_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[10] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_1011_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[10] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_1011_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[10] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_1011_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[10] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_1011_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[10] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_1100_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[10] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_1100_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[10] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_1100_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[10] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_1100_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[10] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_1100_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[10] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_1100_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[10] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_1100_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[10] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_1100_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[10] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_1100_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[10] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_1100_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[10] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_1100_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[10] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_1100_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[10] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_1100_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[10] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_1100_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[10] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_1100_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[10] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_1100_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[10] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_1101_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[10] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_1101_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[10] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_1101_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[10] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_1101_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[10] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_1101_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[10] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_1101_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[10] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_1101_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[10] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_1101_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[10] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_1101_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[10] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_1101_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[10] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_1101_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[10] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_1101_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[10] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_1101_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[10] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_1101_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[10] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_1101_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[10] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_1101_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[10] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_1110_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[10] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_1110_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[10] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_1110_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[10] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_1110_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[10] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_1110_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[10] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_1110_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[10] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_1110_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[10] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_1110_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[10] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_1110_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[10] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_1110_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[10] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_1110_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[10] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_1110_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[10] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_1110_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[10] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_1110_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[10] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_1110_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[10] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_1110_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[10] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_1111_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[10] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_1111_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[10] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_1111_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[10] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_1111_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[10] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_1111_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[10] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_1111_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[10] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_1111_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[10] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_1111_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[10] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_1111_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[10] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_1111_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[10] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_1111_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[10] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_1111_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[10] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_1111_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[10] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_1111_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[10] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_1111_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[10] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_1111_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[10] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_0000_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[11] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_0000_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[11] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_0000_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[11] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_0000_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[11] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_0000_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[11] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_0000_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[11] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_0000_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[11] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_0000_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[11] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_0000_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[11] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_0000_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[11] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_0000_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[11] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_0000_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[11] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_0000_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[11] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_0000_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[11] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_0000_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[11] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_0000_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[11] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_0001_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[11] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_0001_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[11] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_0001_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[11] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_0001_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[11] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_0001_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[11] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_0001_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[11] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_0001_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[11] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_0001_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[11] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_0001_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[11] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_0001_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[11] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_0001_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[11] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_0001_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[11] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_0001_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[11] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_0001_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[11] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_0001_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[11] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_0001_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[11] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_0010_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[11] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_0010_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[11] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_0010_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[11] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_0010_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[11] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_0010_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[11] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_0010_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[11] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_0010_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[11] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_0010_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[11] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_0010_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[11] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_0010_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[11] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_0010_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[11] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_0010_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[11] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_0010_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[11] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_0010_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[11] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_0010_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[11] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_0010_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[11] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_0011_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[11] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_0011_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[11] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_0011_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[11] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_0011_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[11] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_0011_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[11] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_0011_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[11] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_0011_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[11] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_0011_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[11] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_0011_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[11] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_0011_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[11] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_0011_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[11] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_0011_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[11] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_0011_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[11] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_0011_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[11] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_0011_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[11] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_0011_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[11] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_0100_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[11] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_0100_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[11] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_0100_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[11] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_0100_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[11] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_0100_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[11] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_0100_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[11] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_0100_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[11] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_0100_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[11] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_0100_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[11] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_0100_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[11] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_0100_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[11] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_0100_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[11] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_0100_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[11] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_0100_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[11] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_0100_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[11] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_0100_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[11] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_0101_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[11] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_0101_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[11] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_0101_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[11] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_0101_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[11] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_0101_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[11] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_0101_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[11] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_0101_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[11] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_0101_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[11] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_0101_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[11] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_0101_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[11] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_0101_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[11] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_0101_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[11] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_0101_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[11] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_0101_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[11] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_0101_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[11] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_0101_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[11] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_0110_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[11] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_0110_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[11] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_0110_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[11] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_0110_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[11] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_0110_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[11] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_0110_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[11] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_0110_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[11] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_0110_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[11] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_0110_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[11] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_0110_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[11] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_0110_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[11] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_0110_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[11] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_0110_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[11] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_0110_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[11] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_0110_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[11] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_0110_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[11] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_0111_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[11] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_0111_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[11] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_0111_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[11] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_0111_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[11] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_0111_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[11] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_0111_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[11] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_0111_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[11] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_0111_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[11] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_0111_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[11] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_0111_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[11] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_0111_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[11] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_0111_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[11] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_0111_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[11] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_0111_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[11] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_0111_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[11] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_0111_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[11] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_1000_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[11] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_1000_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[11] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_1000_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[11] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_1000_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[11] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_1000_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[11] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_1000_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[11] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_1000_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[11] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_1000_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[11] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_1000_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[11] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_1000_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[11] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_1000_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[11] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_1000_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[11] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_1000_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[11] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_1000_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[11] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_1000_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[11] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_1000_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[11] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_1001_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[11] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_1001_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[11] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_1001_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[11] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_1001_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[11] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_1001_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[11] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_1001_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[11] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_1001_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[11] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_1001_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[11] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_1001_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[11] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_1001_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[11] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_1001_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[11] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_1001_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[11] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_1001_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[11] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_1001_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[11] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_1001_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[11] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_1001_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[11] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_1010_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[11] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_1010_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[11] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_1010_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[11] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_1010_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[11] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_1010_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[11] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_1010_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[11] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_1010_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[11] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_1010_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[11] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_1010_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[11] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_1010_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[11] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_1010_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[11] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_1010_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[11] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_1010_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[11] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_1010_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[11] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_1010_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[11] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_1010_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[11] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_1011_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[11] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_1011_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[11] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_1011_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[11] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_1011_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[11] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_1011_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[11] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_1011_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[11] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_1011_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[11] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_1011_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[11] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_1011_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[11] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_1011_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[11] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_1011_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[11] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_1011_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[11] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_1011_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[11] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_1011_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[11] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_1011_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[11] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_1011_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[11] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_1100_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[11] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_1100_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[11] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_1100_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[11] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_1100_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[11] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_1100_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[11] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_1100_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[11] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_1100_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[11] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_1100_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[11] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_1100_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[11] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_1100_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[11] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_1100_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[11] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_1100_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[11] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_1100_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[11] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_1100_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[11] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_1100_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[11] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_1100_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[11] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_1101_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[11] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_1101_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[11] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_1101_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[11] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_1101_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[11] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_1101_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[11] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_1101_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[11] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_1101_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[11] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_1101_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[11] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_1101_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[11] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_1101_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[11] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_1101_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[11] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_1101_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[11] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_1101_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[11] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_1101_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[11] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_1101_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[11] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_1101_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[11] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_1110_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[11] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_1110_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[11] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_1110_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[11] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_1110_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[11] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_1110_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[11] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_1110_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[11] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_1110_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[11] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_1110_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[11] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_1110_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[11] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_1110_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[11] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_1110_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[11] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_1110_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[11] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_1110_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[11] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_1110_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[11] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_1110_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[11] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_1110_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[11] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_1111_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[11] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_1111_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[11] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_1111_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[11] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_1111_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[11] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_1111_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[11] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_1111_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[11] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_1111_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[11] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_1111_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[11] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_1111_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[11] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_1111_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[11] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_1111_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[11] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_1111_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[11] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_1111_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[11] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_1111_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[11] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_1111_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[11] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_1111_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[11] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_0000_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[12] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_0000_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[12] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_0000_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[12] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_0000_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[12] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_0000_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[12] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_0000_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[12] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_0000_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[12] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_0000_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[12] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_0000_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[12] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_0000_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[12] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_0000_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[12] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_0000_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[12] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_0000_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[12] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_0000_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[12] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_0000_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[12] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_0000_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[12] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_0001_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[12] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_0001_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[12] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_0001_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[12] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_0001_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[12] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_0001_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[12] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_0001_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[12] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_0001_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[12] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_0001_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[12] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_0001_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[12] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_0001_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[12] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_0001_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[12] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_0001_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[12] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_0001_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[12] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_0001_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[12] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_0001_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[12] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_0001_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[12] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_0010_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[12] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_0010_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[12] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_0010_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[12] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_0010_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[12] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_0010_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[12] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_0010_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[12] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_0010_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[12] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_0010_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[12] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_0010_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[12] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_0010_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[12] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_0010_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[12] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_0010_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[12] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_0010_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[12] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_0010_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[12] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_0010_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[12] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_0010_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[12] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_0011_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[12] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_0011_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[12] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_0011_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[12] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_0011_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[12] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_0011_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[12] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_0011_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[12] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_0011_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[12] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_0011_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[12] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_0011_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[12] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_0011_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[12] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_0011_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[12] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_0011_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[12] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_0011_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[12] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_0011_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[12] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_0011_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[12] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_0011_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[12] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_0100_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[12] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_0100_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[12] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_0100_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[12] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_0100_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[12] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_0100_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[12] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_0100_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[12] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_0100_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[12] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_0100_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[12] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_0100_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[12] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_0100_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[12] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_0100_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[12] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_0100_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[12] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_0100_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[12] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_0100_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[12] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_0100_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[12] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_0100_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[12] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_0101_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[12] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_0101_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[12] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_0101_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[12] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_0101_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[12] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_0101_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[12] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_0101_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[12] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_0101_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[12] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_0101_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[12] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_0101_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[12] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_0101_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[12] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_0101_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[12] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_0101_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[12] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_0101_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[12] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_0101_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[12] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_0101_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[12] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_0101_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[12] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_0110_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[12] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_0110_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[12] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_0110_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[12] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_0110_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[12] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_0110_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[12] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_0110_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[12] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_0110_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[12] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_0110_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[12] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_0110_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[12] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_0110_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[12] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_0110_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[12] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_0110_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[12] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_0110_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[12] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_0110_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[12] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_0110_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[12] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_0110_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[12] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_0111_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[12] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_0111_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[12] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_0111_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[12] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_0111_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[12] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_0111_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[12] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_0111_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[12] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_0111_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[12] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_0111_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[12] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_0111_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[12] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_0111_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[12] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_0111_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[12] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_0111_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[12] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_0111_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[12] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_0111_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[12] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_0111_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[12] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_0111_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[12] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_1000_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[12] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_1000_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[12] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_1000_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[12] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_1000_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[12] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_1000_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[12] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_1000_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[12] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_1000_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[12] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_1000_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[12] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_1000_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[12] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_1000_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[12] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_1000_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[12] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_1000_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[12] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_1000_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[12] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_1000_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[12] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_1000_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[12] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_1000_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[12] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_1001_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[12] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_1001_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[12] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_1001_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[12] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_1001_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[12] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_1001_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[12] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_1001_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[12] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_1001_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[12] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_1001_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[12] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_1001_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[12] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_1001_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[12] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_1001_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[12] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_1001_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[12] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_1001_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[12] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_1001_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[12] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_1001_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[12] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_1001_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[12] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_1010_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[12] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_1010_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[12] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_1010_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[12] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_1010_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[12] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_1010_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[12] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_1010_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[12] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_1010_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[12] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_1010_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[12] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_1010_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[12] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_1010_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[12] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_1010_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[12] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_1010_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[12] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_1010_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[12] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_1010_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[12] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_1010_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[12] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_1010_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[12] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_1011_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[12] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_1011_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[12] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_1011_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[12] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_1011_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[12] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_1011_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[12] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_1011_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[12] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_1011_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[12] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_1011_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[12] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_1011_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[12] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_1011_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[12] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_1011_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[12] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_1011_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[12] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_1011_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[12] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_1011_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[12] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_1011_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[12] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_1011_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[12] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_1100_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[12] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_1100_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[12] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_1100_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[12] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_1100_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[12] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_1100_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[12] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_1100_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[12] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_1100_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[12] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_1100_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[12] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_1100_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[12] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_1100_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[12] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_1100_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[12] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_1100_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[12] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_1100_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[12] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_1100_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[12] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_1100_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[12] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_1100_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[12] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_1101_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[12] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_1101_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[12] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_1101_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[12] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_1101_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[12] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_1101_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[12] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_1101_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[12] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_1101_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[12] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_1101_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[12] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_1101_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[12] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_1101_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[12] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_1101_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[12] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_1101_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[12] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_1101_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[12] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_1101_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[12] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_1101_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[12] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_1101_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[12] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_1110_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[12] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_1110_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[12] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_1110_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[12] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_1110_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[12] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_1110_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[12] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_1110_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[12] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_1110_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[12] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_1110_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[12] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_1110_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[12] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_1110_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[12] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_1110_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[12] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_1110_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[12] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_1110_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[12] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_1110_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[12] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_1110_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[12] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_1110_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[12] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_1111_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[12] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_1111_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[12] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_1111_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[12] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_1111_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[12] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_1111_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[12] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_1111_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[12] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_1111_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[12] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_1111_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[12] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_1111_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[12] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_1111_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[12] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_1111_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[12] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_1111_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[12] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_1111_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[12] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_1111_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[12] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_1111_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[12] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_1111_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[12] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_0000_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[13] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_0000_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[13] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_0000_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[13] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_0000_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[13] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_0000_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[13] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_0000_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[13] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_0000_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[13] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_0000_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[13] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_0000_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[13] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_0000_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[13] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_0000_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[13] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_0000_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[13] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_0000_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[13] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_0000_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[13] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_0000_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[13] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_0000_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[13] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_0001_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[13] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_0001_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[13] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_0001_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[13] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_0001_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[13] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_0001_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[13] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_0001_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[13] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_0001_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[13] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_0001_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[13] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_0001_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[13] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_0001_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[13] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_0001_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[13] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_0001_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[13] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_0001_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[13] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_0001_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[13] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_0001_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[13] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_0001_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[13] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_0010_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[13] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_0010_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[13] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_0010_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[13] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_0010_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[13] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_0010_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[13] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_0010_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[13] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_0010_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[13] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_0010_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[13] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_0010_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[13] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_0010_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[13] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_0010_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[13] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_0010_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[13] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_0010_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[13] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_0010_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[13] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_0010_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[13] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_0010_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[13] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_0011_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[13] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_0011_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[13] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_0011_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[13] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_0011_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[13] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_0011_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[13] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_0011_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[13] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_0011_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[13] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_0011_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[13] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_0011_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[13] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_0011_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[13] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_0011_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[13] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_0011_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[13] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_0011_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[13] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_0011_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[13] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_0011_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[13] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_0011_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[13] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_0100_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[13] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_0100_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[13] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_0100_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[13] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_0100_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[13] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_0100_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[13] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_0100_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[13] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_0100_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[13] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_0100_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[13] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_0100_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[13] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_0100_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[13] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_0100_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[13] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_0100_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[13] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_0100_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[13] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_0100_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[13] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_0100_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[13] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_0100_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[13] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_0101_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[13] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_0101_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[13] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_0101_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[13] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_0101_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[13] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_0101_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[13] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_0101_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[13] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_0101_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[13] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_0101_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[13] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_0101_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[13] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_0101_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[13] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_0101_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[13] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_0101_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[13] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_0101_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[13] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_0101_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[13] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_0101_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[13] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_0101_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[13] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_0110_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[13] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_0110_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[13] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_0110_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[13] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_0110_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[13] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_0110_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[13] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_0110_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[13] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_0110_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[13] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_0110_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[13] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_0110_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[13] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_0110_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[13] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_0110_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[13] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_0110_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[13] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_0110_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[13] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_0110_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[13] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_0110_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[13] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_0110_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[13] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_0111_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[13] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_0111_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[13] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_0111_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[13] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_0111_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[13] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_0111_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[13] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_0111_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[13] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_0111_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[13] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_0111_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[13] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_0111_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[13] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_0111_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[13] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_0111_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[13] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_0111_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[13] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_0111_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[13] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_0111_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[13] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_0111_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[13] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_0111_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[13] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_1000_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[13] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_1000_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[13] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_1000_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[13] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_1000_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[13] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_1000_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[13] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_1000_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[13] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_1000_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[13] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_1000_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[13] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_1000_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[13] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_1000_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[13] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_1000_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[13] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_1000_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[13] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_1000_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[13] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_1000_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[13] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_1000_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[13] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_1000_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[13] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_1001_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[13] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_1001_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[13] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_1001_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[13] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_1001_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[13] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_1001_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[13] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_1001_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[13] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_1001_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[13] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_1001_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[13] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_1001_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[13] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_1001_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[13] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_1001_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[13] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_1001_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[13] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_1001_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[13] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_1001_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[13] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_1001_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[13] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_1001_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[13] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_1010_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[13] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_1010_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[13] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_1010_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[13] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_1010_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[13] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_1010_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[13] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_1010_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[13] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_1010_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[13] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_1010_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[13] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_1010_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[13] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_1010_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[13] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_1010_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[13] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_1010_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[13] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_1010_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[13] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_1010_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[13] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_1010_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[13] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_1010_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[13] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_1011_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[13] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_1011_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[13] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_1011_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[13] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_1011_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[13] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_1011_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[13] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_1011_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[13] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_1011_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[13] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_1011_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[13] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_1011_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[13] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_1011_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[13] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_1011_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[13] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_1011_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[13] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_1011_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[13] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_1011_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[13] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_1011_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[13] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_1011_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[13] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_1100_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[13] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_1100_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[13] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_1100_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[13] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_1100_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[13] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_1100_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[13] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_1100_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[13] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_1100_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[13] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_1100_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[13] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_1100_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[13] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_1100_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[13] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_1100_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[13] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_1100_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[13] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_1100_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[13] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_1100_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[13] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_1100_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[13] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_1100_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[13] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_1101_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[13] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_1101_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[13] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_1101_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[13] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_1101_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[13] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_1101_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[13] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_1101_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[13] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_1101_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[13] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_1101_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[13] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_1101_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[13] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_1101_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[13] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_1101_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[13] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_1101_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[13] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_1101_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[13] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_1101_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[13] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_1101_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[13] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_1101_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[13] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_1110_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[13] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_1110_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[13] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_1110_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[13] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_1110_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[13] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_1110_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[13] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_1110_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[13] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_1110_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[13] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_1110_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[13] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_1110_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[13] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_1110_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[13] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_1110_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[13] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_1110_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[13] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_1110_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[13] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_1110_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[13] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_1110_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[13] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_1110_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[13] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_1111_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[13] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_1111_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[13] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_1111_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[13] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_1111_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[13] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_1111_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[13] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_1111_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[13] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_1111_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[13] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_1111_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[13] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_1111_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[13] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_1111_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[13] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_1111_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[13] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_1111_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[13] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_1111_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[13] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_1111_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[13] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_1111_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[13] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_1111_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[13] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_0000_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[14] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_0000_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[14] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_0000_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[14] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_0000_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[14] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_0000_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[14] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_0000_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[14] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_0000_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[14] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_0000_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[14] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_0000_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[14] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_0000_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[14] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_0000_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[14] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_0000_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[14] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_0000_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[14] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_0000_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[14] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_0000_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[14] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_0000_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[14] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_0001_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[14] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_0001_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[14] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_0001_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[14] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_0001_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[14] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_0001_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[14] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_0001_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[14] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_0001_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[14] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_0001_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[14] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_0001_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[14] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_0001_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[14] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_0001_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[14] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_0001_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[14] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_0001_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[14] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_0001_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[14] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_0001_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[14] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_0001_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[14] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_0010_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[14] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_0010_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[14] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_0010_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[14] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_0010_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[14] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_0010_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[14] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_0010_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[14] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_0010_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[14] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_0010_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[14] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_0010_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[14] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_0010_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[14] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_0010_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[14] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_0010_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[14] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_0010_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[14] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_0010_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[14] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_0010_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[14] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_0010_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[14] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_0011_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[14] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_0011_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[14] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_0011_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[14] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_0011_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[14] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_0011_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[14] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_0011_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[14] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_0011_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[14] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_0011_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[14] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_0011_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[14] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_0011_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[14] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_0011_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[14] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_0011_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[14] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_0011_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[14] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_0011_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[14] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_0011_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[14] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_0011_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[14] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_0100_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[14] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_0100_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[14] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_0100_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[14] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_0100_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[14] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_0100_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[14] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_0100_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[14] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_0100_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[14] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_0100_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[14] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_0100_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[14] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_0100_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[14] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_0100_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[14] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_0100_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[14] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_0100_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[14] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_0100_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[14] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_0100_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[14] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_0100_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[14] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_0101_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[14] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_0101_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[14] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_0101_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[14] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_0101_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[14] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_0101_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[14] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_0101_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[14] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_0101_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[14] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_0101_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[14] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_0101_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[14] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_0101_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[14] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_0101_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[14] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_0101_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[14] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_0101_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[14] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_0101_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[14] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_0101_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[14] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_0101_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[14] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_0110_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[14] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_0110_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[14] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_0110_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[14] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_0110_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[14] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_0110_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[14] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_0110_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[14] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_0110_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[14] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_0110_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[14] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_0110_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[14] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_0110_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[14] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_0110_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[14] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_0110_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[14] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_0110_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[14] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_0110_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[14] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_0110_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[14] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_0110_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[14] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_0111_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[14] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_0111_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[14] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_0111_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[14] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_0111_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[14] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_0111_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[14] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_0111_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[14] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_0111_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[14] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_0111_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[14] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_0111_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[14] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_0111_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[14] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_0111_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[14] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_0111_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[14] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_0111_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[14] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_0111_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[14] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_0111_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[14] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_0111_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[14] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_1000_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[14] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_1000_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[14] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_1000_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[14] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_1000_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[14] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_1000_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[14] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_1000_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[14] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_1000_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[14] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_1000_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[14] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_1000_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[14] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_1000_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[14] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_1000_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[14] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_1000_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[14] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_1000_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[14] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_1000_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[14] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_1000_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[14] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_1000_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[14] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_1001_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[14] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_1001_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[14] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_1001_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[14] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_1001_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[14] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_1001_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[14] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_1001_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[14] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_1001_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[14] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_1001_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[14] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_1001_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[14] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_1001_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[14] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_1001_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[14] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_1001_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[14] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_1001_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[14] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_1001_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[14] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_1001_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[14] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_1001_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[14] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_1010_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[14] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_1010_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[14] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_1010_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[14] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_1010_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[14] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_1010_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[14] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_1010_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[14] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_1010_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[14] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_1010_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[14] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_1010_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[14] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_1010_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[14] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_1010_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[14] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_1010_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[14] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_1010_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[14] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_1010_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[14] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_1010_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[14] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_1010_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[14] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_1011_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[14] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_1011_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[14] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_1011_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[14] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_1011_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[14] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_1011_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[14] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_1011_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[14] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_1011_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[14] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_1011_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[14] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_1011_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[14] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_1011_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[14] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_1011_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[14] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_1011_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[14] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_1011_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[14] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_1011_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[14] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_1011_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[14] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_1011_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[14] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_1100_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[14] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_1100_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[14] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_1100_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[14] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_1100_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[14] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_1100_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[14] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_1100_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[14] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_1100_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[14] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_1100_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[14] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_1100_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[14] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_1100_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[14] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_1100_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[14] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_1100_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[14] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_1100_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[14] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_1100_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[14] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_1100_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[14] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_1100_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[14] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_1101_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[14] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_1101_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[14] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_1101_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[14] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_1101_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[14] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_1101_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[14] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_1101_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[14] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_1101_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[14] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_1101_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[14] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_1101_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[14] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_1101_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[14] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_1101_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[14] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_1101_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[14] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_1101_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[14] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_1101_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[14] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_1101_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[14] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_1101_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[14] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_1110_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[14] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_1110_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[14] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_1110_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[14] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_1110_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[14] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_1110_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[14] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_1110_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[14] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_1110_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[14] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_1110_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[14] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_1110_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[14] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_1110_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[14] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_1110_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[14] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_1110_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[14] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_1110_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[14] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_1110_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[14] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_1110_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[14] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_1110_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[14] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_1111_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[14] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_1111_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[14] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_1111_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[14] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_1111_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[14] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_1111_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[14] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_1111_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[14] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_1111_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[14] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_1111_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[14] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_1111_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[14] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_1111_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[14] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_1111_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[14] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_1111_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[14] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_1111_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[14] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_1111_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[14] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_1111_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[14] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_1111_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[14] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_0000_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[15] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_0000_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[15] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_0000_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[15] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_0000_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[15] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_0000_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[15] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_0000_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[15] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_0000_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[15] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_0000_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[15] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_0000_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[15] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_0000_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[15] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_0000_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[15] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_0000_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[15] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_0000_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[15] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_0000_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[15] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_0000_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[15] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_0000_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[15] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_0001_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[15] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_0001_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[15] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_0001_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[15] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_0001_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[15] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_0001_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[15] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_0001_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[15] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_0001_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[15] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_0001_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[15] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_0001_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[15] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_0001_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[15] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_0001_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[15] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_0001_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[15] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_0001_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[15] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_0001_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[15] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_0001_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[15] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_0001_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[15] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_0010_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[15] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_0010_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[15] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_0010_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[15] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_0010_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[15] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_0010_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[15] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_0010_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[15] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_0010_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[15] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_0010_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[15] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_0010_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[15] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_0010_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[15] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_0010_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[15] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_0010_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[15] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_0010_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[15] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_0010_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[15] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_0010_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[15] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_0010_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[15] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_0011_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[15] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_0011_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[15] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_0011_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[15] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_0011_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[15] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_0011_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[15] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_0011_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[15] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_0011_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[15] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_0011_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[15] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_0011_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[15] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_0011_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[15] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_0011_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[15] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_0011_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[15] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_0011_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[15] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_0011_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[15] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_0011_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[15] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_0011_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[15] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_0100_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[15] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_0100_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[15] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_0100_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[15] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_0100_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[15] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_0100_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[15] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_0100_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[15] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_0100_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[15] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_0100_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[15] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_0100_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[15] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_0100_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[15] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_0100_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[15] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_0100_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[15] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_0100_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[15] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_0100_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[15] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_0100_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[15] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_0100_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[15] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_0101_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[15] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_0101_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[15] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_0101_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[15] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_0101_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[15] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_0101_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[15] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_0101_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[15] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_0101_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[15] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_0101_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[15] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_0101_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[15] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_0101_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[15] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_0101_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[15] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_0101_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[15] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_0101_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[15] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_0101_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[15] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_0101_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[15] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_0101_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[15] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_0110_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[15] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_0110_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[15] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_0110_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[15] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_0110_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[15] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_0110_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[15] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_0110_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[15] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_0110_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[15] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_0110_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[15] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_0110_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[15] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_0110_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[15] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_0110_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[15] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_0110_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[15] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_0110_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[15] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_0110_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[15] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_0110_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[15] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_0110_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[15] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_0111_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[15] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_0111_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[15] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_0111_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[15] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_0111_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[15] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_0111_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[15] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_0111_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[15] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_0111_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[15] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_0111_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[15] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_0111_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[15] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_0111_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[15] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_0111_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[15] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_0111_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[15] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_0111_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[15] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_0111_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[15] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_0111_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[15] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_0111_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[15] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_1000_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[15] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_1000_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[15] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_1000_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[15] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_1000_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[15] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_1000_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[15] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_1000_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[15] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_1000_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[15] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_1000_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[15] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_1000_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[15] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_1000_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[15] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_1000_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[15] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_1000_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[15] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_1000_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[15] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_1000_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[15] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_1000_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[15] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_1000_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[15] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_1001_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[15] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_1001_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[15] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_1001_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[15] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_1001_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[15] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_1001_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[15] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_1001_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[15] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_1001_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[15] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_1001_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[15] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_1001_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[15] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_1001_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[15] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_1001_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[15] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_1001_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[15] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_1001_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[15] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_1001_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[15] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_1001_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[15] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_1001_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[15] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_1010_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[15] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_1010_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[15] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_1010_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[15] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_1010_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[15] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_1010_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[15] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_1010_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[15] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_1010_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[15] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_1010_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[15] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_1010_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[15] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_1010_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[15] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_1010_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[15] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_1010_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[15] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_1010_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[15] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_1010_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[15] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_1010_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[15] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_1010_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[15] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_1011_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[15] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_1011_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[15] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_1011_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[15] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_1011_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[15] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_1011_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[15] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_1011_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[15] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_1011_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[15] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_1011_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[15] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_1011_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[15] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_1011_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[15] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_1011_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[15] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_1011_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[15] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_1011_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[15] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_1011_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[15] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_1011_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[15] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_1011_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[15] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_1100_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[15] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_1100_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[15] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_1100_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[15] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_1100_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[15] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_1100_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[15] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_1100_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[15] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_1100_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[15] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_1100_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[15] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_1100_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[15] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_1100_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[15] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_1100_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[15] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_1100_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[15] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_1100_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[15] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_1100_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[15] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_1100_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[15] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_1100_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[15] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_1101_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[15] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_1101_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[15] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_1101_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[15] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_1101_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[15] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_1101_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[15] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_1101_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[15] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_1101_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[15] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_1101_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[15] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_1101_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[15] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_1101_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[15] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_1101_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[15] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_1101_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[15] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_1101_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[15] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_1101_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[15] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_1101_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[15] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_1101_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[15] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_1110_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[15] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_1110_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[15] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_1110_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[15] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_1110_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[15] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_1110_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[15] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_1110_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[15] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_1110_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[15] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_1110_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[15] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_1110_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[15] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_1110_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[15] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_1110_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[15] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_1110_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[15] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_1110_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[15] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_1110_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[15] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_1110_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[15] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_1110_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[15] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0000_M_1111_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[15] + 0;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0001_M_1111_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[15] + 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0010_M_1111_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[15] + 8;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0011_M_1111_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[15] + 12;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0100_M_1111_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[15] + 16;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0101_M_1111_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[15] + 20;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0110_M_1111_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[15] + 24;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_0111_M_1111_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[15] + 28;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1000_M_1111_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 32;
	context->scratch2 = context->gpr[15] + 32;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1001_M_1111_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 36;
	context->scratch2 = context->gpr[15] + 36;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1010_M_1111_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 40;
	context->scratch2 = context->gpr[15] + 40;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1011_M_1111_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 44;
	context->scratch2 = context->gpr[15] + 44;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1100_M_1111_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 48;
	context->scratch2 = context->gpr[15] + 48;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1101_M_1111_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 52;
	context->scratch2 = context->gpr[15] + 52;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1110_M_1111_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 56;
	context->scratch2 = context->gpr[15] + 56;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_disp_rn_l_D_1111_M_1111_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 60;
	context->scratch2 = context->gpr[15] + 60;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_0000_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[0] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[0], context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_0000_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[0] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[0], context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_0000_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[0] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[0], context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_0000_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->gpr[0] = context->gpr[0] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_0000_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->gpr[0] = context->gpr[0] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_0000_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->gpr[0] = context->gpr[0] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_0000_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[0] >> 31;
	context->m = context->gpr[0] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_0000_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[0] & context->gpr[0];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_0000_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[0] = context->gpr[0] & context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_0000_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[0] = context->gpr[0] ^ context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_0000_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[0] = context->gpr[0] | context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_0000_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[0] ^ context->gpr[0];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_0000_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] << 16;
	context->gpr[0] = context->gpr[0] >> 16;
	context->gpr[0] = context->scratch1 | context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_0000_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[0] & 65535)) * ((uint32_t)(context->gpr[0] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_0000_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[0])) * ((int32_t)((int16_t)context->gpr[0])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_0001_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[0] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[0], context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_0001_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[0] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[0], context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_0001_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[0] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[0], context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_0001_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->gpr[0] = context->gpr[0] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_0001_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->gpr[0] = context->gpr[0] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_0001_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->gpr[0] = context->gpr[0] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_0001_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[0] >> 31;
	context->m = context->gpr[1] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_0001_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[0] & context->gpr[1];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_0001_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[0] = context->gpr[1] & context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_0001_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[0] = context->gpr[1] ^ context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_0001_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[0] = context->gpr[1] | context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_0001_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[1] ^ context->gpr[0];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_0001_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[1] << 16;
	context->gpr[0] = context->gpr[0] >> 16;
	context->gpr[0] = context->scratch1 | context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_0001_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[0] & 65535)) * ((uint32_t)(context->gpr[1] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_0001_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[0])) * ((int32_t)((int16_t)context->gpr[1])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_0010_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[0] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[0], context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_0010_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[0] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[0], context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_0010_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[0] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[0], context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_0010_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->gpr[0] = context->gpr[0] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_0010_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->gpr[0] = context->gpr[0] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_0010_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->gpr[0] = context->gpr[0] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_0010_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[0] >> 31;
	context->m = context->gpr[2] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_0010_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[0] & context->gpr[2];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_0010_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[0] = context->gpr[2] & context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_0010_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[0] = context->gpr[2] ^ context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_0010_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[0] = context->gpr[2] | context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_0010_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[2] ^ context->gpr[0];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_0010_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[2] << 16;
	context->gpr[0] = context->gpr[0] >> 16;
	context->gpr[0] = context->scratch1 | context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_0010_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[0] & 65535)) * ((uint32_t)(context->gpr[2] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_0010_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[0])) * ((int32_t)((int16_t)context->gpr[2])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_0011_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[0] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[0], context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_0011_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[0] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[0], context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_0011_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[0] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[0], context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_0011_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->gpr[0] = context->gpr[0] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_0011_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->gpr[0] = context->gpr[0] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_0011_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->gpr[0] = context->gpr[0] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_0011_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[0] >> 31;
	context->m = context->gpr[3] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_0011_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[0] & context->gpr[3];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_0011_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[0] = context->gpr[3] & context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_0011_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[0] = context->gpr[3] ^ context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_0011_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[0] = context->gpr[3] | context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_0011_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[3] ^ context->gpr[0];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_0011_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[3] << 16;
	context->gpr[0] = context->gpr[0] >> 16;
	context->gpr[0] = context->scratch1 | context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_0011_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[0] & 65535)) * ((uint32_t)(context->gpr[3] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_0011_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[0])) * ((int32_t)((int16_t)context->gpr[3])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_0100_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[0] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[0], context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_0100_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[0] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[0], context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_0100_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[0] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[0], context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_0100_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->gpr[0] = context->gpr[0] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_0100_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->gpr[0] = context->gpr[0] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_0100_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->gpr[0] = context->gpr[0] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_0100_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[0] >> 31;
	context->m = context->gpr[4] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_0100_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[0] & context->gpr[4];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_0100_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[0] = context->gpr[4] & context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_0100_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[0] = context->gpr[4] ^ context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_0100_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[0] = context->gpr[4] | context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_0100_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[4] ^ context->gpr[0];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_0100_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[4] << 16;
	context->gpr[0] = context->gpr[0] >> 16;
	context->gpr[0] = context->scratch1 | context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_0100_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[0] & 65535)) * ((uint32_t)(context->gpr[4] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_0100_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[0])) * ((int32_t)((int16_t)context->gpr[4])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_0101_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[0] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[0], context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_0101_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[0] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[0], context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_0101_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[0] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[0], context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_0101_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->gpr[0] = context->gpr[0] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_0101_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->gpr[0] = context->gpr[0] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_0101_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->gpr[0] = context->gpr[0] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_0101_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[0] >> 31;
	context->m = context->gpr[5] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_0101_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[0] & context->gpr[5];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_0101_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[0] = context->gpr[5] & context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_0101_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[0] = context->gpr[5] ^ context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_0101_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[0] = context->gpr[5] | context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_0101_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[5] ^ context->gpr[0];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_0101_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[5] << 16;
	context->gpr[0] = context->gpr[0] >> 16;
	context->gpr[0] = context->scratch1 | context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_0101_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[0] & 65535)) * ((uint32_t)(context->gpr[5] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_0101_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[0])) * ((int32_t)((int16_t)context->gpr[5])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_0110_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[0] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[0], context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_0110_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[0] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[0], context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_0110_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[0] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[0], context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_0110_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->gpr[0] = context->gpr[0] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_0110_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->gpr[0] = context->gpr[0] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_0110_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->gpr[0] = context->gpr[0] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_0110_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[0] >> 31;
	context->m = context->gpr[6] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_0110_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[0] & context->gpr[6];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_0110_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[0] = context->gpr[6] & context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_0110_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[0] = context->gpr[6] ^ context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_0110_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[0] = context->gpr[6] | context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_0110_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[6] ^ context->gpr[0];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_0110_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[6] << 16;
	context->gpr[0] = context->gpr[0] >> 16;
	context->gpr[0] = context->scratch1 | context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_0110_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[0] & 65535)) * ((uint32_t)(context->gpr[6] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_0110_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[0])) * ((int32_t)((int16_t)context->gpr[6])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_0111_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[0] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[0], context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_0111_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[0] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[0], context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_0111_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[0] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[0], context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_0111_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->gpr[0] = context->gpr[0] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_0111_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->gpr[0] = context->gpr[0] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_0111_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->gpr[0] = context->gpr[0] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_0111_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[0] >> 31;
	context->m = context->gpr[7] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_0111_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[0] & context->gpr[7];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_0111_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[0] = context->gpr[7] & context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_0111_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[0] = context->gpr[7] ^ context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_0111_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[0] = context->gpr[7] | context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_0111_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[7] ^ context->gpr[0];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_0111_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[7] << 16;
	context->gpr[0] = context->gpr[0] >> 16;
	context->gpr[0] = context->scratch1 | context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_0111_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[0] & 65535)) * ((uint32_t)(context->gpr[7] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_0111_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[0])) * ((int32_t)((int16_t)context->gpr[7])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_1000_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[0] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[0], context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_1000_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[0] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[0], context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_1000_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[0] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[0], context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_1000_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->gpr[0] = context->gpr[0] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_1000_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->gpr[0] = context->gpr[0] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_1000_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->gpr[0] = context->gpr[0] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_1000_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[0] >> 31;
	context->m = context->gpr[8] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_1000_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[0] & context->gpr[8];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_1000_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[0] = context->gpr[8] & context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_1000_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[0] = context->gpr[8] ^ context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_1000_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[0] = context->gpr[8] | context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_1000_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[8] ^ context->gpr[0];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_1000_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[8] << 16;
	context->gpr[0] = context->gpr[0] >> 16;
	context->gpr[0] = context->scratch1 | context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_1000_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[0] & 65535)) * ((uint32_t)(context->gpr[8] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_1000_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[0])) * ((int32_t)((int16_t)context->gpr[8])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_1001_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[0] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[0], context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_1001_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[0] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[0], context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_1001_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[0] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[0], context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_1001_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->gpr[0] = context->gpr[0] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_1001_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->gpr[0] = context->gpr[0] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_1001_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->gpr[0] = context->gpr[0] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_1001_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[0] >> 31;
	context->m = context->gpr[9] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_1001_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[0] & context->gpr[9];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_1001_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[0] = context->gpr[9] & context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_1001_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[0] = context->gpr[9] ^ context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_1001_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[0] = context->gpr[9] | context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_1001_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[9] ^ context->gpr[0];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_1001_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[9] << 16;
	context->gpr[0] = context->gpr[0] >> 16;
	context->gpr[0] = context->scratch1 | context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_1001_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[0] & 65535)) * ((uint32_t)(context->gpr[9] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_1001_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[0])) * ((int32_t)((int16_t)context->gpr[9])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_1010_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[0] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[0], context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_1010_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[0] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[0], context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_1010_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[0] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[0], context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_1010_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->gpr[0] = context->gpr[0] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_1010_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->gpr[0] = context->gpr[0] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_1010_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->gpr[0] = context->gpr[0] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_1010_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[0] >> 31;
	context->m = context->gpr[10] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_1010_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[0] & context->gpr[10];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_1010_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[0] = context->gpr[10] & context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_1010_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[0] = context->gpr[10] ^ context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_1010_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[0] = context->gpr[10] | context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_1010_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[10] ^ context->gpr[0];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_1010_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[10] << 16;
	context->gpr[0] = context->gpr[0] >> 16;
	context->gpr[0] = context->scratch1 | context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_1010_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[0] & 65535)) * ((uint32_t)(context->gpr[10] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_1010_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[0])) * ((int32_t)((int16_t)context->gpr[10])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_1011_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[0] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[0], context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_1011_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[0] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[0], context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_1011_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[0] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[0], context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_1011_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->gpr[0] = context->gpr[0] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_1011_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->gpr[0] = context->gpr[0] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_1011_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->gpr[0] = context->gpr[0] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_1011_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[0] >> 31;
	context->m = context->gpr[11] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_1011_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[0] & context->gpr[11];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_1011_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[0] = context->gpr[11] & context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_1011_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[0] = context->gpr[11] ^ context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_1011_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[0] = context->gpr[11] | context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_1011_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[11] ^ context->gpr[0];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_1011_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[11] << 16;
	context->gpr[0] = context->gpr[0] >> 16;
	context->gpr[0] = context->scratch1 | context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_1011_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[0] & 65535)) * ((uint32_t)(context->gpr[11] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_1011_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[0])) * ((int32_t)((int16_t)context->gpr[11])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_1100_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[0] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[0], context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_1100_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[0] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[0], context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_1100_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[0] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[0], context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_1100_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->gpr[0] = context->gpr[0] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_1100_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->gpr[0] = context->gpr[0] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_1100_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->gpr[0] = context->gpr[0] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_1100_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[0] >> 31;
	context->m = context->gpr[12] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_1100_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[0] & context->gpr[12];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_1100_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[0] = context->gpr[12] & context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_1100_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[0] = context->gpr[12] ^ context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_1100_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[0] = context->gpr[12] | context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_1100_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[12] ^ context->gpr[0];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_1100_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[12] << 16;
	context->gpr[0] = context->gpr[0] >> 16;
	context->gpr[0] = context->scratch1 | context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_1100_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[0] & 65535)) * ((uint32_t)(context->gpr[12] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_1100_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[0])) * ((int32_t)((int16_t)context->gpr[12])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_1101_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[0] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[0], context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_1101_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[0] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[0], context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_1101_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[0] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[0], context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_1101_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->gpr[0] = context->gpr[0] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_1101_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->gpr[0] = context->gpr[0] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_1101_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->gpr[0] = context->gpr[0] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_1101_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[0] >> 31;
	context->m = context->gpr[13] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_1101_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[0] & context->gpr[13];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_1101_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[0] = context->gpr[13] & context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_1101_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[0] = context->gpr[13] ^ context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_1101_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[0] = context->gpr[13] | context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_1101_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[13] ^ context->gpr[0];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_1101_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[13] << 16;
	context->gpr[0] = context->gpr[0] >> 16;
	context->gpr[0] = context->scratch1 | context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_1101_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[0] & 65535)) * ((uint32_t)(context->gpr[13] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_1101_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[0])) * ((int32_t)((int16_t)context->gpr[13])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_1110_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[0] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[0], context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_1110_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[0] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[0], context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_1110_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[0] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[0], context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_1110_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->gpr[0] = context->gpr[0] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_1110_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->gpr[0] = context->gpr[0] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_1110_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->gpr[0] = context->gpr[0] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_1110_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[0] >> 31;
	context->m = context->gpr[14] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_1110_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[0] & context->gpr[14];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_1110_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[0] = context->gpr[14] & context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_1110_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[0] = context->gpr[14] ^ context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_1110_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[0] = context->gpr[14] | context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_1110_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[14] ^ context->gpr[0];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_1110_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[14] << 16;
	context->gpr[0] = context->gpr[0] >> 16;
	context->gpr[0] = context->scratch1 | context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_1110_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[0] & 65535)) * ((uint32_t)(context->gpr[14] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_1110_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[0])) * ((int32_t)((int16_t)context->gpr[14])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_1111_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[0] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[0], context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_1111_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[0] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[0], context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_1111_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[0] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[0], context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_1111_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->gpr[0] = context->gpr[0] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_1111_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->gpr[0] = context->gpr[0] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_1111_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->gpr[0] = context->gpr[0] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_1111_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[0] >> 31;
	context->m = context->gpr[15] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_1111_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[0] & context->gpr[15];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_1111_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[0] = context->gpr[15] & context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_1111_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[0] = context->gpr[15] ^ context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_1111_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[0] = context->gpr[15] | context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_1111_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[15] ^ context->gpr[0];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_1111_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[15] << 16;
	context->gpr[0] = context->gpr[0] >> 16;
	context->gpr[0] = context->scratch1 | context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_1111_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[0] & 65535)) * ((uint32_t)(context->gpr[15] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_1111_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[0])) * ((int32_t)((int16_t)context->gpr[15])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_0000_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[1] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[1], context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_0000_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[1] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[1], context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_0000_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[1] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[1], context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_0000_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[1] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->gpr[1] = context->gpr[1] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_0000_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[1] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->gpr[1] = context->gpr[1] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_0000_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[1] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->gpr[1] = context->gpr[1] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_0000_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[1] >> 31;
	context->m = context->gpr[0] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_0000_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[1] & context->gpr[0];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_0000_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[1] = context->gpr[0] & context->gpr[1];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_0000_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[1] = context->gpr[0] ^ context->gpr[1];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_0000_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[1] = context->gpr[0] | context->gpr[1];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_0000_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[0] ^ context->gpr[1];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_0000_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] << 16;
	context->gpr[1] = context->gpr[1] >> 16;
	context->gpr[1] = context->scratch1 | context->gpr[1];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_0000_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[1] & 65535)) * ((uint32_t)(context->gpr[0] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_0000_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[1])) * ((int32_t)((int16_t)context->gpr[0])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_0001_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[1] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[1], context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_0001_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[1] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[1], context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_0001_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[1] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[1], context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_0001_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[1] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->gpr[1] = context->gpr[1] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_0001_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[1] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->gpr[1] = context->gpr[1] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_0001_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[1] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->gpr[1] = context->gpr[1] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_0001_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[1] >> 31;
	context->m = context->gpr[1] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_0001_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[1] & context->gpr[1];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_0001_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[1] = context->gpr[1] & context->gpr[1];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_0001_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[1] = context->gpr[1] ^ context->gpr[1];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_0001_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[1] = context->gpr[1] | context->gpr[1];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_0001_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[1] ^ context->gpr[1];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_0001_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[1] << 16;
	context->gpr[1] = context->gpr[1] >> 16;
	context->gpr[1] = context->scratch1 | context->gpr[1];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_0001_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[1] & 65535)) * ((uint32_t)(context->gpr[1] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_0001_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[1])) * ((int32_t)((int16_t)context->gpr[1])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_0010_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[1] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[1], context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_0010_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[1] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[1], context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_0010_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[1] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[1], context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_0010_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[1] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->gpr[1] = context->gpr[1] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_0010_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[1] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->gpr[1] = context->gpr[1] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_0010_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[1] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->gpr[1] = context->gpr[1] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_0010_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[1] >> 31;
	context->m = context->gpr[2] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_0010_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[1] & context->gpr[2];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_0010_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[1] = context->gpr[2] & context->gpr[1];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_0010_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[1] = context->gpr[2] ^ context->gpr[1];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_0010_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[1] = context->gpr[2] | context->gpr[1];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_0010_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[2] ^ context->gpr[1];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_0010_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[2] << 16;
	context->gpr[1] = context->gpr[1] >> 16;
	context->gpr[1] = context->scratch1 | context->gpr[1];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_0010_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[1] & 65535)) * ((uint32_t)(context->gpr[2] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_0010_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[1])) * ((int32_t)((int16_t)context->gpr[2])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_0011_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[1] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[1], context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_0011_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[1] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[1], context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_0011_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[1] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[1], context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_0011_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[1] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->gpr[1] = context->gpr[1] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_0011_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[1] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->gpr[1] = context->gpr[1] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_0011_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[1] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->gpr[1] = context->gpr[1] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_0011_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[1] >> 31;
	context->m = context->gpr[3] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_0011_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[1] & context->gpr[3];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_0011_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[1] = context->gpr[3] & context->gpr[1];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_0011_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[1] = context->gpr[3] ^ context->gpr[1];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_0011_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[1] = context->gpr[3] | context->gpr[1];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_0011_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[3] ^ context->gpr[1];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_0011_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[3] << 16;
	context->gpr[1] = context->gpr[1] >> 16;
	context->gpr[1] = context->scratch1 | context->gpr[1];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_0011_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[1] & 65535)) * ((uint32_t)(context->gpr[3] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_0011_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[1])) * ((int32_t)((int16_t)context->gpr[3])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_0100_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[1] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[1], context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_0100_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[1] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[1], context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_0100_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[1] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[1], context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_0100_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[1] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->gpr[1] = context->gpr[1] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_0100_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[1] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->gpr[1] = context->gpr[1] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_0100_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[1] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->gpr[1] = context->gpr[1] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_0100_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[1] >> 31;
	context->m = context->gpr[4] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_0100_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[1] & context->gpr[4];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_0100_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[1] = context->gpr[4] & context->gpr[1];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_0100_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[1] = context->gpr[4] ^ context->gpr[1];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_0100_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[1] = context->gpr[4] | context->gpr[1];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_0100_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[4] ^ context->gpr[1];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_0100_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[4] << 16;
	context->gpr[1] = context->gpr[1] >> 16;
	context->gpr[1] = context->scratch1 | context->gpr[1];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_0100_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[1] & 65535)) * ((uint32_t)(context->gpr[4] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_0100_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[1])) * ((int32_t)((int16_t)context->gpr[4])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_0101_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[1] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[1], context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_0101_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[1] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[1], context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_0101_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[1] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[1], context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_0101_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[1] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->gpr[1] = context->gpr[1] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_0101_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[1] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->gpr[1] = context->gpr[1] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_0101_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[1] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->gpr[1] = context->gpr[1] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_0101_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[1] >> 31;
	context->m = context->gpr[5] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_0101_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[1] & context->gpr[5];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_0101_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[1] = context->gpr[5] & context->gpr[1];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_0101_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[1] = context->gpr[5] ^ context->gpr[1];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_0101_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[1] = context->gpr[5] | context->gpr[1];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_0101_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[5] ^ context->gpr[1];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_0101_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[5] << 16;
	context->gpr[1] = context->gpr[1] >> 16;
	context->gpr[1] = context->scratch1 | context->gpr[1];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_0101_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[1] & 65535)) * ((uint32_t)(context->gpr[5] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_0101_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[1])) * ((int32_t)((int16_t)context->gpr[5])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_0110_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[1] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[1], context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_0110_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[1] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[1], context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_0110_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[1] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[1], context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_0110_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[1] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->gpr[1] = context->gpr[1] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_0110_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[1] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->gpr[1] = context->gpr[1] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_0110_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[1] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->gpr[1] = context->gpr[1] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_0110_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[1] >> 31;
	context->m = context->gpr[6] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_0110_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[1] & context->gpr[6];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_0110_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[1] = context->gpr[6] & context->gpr[1];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_0110_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[1] = context->gpr[6] ^ context->gpr[1];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_0110_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[1] = context->gpr[6] | context->gpr[1];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_0110_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[6] ^ context->gpr[1];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_0110_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[6] << 16;
	context->gpr[1] = context->gpr[1] >> 16;
	context->gpr[1] = context->scratch1 | context->gpr[1];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_0110_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[1] & 65535)) * ((uint32_t)(context->gpr[6] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_0110_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[1])) * ((int32_t)((int16_t)context->gpr[6])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_0111_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[1] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[1], context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_0111_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[1] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[1], context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_0111_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[1] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[1], context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_0111_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[1] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->gpr[1] = context->gpr[1] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_0111_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[1] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->gpr[1] = context->gpr[1] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_0111_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[1] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->gpr[1] = context->gpr[1] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_0111_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[1] >> 31;
	context->m = context->gpr[7] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_0111_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[1] & context->gpr[7];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_0111_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[1] = context->gpr[7] & context->gpr[1];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_0111_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[1] = context->gpr[7] ^ context->gpr[1];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_0111_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[1] = context->gpr[7] | context->gpr[1];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_0111_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[7] ^ context->gpr[1];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_0111_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[7] << 16;
	context->gpr[1] = context->gpr[1] >> 16;
	context->gpr[1] = context->scratch1 | context->gpr[1];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_0111_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[1] & 65535)) * ((uint32_t)(context->gpr[7] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_0111_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[1])) * ((int32_t)((int16_t)context->gpr[7])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_1000_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[1] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[1], context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_1000_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[1] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[1], context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_1000_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[1] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[1], context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_1000_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[1] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->gpr[1] = context->gpr[1] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_1000_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[1] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->gpr[1] = context->gpr[1] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_1000_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[1] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->gpr[1] = context->gpr[1] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_1000_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[1] >> 31;
	context->m = context->gpr[8] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_1000_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[1] & context->gpr[8];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_1000_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[1] = context->gpr[8] & context->gpr[1];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_1000_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[1] = context->gpr[8] ^ context->gpr[1];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_1000_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[1] = context->gpr[8] | context->gpr[1];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_1000_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[8] ^ context->gpr[1];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_1000_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[8] << 16;
	context->gpr[1] = context->gpr[1] >> 16;
	context->gpr[1] = context->scratch1 | context->gpr[1];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_1000_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[1] & 65535)) * ((uint32_t)(context->gpr[8] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_1000_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[1])) * ((int32_t)((int16_t)context->gpr[8])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_1001_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[1] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[1], context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_1001_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[1] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[1], context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_1001_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[1] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[1], context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_1001_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[1] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->gpr[1] = context->gpr[1] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_1001_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[1] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->gpr[1] = context->gpr[1] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_1001_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[1] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->gpr[1] = context->gpr[1] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_1001_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[1] >> 31;
	context->m = context->gpr[9] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_1001_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[1] & context->gpr[9];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_1001_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[1] = context->gpr[9] & context->gpr[1];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_1001_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[1] = context->gpr[9] ^ context->gpr[1];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_1001_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[1] = context->gpr[9] | context->gpr[1];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_1001_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[9] ^ context->gpr[1];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_1001_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[9] << 16;
	context->gpr[1] = context->gpr[1] >> 16;
	context->gpr[1] = context->scratch1 | context->gpr[1];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_1001_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[1] & 65535)) * ((uint32_t)(context->gpr[9] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_1001_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[1])) * ((int32_t)((int16_t)context->gpr[9])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_1010_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[1] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[1], context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_1010_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[1] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[1], context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_1010_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[1] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[1], context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_1010_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[1] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->gpr[1] = context->gpr[1] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_1010_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[1] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->gpr[1] = context->gpr[1] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_1010_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[1] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->gpr[1] = context->gpr[1] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_1010_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[1] >> 31;
	context->m = context->gpr[10] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_1010_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[1] & context->gpr[10];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_1010_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[1] = context->gpr[10] & context->gpr[1];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_1010_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[1] = context->gpr[10] ^ context->gpr[1];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_1010_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[1] = context->gpr[10] | context->gpr[1];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_1010_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[10] ^ context->gpr[1];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_1010_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[10] << 16;
	context->gpr[1] = context->gpr[1] >> 16;
	context->gpr[1] = context->scratch1 | context->gpr[1];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_1010_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[1] & 65535)) * ((uint32_t)(context->gpr[10] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_1010_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[1])) * ((int32_t)((int16_t)context->gpr[10])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_1011_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[1] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[1], context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_1011_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[1] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[1], context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_1011_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[1] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[1], context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_1011_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[1] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->gpr[1] = context->gpr[1] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_1011_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[1] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->gpr[1] = context->gpr[1] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_1011_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[1] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->gpr[1] = context->gpr[1] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_1011_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[1] >> 31;
	context->m = context->gpr[11] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_1011_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[1] & context->gpr[11];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_1011_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[1] = context->gpr[11] & context->gpr[1];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_1011_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[1] = context->gpr[11] ^ context->gpr[1];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_1011_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[1] = context->gpr[11] | context->gpr[1];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_1011_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[11] ^ context->gpr[1];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_1011_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[11] << 16;
	context->gpr[1] = context->gpr[1] >> 16;
	context->gpr[1] = context->scratch1 | context->gpr[1];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_1011_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[1] & 65535)) * ((uint32_t)(context->gpr[11] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_1011_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[1])) * ((int32_t)((int16_t)context->gpr[11])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_1100_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[1] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[1], context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_1100_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[1] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[1], context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_1100_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[1] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[1], context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_1100_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[1] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->gpr[1] = context->gpr[1] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_1100_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[1] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->gpr[1] = context->gpr[1] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_1100_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[1] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->gpr[1] = context->gpr[1] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_1100_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[1] >> 31;
	context->m = context->gpr[12] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_1100_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[1] & context->gpr[12];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_1100_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[1] = context->gpr[12] & context->gpr[1];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_1100_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[1] = context->gpr[12] ^ context->gpr[1];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_1100_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[1] = context->gpr[12] | context->gpr[1];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_1100_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[12] ^ context->gpr[1];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_1100_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[12] << 16;
	context->gpr[1] = context->gpr[1] >> 16;
	context->gpr[1] = context->scratch1 | context->gpr[1];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_1100_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[1] & 65535)) * ((uint32_t)(context->gpr[12] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_1100_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[1])) * ((int32_t)((int16_t)context->gpr[12])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_1101_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[1] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[1], context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_1101_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[1] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[1], context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_1101_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[1] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[1], context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_1101_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[1] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->gpr[1] = context->gpr[1] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_1101_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[1] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->gpr[1] = context->gpr[1] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_1101_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[1] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->gpr[1] = context->gpr[1] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_1101_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[1] >> 31;
	context->m = context->gpr[13] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_1101_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[1] & context->gpr[13];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_1101_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[1] = context->gpr[13] & context->gpr[1];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_1101_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[1] = context->gpr[13] ^ context->gpr[1];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_1101_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[1] = context->gpr[13] | context->gpr[1];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_1101_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[13] ^ context->gpr[1];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_1101_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[13] << 16;
	context->gpr[1] = context->gpr[1] >> 16;
	context->gpr[1] = context->scratch1 | context->gpr[1];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_1101_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[1] & 65535)) * ((uint32_t)(context->gpr[13] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_1101_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[1])) * ((int32_t)((int16_t)context->gpr[13])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_1110_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[1] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[1], context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_1110_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[1] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[1], context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_1110_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[1] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[1], context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_1110_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[1] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->gpr[1] = context->gpr[1] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_1110_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[1] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->gpr[1] = context->gpr[1] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_1110_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[1] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->gpr[1] = context->gpr[1] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_1110_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[1] >> 31;
	context->m = context->gpr[14] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_1110_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[1] & context->gpr[14];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_1110_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[1] = context->gpr[14] & context->gpr[1];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_1110_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[1] = context->gpr[14] ^ context->gpr[1];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_1110_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[1] = context->gpr[14] | context->gpr[1];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_1110_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[14] ^ context->gpr[1];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_1110_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[14] << 16;
	context->gpr[1] = context->gpr[1] >> 16;
	context->gpr[1] = context->scratch1 | context->gpr[1];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_1110_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[1] & 65535)) * ((uint32_t)(context->gpr[14] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_1110_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[1])) * ((int32_t)((int16_t)context->gpr[14])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_1111_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[1] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[1], context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_1111_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[1] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[1], context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_1111_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[1] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[1], context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_1111_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[1] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->gpr[1] = context->gpr[1] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_1111_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[1] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->gpr[1] = context->gpr[1] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_1111_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[1] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->gpr[1] = context->gpr[1] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_1111_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[1] >> 31;
	context->m = context->gpr[15] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_1111_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[1] & context->gpr[15];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_1111_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[1] = context->gpr[15] & context->gpr[1];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_1111_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[1] = context->gpr[15] ^ context->gpr[1];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_1111_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[1] = context->gpr[15] | context->gpr[1];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_1111_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[15] ^ context->gpr[1];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_1111_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[15] << 16;
	context->gpr[1] = context->gpr[1] >> 16;
	context->gpr[1] = context->scratch1 | context->gpr[1];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_1111_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[1] & 65535)) * ((uint32_t)(context->gpr[15] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_1111_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[1])) * ((int32_t)((int16_t)context->gpr[15])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_0000_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[2] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[2], context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_0000_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[2] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[2], context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_0000_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[2] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[2], context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_0000_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[2] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->gpr[2] = context->gpr[2] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_0000_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[2] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->gpr[2] = context->gpr[2] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_0000_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[2] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->gpr[2] = context->gpr[2] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_0000_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[2] >> 31;
	context->m = context->gpr[0] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_0000_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[2] & context->gpr[0];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_0000_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[2] = context->gpr[0] & context->gpr[2];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_0000_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[2] = context->gpr[0] ^ context->gpr[2];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_0000_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[2] = context->gpr[0] | context->gpr[2];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_0000_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[0] ^ context->gpr[2];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_0000_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] << 16;
	context->gpr[2] = context->gpr[2] >> 16;
	context->gpr[2] = context->scratch1 | context->gpr[2];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_0000_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[2] & 65535)) * ((uint32_t)(context->gpr[0] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_0000_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[2])) * ((int32_t)((int16_t)context->gpr[0])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_0001_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[2] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[2], context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_0001_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[2] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[2], context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_0001_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[2] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[2], context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_0001_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[2] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->gpr[2] = context->gpr[2] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_0001_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[2] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->gpr[2] = context->gpr[2] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_0001_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[2] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->gpr[2] = context->gpr[2] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_0001_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[2] >> 31;
	context->m = context->gpr[1] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_0001_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[2] & context->gpr[1];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_0001_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[2] = context->gpr[1] & context->gpr[2];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_0001_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[2] = context->gpr[1] ^ context->gpr[2];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_0001_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[2] = context->gpr[1] | context->gpr[2];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_0001_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[1] ^ context->gpr[2];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_0001_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[1] << 16;
	context->gpr[2] = context->gpr[2] >> 16;
	context->gpr[2] = context->scratch1 | context->gpr[2];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_0001_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[2] & 65535)) * ((uint32_t)(context->gpr[1] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_0001_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[2])) * ((int32_t)((int16_t)context->gpr[1])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_0010_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[2] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[2], context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_0010_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[2] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[2], context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_0010_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[2] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[2], context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_0010_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[2] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->gpr[2] = context->gpr[2] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_0010_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[2] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->gpr[2] = context->gpr[2] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_0010_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[2] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->gpr[2] = context->gpr[2] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_0010_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[2] >> 31;
	context->m = context->gpr[2] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_0010_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[2] & context->gpr[2];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_0010_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[2] = context->gpr[2] & context->gpr[2];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_0010_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[2] = context->gpr[2] ^ context->gpr[2];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_0010_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[2] = context->gpr[2] | context->gpr[2];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_0010_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[2] ^ context->gpr[2];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_0010_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[2] << 16;
	context->gpr[2] = context->gpr[2] >> 16;
	context->gpr[2] = context->scratch1 | context->gpr[2];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_0010_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[2] & 65535)) * ((uint32_t)(context->gpr[2] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_0010_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[2])) * ((int32_t)((int16_t)context->gpr[2])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_0011_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[2] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[2], context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_0011_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[2] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[2], context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_0011_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[2] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[2], context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_0011_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[2] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->gpr[2] = context->gpr[2] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_0011_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[2] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->gpr[2] = context->gpr[2] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_0011_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[2] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->gpr[2] = context->gpr[2] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_0011_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[2] >> 31;
	context->m = context->gpr[3] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_0011_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[2] & context->gpr[3];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_0011_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[2] = context->gpr[3] & context->gpr[2];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_0011_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[2] = context->gpr[3] ^ context->gpr[2];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_0011_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[2] = context->gpr[3] | context->gpr[2];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_0011_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[3] ^ context->gpr[2];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_0011_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[3] << 16;
	context->gpr[2] = context->gpr[2] >> 16;
	context->gpr[2] = context->scratch1 | context->gpr[2];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_0011_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[2] & 65535)) * ((uint32_t)(context->gpr[3] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_0011_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[2])) * ((int32_t)((int16_t)context->gpr[3])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_0100_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[2] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[2], context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_0100_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[2] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[2], context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_0100_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[2] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[2], context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_0100_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[2] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->gpr[2] = context->gpr[2] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_0100_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[2] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->gpr[2] = context->gpr[2] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_0100_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[2] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->gpr[2] = context->gpr[2] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_0100_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[2] >> 31;
	context->m = context->gpr[4] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_0100_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[2] & context->gpr[4];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_0100_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[2] = context->gpr[4] & context->gpr[2];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_0100_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[2] = context->gpr[4] ^ context->gpr[2];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_0100_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[2] = context->gpr[4] | context->gpr[2];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_0100_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[4] ^ context->gpr[2];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_0100_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[4] << 16;
	context->gpr[2] = context->gpr[2] >> 16;
	context->gpr[2] = context->scratch1 | context->gpr[2];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_0100_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[2] & 65535)) * ((uint32_t)(context->gpr[4] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_0100_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[2])) * ((int32_t)((int16_t)context->gpr[4])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_0101_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[2] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[2], context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_0101_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[2] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[2], context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_0101_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[2] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[2], context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_0101_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[2] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->gpr[2] = context->gpr[2] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_0101_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[2] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->gpr[2] = context->gpr[2] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_0101_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[2] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->gpr[2] = context->gpr[2] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_0101_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[2] >> 31;
	context->m = context->gpr[5] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_0101_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[2] & context->gpr[5];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_0101_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[2] = context->gpr[5] & context->gpr[2];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_0101_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[2] = context->gpr[5] ^ context->gpr[2];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_0101_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[2] = context->gpr[5] | context->gpr[2];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_0101_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[5] ^ context->gpr[2];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_0101_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[5] << 16;
	context->gpr[2] = context->gpr[2] >> 16;
	context->gpr[2] = context->scratch1 | context->gpr[2];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_0101_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[2] & 65535)) * ((uint32_t)(context->gpr[5] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_0101_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[2])) * ((int32_t)((int16_t)context->gpr[5])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_0110_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[2] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[2], context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_0110_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[2] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[2], context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_0110_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[2] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[2], context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_0110_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[2] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->gpr[2] = context->gpr[2] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_0110_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[2] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->gpr[2] = context->gpr[2] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_0110_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[2] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->gpr[2] = context->gpr[2] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_0110_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[2] >> 31;
	context->m = context->gpr[6] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_0110_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[2] & context->gpr[6];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_0110_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[2] = context->gpr[6] & context->gpr[2];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_0110_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[2] = context->gpr[6] ^ context->gpr[2];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_0110_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[2] = context->gpr[6] | context->gpr[2];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_0110_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[6] ^ context->gpr[2];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_0110_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[6] << 16;
	context->gpr[2] = context->gpr[2] >> 16;
	context->gpr[2] = context->scratch1 | context->gpr[2];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_0110_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[2] & 65535)) * ((uint32_t)(context->gpr[6] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_0110_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[2])) * ((int32_t)((int16_t)context->gpr[6])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_0111_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[2] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[2], context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_0111_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[2] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[2], context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_0111_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[2] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[2], context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_0111_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[2] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->gpr[2] = context->gpr[2] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_0111_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[2] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->gpr[2] = context->gpr[2] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_0111_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[2] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->gpr[2] = context->gpr[2] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_0111_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[2] >> 31;
	context->m = context->gpr[7] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_0111_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[2] & context->gpr[7];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_0111_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[2] = context->gpr[7] & context->gpr[2];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_0111_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[2] = context->gpr[7] ^ context->gpr[2];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_0111_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[2] = context->gpr[7] | context->gpr[2];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_0111_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[7] ^ context->gpr[2];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_0111_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[7] << 16;
	context->gpr[2] = context->gpr[2] >> 16;
	context->gpr[2] = context->scratch1 | context->gpr[2];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_0111_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[2] & 65535)) * ((uint32_t)(context->gpr[7] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_0111_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[2])) * ((int32_t)((int16_t)context->gpr[7])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_1000_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[2] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[2], context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_1000_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[2] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[2], context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_1000_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[2] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[2], context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_1000_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[2] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->gpr[2] = context->gpr[2] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_1000_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[2] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->gpr[2] = context->gpr[2] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_1000_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[2] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->gpr[2] = context->gpr[2] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_1000_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[2] >> 31;
	context->m = context->gpr[8] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_1000_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[2] & context->gpr[8];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_1000_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[2] = context->gpr[8] & context->gpr[2];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_1000_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[2] = context->gpr[8] ^ context->gpr[2];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_1000_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[2] = context->gpr[8] | context->gpr[2];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_1000_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[8] ^ context->gpr[2];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_1000_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[8] << 16;
	context->gpr[2] = context->gpr[2] >> 16;
	context->gpr[2] = context->scratch1 | context->gpr[2];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_1000_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[2] & 65535)) * ((uint32_t)(context->gpr[8] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_1000_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[2])) * ((int32_t)((int16_t)context->gpr[8])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_1001_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[2] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[2], context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_1001_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[2] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[2], context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_1001_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[2] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[2], context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_1001_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[2] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->gpr[2] = context->gpr[2] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_1001_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[2] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->gpr[2] = context->gpr[2] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_1001_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[2] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->gpr[2] = context->gpr[2] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_1001_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[2] >> 31;
	context->m = context->gpr[9] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_1001_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[2] & context->gpr[9];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_1001_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[2] = context->gpr[9] & context->gpr[2];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_1001_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[2] = context->gpr[9] ^ context->gpr[2];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_1001_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[2] = context->gpr[9] | context->gpr[2];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_1001_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[9] ^ context->gpr[2];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_1001_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[9] << 16;
	context->gpr[2] = context->gpr[2] >> 16;
	context->gpr[2] = context->scratch1 | context->gpr[2];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_1001_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[2] & 65535)) * ((uint32_t)(context->gpr[9] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_1001_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[2])) * ((int32_t)((int16_t)context->gpr[9])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_1010_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[2] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[2], context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_1010_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[2] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[2], context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_1010_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[2] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[2], context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_1010_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[2] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->gpr[2] = context->gpr[2] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_1010_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[2] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->gpr[2] = context->gpr[2] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_1010_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[2] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->gpr[2] = context->gpr[2] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_1010_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[2] >> 31;
	context->m = context->gpr[10] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_1010_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[2] & context->gpr[10];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_1010_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[2] = context->gpr[10] & context->gpr[2];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_1010_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[2] = context->gpr[10] ^ context->gpr[2];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_1010_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[2] = context->gpr[10] | context->gpr[2];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_1010_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[10] ^ context->gpr[2];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_1010_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[10] << 16;
	context->gpr[2] = context->gpr[2] >> 16;
	context->gpr[2] = context->scratch1 | context->gpr[2];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_1010_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[2] & 65535)) * ((uint32_t)(context->gpr[10] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_1010_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[2])) * ((int32_t)((int16_t)context->gpr[10])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_1011_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[2] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[2], context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_1011_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[2] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[2], context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_1011_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[2] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[2], context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_1011_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[2] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->gpr[2] = context->gpr[2] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_1011_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[2] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->gpr[2] = context->gpr[2] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_1011_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[2] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->gpr[2] = context->gpr[2] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_1011_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[2] >> 31;
	context->m = context->gpr[11] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_1011_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[2] & context->gpr[11];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_1011_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[2] = context->gpr[11] & context->gpr[2];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_1011_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[2] = context->gpr[11] ^ context->gpr[2];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_1011_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[2] = context->gpr[11] | context->gpr[2];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_1011_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[11] ^ context->gpr[2];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_1011_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[11] << 16;
	context->gpr[2] = context->gpr[2] >> 16;
	context->gpr[2] = context->scratch1 | context->gpr[2];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_1011_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[2] & 65535)) * ((uint32_t)(context->gpr[11] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_1011_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[2])) * ((int32_t)((int16_t)context->gpr[11])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_1100_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[2] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[2], context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_1100_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[2] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[2], context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_1100_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[2] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[2], context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_1100_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[2] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->gpr[2] = context->gpr[2] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_1100_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[2] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->gpr[2] = context->gpr[2] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_1100_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[2] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->gpr[2] = context->gpr[2] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_1100_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[2] >> 31;
	context->m = context->gpr[12] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_1100_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[2] & context->gpr[12];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_1100_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[2] = context->gpr[12] & context->gpr[2];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_1100_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[2] = context->gpr[12] ^ context->gpr[2];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_1100_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[2] = context->gpr[12] | context->gpr[2];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_1100_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[12] ^ context->gpr[2];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_1100_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[12] << 16;
	context->gpr[2] = context->gpr[2] >> 16;
	context->gpr[2] = context->scratch1 | context->gpr[2];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_1100_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[2] & 65535)) * ((uint32_t)(context->gpr[12] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_1100_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[2])) * ((int32_t)((int16_t)context->gpr[12])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_1101_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[2] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[2], context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_1101_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[2] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[2], context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_1101_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[2] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[2], context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_1101_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[2] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->gpr[2] = context->gpr[2] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_1101_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[2] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->gpr[2] = context->gpr[2] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_1101_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[2] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->gpr[2] = context->gpr[2] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_1101_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[2] >> 31;
	context->m = context->gpr[13] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_1101_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[2] & context->gpr[13];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_1101_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[2] = context->gpr[13] & context->gpr[2];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_1101_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[2] = context->gpr[13] ^ context->gpr[2];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_1101_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[2] = context->gpr[13] | context->gpr[2];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_1101_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[13] ^ context->gpr[2];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_1101_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[13] << 16;
	context->gpr[2] = context->gpr[2] >> 16;
	context->gpr[2] = context->scratch1 | context->gpr[2];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_1101_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[2] & 65535)) * ((uint32_t)(context->gpr[13] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_1101_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[2])) * ((int32_t)((int16_t)context->gpr[13])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_1110_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[2] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[2], context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_1110_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[2] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[2], context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_1110_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[2] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[2], context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_1110_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[2] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->gpr[2] = context->gpr[2] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_1110_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[2] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->gpr[2] = context->gpr[2] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_1110_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[2] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->gpr[2] = context->gpr[2] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_1110_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[2] >> 31;
	context->m = context->gpr[14] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_1110_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[2] & context->gpr[14];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_1110_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[2] = context->gpr[14] & context->gpr[2];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_1110_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[2] = context->gpr[14] ^ context->gpr[2];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_1110_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[2] = context->gpr[14] | context->gpr[2];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_1110_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[14] ^ context->gpr[2];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_1110_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[14] << 16;
	context->gpr[2] = context->gpr[2] >> 16;
	context->gpr[2] = context->scratch1 | context->gpr[2];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_1110_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[2] & 65535)) * ((uint32_t)(context->gpr[14] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_1110_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[2])) * ((int32_t)((int16_t)context->gpr[14])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_1111_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[2] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[2], context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_1111_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[2] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[2], context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_1111_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[2] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[2], context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_1111_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[2] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->gpr[2] = context->gpr[2] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_1111_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[2] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->gpr[2] = context->gpr[2] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_1111_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[2] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->gpr[2] = context->gpr[2] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_1111_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[2] >> 31;
	context->m = context->gpr[15] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_1111_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[2] & context->gpr[15];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_1111_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[2] = context->gpr[15] & context->gpr[2];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_1111_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[2] = context->gpr[15] ^ context->gpr[2];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_1111_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[2] = context->gpr[15] | context->gpr[2];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_1111_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[15] ^ context->gpr[2];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_1111_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[15] << 16;
	context->gpr[2] = context->gpr[2] >> 16;
	context->gpr[2] = context->scratch1 | context->gpr[2];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_1111_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[2] & 65535)) * ((uint32_t)(context->gpr[15] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_1111_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[2])) * ((int32_t)((int16_t)context->gpr[15])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_0000_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[3] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[3], context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_0000_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[3] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[3], context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_0000_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[3] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[3], context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_0000_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[3] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->gpr[3] = context->gpr[3] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_0000_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[3] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->gpr[3] = context->gpr[3] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_0000_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[3] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->gpr[3] = context->gpr[3] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_0000_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[3] >> 31;
	context->m = context->gpr[0] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_0000_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[3] & context->gpr[0];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_0000_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[3] = context->gpr[0] & context->gpr[3];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_0000_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[3] = context->gpr[0] ^ context->gpr[3];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_0000_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[3] = context->gpr[0] | context->gpr[3];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_0000_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[0] ^ context->gpr[3];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_0000_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] << 16;
	context->gpr[3] = context->gpr[3] >> 16;
	context->gpr[3] = context->scratch1 | context->gpr[3];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_0000_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[3] & 65535)) * ((uint32_t)(context->gpr[0] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_0000_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[3])) * ((int32_t)((int16_t)context->gpr[0])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_0001_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[3] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[3], context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_0001_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[3] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[3], context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_0001_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[3] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[3], context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_0001_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[3] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->gpr[3] = context->gpr[3] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_0001_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[3] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->gpr[3] = context->gpr[3] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_0001_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[3] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->gpr[3] = context->gpr[3] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_0001_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[3] >> 31;
	context->m = context->gpr[1] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_0001_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[3] & context->gpr[1];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_0001_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[3] = context->gpr[1] & context->gpr[3];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_0001_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[3] = context->gpr[1] ^ context->gpr[3];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_0001_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[3] = context->gpr[1] | context->gpr[3];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_0001_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[1] ^ context->gpr[3];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_0001_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[1] << 16;
	context->gpr[3] = context->gpr[3] >> 16;
	context->gpr[3] = context->scratch1 | context->gpr[3];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_0001_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[3] & 65535)) * ((uint32_t)(context->gpr[1] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_0001_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[3])) * ((int32_t)((int16_t)context->gpr[1])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_0010_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[3] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[3], context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_0010_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[3] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[3], context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_0010_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[3] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[3], context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_0010_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[3] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->gpr[3] = context->gpr[3] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_0010_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[3] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->gpr[3] = context->gpr[3] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_0010_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[3] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->gpr[3] = context->gpr[3] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_0010_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[3] >> 31;
	context->m = context->gpr[2] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_0010_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[3] & context->gpr[2];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_0010_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[3] = context->gpr[2] & context->gpr[3];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_0010_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[3] = context->gpr[2] ^ context->gpr[3];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_0010_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[3] = context->gpr[2] | context->gpr[3];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_0010_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[2] ^ context->gpr[3];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_0010_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[2] << 16;
	context->gpr[3] = context->gpr[3] >> 16;
	context->gpr[3] = context->scratch1 | context->gpr[3];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_0010_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[3] & 65535)) * ((uint32_t)(context->gpr[2] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_0010_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[3])) * ((int32_t)((int16_t)context->gpr[2])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_0011_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[3] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[3], context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_0011_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[3] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[3], context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_0011_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[3] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[3], context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_0011_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[3] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->gpr[3] = context->gpr[3] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_0011_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[3] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->gpr[3] = context->gpr[3] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_0011_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[3] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->gpr[3] = context->gpr[3] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_0011_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[3] >> 31;
	context->m = context->gpr[3] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_0011_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[3] & context->gpr[3];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_0011_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[3] = context->gpr[3] & context->gpr[3];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_0011_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[3] = context->gpr[3] ^ context->gpr[3];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_0011_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[3] = context->gpr[3] | context->gpr[3];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_0011_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[3] ^ context->gpr[3];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_0011_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[3] << 16;
	context->gpr[3] = context->gpr[3] >> 16;
	context->gpr[3] = context->scratch1 | context->gpr[3];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_0011_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[3] & 65535)) * ((uint32_t)(context->gpr[3] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_0011_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[3])) * ((int32_t)((int16_t)context->gpr[3])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_0100_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[3] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[3], context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_0100_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[3] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[3], context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_0100_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[3] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[3], context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_0100_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[3] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->gpr[3] = context->gpr[3] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_0100_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[3] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->gpr[3] = context->gpr[3] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_0100_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[3] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->gpr[3] = context->gpr[3] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_0100_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[3] >> 31;
	context->m = context->gpr[4] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_0100_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[3] & context->gpr[4];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_0100_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[3] = context->gpr[4] & context->gpr[3];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_0100_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[3] = context->gpr[4] ^ context->gpr[3];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_0100_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[3] = context->gpr[4] | context->gpr[3];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_0100_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[4] ^ context->gpr[3];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_0100_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[4] << 16;
	context->gpr[3] = context->gpr[3] >> 16;
	context->gpr[3] = context->scratch1 | context->gpr[3];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_0100_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[3] & 65535)) * ((uint32_t)(context->gpr[4] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_0100_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[3])) * ((int32_t)((int16_t)context->gpr[4])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_0101_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[3] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[3], context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_0101_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[3] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[3], context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_0101_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[3] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[3], context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_0101_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[3] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->gpr[3] = context->gpr[3] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_0101_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[3] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->gpr[3] = context->gpr[3] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_0101_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[3] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->gpr[3] = context->gpr[3] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_0101_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[3] >> 31;
	context->m = context->gpr[5] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_0101_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[3] & context->gpr[5];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_0101_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[3] = context->gpr[5] & context->gpr[3];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_0101_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[3] = context->gpr[5] ^ context->gpr[3];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_0101_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[3] = context->gpr[5] | context->gpr[3];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_0101_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[5] ^ context->gpr[3];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_0101_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[5] << 16;
	context->gpr[3] = context->gpr[3] >> 16;
	context->gpr[3] = context->scratch1 | context->gpr[3];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_0101_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[3] & 65535)) * ((uint32_t)(context->gpr[5] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_0101_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[3])) * ((int32_t)((int16_t)context->gpr[5])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_0110_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[3] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[3], context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_0110_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[3] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[3], context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_0110_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[3] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[3], context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_0110_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[3] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->gpr[3] = context->gpr[3] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_0110_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[3] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->gpr[3] = context->gpr[3] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_0110_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[3] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->gpr[3] = context->gpr[3] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_0110_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[3] >> 31;
	context->m = context->gpr[6] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_0110_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[3] & context->gpr[6];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_0110_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[3] = context->gpr[6] & context->gpr[3];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_0110_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[3] = context->gpr[6] ^ context->gpr[3];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_0110_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[3] = context->gpr[6] | context->gpr[3];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_0110_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[6] ^ context->gpr[3];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_0110_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[6] << 16;
	context->gpr[3] = context->gpr[3] >> 16;
	context->gpr[3] = context->scratch1 | context->gpr[3];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_0110_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[3] & 65535)) * ((uint32_t)(context->gpr[6] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_0110_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[3])) * ((int32_t)((int16_t)context->gpr[6])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_0111_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[3] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[3], context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_0111_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[3] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[3], context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_0111_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[3] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[3], context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_0111_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[3] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->gpr[3] = context->gpr[3] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_0111_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[3] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->gpr[3] = context->gpr[3] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_0111_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[3] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->gpr[3] = context->gpr[3] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_0111_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[3] >> 31;
	context->m = context->gpr[7] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_0111_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[3] & context->gpr[7];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_0111_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[3] = context->gpr[7] & context->gpr[3];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_0111_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[3] = context->gpr[7] ^ context->gpr[3];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_0111_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[3] = context->gpr[7] | context->gpr[3];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_0111_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[7] ^ context->gpr[3];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_0111_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[7] << 16;
	context->gpr[3] = context->gpr[3] >> 16;
	context->gpr[3] = context->scratch1 | context->gpr[3];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_0111_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[3] & 65535)) * ((uint32_t)(context->gpr[7] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_0111_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[3])) * ((int32_t)((int16_t)context->gpr[7])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_1000_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[3] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[3], context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_1000_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[3] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[3], context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_1000_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[3] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[3], context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_1000_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[3] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->gpr[3] = context->gpr[3] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_1000_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[3] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->gpr[3] = context->gpr[3] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_1000_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[3] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->gpr[3] = context->gpr[3] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_1000_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[3] >> 31;
	context->m = context->gpr[8] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_1000_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[3] & context->gpr[8];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_1000_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[3] = context->gpr[8] & context->gpr[3];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_1000_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[3] = context->gpr[8] ^ context->gpr[3];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_1000_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[3] = context->gpr[8] | context->gpr[3];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_1000_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[8] ^ context->gpr[3];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_1000_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[8] << 16;
	context->gpr[3] = context->gpr[3] >> 16;
	context->gpr[3] = context->scratch1 | context->gpr[3];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_1000_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[3] & 65535)) * ((uint32_t)(context->gpr[8] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_1000_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[3])) * ((int32_t)((int16_t)context->gpr[8])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_1001_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[3] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[3], context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_1001_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[3] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[3], context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_1001_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[3] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[3], context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_1001_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[3] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->gpr[3] = context->gpr[3] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_1001_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[3] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->gpr[3] = context->gpr[3] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_1001_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[3] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->gpr[3] = context->gpr[3] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_1001_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[3] >> 31;
	context->m = context->gpr[9] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_1001_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[3] & context->gpr[9];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_1001_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[3] = context->gpr[9] & context->gpr[3];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_1001_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[3] = context->gpr[9] ^ context->gpr[3];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_1001_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[3] = context->gpr[9] | context->gpr[3];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_1001_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[9] ^ context->gpr[3];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_1001_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[9] << 16;
	context->gpr[3] = context->gpr[3] >> 16;
	context->gpr[3] = context->scratch1 | context->gpr[3];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_1001_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[3] & 65535)) * ((uint32_t)(context->gpr[9] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_1001_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[3])) * ((int32_t)((int16_t)context->gpr[9])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_1010_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[3] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[3], context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_1010_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[3] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[3], context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_1010_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[3] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[3], context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_1010_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[3] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->gpr[3] = context->gpr[3] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_1010_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[3] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->gpr[3] = context->gpr[3] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_1010_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[3] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->gpr[3] = context->gpr[3] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_1010_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[3] >> 31;
	context->m = context->gpr[10] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_1010_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[3] & context->gpr[10];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_1010_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[3] = context->gpr[10] & context->gpr[3];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_1010_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[3] = context->gpr[10] ^ context->gpr[3];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_1010_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[3] = context->gpr[10] | context->gpr[3];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_1010_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[10] ^ context->gpr[3];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_1010_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[10] << 16;
	context->gpr[3] = context->gpr[3] >> 16;
	context->gpr[3] = context->scratch1 | context->gpr[3];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_1010_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[3] & 65535)) * ((uint32_t)(context->gpr[10] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_1010_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[3])) * ((int32_t)((int16_t)context->gpr[10])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_1011_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[3] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[3], context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_1011_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[3] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[3], context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_1011_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[3] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[3], context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_1011_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[3] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->gpr[3] = context->gpr[3] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_1011_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[3] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->gpr[3] = context->gpr[3] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_1011_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[3] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->gpr[3] = context->gpr[3] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_1011_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[3] >> 31;
	context->m = context->gpr[11] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_1011_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[3] & context->gpr[11];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_1011_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[3] = context->gpr[11] & context->gpr[3];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_1011_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[3] = context->gpr[11] ^ context->gpr[3];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_1011_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[3] = context->gpr[11] | context->gpr[3];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_1011_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[11] ^ context->gpr[3];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_1011_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[11] << 16;
	context->gpr[3] = context->gpr[3] >> 16;
	context->gpr[3] = context->scratch1 | context->gpr[3];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_1011_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[3] & 65535)) * ((uint32_t)(context->gpr[11] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_1011_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[3])) * ((int32_t)((int16_t)context->gpr[11])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_1100_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[3] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[3], context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_1100_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[3] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[3], context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_1100_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[3] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[3], context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_1100_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[3] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->gpr[3] = context->gpr[3] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_1100_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[3] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->gpr[3] = context->gpr[3] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_1100_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[3] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->gpr[3] = context->gpr[3] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_1100_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[3] >> 31;
	context->m = context->gpr[12] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_1100_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[3] & context->gpr[12];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_1100_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[3] = context->gpr[12] & context->gpr[3];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_1100_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[3] = context->gpr[12] ^ context->gpr[3];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_1100_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[3] = context->gpr[12] | context->gpr[3];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_1100_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[12] ^ context->gpr[3];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_1100_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[12] << 16;
	context->gpr[3] = context->gpr[3] >> 16;
	context->gpr[3] = context->scratch1 | context->gpr[3];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_1100_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[3] & 65535)) * ((uint32_t)(context->gpr[12] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_1100_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[3])) * ((int32_t)((int16_t)context->gpr[12])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_1101_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[3] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[3], context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_1101_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[3] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[3], context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_1101_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[3] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[3], context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_1101_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[3] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->gpr[3] = context->gpr[3] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_1101_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[3] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->gpr[3] = context->gpr[3] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_1101_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[3] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->gpr[3] = context->gpr[3] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_1101_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[3] >> 31;
	context->m = context->gpr[13] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_1101_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[3] & context->gpr[13];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_1101_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[3] = context->gpr[13] & context->gpr[3];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_1101_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[3] = context->gpr[13] ^ context->gpr[3];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_1101_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[3] = context->gpr[13] | context->gpr[3];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_1101_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[13] ^ context->gpr[3];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_1101_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[13] << 16;
	context->gpr[3] = context->gpr[3] >> 16;
	context->gpr[3] = context->scratch1 | context->gpr[3];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_1101_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[3] & 65535)) * ((uint32_t)(context->gpr[13] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_1101_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[3])) * ((int32_t)((int16_t)context->gpr[13])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_1110_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[3] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[3], context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_1110_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[3] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[3], context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_1110_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[3] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[3], context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_1110_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[3] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->gpr[3] = context->gpr[3] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_1110_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[3] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->gpr[3] = context->gpr[3] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_1110_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[3] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->gpr[3] = context->gpr[3] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_1110_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[3] >> 31;
	context->m = context->gpr[14] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_1110_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[3] & context->gpr[14];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_1110_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[3] = context->gpr[14] & context->gpr[3];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_1110_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[3] = context->gpr[14] ^ context->gpr[3];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_1110_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[3] = context->gpr[14] | context->gpr[3];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_1110_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[14] ^ context->gpr[3];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_1110_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[14] << 16;
	context->gpr[3] = context->gpr[3] >> 16;
	context->gpr[3] = context->scratch1 | context->gpr[3];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_1110_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[3] & 65535)) * ((uint32_t)(context->gpr[14] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_1110_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[3])) * ((int32_t)((int16_t)context->gpr[14])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_1111_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[3] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[3], context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_1111_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[3] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[3], context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_1111_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[3] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[3], context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_1111_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[3] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->gpr[3] = context->gpr[3] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_1111_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[3] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->gpr[3] = context->gpr[3] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_1111_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[3] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->gpr[3] = context->gpr[3] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_1111_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[3] >> 31;
	context->m = context->gpr[15] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_1111_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[3] & context->gpr[15];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_1111_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[3] = context->gpr[15] & context->gpr[3];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_1111_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[3] = context->gpr[15] ^ context->gpr[3];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_1111_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[3] = context->gpr[15] | context->gpr[3];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_1111_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[15] ^ context->gpr[3];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_1111_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[15] << 16;
	context->gpr[3] = context->gpr[3] >> 16;
	context->gpr[3] = context->scratch1 | context->gpr[3];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_1111_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[3] & 65535)) * ((uint32_t)(context->gpr[15] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_1111_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[3])) * ((int32_t)((int16_t)context->gpr[15])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_0000_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[4] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[4], context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_0000_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[4] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[4], context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_0000_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[4] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[4], context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_0000_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[4] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->gpr[4] = context->gpr[4] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_0000_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[4] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->gpr[4] = context->gpr[4] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_0000_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[4] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->gpr[4] = context->gpr[4] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_0000_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[4] >> 31;
	context->m = context->gpr[0] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_0000_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[4] & context->gpr[0];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_0000_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[4] = context->gpr[0] & context->gpr[4];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_0000_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[4] = context->gpr[0] ^ context->gpr[4];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_0000_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[4] = context->gpr[0] | context->gpr[4];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_0000_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[0] ^ context->gpr[4];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_0000_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] << 16;
	context->gpr[4] = context->gpr[4] >> 16;
	context->gpr[4] = context->scratch1 | context->gpr[4];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_0000_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[4] & 65535)) * ((uint32_t)(context->gpr[0] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_0000_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[4])) * ((int32_t)((int16_t)context->gpr[0])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_0001_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[4] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[4], context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_0001_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[4] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[4], context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_0001_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[4] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[4], context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_0001_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[4] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->gpr[4] = context->gpr[4] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_0001_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[4] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->gpr[4] = context->gpr[4] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_0001_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[4] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->gpr[4] = context->gpr[4] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_0001_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[4] >> 31;
	context->m = context->gpr[1] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_0001_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[4] & context->gpr[1];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_0001_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[4] = context->gpr[1] & context->gpr[4];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_0001_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[4] = context->gpr[1] ^ context->gpr[4];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_0001_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[4] = context->gpr[1] | context->gpr[4];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_0001_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[1] ^ context->gpr[4];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_0001_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[1] << 16;
	context->gpr[4] = context->gpr[4] >> 16;
	context->gpr[4] = context->scratch1 | context->gpr[4];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_0001_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[4] & 65535)) * ((uint32_t)(context->gpr[1] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_0001_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[4])) * ((int32_t)((int16_t)context->gpr[1])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_0010_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[4] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[4], context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_0010_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[4] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[4], context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_0010_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[4] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[4], context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_0010_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[4] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->gpr[4] = context->gpr[4] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_0010_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[4] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->gpr[4] = context->gpr[4] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_0010_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[4] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->gpr[4] = context->gpr[4] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_0010_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[4] >> 31;
	context->m = context->gpr[2] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_0010_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[4] & context->gpr[2];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_0010_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[4] = context->gpr[2] & context->gpr[4];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_0010_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[4] = context->gpr[2] ^ context->gpr[4];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_0010_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[4] = context->gpr[2] | context->gpr[4];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_0010_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[2] ^ context->gpr[4];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_0010_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[2] << 16;
	context->gpr[4] = context->gpr[4] >> 16;
	context->gpr[4] = context->scratch1 | context->gpr[4];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_0010_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[4] & 65535)) * ((uint32_t)(context->gpr[2] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_0010_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[4])) * ((int32_t)((int16_t)context->gpr[2])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_0011_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[4] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[4], context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_0011_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[4] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[4], context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_0011_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[4] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[4], context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_0011_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[4] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->gpr[4] = context->gpr[4] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_0011_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[4] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->gpr[4] = context->gpr[4] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_0011_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[4] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->gpr[4] = context->gpr[4] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_0011_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[4] >> 31;
	context->m = context->gpr[3] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_0011_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[4] & context->gpr[3];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_0011_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[4] = context->gpr[3] & context->gpr[4];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_0011_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[4] = context->gpr[3] ^ context->gpr[4];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_0011_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[4] = context->gpr[3] | context->gpr[4];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_0011_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[3] ^ context->gpr[4];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_0011_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[3] << 16;
	context->gpr[4] = context->gpr[4] >> 16;
	context->gpr[4] = context->scratch1 | context->gpr[4];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_0011_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[4] & 65535)) * ((uint32_t)(context->gpr[3] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_0011_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[4])) * ((int32_t)((int16_t)context->gpr[3])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_0100_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[4] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[4], context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_0100_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[4] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[4], context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_0100_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[4] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[4], context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_0100_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[4] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->gpr[4] = context->gpr[4] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_0100_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[4] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->gpr[4] = context->gpr[4] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_0100_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[4] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->gpr[4] = context->gpr[4] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_0100_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[4] >> 31;
	context->m = context->gpr[4] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_0100_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[4] & context->gpr[4];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_0100_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[4] = context->gpr[4] & context->gpr[4];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_0100_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[4] = context->gpr[4] ^ context->gpr[4];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_0100_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[4] = context->gpr[4] | context->gpr[4];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_0100_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[4] ^ context->gpr[4];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_0100_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[4] << 16;
	context->gpr[4] = context->gpr[4] >> 16;
	context->gpr[4] = context->scratch1 | context->gpr[4];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_0100_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[4] & 65535)) * ((uint32_t)(context->gpr[4] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_0100_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[4])) * ((int32_t)((int16_t)context->gpr[4])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_0101_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[4] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[4], context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_0101_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[4] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[4], context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_0101_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[4] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[4], context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_0101_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[4] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->gpr[4] = context->gpr[4] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_0101_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[4] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->gpr[4] = context->gpr[4] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_0101_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[4] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->gpr[4] = context->gpr[4] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_0101_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[4] >> 31;
	context->m = context->gpr[5] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_0101_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[4] & context->gpr[5];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_0101_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[4] = context->gpr[5] & context->gpr[4];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_0101_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[4] = context->gpr[5] ^ context->gpr[4];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_0101_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[4] = context->gpr[5] | context->gpr[4];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_0101_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[5] ^ context->gpr[4];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_0101_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[5] << 16;
	context->gpr[4] = context->gpr[4] >> 16;
	context->gpr[4] = context->scratch1 | context->gpr[4];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_0101_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[4] & 65535)) * ((uint32_t)(context->gpr[5] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_0101_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[4])) * ((int32_t)((int16_t)context->gpr[5])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_0110_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[4] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[4], context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_0110_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[4] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[4], context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_0110_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[4] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[4], context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_0110_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[4] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->gpr[4] = context->gpr[4] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_0110_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[4] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->gpr[4] = context->gpr[4] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_0110_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[4] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->gpr[4] = context->gpr[4] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_0110_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[4] >> 31;
	context->m = context->gpr[6] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_0110_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[4] & context->gpr[6];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_0110_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[4] = context->gpr[6] & context->gpr[4];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_0110_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[4] = context->gpr[6] ^ context->gpr[4];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_0110_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[4] = context->gpr[6] | context->gpr[4];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_0110_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[6] ^ context->gpr[4];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_0110_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[6] << 16;
	context->gpr[4] = context->gpr[4] >> 16;
	context->gpr[4] = context->scratch1 | context->gpr[4];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_0110_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[4] & 65535)) * ((uint32_t)(context->gpr[6] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_0110_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[4])) * ((int32_t)((int16_t)context->gpr[6])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_0111_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[4] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[4], context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_0111_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[4] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[4], context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_0111_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[4] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[4], context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_0111_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[4] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->gpr[4] = context->gpr[4] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_0111_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[4] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->gpr[4] = context->gpr[4] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_0111_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[4] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->gpr[4] = context->gpr[4] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_0111_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[4] >> 31;
	context->m = context->gpr[7] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_0111_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[4] & context->gpr[7];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_0111_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[4] = context->gpr[7] & context->gpr[4];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_0111_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[4] = context->gpr[7] ^ context->gpr[4];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_0111_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[4] = context->gpr[7] | context->gpr[4];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_0111_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[7] ^ context->gpr[4];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_0111_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[7] << 16;
	context->gpr[4] = context->gpr[4] >> 16;
	context->gpr[4] = context->scratch1 | context->gpr[4];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_0111_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[4] & 65535)) * ((uint32_t)(context->gpr[7] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_0111_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[4])) * ((int32_t)((int16_t)context->gpr[7])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_1000_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[4] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[4], context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_1000_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[4] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[4], context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_1000_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[4] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[4], context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_1000_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[4] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->gpr[4] = context->gpr[4] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_1000_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[4] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->gpr[4] = context->gpr[4] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_1000_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[4] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->gpr[4] = context->gpr[4] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_1000_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[4] >> 31;
	context->m = context->gpr[8] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_1000_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[4] & context->gpr[8];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_1000_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[4] = context->gpr[8] & context->gpr[4];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_1000_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[4] = context->gpr[8] ^ context->gpr[4];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_1000_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[4] = context->gpr[8] | context->gpr[4];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_1000_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[8] ^ context->gpr[4];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_1000_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[8] << 16;
	context->gpr[4] = context->gpr[4] >> 16;
	context->gpr[4] = context->scratch1 | context->gpr[4];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_1000_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[4] & 65535)) * ((uint32_t)(context->gpr[8] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_1000_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[4])) * ((int32_t)((int16_t)context->gpr[8])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_1001_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[4] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[4], context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_1001_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[4] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[4], context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_1001_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[4] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[4], context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_1001_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[4] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->gpr[4] = context->gpr[4] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_1001_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[4] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->gpr[4] = context->gpr[4] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_1001_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[4] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->gpr[4] = context->gpr[4] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_1001_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[4] >> 31;
	context->m = context->gpr[9] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_1001_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[4] & context->gpr[9];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_1001_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[4] = context->gpr[9] & context->gpr[4];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_1001_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[4] = context->gpr[9] ^ context->gpr[4];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_1001_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[4] = context->gpr[9] | context->gpr[4];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_1001_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[9] ^ context->gpr[4];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_1001_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[9] << 16;
	context->gpr[4] = context->gpr[4] >> 16;
	context->gpr[4] = context->scratch1 | context->gpr[4];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_1001_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[4] & 65535)) * ((uint32_t)(context->gpr[9] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_1001_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[4])) * ((int32_t)((int16_t)context->gpr[9])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_1010_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[4] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[4], context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_1010_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[4] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[4], context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_1010_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[4] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[4], context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_1010_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[4] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->gpr[4] = context->gpr[4] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_1010_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[4] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->gpr[4] = context->gpr[4] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_1010_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[4] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->gpr[4] = context->gpr[4] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_1010_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[4] >> 31;
	context->m = context->gpr[10] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_1010_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[4] & context->gpr[10];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_1010_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[4] = context->gpr[10] & context->gpr[4];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_1010_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[4] = context->gpr[10] ^ context->gpr[4];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_1010_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[4] = context->gpr[10] | context->gpr[4];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_1010_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[10] ^ context->gpr[4];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_1010_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[10] << 16;
	context->gpr[4] = context->gpr[4] >> 16;
	context->gpr[4] = context->scratch1 | context->gpr[4];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_1010_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[4] & 65535)) * ((uint32_t)(context->gpr[10] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_1010_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[4])) * ((int32_t)((int16_t)context->gpr[10])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_1011_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[4] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[4], context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_1011_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[4] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[4], context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_1011_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[4] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[4], context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_1011_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[4] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->gpr[4] = context->gpr[4] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_1011_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[4] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->gpr[4] = context->gpr[4] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_1011_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[4] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->gpr[4] = context->gpr[4] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_1011_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[4] >> 31;
	context->m = context->gpr[11] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_1011_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[4] & context->gpr[11];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_1011_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[4] = context->gpr[11] & context->gpr[4];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_1011_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[4] = context->gpr[11] ^ context->gpr[4];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_1011_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[4] = context->gpr[11] | context->gpr[4];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_1011_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[11] ^ context->gpr[4];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_1011_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[11] << 16;
	context->gpr[4] = context->gpr[4] >> 16;
	context->gpr[4] = context->scratch1 | context->gpr[4];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_1011_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[4] & 65535)) * ((uint32_t)(context->gpr[11] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_1011_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[4])) * ((int32_t)((int16_t)context->gpr[11])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_1100_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[4] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[4], context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_1100_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[4] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[4], context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_1100_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[4] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[4], context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_1100_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[4] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->gpr[4] = context->gpr[4] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_1100_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[4] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->gpr[4] = context->gpr[4] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_1100_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[4] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->gpr[4] = context->gpr[4] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_1100_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[4] >> 31;
	context->m = context->gpr[12] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_1100_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[4] & context->gpr[12];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_1100_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[4] = context->gpr[12] & context->gpr[4];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_1100_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[4] = context->gpr[12] ^ context->gpr[4];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_1100_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[4] = context->gpr[12] | context->gpr[4];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_1100_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[12] ^ context->gpr[4];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_1100_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[12] << 16;
	context->gpr[4] = context->gpr[4] >> 16;
	context->gpr[4] = context->scratch1 | context->gpr[4];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_1100_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[4] & 65535)) * ((uint32_t)(context->gpr[12] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_1100_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[4])) * ((int32_t)((int16_t)context->gpr[12])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_1101_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[4] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[4], context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_1101_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[4] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[4], context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_1101_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[4] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[4], context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_1101_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[4] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->gpr[4] = context->gpr[4] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_1101_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[4] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->gpr[4] = context->gpr[4] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_1101_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[4] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->gpr[4] = context->gpr[4] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_1101_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[4] >> 31;
	context->m = context->gpr[13] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_1101_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[4] & context->gpr[13];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_1101_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[4] = context->gpr[13] & context->gpr[4];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_1101_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[4] = context->gpr[13] ^ context->gpr[4];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_1101_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[4] = context->gpr[13] | context->gpr[4];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_1101_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[13] ^ context->gpr[4];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_1101_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[13] << 16;
	context->gpr[4] = context->gpr[4] >> 16;
	context->gpr[4] = context->scratch1 | context->gpr[4];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_1101_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[4] & 65535)) * ((uint32_t)(context->gpr[13] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_1101_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[4])) * ((int32_t)((int16_t)context->gpr[13])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_1110_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[4] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[4], context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_1110_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[4] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[4], context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_1110_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[4] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[4], context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_1110_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[4] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->gpr[4] = context->gpr[4] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_1110_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[4] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->gpr[4] = context->gpr[4] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_1110_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[4] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->gpr[4] = context->gpr[4] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_1110_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[4] >> 31;
	context->m = context->gpr[14] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_1110_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[4] & context->gpr[14];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_1110_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[4] = context->gpr[14] & context->gpr[4];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_1110_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[4] = context->gpr[14] ^ context->gpr[4];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_1110_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[4] = context->gpr[14] | context->gpr[4];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_1110_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[14] ^ context->gpr[4];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_1110_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[14] << 16;
	context->gpr[4] = context->gpr[4] >> 16;
	context->gpr[4] = context->scratch1 | context->gpr[4];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_1110_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[4] & 65535)) * ((uint32_t)(context->gpr[14] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_1110_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[4])) * ((int32_t)((int16_t)context->gpr[14])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_1111_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[4] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[4], context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_1111_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[4] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[4], context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_1111_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[4] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[4], context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_1111_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[4] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->gpr[4] = context->gpr[4] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_1111_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[4] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->gpr[4] = context->gpr[4] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_1111_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[4] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->gpr[4] = context->gpr[4] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_1111_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[4] >> 31;
	context->m = context->gpr[15] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_1111_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[4] & context->gpr[15];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_1111_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[4] = context->gpr[15] & context->gpr[4];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_1111_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[4] = context->gpr[15] ^ context->gpr[4];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_1111_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[4] = context->gpr[15] | context->gpr[4];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_1111_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[15] ^ context->gpr[4];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_1111_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[15] << 16;
	context->gpr[4] = context->gpr[4] >> 16;
	context->gpr[4] = context->scratch1 | context->gpr[4];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_1111_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[4] & 65535)) * ((uint32_t)(context->gpr[15] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_1111_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[4])) * ((int32_t)((int16_t)context->gpr[15])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_0000_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[5] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[5], context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_0000_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[5] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[5], context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_0000_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[5] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[5], context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_0000_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[5] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->gpr[5] = context->gpr[5] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_0000_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[5] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->gpr[5] = context->gpr[5] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_0000_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[5] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->gpr[5] = context->gpr[5] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_0000_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[5] >> 31;
	context->m = context->gpr[0] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_0000_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[5] & context->gpr[0];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_0000_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[5] = context->gpr[0] & context->gpr[5];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_0000_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[5] = context->gpr[0] ^ context->gpr[5];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_0000_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[5] = context->gpr[0] | context->gpr[5];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_0000_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[0] ^ context->gpr[5];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_0000_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] << 16;
	context->gpr[5] = context->gpr[5] >> 16;
	context->gpr[5] = context->scratch1 | context->gpr[5];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_0000_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[5] & 65535)) * ((uint32_t)(context->gpr[0] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_0000_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[5])) * ((int32_t)((int16_t)context->gpr[0])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_0001_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[5] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[5], context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_0001_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[5] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[5], context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_0001_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[5] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[5], context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_0001_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[5] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->gpr[5] = context->gpr[5] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_0001_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[5] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->gpr[5] = context->gpr[5] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_0001_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[5] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->gpr[5] = context->gpr[5] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_0001_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[5] >> 31;
	context->m = context->gpr[1] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_0001_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[5] & context->gpr[1];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_0001_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[5] = context->gpr[1] & context->gpr[5];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_0001_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[5] = context->gpr[1] ^ context->gpr[5];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_0001_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[5] = context->gpr[1] | context->gpr[5];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_0001_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[1] ^ context->gpr[5];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_0001_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[1] << 16;
	context->gpr[5] = context->gpr[5] >> 16;
	context->gpr[5] = context->scratch1 | context->gpr[5];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_0001_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[5] & 65535)) * ((uint32_t)(context->gpr[1] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_0001_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[5])) * ((int32_t)((int16_t)context->gpr[1])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_0010_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[5] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[5], context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_0010_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[5] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[5], context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_0010_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[5] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[5], context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_0010_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[5] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->gpr[5] = context->gpr[5] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_0010_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[5] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->gpr[5] = context->gpr[5] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_0010_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[5] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->gpr[5] = context->gpr[5] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_0010_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[5] >> 31;
	context->m = context->gpr[2] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_0010_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[5] & context->gpr[2];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_0010_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[5] = context->gpr[2] & context->gpr[5];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_0010_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[5] = context->gpr[2] ^ context->gpr[5];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_0010_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[5] = context->gpr[2] | context->gpr[5];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_0010_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[2] ^ context->gpr[5];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_0010_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[2] << 16;
	context->gpr[5] = context->gpr[5] >> 16;
	context->gpr[5] = context->scratch1 | context->gpr[5];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_0010_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[5] & 65535)) * ((uint32_t)(context->gpr[2] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_0010_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[5])) * ((int32_t)((int16_t)context->gpr[2])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_0011_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[5] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[5], context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_0011_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[5] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[5], context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_0011_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[5] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[5], context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_0011_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[5] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->gpr[5] = context->gpr[5] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_0011_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[5] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->gpr[5] = context->gpr[5] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_0011_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[5] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->gpr[5] = context->gpr[5] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_0011_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[5] >> 31;
	context->m = context->gpr[3] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_0011_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[5] & context->gpr[3];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_0011_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[5] = context->gpr[3] & context->gpr[5];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_0011_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[5] = context->gpr[3] ^ context->gpr[5];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_0011_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[5] = context->gpr[3] | context->gpr[5];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_0011_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[3] ^ context->gpr[5];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_0011_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[3] << 16;
	context->gpr[5] = context->gpr[5] >> 16;
	context->gpr[5] = context->scratch1 | context->gpr[5];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_0011_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[5] & 65535)) * ((uint32_t)(context->gpr[3] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_0011_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[5])) * ((int32_t)((int16_t)context->gpr[3])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_0100_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[5] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[5], context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_0100_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[5] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[5], context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_0100_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[5] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[5], context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_0100_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[5] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->gpr[5] = context->gpr[5] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_0100_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[5] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->gpr[5] = context->gpr[5] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_0100_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[5] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->gpr[5] = context->gpr[5] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_0100_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[5] >> 31;
	context->m = context->gpr[4] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_0100_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[5] & context->gpr[4];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_0100_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[5] = context->gpr[4] & context->gpr[5];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_0100_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[5] = context->gpr[4] ^ context->gpr[5];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_0100_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[5] = context->gpr[4] | context->gpr[5];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_0100_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[4] ^ context->gpr[5];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_0100_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[4] << 16;
	context->gpr[5] = context->gpr[5] >> 16;
	context->gpr[5] = context->scratch1 | context->gpr[5];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_0100_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[5] & 65535)) * ((uint32_t)(context->gpr[4] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_0100_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[5])) * ((int32_t)((int16_t)context->gpr[4])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_0101_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[5] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[5], context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_0101_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[5] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[5], context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_0101_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[5] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[5], context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_0101_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[5] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->gpr[5] = context->gpr[5] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_0101_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[5] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->gpr[5] = context->gpr[5] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_0101_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[5] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->gpr[5] = context->gpr[5] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_0101_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[5] >> 31;
	context->m = context->gpr[5] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_0101_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[5] & context->gpr[5];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_0101_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[5] = context->gpr[5] & context->gpr[5];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_0101_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[5] = context->gpr[5] ^ context->gpr[5];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_0101_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[5] = context->gpr[5] | context->gpr[5];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_0101_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[5] ^ context->gpr[5];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_0101_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[5] << 16;
	context->gpr[5] = context->gpr[5] >> 16;
	context->gpr[5] = context->scratch1 | context->gpr[5];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_0101_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[5] & 65535)) * ((uint32_t)(context->gpr[5] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_0101_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[5])) * ((int32_t)((int16_t)context->gpr[5])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_0110_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[5] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[5], context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_0110_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[5] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[5], context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_0110_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[5] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[5], context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_0110_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[5] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->gpr[5] = context->gpr[5] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_0110_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[5] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->gpr[5] = context->gpr[5] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_0110_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[5] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->gpr[5] = context->gpr[5] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_0110_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[5] >> 31;
	context->m = context->gpr[6] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_0110_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[5] & context->gpr[6];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_0110_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[5] = context->gpr[6] & context->gpr[5];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_0110_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[5] = context->gpr[6] ^ context->gpr[5];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_0110_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[5] = context->gpr[6] | context->gpr[5];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_0110_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[6] ^ context->gpr[5];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_0110_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[6] << 16;
	context->gpr[5] = context->gpr[5] >> 16;
	context->gpr[5] = context->scratch1 | context->gpr[5];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_0110_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[5] & 65535)) * ((uint32_t)(context->gpr[6] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_0110_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[5])) * ((int32_t)((int16_t)context->gpr[6])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_0111_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[5] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[5], context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_0111_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[5] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[5], context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_0111_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[5] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[5], context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_0111_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[5] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->gpr[5] = context->gpr[5] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_0111_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[5] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->gpr[5] = context->gpr[5] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_0111_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[5] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->gpr[5] = context->gpr[5] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_0111_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[5] >> 31;
	context->m = context->gpr[7] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_0111_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[5] & context->gpr[7];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_0111_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[5] = context->gpr[7] & context->gpr[5];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_0111_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[5] = context->gpr[7] ^ context->gpr[5];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_0111_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[5] = context->gpr[7] | context->gpr[5];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_0111_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[7] ^ context->gpr[5];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_0111_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[7] << 16;
	context->gpr[5] = context->gpr[5] >> 16;
	context->gpr[5] = context->scratch1 | context->gpr[5];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_0111_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[5] & 65535)) * ((uint32_t)(context->gpr[7] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_0111_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[5])) * ((int32_t)((int16_t)context->gpr[7])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_1000_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[5] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[5], context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_1000_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[5] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[5], context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_1000_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[5] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[5], context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_1000_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[5] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->gpr[5] = context->gpr[5] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_1000_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[5] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->gpr[5] = context->gpr[5] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_1000_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[5] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->gpr[5] = context->gpr[5] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_1000_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[5] >> 31;
	context->m = context->gpr[8] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_1000_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[5] & context->gpr[8];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_1000_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[5] = context->gpr[8] & context->gpr[5];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_1000_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[5] = context->gpr[8] ^ context->gpr[5];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_1000_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[5] = context->gpr[8] | context->gpr[5];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_1000_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[8] ^ context->gpr[5];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_1000_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[8] << 16;
	context->gpr[5] = context->gpr[5] >> 16;
	context->gpr[5] = context->scratch1 | context->gpr[5];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_1000_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[5] & 65535)) * ((uint32_t)(context->gpr[8] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_1000_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[5])) * ((int32_t)((int16_t)context->gpr[8])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_1001_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[5] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[5], context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_1001_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[5] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[5], context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_1001_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[5] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[5], context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_1001_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[5] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->gpr[5] = context->gpr[5] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_1001_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[5] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->gpr[5] = context->gpr[5] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_1001_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[5] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->gpr[5] = context->gpr[5] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_1001_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[5] >> 31;
	context->m = context->gpr[9] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_1001_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[5] & context->gpr[9];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_1001_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[5] = context->gpr[9] & context->gpr[5];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_1001_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[5] = context->gpr[9] ^ context->gpr[5];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_1001_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[5] = context->gpr[9] | context->gpr[5];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_1001_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[9] ^ context->gpr[5];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_1001_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[9] << 16;
	context->gpr[5] = context->gpr[5] >> 16;
	context->gpr[5] = context->scratch1 | context->gpr[5];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_1001_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[5] & 65535)) * ((uint32_t)(context->gpr[9] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_1001_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[5])) * ((int32_t)((int16_t)context->gpr[9])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_1010_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[5] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[5], context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_1010_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[5] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[5], context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_1010_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[5] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[5], context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_1010_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[5] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->gpr[5] = context->gpr[5] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_1010_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[5] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->gpr[5] = context->gpr[5] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_1010_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[5] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->gpr[5] = context->gpr[5] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_1010_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[5] >> 31;
	context->m = context->gpr[10] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_1010_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[5] & context->gpr[10];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_1010_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[5] = context->gpr[10] & context->gpr[5];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_1010_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[5] = context->gpr[10] ^ context->gpr[5];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_1010_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[5] = context->gpr[10] | context->gpr[5];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_1010_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[10] ^ context->gpr[5];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_1010_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[10] << 16;
	context->gpr[5] = context->gpr[5] >> 16;
	context->gpr[5] = context->scratch1 | context->gpr[5];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_1010_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[5] & 65535)) * ((uint32_t)(context->gpr[10] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_1010_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[5])) * ((int32_t)((int16_t)context->gpr[10])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_1011_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[5] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[5], context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_1011_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[5] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[5], context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_1011_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[5] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[5], context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_1011_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[5] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->gpr[5] = context->gpr[5] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_1011_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[5] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->gpr[5] = context->gpr[5] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_1011_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[5] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->gpr[5] = context->gpr[5] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_1011_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[5] >> 31;
	context->m = context->gpr[11] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_1011_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[5] & context->gpr[11];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_1011_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[5] = context->gpr[11] & context->gpr[5];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_1011_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[5] = context->gpr[11] ^ context->gpr[5];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_1011_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[5] = context->gpr[11] | context->gpr[5];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_1011_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[11] ^ context->gpr[5];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_1011_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[11] << 16;
	context->gpr[5] = context->gpr[5] >> 16;
	context->gpr[5] = context->scratch1 | context->gpr[5];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_1011_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[5] & 65535)) * ((uint32_t)(context->gpr[11] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_1011_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[5])) * ((int32_t)((int16_t)context->gpr[11])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_1100_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[5] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[5], context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_1100_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[5] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[5], context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_1100_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[5] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[5], context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_1100_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[5] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->gpr[5] = context->gpr[5] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_1100_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[5] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->gpr[5] = context->gpr[5] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_1100_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[5] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->gpr[5] = context->gpr[5] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_1100_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[5] >> 31;
	context->m = context->gpr[12] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_1100_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[5] & context->gpr[12];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_1100_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[5] = context->gpr[12] & context->gpr[5];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_1100_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[5] = context->gpr[12] ^ context->gpr[5];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_1100_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[5] = context->gpr[12] | context->gpr[5];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_1100_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[12] ^ context->gpr[5];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_1100_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[12] << 16;
	context->gpr[5] = context->gpr[5] >> 16;
	context->gpr[5] = context->scratch1 | context->gpr[5];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_1100_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[5] & 65535)) * ((uint32_t)(context->gpr[12] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_1100_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[5])) * ((int32_t)((int16_t)context->gpr[12])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_1101_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[5] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[5], context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_1101_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[5] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[5], context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_1101_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[5] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[5], context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_1101_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[5] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->gpr[5] = context->gpr[5] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_1101_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[5] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->gpr[5] = context->gpr[5] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_1101_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[5] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->gpr[5] = context->gpr[5] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_1101_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[5] >> 31;
	context->m = context->gpr[13] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_1101_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[5] & context->gpr[13];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_1101_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[5] = context->gpr[13] & context->gpr[5];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_1101_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[5] = context->gpr[13] ^ context->gpr[5];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_1101_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[5] = context->gpr[13] | context->gpr[5];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_1101_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[13] ^ context->gpr[5];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_1101_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[13] << 16;
	context->gpr[5] = context->gpr[5] >> 16;
	context->gpr[5] = context->scratch1 | context->gpr[5];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_1101_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[5] & 65535)) * ((uint32_t)(context->gpr[13] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_1101_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[5])) * ((int32_t)((int16_t)context->gpr[13])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_1110_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[5] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[5], context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_1110_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[5] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[5], context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_1110_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[5] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[5], context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_1110_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[5] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->gpr[5] = context->gpr[5] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_1110_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[5] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->gpr[5] = context->gpr[5] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_1110_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[5] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->gpr[5] = context->gpr[5] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_1110_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[5] >> 31;
	context->m = context->gpr[14] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_1110_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[5] & context->gpr[14];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_1110_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[5] = context->gpr[14] & context->gpr[5];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_1110_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[5] = context->gpr[14] ^ context->gpr[5];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_1110_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[5] = context->gpr[14] | context->gpr[5];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_1110_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[14] ^ context->gpr[5];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_1110_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[14] << 16;
	context->gpr[5] = context->gpr[5] >> 16;
	context->gpr[5] = context->scratch1 | context->gpr[5];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_1110_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[5] & 65535)) * ((uint32_t)(context->gpr[14] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_1110_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[5])) * ((int32_t)((int16_t)context->gpr[14])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_1111_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[5] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[5], context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_1111_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[5] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[5], context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_1111_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[5] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[5], context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_1111_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[5] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->gpr[5] = context->gpr[5] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_1111_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[5] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->gpr[5] = context->gpr[5] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_1111_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[5] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->gpr[5] = context->gpr[5] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_1111_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[5] >> 31;
	context->m = context->gpr[15] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_1111_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[5] & context->gpr[15];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_1111_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[5] = context->gpr[15] & context->gpr[5];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_1111_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[5] = context->gpr[15] ^ context->gpr[5];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_1111_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[5] = context->gpr[15] | context->gpr[5];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_1111_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[15] ^ context->gpr[5];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_1111_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[15] << 16;
	context->gpr[5] = context->gpr[5] >> 16;
	context->gpr[5] = context->scratch1 | context->gpr[5];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_1111_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[5] & 65535)) * ((uint32_t)(context->gpr[15] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_1111_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[5])) * ((int32_t)((int16_t)context->gpr[15])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_0000_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[6] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[6], context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_0000_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[6] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[6], context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_0000_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[6] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[6], context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_0000_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[6] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->gpr[6] = context->gpr[6] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_0000_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[6] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->gpr[6] = context->gpr[6] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_0000_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[6] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->gpr[6] = context->gpr[6] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_0000_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[6] >> 31;
	context->m = context->gpr[0] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_0000_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[6] & context->gpr[0];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_0000_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[6] = context->gpr[0] & context->gpr[6];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_0000_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[6] = context->gpr[0] ^ context->gpr[6];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_0000_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[6] = context->gpr[0] | context->gpr[6];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_0000_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[0] ^ context->gpr[6];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_0000_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] << 16;
	context->gpr[6] = context->gpr[6] >> 16;
	context->gpr[6] = context->scratch1 | context->gpr[6];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_0000_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[6] & 65535)) * ((uint32_t)(context->gpr[0] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_0000_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[6])) * ((int32_t)((int16_t)context->gpr[0])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_0001_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[6] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[6], context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_0001_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[6] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[6], context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_0001_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[6] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[6], context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_0001_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[6] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->gpr[6] = context->gpr[6] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_0001_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[6] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->gpr[6] = context->gpr[6] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_0001_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[6] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->gpr[6] = context->gpr[6] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_0001_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[6] >> 31;
	context->m = context->gpr[1] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_0001_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[6] & context->gpr[1];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_0001_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[6] = context->gpr[1] & context->gpr[6];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_0001_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[6] = context->gpr[1] ^ context->gpr[6];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_0001_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[6] = context->gpr[1] | context->gpr[6];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_0001_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[1] ^ context->gpr[6];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_0001_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[1] << 16;
	context->gpr[6] = context->gpr[6] >> 16;
	context->gpr[6] = context->scratch1 | context->gpr[6];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_0001_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[6] & 65535)) * ((uint32_t)(context->gpr[1] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_0001_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[6])) * ((int32_t)((int16_t)context->gpr[1])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_0010_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[6] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[6], context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_0010_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[6] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[6], context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_0010_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[6] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[6], context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_0010_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[6] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->gpr[6] = context->gpr[6] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_0010_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[6] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->gpr[6] = context->gpr[6] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_0010_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[6] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->gpr[6] = context->gpr[6] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_0010_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[6] >> 31;
	context->m = context->gpr[2] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_0010_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[6] & context->gpr[2];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_0010_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[6] = context->gpr[2] & context->gpr[6];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_0010_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[6] = context->gpr[2] ^ context->gpr[6];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_0010_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[6] = context->gpr[2] | context->gpr[6];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_0010_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[2] ^ context->gpr[6];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_0010_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[2] << 16;
	context->gpr[6] = context->gpr[6] >> 16;
	context->gpr[6] = context->scratch1 | context->gpr[6];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_0010_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[6] & 65535)) * ((uint32_t)(context->gpr[2] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_0010_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[6])) * ((int32_t)((int16_t)context->gpr[2])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_0011_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[6] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[6], context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_0011_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[6] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[6], context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_0011_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[6] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[6], context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_0011_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[6] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->gpr[6] = context->gpr[6] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_0011_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[6] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->gpr[6] = context->gpr[6] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_0011_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[6] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->gpr[6] = context->gpr[6] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_0011_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[6] >> 31;
	context->m = context->gpr[3] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_0011_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[6] & context->gpr[3];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_0011_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[6] = context->gpr[3] & context->gpr[6];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_0011_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[6] = context->gpr[3] ^ context->gpr[6];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_0011_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[6] = context->gpr[3] | context->gpr[6];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_0011_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[3] ^ context->gpr[6];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_0011_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[3] << 16;
	context->gpr[6] = context->gpr[6] >> 16;
	context->gpr[6] = context->scratch1 | context->gpr[6];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_0011_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[6] & 65535)) * ((uint32_t)(context->gpr[3] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_0011_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[6])) * ((int32_t)((int16_t)context->gpr[3])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_0100_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[6] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[6], context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_0100_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[6] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[6], context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_0100_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[6] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[6], context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_0100_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[6] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->gpr[6] = context->gpr[6] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_0100_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[6] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->gpr[6] = context->gpr[6] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_0100_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[6] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->gpr[6] = context->gpr[6] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_0100_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[6] >> 31;
	context->m = context->gpr[4] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_0100_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[6] & context->gpr[4];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_0100_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[6] = context->gpr[4] & context->gpr[6];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_0100_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[6] = context->gpr[4] ^ context->gpr[6];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_0100_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[6] = context->gpr[4] | context->gpr[6];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_0100_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[4] ^ context->gpr[6];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_0100_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[4] << 16;
	context->gpr[6] = context->gpr[6] >> 16;
	context->gpr[6] = context->scratch1 | context->gpr[6];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_0100_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[6] & 65535)) * ((uint32_t)(context->gpr[4] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_0100_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[6])) * ((int32_t)((int16_t)context->gpr[4])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_0101_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[6] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[6], context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_0101_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[6] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[6], context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_0101_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[6] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[6], context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_0101_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[6] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->gpr[6] = context->gpr[6] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_0101_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[6] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->gpr[6] = context->gpr[6] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_0101_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[6] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->gpr[6] = context->gpr[6] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_0101_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[6] >> 31;
	context->m = context->gpr[5] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_0101_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[6] & context->gpr[5];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_0101_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[6] = context->gpr[5] & context->gpr[6];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_0101_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[6] = context->gpr[5] ^ context->gpr[6];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_0101_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[6] = context->gpr[5] | context->gpr[6];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_0101_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[5] ^ context->gpr[6];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_0101_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[5] << 16;
	context->gpr[6] = context->gpr[6] >> 16;
	context->gpr[6] = context->scratch1 | context->gpr[6];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_0101_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[6] & 65535)) * ((uint32_t)(context->gpr[5] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_0101_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[6])) * ((int32_t)((int16_t)context->gpr[5])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_0110_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[6] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[6], context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_0110_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[6] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[6], context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_0110_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[6] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[6], context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_0110_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[6] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->gpr[6] = context->gpr[6] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_0110_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[6] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->gpr[6] = context->gpr[6] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_0110_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[6] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->gpr[6] = context->gpr[6] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_0110_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[6] >> 31;
	context->m = context->gpr[6] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_0110_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[6] & context->gpr[6];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_0110_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[6] = context->gpr[6] & context->gpr[6];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_0110_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[6] = context->gpr[6] ^ context->gpr[6];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_0110_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[6] = context->gpr[6] | context->gpr[6];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_0110_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[6] ^ context->gpr[6];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_0110_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[6] << 16;
	context->gpr[6] = context->gpr[6] >> 16;
	context->gpr[6] = context->scratch1 | context->gpr[6];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_0110_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[6] & 65535)) * ((uint32_t)(context->gpr[6] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_0110_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[6])) * ((int32_t)((int16_t)context->gpr[6])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_0111_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[6] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[6], context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_0111_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[6] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[6], context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_0111_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[6] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[6], context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_0111_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[6] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->gpr[6] = context->gpr[6] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_0111_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[6] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->gpr[6] = context->gpr[6] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_0111_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[6] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->gpr[6] = context->gpr[6] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_0111_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[6] >> 31;
	context->m = context->gpr[7] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_0111_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[6] & context->gpr[7];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_0111_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[6] = context->gpr[7] & context->gpr[6];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_0111_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[6] = context->gpr[7] ^ context->gpr[6];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_0111_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[6] = context->gpr[7] | context->gpr[6];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_0111_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[7] ^ context->gpr[6];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_0111_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[7] << 16;
	context->gpr[6] = context->gpr[6] >> 16;
	context->gpr[6] = context->scratch1 | context->gpr[6];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_0111_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[6] & 65535)) * ((uint32_t)(context->gpr[7] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_0111_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[6])) * ((int32_t)((int16_t)context->gpr[7])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_1000_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[6] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[6], context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_1000_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[6] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[6], context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_1000_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[6] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[6], context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_1000_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[6] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->gpr[6] = context->gpr[6] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_1000_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[6] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->gpr[6] = context->gpr[6] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_1000_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[6] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->gpr[6] = context->gpr[6] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_1000_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[6] >> 31;
	context->m = context->gpr[8] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_1000_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[6] & context->gpr[8];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_1000_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[6] = context->gpr[8] & context->gpr[6];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_1000_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[6] = context->gpr[8] ^ context->gpr[6];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_1000_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[6] = context->gpr[8] | context->gpr[6];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_1000_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[8] ^ context->gpr[6];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_1000_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[8] << 16;
	context->gpr[6] = context->gpr[6] >> 16;
	context->gpr[6] = context->scratch1 | context->gpr[6];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_1000_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[6] & 65535)) * ((uint32_t)(context->gpr[8] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_1000_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[6])) * ((int32_t)((int16_t)context->gpr[8])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_1001_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[6] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[6], context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_1001_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[6] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[6], context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_1001_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[6] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[6], context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_1001_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[6] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->gpr[6] = context->gpr[6] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_1001_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[6] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->gpr[6] = context->gpr[6] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_1001_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[6] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->gpr[6] = context->gpr[6] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_1001_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[6] >> 31;
	context->m = context->gpr[9] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_1001_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[6] & context->gpr[9];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_1001_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[6] = context->gpr[9] & context->gpr[6];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_1001_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[6] = context->gpr[9] ^ context->gpr[6];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_1001_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[6] = context->gpr[9] | context->gpr[6];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_1001_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[9] ^ context->gpr[6];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_1001_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[9] << 16;
	context->gpr[6] = context->gpr[6] >> 16;
	context->gpr[6] = context->scratch1 | context->gpr[6];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_1001_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[6] & 65535)) * ((uint32_t)(context->gpr[9] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_1001_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[6])) * ((int32_t)((int16_t)context->gpr[9])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_1010_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[6] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[6], context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_1010_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[6] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[6], context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_1010_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[6] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[6], context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_1010_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[6] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->gpr[6] = context->gpr[6] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_1010_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[6] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->gpr[6] = context->gpr[6] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_1010_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[6] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->gpr[6] = context->gpr[6] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_1010_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[6] >> 31;
	context->m = context->gpr[10] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_1010_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[6] & context->gpr[10];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_1010_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[6] = context->gpr[10] & context->gpr[6];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_1010_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[6] = context->gpr[10] ^ context->gpr[6];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_1010_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[6] = context->gpr[10] | context->gpr[6];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_1010_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[10] ^ context->gpr[6];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_1010_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[10] << 16;
	context->gpr[6] = context->gpr[6] >> 16;
	context->gpr[6] = context->scratch1 | context->gpr[6];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_1010_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[6] & 65535)) * ((uint32_t)(context->gpr[10] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_1010_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[6])) * ((int32_t)((int16_t)context->gpr[10])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_1011_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[6] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[6], context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_1011_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[6] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[6], context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_1011_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[6] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[6], context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_1011_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[6] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->gpr[6] = context->gpr[6] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_1011_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[6] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->gpr[6] = context->gpr[6] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_1011_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[6] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->gpr[6] = context->gpr[6] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_1011_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[6] >> 31;
	context->m = context->gpr[11] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_1011_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[6] & context->gpr[11];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_1011_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[6] = context->gpr[11] & context->gpr[6];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_1011_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[6] = context->gpr[11] ^ context->gpr[6];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_1011_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[6] = context->gpr[11] | context->gpr[6];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_1011_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[11] ^ context->gpr[6];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_1011_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[11] << 16;
	context->gpr[6] = context->gpr[6] >> 16;
	context->gpr[6] = context->scratch1 | context->gpr[6];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_1011_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[6] & 65535)) * ((uint32_t)(context->gpr[11] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_1011_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[6])) * ((int32_t)((int16_t)context->gpr[11])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_1100_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[6] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[6], context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_1100_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[6] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[6], context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_1100_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[6] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[6], context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_1100_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[6] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->gpr[6] = context->gpr[6] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_1100_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[6] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->gpr[6] = context->gpr[6] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_1100_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[6] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->gpr[6] = context->gpr[6] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_1100_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[6] >> 31;
	context->m = context->gpr[12] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_1100_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[6] & context->gpr[12];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_1100_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[6] = context->gpr[12] & context->gpr[6];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_1100_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[6] = context->gpr[12] ^ context->gpr[6];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_1100_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[6] = context->gpr[12] | context->gpr[6];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_1100_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[12] ^ context->gpr[6];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_1100_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[12] << 16;
	context->gpr[6] = context->gpr[6] >> 16;
	context->gpr[6] = context->scratch1 | context->gpr[6];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_1100_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[6] & 65535)) * ((uint32_t)(context->gpr[12] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_1100_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[6])) * ((int32_t)((int16_t)context->gpr[12])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_1101_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[6] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[6], context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_1101_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[6] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[6], context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_1101_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[6] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[6], context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_1101_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[6] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->gpr[6] = context->gpr[6] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_1101_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[6] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->gpr[6] = context->gpr[6] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_1101_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[6] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->gpr[6] = context->gpr[6] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_1101_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[6] >> 31;
	context->m = context->gpr[13] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_1101_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[6] & context->gpr[13];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_1101_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[6] = context->gpr[13] & context->gpr[6];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_1101_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[6] = context->gpr[13] ^ context->gpr[6];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_1101_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[6] = context->gpr[13] | context->gpr[6];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_1101_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[13] ^ context->gpr[6];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_1101_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[13] << 16;
	context->gpr[6] = context->gpr[6] >> 16;
	context->gpr[6] = context->scratch1 | context->gpr[6];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_1101_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[6] & 65535)) * ((uint32_t)(context->gpr[13] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_1101_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[6])) * ((int32_t)((int16_t)context->gpr[13])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_1110_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[6] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[6], context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_1110_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[6] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[6], context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_1110_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[6] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[6], context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_1110_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[6] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->gpr[6] = context->gpr[6] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_1110_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[6] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->gpr[6] = context->gpr[6] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_1110_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[6] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->gpr[6] = context->gpr[6] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_1110_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[6] >> 31;
	context->m = context->gpr[14] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_1110_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[6] & context->gpr[14];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_1110_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[6] = context->gpr[14] & context->gpr[6];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_1110_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[6] = context->gpr[14] ^ context->gpr[6];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_1110_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[6] = context->gpr[14] | context->gpr[6];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_1110_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[14] ^ context->gpr[6];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_1110_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[14] << 16;
	context->gpr[6] = context->gpr[6] >> 16;
	context->gpr[6] = context->scratch1 | context->gpr[6];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_1110_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[6] & 65535)) * ((uint32_t)(context->gpr[14] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_1110_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[6])) * ((int32_t)((int16_t)context->gpr[14])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_1111_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[6] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[6], context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_1111_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[6] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[6], context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_1111_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[6] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[6], context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_1111_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[6] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->gpr[6] = context->gpr[6] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_1111_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[6] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->gpr[6] = context->gpr[6] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_1111_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[6] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->gpr[6] = context->gpr[6] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_1111_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[6] >> 31;
	context->m = context->gpr[15] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_1111_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[6] & context->gpr[15];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_1111_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[6] = context->gpr[15] & context->gpr[6];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_1111_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[6] = context->gpr[15] ^ context->gpr[6];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_1111_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[6] = context->gpr[15] | context->gpr[6];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_1111_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[15] ^ context->gpr[6];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_1111_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[15] << 16;
	context->gpr[6] = context->gpr[6] >> 16;
	context->gpr[6] = context->scratch1 | context->gpr[6];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_1111_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[6] & 65535)) * ((uint32_t)(context->gpr[15] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_1111_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[6])) * ((int32_t)((int16_t)context->gpr[15])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_0000_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[7] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[7], context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_0000_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[7] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[7], context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_0000_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[7] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[7], context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_0000_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[7] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->gpr[7] = context->gpr[7] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_0000_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[7] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->gpr[7] = context->gpr[7] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_0000_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[7] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->gpr[7] = context->gpr[7] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_0000_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[7] >> 31;
	context->m = context->gpr[0] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_0000_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[7] & context->gpr[0];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_0000_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[7] = context->gpr[0] & context->gpr[7];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_0000_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[7] = context->gpr[0] ^ context->gpr[7];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_0000_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[7] = context->gpr[0] | context->gpr[7];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_0000_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[0] ^ context->gpr[7];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_0000_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] << 16;
	context->gpr[7] = context->gpr[7] >> 16;
	context->gpr[7] = context->scratch1 | context->gpr[7];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_0000_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[7] & 65535)) * ((uint32_t)(context->gpr[0] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_0000_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[7])) * ((int32_t)((int16_t)context->gpr[0])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_0001_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[7] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[7], context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_0001_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[7] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[7], context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_0001_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[7] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[7], context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_0001_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[7] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->gpr[7] = context->gpr[7] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_0001_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[7] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->gpr[7] = context->gpr[7] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_0001_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[7] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->gpr[7] = context->gpr[7] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_0001_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[7] >> 31;
	context->m = context->gpr[1] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_0001_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[7] & context->gpr[1];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_0001_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[7] = context->gpr[1] & context->gpr[7];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_0001_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[7] = context->gpr[1] ^ context->gpr[7];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_0001_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[7] = context->gpr[1] | context->gpr[7];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_0001_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[1] ^ context->gpr[7];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_0001_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[1] << 16;
	context->gpr[7] = context->gpr[7] >> 16;
	context->gpr[7] = context->scratch1 | context->gpr[7];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_0001_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[7] & 65535)) * ((uint32_t)(context->gpr[1] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_0001_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[7])) * ((int32_t)((int16_t)context->gpr[1])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_0010_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[7] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[7], context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_0010_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[7] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[7], context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_0010_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[7] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[7], context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_0010_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[7] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->gpr[7] = context->gpr[7] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_0010_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[7] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->gpr[7] = context->gpr[7] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_0010_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[7] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->gpr[7] = context->gpr[7] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_0010_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[7] >> 31;
	context->m = context->gpr[2] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_0010_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[7] & context->gpr[2];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_0010_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[7] = context->gpr[2] & context->gpr[7];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_0010_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[7] = context->gpr[2] ^ context->gpr[7];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_0010_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[7] = context->gpr[2] | context->gpr[7];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_0010_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[2] ^ context->gpr[7];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_0010_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[2] << 16;
	context->gpr[7] = context->gpr[7] >> 16;
	context->gpr[7] = context->scratch1 | context->gpr[7];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_0010_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[7] & 65535)) * ((uint32_t)(context->gpr[2] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_0010_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[7])) * ((int32_t)((int16_t)context->gpr[2])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_0011_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[7] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[7], context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_0011_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[7] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[7], context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_0011_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[7] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[7], context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_0011_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[7] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->gpr[7] = context->gpr[7] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_0011_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[7] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->gpr[7] = context->gpr[7] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_0011_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[7] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->gpr[7] = context->gpr[7] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_0011_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[7] >> 31;
	context->m = context->gpr[3] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_0011_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[7] & context->gpr[3];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_0011_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[7] = context->gpr[3] & context->gpr[7];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_0011_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[7] = context->gpr[3] ^ context->gpr[7];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_0011_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[7] = context->gpr[3] | context->gpr[7];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_0011_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[3] ^ context->gpr[7];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_0011_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[3] << 16;
	context->gpr[7] = context->gpr[7] >> 16;
	context->gpr[7] = context->scratch1 | context->gpr[7];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_0011_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[7] & 65535)) * ((uint32_t)(context->gpr[3] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_0011_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[7])) * ((int32_t)((int16_t)context->gpr[3])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_0100_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[7] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[7], context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_0100_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[7] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[7], context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_0100_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[7] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[7], context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_0100_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[7] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->gpr[7] = context->gpr[7] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_0100_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[7] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->gpr[7] = context->gpr[7] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_0100_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[7] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->gpr[7] = context->gpr[7] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_0100_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[7] >> 31;
	context->m = context->gpr[4] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_0100_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[7] & context->gpr[4];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_0100_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[7] = context->gpr[4] & context->gpr[7];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_0100_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[7] = context->gpr[4] ^ context->gpr[7];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_0100_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[7] = context->gpr[4] | context->gpr[7];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_0100_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[4] ^ context->gpr[7];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_0100_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[4] << 16;
	context->gpr[7] = context->gpr[7] >> 16;
	context->gpr[7] = context->scratch1 | context->gpr[7];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_0100_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[7] & 65535)) * ((uint32_t)(context->gpr[4] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_0100_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[7])) * ((int32_t)((int16_t)context->gpr[4])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_0101_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[7] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[7], context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_0101_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[7] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[7], context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_0101_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[7] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[7], context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_0101_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[7] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->gpr[7] = context->gpr[7] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_0101_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[7] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->gpr[7] = context->gpr[7] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_0101_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[7] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->gpr[7] = context->gpr[7] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_0101_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[7] >> 31;
	context->m = context->gpr[5] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_0101_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[7] & context->gpr[5];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_0101_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[7] = context->gpr[5] & context->gpr[7];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_0101_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[7] = context->gpr[5] ^ context->gpr[7];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_0101_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[7] = context->gpr[5] | context->gpr[7];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_0101_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[5] ^ context->gpr[7];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_0101_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[5] << 16;
	context->gpr[7] = context->gpr[7] >> 16;
	context->gpr[7] = context->scratch1 | context->gpr[7];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_0101_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[7] & 65535)) * ((uint32_t)(context->gpr[5] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_0101_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[7])) * ((int32_t)((int16_t)context->gpr[5])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_0110_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[7] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[7], context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_0110_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[7] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[7], context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_0110_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[7] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[7], context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_0110_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[7] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->gpr[7] = context->gpr[7] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_0110_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[7] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->gpr[7] = context->gpr[7] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_0110_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[7] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->gpr[7] = context->gpr[7] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_0110_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[7] >> 31;
	context->m = context->gpr[6] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_0110_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[7] & context->gpr[6];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_0110_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[7] = context->gpr[6] & context->gpr[7];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_0110_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[7] = context->gpr[6] ^ context->gpr[7];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_0110_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[7] = context->gpr[6] | context->gpr[7];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_0110_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[6] ^ context->gpr[7];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_0110_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[6] << 16;
	context->gpr[7] = context->gpr[7] >> 16;
	context->gpr[7] = context->scratch1 | context->gpr[7];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_0110_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[7] & 65535)) * ((uint32_t)(context->gpr[6] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_0110_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[7])) * ((int32_t)((int16_t)context->gpr[6])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_0111_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[7] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[7], context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_0111_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[7] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[7], context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_0111_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[7] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[7], context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_0111_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[7] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->gpr[7] = context->gpr[7] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_0111_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[7] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->gpr[7] = context->gpr[7] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_0111_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[7] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->gpr[7] = context->gpr[7] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_0111_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[7] >> 31;
	context->m = context->gpr[7] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_0111_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[7] & context->gpr[7];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_0111_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[7] = context->gpr[7] & context->gpr[7];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_0111_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[7] = context->gpr[7] ^ context->gpr[7];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_0111_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[7] = context->gpr[7] | context->gpr[7];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_0111_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[7] ^ context->gpr[7];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_0111_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[7] << 16;
	context->gpr[7] = context->gpr[7] >> 16;
	context->gpr[7] = context->scratch1 | context->gpr[7];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_0111_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[7] & 65535)) * ((uint32_t)(context->gpr[7] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_0111_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[7])) * ((int32_t)((int16_t)context->gpr[7])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_1000_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[7] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[7], context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_1000_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[7] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[7], context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_1000_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[7] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[7], context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_1000_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[7] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->gpr[7] = context->gpr[7] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_1000_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[7] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->gpr[7] = context->gpr[7] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_1000_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[7] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->gpr[7] = context->gpr[7] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_1000_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[7] >> 31;
	context->m = context->gpr[8] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_1000_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[7] & context->gpr[8];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_1000_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[7] = context->gpr[8] & context->gpr[7];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_1000_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[7] = context->gpr[8] ^ context->gpr[7];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_1000_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[7] = context->gpr[8] | context->gpr[7];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_1000_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[8] ^ context->gpr[7];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_1000_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[8] << 16;
	context->gpr[7] = context->gpr[7] >> 16;
	context->gpr[7] = context->scratch1 | context->gpr[7];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_1000_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[7] & 65535)) * ((uint32_t)(context->gpr[8] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_1000_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[7])) * ((int32_t)((int16_t)context->gpr[8])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_1001_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[7] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[7], context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_1001_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[7] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[7], context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_1001_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[7] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[7], context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_1001_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[7] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->gpr[7] = context->gpr[7] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_1001_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[7] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->gpr[7] = context->gpr[7] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_1001_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[7] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->gpr[7] = context->gpr[7] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_1001_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[7] >> 31;
	context->m = context->gpr[9] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_1001_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[7] & context->gpr[9];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_1001_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[7] = context->gpr[9] & context->gpr[7];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_1001_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[7] = context->gpr[9] ^ context->gpr[7];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_1001_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[7] = context->gpr[9] | context->gpr[7];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_1001_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[9] ^ context->gpr[7];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_1001_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[9] << 16;
	context->gpr[7] = context->gpr[7] >> 16;
	context->gpr[7] = context->scratch1 | context->gpr[7];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_1001_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[7] & 65535)) * ((uint32_t)(context->gpr[9] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_1001_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[7])) * ((int32_t)((int16_t)context->gpr[9])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_1010_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[7] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[7], context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_1010_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[7] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[7], context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_1010_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[7] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[7], context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_1010_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[7] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->gpr[7] = context->gpr[7] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_1010_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[7] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->gpr[7] = context->gpr[7] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_1010_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[7] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->gpr[7] = context->gpr[7] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_1010_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[7] >> 31;
	context->m = context->gpr[10] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_1010_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[7] & context->gpr[10];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_1010_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[7] = context->gpr[10] & context->gpr[7];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_1010_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[7] = context->gpr[10] ^ context->gpr[7];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_1010_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[7] = context->gpr[10] | context->gpr[7];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_1010_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[10] ^ context->gpr[7];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_1010_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[10] << 16;
	context->gpr[7] = context->gpr[7] >> 16;
	context->gpr[7] = context->scratch1 | context->gpr[7];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_1010_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[7] & 65535)) * ((uint32_t)(context->gpr[10] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_1010_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[7])) * ((int32_t)((int16_t)context->gpr[10])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_1011_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[7] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[7], context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_1011_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[7] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[7], context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_1011_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[7] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[7], context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_1011_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[7] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->gpr[7] = context->gpr[7] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_1011_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[7] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->gpr[7] = context->gpr[7] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_1011_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[7] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->gpr[7] = context->gpr[7] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_1011_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[7] >> 31;
	context->m = context->gpr[11] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_1011_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[7] & context->gpr[11];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_1011_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[7] = context->gpr[11] & context->gpr[7];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_1011_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[7] = context->gpr[11] ^ context->gpr[7];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_1011_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[7] = context->gpr[11] | context->gpr[7];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_1011_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[11] ^ context->gpr[7];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_1011_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[11] << 16;
	context->gpr[7] = context->gpr[7] >> 16;
	context->gpr[7] = context->scratch1 | context->gpr[7];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_1011_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[7] & 65535)) * ((uint32_t)(context->gpr[11] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_1011_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[7])) * ((int32_t)((int16_t)context->gpr[11])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_1100_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[7] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[7], context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_1100_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[7] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[7], context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_1100_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[7] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[7], context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_1100_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[7] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->gpr[7] = context->gpr[7] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_1100_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[7] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->gpr[7] = context->gpr[7] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_1100_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[7] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->gpr[7] = context->gpr[7] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_1100_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[7] >> 31;
	context->m = context->gpr[12] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_1100_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[7] & context->gpr[12];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_1100_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[7] = context->gpr[12] & context->gpr[7];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_1100_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[7] = context->gpr[12] ^ context->gpr[7];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_1100_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[7] = context->gpr[12] | context->gpr[7];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_1100_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[12] ^ context->gpr[7];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_1100_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[12] << 16;
	context->gpr[7] = context->gpr[7] >> 16;
	context->gpr[7] = context->scratch1 | context->gpr[7];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_1100_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[7] & 65535)) * ((uint32_t)(context->gpr[12] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_1100_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[7])) * ((int32_t)((int16_t)context->gpr[12])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_1101_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[7] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[7], context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_1101_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[7] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[7], context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_1101_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[7] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[7], context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_1101_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[7] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->gpr[7] = context->gpr[7] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_1101_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[7] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->gpr[7] = context->gpr[7] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_1101_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[7] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->gpr[7] = context->gpr[7] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_1101_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[7] >> 31;
	context->m = context->gpr[13] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_1101_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[7] & context->gpr[13];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_1101_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[7] = context->gpr[13] & context->gpr[7];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_1101_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[7] = context->gpr[13] ^ context->gpr[7];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_1101_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[7] = context->gpr[13] | context->gpr[7];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_1101_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[13] ^ context->gpr[7];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_1101_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[13] << 16;
	context->gpr[7] = context->gpr[7] >> 16;
	context->gpr[7] = context->scratch1 | context->gpr[7];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_1101_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[7] & 65535)) * ((uint32_t)(context->gpr[13] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_1101_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[7])) * ((int32_t)((int16_t)context->gpr[13])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_1110_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[7] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[7], context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_1110_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[7] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[7], context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_1110_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[7] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[7], context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_1110_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[7] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->gpr[7] = context->gpr[7] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_1110_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[7] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->gpr[7] = context->gpr[7] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_1110_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[7] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->gpr[7] = context->gpr[7] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_1110_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[7] >> 31;
	context->m = context->gpr[14] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_1110_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[7] & context->gpr[14];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_1110_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[7] = context->gpr[14] & context->gpr[7];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_1110_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[7] = context->gpr[14] ^ context->gpr[7];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_1110_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[7] = context->gpr[14] | context->gpr[7];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_1110_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[14] ^ context->gpr[7];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_1110_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[14] << 16;
	context->gpr[7] = context->gpr[7] >> 16;
	context->gpr[7] = context->scratch1 | context->gpr[7];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_1110_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[7] & 65535)) * ((uint32_t)(context->gpr[14] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_1110_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[7])) * ((int32_t)((int16_t)context->gpr[14])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_1111_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[7] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[7], context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_1111_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[7] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[7], context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_1111_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[7] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[7], context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_1111_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[7] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->gpr[7] = context->gpr[7] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_1111_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[7] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->gpr[7] = context->gpr[7] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_1111_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[7] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->gpr[7] = context->gpr[7] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_1111_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[7] >> 31;
	context->m = context->gpr[15] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_1111_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[7] & context->gpr[15];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_1111_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[7] = context->gpr[15] & context->gpr[7];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_1111_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[7] = context->gpr[15] ^ context->gpr[7];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_1111_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[7] = context->gpr[15] | context->gpr[7];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_1111_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[15] ^ context->gpr[7];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_1111_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[15] << 16;
	context->gpr[7] = context->gpr[7] >> 16;
	context->gpr[7] = context->scratch1 | context->gpr[7];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_1111_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[7] & 65535)) * ((uint32_t)(context->gpr[15] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_1111_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[7])) * ((int32_t)((int16_t)context->gpr[15])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_0000_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[8] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[8], context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_0000_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[8] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[8], context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_0000_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[8] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[8], context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_0000_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[8] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->gpr[8] = context->gpr[8] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_0000_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[8] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->gpr[8] = context->gpr[8] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_0000_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[8] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->gpr[8] = context->gpr[8] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_0000_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[8] >> 31;
	context->m = context->gpr[0] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_0000_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[8] & context->gpr[0];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_0000_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[8] = context->gpr[0] & context->gpr[8];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_0000_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[8] = context->gpr[0] ^ context->gpr[8];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_0000_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[8] = context->gpr[0] | context->gpr[8];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_0000_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[0] ^ context->gpr[8];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_0000_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] << 16;
	context->gpr[8] = context->gpr[8] >> 16;
	context->gpr[8] = context->scratch1 | context->gpr[8];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_0000_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[8] & 65535)) * ((uint32_t)(context->gpr[0] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_0000_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[8])) * ((int32_t)((int16_t)context->gpr[0])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_0001_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[8] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[8], context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_0001_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[8] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[8], context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_0001_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[8] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[8], context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_0001_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[8] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->gpr[8] = context->gpr[8] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_0001_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[8] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->gpr[8] = context->gpr[8] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_0001_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[8] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->gpr[8] = context->gpr[8] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_0001_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[8] >> 31;
	context->m = context->gpr[1] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_0001_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[8] & context->gpr[1];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_0001_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[8] = context->gpr[1] & context->gpr[8];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_0001_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[8] = context->gpr[1] ^ context->gpr[8];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_0001_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[8] = context->gpr[1] | context->gpr[8];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_0001_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[1] ^ context->gpr[8];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_0001_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[1] << 16;
	context->gpr[8] = context->gpr[8] >> 16;
	context->gpr[8] = context->scratch1 | context->gpr[8];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_0001_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[8] & 65535)) * ((uint32_t)(context->gpr[1] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_0001_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[8])) * ((int32_t)((int16_t)context->gpr[1])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_0010_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[8] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[8], context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_0010_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[8] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[8], context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_0010_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[8] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[8], context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_0010_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[8] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->gpr[8] = context->gpr[8] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_0010_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[8] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->gpr[8] = context->gpr[8] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_0010_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[8] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->gpr[8] = context->gpr[8] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_0010_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[8] >> 31;
	context->m = context->gpr[2] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_0010_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[8] & context->gpr[2];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_0010_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[8] = context->gpr[2] & context->gpr[8];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_0010_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[8] = context->gpr[2] ^ context->gpr[8];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_0010_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[8] = context->gpr[2] | context->gpr[8];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_0010_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[2] ^ context->gpr[8];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_0010_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[2] << 16;
	context->gpr[8] = context->gpr[8] >> 16;
	context->gpr[8] = context->scratch1 | context->gpr[8];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_0010_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[8] & 65535)) * ((uint32_t)(context->gpr[2] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_0010_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[8])) * ((int32_t)((int16_t)context->gpr[2])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_0011_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[8] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[8], context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_0011_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[8] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[8], context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_0011_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[8] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[8], context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_0011_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[8] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->gpr[8] = context->gpr[8] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_0011_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[8] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->gpr[8] = context->gpr[8] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_0011_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[8] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->gpr[8] = context->gpr[8] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_0011_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[8] >> 31;
	context->m = context->gpr[3] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_0011_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[8] & context->gpr[3];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_0011_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[8] = context->gpr[3] & context->gpr[8];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_0011_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[8] = context->gpr[3] ^ context->gpr[8];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_0011_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[8] = context->gpr[3] | context->gpr[8];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_0011_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[3] ^ context->gpr[8];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_0011_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[3] << 16;
	context->gpr[8] = context->gpr[8] >> 16;
	context->gpr[8] = context->scratch1 | context->gpr[8];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_0011_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[8] & 65535)) * ((uint32_t)(context->gpr[3] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_0011_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[8])) * ((int32_t)((int16_t)context->gpr[3])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_0100_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[8] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[8], context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_0100_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[8] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[8], context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_0100_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[8] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[8], context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_0100_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[8] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->gpr[8] = context->gpr[8] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_0100_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[8] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->gpr[8] = context->gpr[8] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_0100_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[8] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->gpr[8] = context->gpr[8] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_0100_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[8] >> 31;
	context->m = context->gpr[4] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_0100_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[8] & context->gpr[4];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_0100_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[8] = context->gpr[4] & context->gpr[8];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_0100_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[8] = context->gpr[4] ^ context->gpr[8];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_0100_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[8] = context->gpr[4] | context->gpr[8];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_0100_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[4] ^ context->gpr[8];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_0100_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[4] << 16;
	context->gpr[8] = context->gpr[8] >> 16;
	context->gpr[8] = context->scratch1 | context->gpr[8];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_0100_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[8] & 65535)) * ((uint32_t)(context->gpr[4] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_0100_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[8])) * ((int32_t)((int16_t)context->gpr[4])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_0101_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[8] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[8], context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_0101_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[8] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[8], context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_0101_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[8] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[8], context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_0101_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[8] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->gpr[8] = context->gpr[8] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_0101_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[8] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->gpr[8] = context->gpr[8] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_0101_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[8] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->gpr[8] = context->gpr[8] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_0101_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[8] >> 31;
	context->m = context->gpr[5] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_0101_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[8] & context->gpr[5];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_0101_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[8] = context->gpr[5] & context->gpr[8];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_0101_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[8] = context->gpr[5] ^ context->gpr[8];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_0101_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[8] = context->gpr[5] | context->gpr[8];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_0101_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[5] ^ context->gpr[8];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_0101_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[5] << 16;
	context->gpr[8] = context->gpr[8] >> 16;
	context->gpr[8] = context->scratch1 | context->gpr[8];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_0101_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[8] & 65535)) * ((uint32_t)(context->gpr[5] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_0101_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[8])) * ((int32_t)((int16_t)context->gpr[5])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_0110_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[8] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[8], context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_0110_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[8] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[8], context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_0110_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[8] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[8], context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_0110_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[8] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->gpr[8] = context->gpr[8] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_0110_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[8] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->gpr[8] = context->gpr[8] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_0110_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[8] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->gpr[8] = context->gpr[8] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_0110_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[8] >> 31;
	context->m = context->gpr[6] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_0110_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[8] & context->gpr[6];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_0110_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[8] = context->gpr[6] & context->gpr[8];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_0110_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[8] = context->gpr[6] ^ context->gpr[8];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_0110_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[8] = context->gpr[6] | context->gpr[8];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_0110_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[6] ^ context->gpr[8];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_0110_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[6] << 16;
	context->gpr[8] = context->gpr[8] >> 16;
	context->gpr[8] = context->scratch1 | context->gpr[8];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_0110_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[8] & 65535)) * ((uint32_t)(context->gpr[6] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_0110_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[8])) * ((int32_t)((int16_t)context->gpr[6])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_0111_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[8] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[8], context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_0111_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[8] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[8], context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_0111_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[8] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[8], context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_0111_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[8] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->gpr[8] = context->gpr[8] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_0111_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[8] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->gpr[8] = context->gpr[8] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_0111_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[8] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->gpr[8] = context->gpr[8] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_0111_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[8] >> 31;
	context->m = context->gpr[7] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_0111_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[8] & context->gpr[7];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_0111_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[8] = context->gpr[7] & context->gpr[8];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_0111_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[8] = context->gpr[7] ^ context->gpr[8];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_0111_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[8] = context->gpr[7] | context->gpr[8];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_0111_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[7] ^ context->gpr[8];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_0111_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[7] << 16;
	context->gpr[8] = context->gpr[8] >> 16;
	context->gpr[8] = context->scratch1 | context->gpr[8];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_0111_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[8] & 65535)) * ((uint32_t)(context->gpr[7] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_0111_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[8])) * ((int32_t)((int16_t)context->gpr[7])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_1000_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[8] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[8], context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_1000_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[8] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[8], context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_1000_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[8] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[8], context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_1000_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[8] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->gpr[8] = context->gpr[8] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_1000_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[8] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->gpr[8] = context->gpr[8] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_1000_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[8] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->gpr[8] = context->gpr[8] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_1000_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[8] >> 31;
	context->m = context->gpr[8] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_1000_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[8] & context->gpr[8];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_1000_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[8] = context->gpr[8] & context->gpr[8];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_1000_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[8] = context->gpr[8] ^ context->gpr[8];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_1000_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[8] = context->gpr[8] | context->gpr[8];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_1000_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[8] ^ context->gpr[8];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_1000_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[8] << 16;
	context->gpr[8] = context->gpr[8] >> 16;
	context->gpr[8] = context->scratch1 | context->gpr[8];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_1000_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[8] & 65535)) * ((uint32_t)(context->gpr[8] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_1000_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[8])) * ((int32_t)((int16_t)context->gpr[8])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_1001_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[8] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[8], context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_1001_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[8] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[8], context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_1001_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[8] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[8], context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_1001_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[8] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->gpr[8] = context->gpr[8] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_1001_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[8] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->gpr[8] = context->gpr[8] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_1001_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[8] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->gpr[8] = context->gpr[8] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_1001_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[8] >> 31;
	context->m = context->gpr[9] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_1001_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[8] & context->gpr[9];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_1001_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[8] = context->gpr[9] & context->gpr[8];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_1001_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[8] = context->gpr[9] ^ context->gpr[8];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_1001_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[8] = context->gpr[9] | context->gpr[8];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_1001_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[9] ^ context->gpr[8];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_1001_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[9] << 16;
	context->gpr[8] = context->gpr[8] >> 16;
	context->gpr[8] = context->scratch1 | context->gpr[8];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_1001_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[8] & 65535)) * ((uint32_t)(context->gpr[9] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_1001_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[8])) * ((int32_t)((int16_t)context->gpr[9])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_1010_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[8] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[8], context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_1010_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[8] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[8], context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_1010_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[8] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[8], context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_1010_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[8] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->gpr[8] = context->gpr[8] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_1010_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[8] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->gpr[8] = context->gpr[8] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_1010_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[8] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->gpr[8] = context->gpr[8] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_1010_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[8] >> 31;
	context->m = context->gpr[10] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_1010_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[8] & context->gpr[10];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_1010_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[8] = context->gpr[10] & context->gpr[8];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_1010_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[8] = context->gpr[10] ^ context->gpr[8];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_1010_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[8] = context->gpr[10] | context->gpr[8];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_1010_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[10] ^ context->gpr[8];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_1010_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[10] << 16;
	context->gpr[8] = context->gpr[8] >> 16;
	context->gpr[8] = context->scratch1 | context->gpr[8];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_1010_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[8] & 65535)) * ((uint32_t)(context->gpr[10] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_1010_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[8])) * ((int32_t)((int16_t)context->gpr[10])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_1011_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[8] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[8], context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_1011_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[8] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[8], context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_1011_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[8] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[8], context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_1011_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[8] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->gpr[8] = context->gpr[8] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_1011_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[8] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->gpr[8] = context->gpr[8] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_1011_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[8] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->gpr[8] = context->gpr[8] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_1011_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[8] >> 31;
	context->m = context->gpr[11] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_1011_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[8] & context->gpr[11];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_1011_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[8] = context->gpr[11] & context->gpr[8];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_1011_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[8] = context->gpr[11] ^ context->gpr[8];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_1011_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[8] = context->gpr[11] | context->gpr[8];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_1011_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[11] ^ context->gpr[8];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_1011_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[11] << 16;
	context->gpr[8] = context->gpr[8] >> 16;
	context->gpr[8] = context->scratch1 | context->gpr[8];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_1011_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[8] & 65535)) * ((uint32_t)(context->gpr[11] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_1011_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[8])) * ((int32_t)((int16_t)context->gpr[11])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_1100_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[8] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[8], context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_1100_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[8] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[8], context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_1100_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[8] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[8], context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_1100_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[8] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->gpr[8] = context->gpr[8] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_1100_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[8] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->gpr[8] = context->gpr[8] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_1100_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[8] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->gpr[8] = context->gpr[8] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_1100_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[8] >> 31;
	context->m = context->gpr[12] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_1100_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[8] & context->gpr[12];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_1100_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[8] = context->gpr[12] & context->gpr[8];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_1100_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[8] = context->gpr[12] ^ context->gpr[8];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_1100_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[8] = context->gpr[12] | context->gpr[8];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_1100_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[12] ^ context->gpr[8];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_1100_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[12] << 16;
	context->gpr[8] = context->gpr[8] >> 16;
	context->gpr[8] = context->scratch1 | context->gpr[8];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_1100_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[8] & 65535)) * ((uint32_t)(context->gpr[12] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_1100_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[8])) * ((int32_t)((int16_t)context->gpr[12])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_1101_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[8] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[8], context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_1101_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[8] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[8], context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_1101_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[8] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[8], context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_1101_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[8] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->gpr[8] = context->gpr[8] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_1101_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[8] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->gpr[8] = context->gpr[8] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_1101_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[8] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->gpr[8] = context->gpr[8] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_1101_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[8] >> 31;
	context->m = context->gpr[13] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_1101_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[8] & context->gpr[13];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_1101_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[8] = context->gpr[13] & context->gpr[8];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_1101_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[8] = context->gpr[13] ^ context->gpr[8];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_1101_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[8] = context->gpr[13] | context->gpr[8];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_1101_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[13] ^ context->gpr[8];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_1101_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[13] << 16;
	context->gpr[8] = context->gpr[8] >> 16;
	context->gpr[8] = context->scratch1 | context->gpr[8];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_1101_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[8] & 65535)) * ((uint32_t)(context->gpr[13] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_1101_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[8])) * ((int32_t)((int16_t)context->gpr[13])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_1110_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[8] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[8], context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_1110_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[8] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[8], context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_1110_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[8] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[8], context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_1110_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[8] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->gpr[8] = context->gpr[8] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_1110_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[8] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->gpr[8] = context->gpr[8] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_1110_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[8] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->gpr[8] = context->gpr[8] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_1110_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[8] >> 31;
	context->m = context->gpr[14] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_1110_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[8] & context->gpr[14];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_1110_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[8] = context->gpr[14] & context->gpr[8];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_1110_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[8] = context->gpr[14] ^ context->gpr[8];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_1110_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[8] = context->gpr[14] | context->gpr[8];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_1110_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[14] ^ context->gpr[8];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_1110_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[14] << 16;
	context->gpr[8] = context->gpr[8] >> 16;
	context->gpr[8] = context->scratch1 | context->gpr[8];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_1110_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[8] & 65535)) * ((uint32_t)(context->gpr[14] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_1110_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[8])) * ((int32_t)((int16_t)context->gpr[14])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_1111_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[8] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[8], context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_1111_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[8] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[8], context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_1111_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[8] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[8], context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_1111_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[8] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->gpr[8] = context->gpr[8] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_1111_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[8] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->gpr[8] = context->gpr[8] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_1111_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[8] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->gpr[8] = context->gpr[8] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_1111_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[8] >> 31;
	context->m = context->gpr[15] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_1111_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[8] & context->gpr[15];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_1111_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[8] = context->gpr[15] & context->gpr[8];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_1111_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[8] = context->gpr[15] ^ context->gpr[8];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_1111_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[8] = context->gpr[15] | context->gpr[8];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_1111_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[15] ^ context->gpr[8];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_1111_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[15] << 16;
	context->gpr[8] = context->gpr[8] >> 16;
	context->gpr[8] = context->scratch1 | context->gpr[8];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_1111_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[8] & 65535)) * ((uint32_t)(context->gpr[15] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_1111_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[8])) * ((int32_t)((int16_t)context->gpr[15])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_0000_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[9] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[9], context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_0000_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[9] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[9], context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_0000_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[9] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[9], context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_0000_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[9] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->gpr[9] = context->gpr[9] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_0000_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[9] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->gpr[9] = context->gpr[9] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_0000_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[9] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->gpr[9] = context->gpr[9] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_0000_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[9] >> 31;
	context->m = context->gpr[0] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_0000_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[9] & context->gpr[0];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_0000_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[9] = context->gpr[0] & context->gpr[9];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_0000_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[9] = context->gpr[0] ^ context->gpr[9];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_0000_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[9] = context->gpr[0] | context->gpr[9];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_0000_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[0] ^ context->gpr[9];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_0000_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] << 16;
	context->gpr[9] = context->gpr[9] >> 16;
	context->gpr[9] = context->scratch1 | context->gpr[9];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_0000_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[9] & 65535)) * ((uint32_t)(context->gpr[0] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_0000_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[9])) * ((int32_t)((int16_t)context->gpr[0])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_0001_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[9] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[9], context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_0001_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[9] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[9], context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_0001_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[9] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[9], context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_0001_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[9] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->gpr[9] = context->gpr[9] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_0001_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[9] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->gpr[9] = context->gpr[9] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_0001_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[9] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->gpr[9] = context->gpr[9] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_0001_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[9] >> 31;
	context->m = context->gpr[1] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_0001_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[9] & context->gpr[1];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_0001_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[9] = context->gpr[1] & context->gpr[9];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_0001_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[9] = context->gpr[1] ^ context->gpr[9];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_0001_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[9] = context->gpr[1] | context->gpr[9];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_0001_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[1] ^ context->gpr[9];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_0001_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[1] << 16;
	context->gpr[9] = context->gpr[9] >> 16;
	context->gpr[9] = context->scratch1 | context->gpr[9];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_0001_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[9] & 65535)) * ((uint32_t)(context->gpr[1] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_0001_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[9])) * ((int32_t)((int16_t)context->gpr[1])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_0010_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[9] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[9], context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_0010_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[9] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[9], context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_0010_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[9] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[9], context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_0010_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[9] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->gpr[9] = context->gpr[9] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_0010_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[9] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->gpr[9] = context->gpr[9] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_0010_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[9] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->gpr[9] = context->gpr[9] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_0010_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[9] >> 31;
	context->m = context->gpr[2] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_0010_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[9] & context->gpr[2];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_0010_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[9] = context->gpr[2] & context->gpr[9];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_0010_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[9] = context->gpr[2] ^ context->gpr[9];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_0010_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[9] = context->gpr[2] | context->gpr[9];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_0010_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[2] ^ context->gpr[9];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_0010_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[2] << 16;
	context->gpr[9] = context->gpr[9] >> 16;
	context->gpr[9] = context->scratch1 | context->gpr[9];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_0010_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[9] & 65535)) * ((uint32_t)(context->gpr[2] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_0010_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[9])) * ((int32_t)((int16_t)context->gpr[2])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_0011_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[9] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[9], context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_0011_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[9] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[9], context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_0011_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[9] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[9], context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_0011_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[9] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->gpr[9] = context->gpr[9] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_0011_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[9] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->gpr[9] = context->gpr[9] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_0011_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[9] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->gpr[9] = context->gpr[9] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_0011_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[9] >> 31;
	context->m = context->gpr[3] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_0011_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[9] & context->gpr[3];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_0011_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[9] = context->gpr[3] & context->gpr[9];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_0011_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[9] = context->gpr[3] ^ context->gpr[9];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_0011_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[9] = context->gpr[3] | context->gpr[9];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_0011_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[3] ^ context->gpr[9];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_0011_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[3] << 16;
	context->gpr[9] = context->gpr[9] >> 16;
	context->gpr[9] = context->scratch1 | context->gpr[9];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_0011_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[9] & 65535)) * ((uint32_t)(context->gpr[3] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_0011_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[9])) * ((int32_t)((int16_t)context->gpr[3])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_0100_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[9] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[9], context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_0100_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[9] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[9], context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_0100_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[9] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[9], context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_0100_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[9] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->gpr[9] = context->gpr[9] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_0100_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[9] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->gpr[9] = context->gpr[9] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_0100_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[9] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->gpr[9] = context->gpr[9] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_0100_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[9] >> 31;
	context->m = context->gpr[4] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_0100_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[9] & context->gpr[4];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_0100_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[9] = context->gpr[4] & context->gpr[9];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_0100_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[9] = context->gpr[4] ^ context->gpr[9];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_0100_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[9] = context->gpr[4] | context->gpr[9];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_0100_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[4] ^ context->gpr[9];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_0100_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[4] << 16;
	context->gpr[9] = context->gpr[9] >> 16;
	context->gpr[9] = context->scratch1 | context->gpr[9];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_0100_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[9] & 65535)) * ((uint32_t)(context->gpr[4] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_0100_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[9])) * ((int32_t)((int16_t)context->gpr[4])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_0101_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[9] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[9], context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_0101_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[9] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[9], context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_0101_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[9] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[9], context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_0101_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[9] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->gpr[9] = context->gpr[9] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_0101_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[9] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->gpr[9] = context->gpr[9] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_0101_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[9] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->gpr[9] = context->gpr[9] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_0101_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[9] >> 31;
	context->m = context->gpr[5] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_0101_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[9] & context->gpr[5];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_0101_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[9] = context->gpr[5] & context->gpr[9];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_0101_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[9] = context->gpr[5] ^ context->gpr[9];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_0101_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[9] = context->gpr[5] | context->gpr[9];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_0101_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[5] ^ context->gpr[9];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_0101_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[5] << 16;
	context->gpr[9] = context->gpr[9] >> 16;
	context->gpr[9] = context->scratch1 | context->gpr[9];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_0101_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[9] & 65535)) * ((uint32_t)(context->gpr[5] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_0101_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[9])) * ((int32_t)((int16_t)context->gpr[5])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_0110_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[9] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[9], context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_0110_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[9] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[9], context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_0110_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[9] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[9], context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_0110_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[9] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->gpr[9] = context->gpr[9] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_0110_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[9] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->gpr[9] = context->gpr[9] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_0110_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[9] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->gpr[9] = context->gpr[9] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_0110_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[9] >> 31;
	context->m = context->gpr[6] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_0110_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[9] & context->gpr[6];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_0110_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[9] = context->gpr[6] & context->gpr[9];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_0110_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[9] = context->gpr[6] ^ context->gpr[9];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_0110_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[9] = context->gpr[6] | context->gpr[9];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_0110_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[6] ^ context->gpr[9];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_0110_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[6] << 16;
	context->gpr[9] = context->gpr[9] >> 16;
	context->gpr[9] = context->scratch1 | context->gpr[9];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_0110_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[9] & 65535)) * ((uint32_t)(context->gpr[6] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_0110_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[9])) * ((int32_t)((int16_t)context->gpr[6])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_0111_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[9] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[9], context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_0111_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[9] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[9], context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_0111_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[9] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[9], context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_0111_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[9] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->gpr[9] = context->gpr[9] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_0111_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[9] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->gpr[9] = context->gpr[9] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_0111_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[9] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->gpr[9] = context->gpr[9] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_0111_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[9] >> 31;
	context->m = context->gpr[7] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_0111_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[9] & context->gpr[7];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_0111_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[9] = context->gpr[7] & context->gpr[9];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_0111_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[9] = context->gpr[7] ^ context->gpr[9];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_0111_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[9] = context->gpr[7] | context->gpr[9];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_0111_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[7] ^ context->gpr[9];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_0111_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[7] << 16;
	context->gpr[9] = context->gpr[9] >> 16;
	context->gpr[9] = context->scratch1 | context->gpr[9];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_0111_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[9] & 65535)) * ((uint32_t)(context->gpr[7] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_0111_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[9])) * ((int32_t)((int16_t)context->gpr[7])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_1000_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[9] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[9], context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_1000_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[9] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[9], context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_1000_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[9] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[9], context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_1000_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[9] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->gpr[9] = context->gpr[9] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_1000_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[9] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->gpr[9] = context->gpr[9] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_1000_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[9] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->gpr[9] = context->gpr[9] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_1000_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[9] >> 31;
	context->m = context->gpr[8] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_1000_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[9] & context->gpr[8];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_1000_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[9] = context->gpr[8] & context->gpr[9];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_1000_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[9] = context->gpr[8] ^ context->gpr[9];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_1000_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[9] = context->gpr[8] | context->gpr[9];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_1000_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[8] ^ context->gpr[9];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_1000_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[8] << 16;
	context->gpr[9] = context->gpr[9] >> 16;
	context->gpr[9] = context->scratch1 | context->gpr[9];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_1000_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[9] & 65535)) * ((uint32_t)(context->gpr[8] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_1000_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[9])) * ((int32_t)((int16_t)context->gpr[8])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_1001_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[9] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[9], context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_1001_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[9] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[9], context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_1001_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[9] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[9], context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_1001_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[9] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->gpr[9] = context->gpr[9] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_1001_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[9] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->gpr[9] = context->gpr[9] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_1001_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[9] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->gpr[9] = context->gpr[9] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_1001_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[9] >> 31;
	context->m = context->gpr[9] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_1001_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[9] & context->gpr[9];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_1001_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[9] = context->gpr[9] & context->gpr[9];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_1001_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[9] = context->gpr[9] ^ context->gpr[9];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_1001_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[9] = context->gpr[9] | context->gpr[9];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_1001_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[9] ^ context->gpr[9];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_1001_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[9] << 16;
	context->gpr[9] = context->gpr[9] >> 16;
	context->gpr[9] = context->scratch1 | context->gpr[9];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_1001_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[9] & 65535)) * ((uint32_t)(context->gpr[9] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_1001_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[9])) * ((int32_t)((int16_t)context->gpr[9])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_1010_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[9] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[9], context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_1010_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[9] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[9], context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_1010_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[9] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[9], context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_1010_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[9] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->gpr[9] = context->gpr[9] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_1010_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[9] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->gpr[9] = context->gpr[9] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_1010_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[9] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->gpr[9] = context->gpr[9] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_1010_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[9] >> 31;
	context->m = context->gpr[10] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_1010_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[9] & context->gpr[10];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_1010_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[9] = context->gpr[10] & context->gpr[9];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_1010_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[9] = context->gpr[10] ^ context->gpr[9];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_1010_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[9] = context->gpr[10] | context->gpr[9];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_1010_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[10] ^ context->gpr[9];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_1010_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[10] << 16;
	context->gpr[9] = context->gpr[9] >> 16;
	context->gpr[9] = context->scratch1 | context->gpr[9];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_1010_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[9] & 65535)) * ((uint32_t)(context->gpr[10] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_1010_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[9])) * ((int32_t)((int16_t)context->gpr[10])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_1011_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[9] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[9], context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_1011_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[9] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[9], context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_1011_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[9] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[9], context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_1011_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[9] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->gpr[9] = context->gpr[9] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_1011_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[9] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->gpr[9] = context->gpr[9] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_1011_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[9] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->gpr[9] = context->gpr[9] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_1011_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[9] >> 31;
	context->m = context->gpr[11] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_1011_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[9] & context->gpr[11];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_1011_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[9] = context->gpr[11] & context->gpr[9];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_1011_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[9] = context->gpr[11] ^ context->gpr[9];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_1011_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[9] = context->gpr[11] | context->gpr[9];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_1011_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[11] ^ context->gpr[9];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_1011_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[11] << 16;
	context->gpr[9] = context->gpr[9] >> 16;
	context->gpr[9] = context->scratch1 | context->gpr[9];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_1011_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[9] & 65535)) * ((uint32_t)(context->gpr[11] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_1011_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[9])) * ((int32_t)((int16_t)context->gpr[11])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_1100_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[9] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[9], context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_1100_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[9] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[9], context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_1100_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[9] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[9], context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_1100_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[9] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->gpr[9] = context->gpr[9] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_1100_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[9] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->gpr[9] = context->gpr[9] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_1100_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[9] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->gpr[9] = context->gpr[9] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_1100_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[9] >> 31;
	context->m = context->gpr[12] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_1100_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[9] & context->gpr[12];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_1100_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[9] = context->gpr[12] & context->gpr[9];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_1100_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[9] = context->gpr[12] ^ context->gpr[9];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_1100_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[9] = context->gpr[12] | context->gpr[9];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_1100_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[12] ^ context->gpr[9];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_1100_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[12] << 16;
	context->gpr[9] = context->gpr[9] >> 16;
	context->gpr[9] = context->scratch1 | context->gpr[9];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_1100_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[9] & 65535)) * ((uint32_t)(context->gpr[12] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_1100_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[9])) * ((int32_t)((int16_t)context->gpr[12])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_1101_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[9] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[9], context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_1101_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[9] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[9], context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_1101_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[9] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[9], context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_1101_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[9] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->gpr[9] = context->gpr[9] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_1101_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[9] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->gpr[9] = context->gpr[9] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_1101_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[9] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->gpr[9] = context->gpr[9] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_1101_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[9] >> 31;
	context->m = context->gpr[13] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_1101_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[9] & context->gpr[13];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_1101_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[9] = context->gpr[13] & context->gpr[9];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_1101_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[9] = context->gpr[13] ^ context->gpr[9];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_1101_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[9] = context->gpr[13] | context->gpr[9];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_1101_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[13] ^ context->gpr[9];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_1101_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[13] << 16;
	context->gpr[9] = context->gpr[9] >> 16;
	context->gpr[9] = context->scratch1 | context->gpr[9];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_1101_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[9] & 65535)) * ((uint32_t)(context->gpr[13] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_1101_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[9])) * ((int32_t)((int16_t)context->gpr[13])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_1110_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[9] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[9], context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_1110_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[9] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[9], context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_1110_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[9] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[9], context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_1110_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[9] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->gpr[9] = context->gpr[9] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_1110_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[9] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->gpr[9] = context->gpr[9] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_1110_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[9] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->gpr[9] = context->gpr[9] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_1110_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[9] >> 31;
	context->m = context->gpr[14] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_1110_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[9] & context->gpr[14];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_1110_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[9] = context->gpr[14] & context->gpr[9];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_1110_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[9] = context->gpr[14] ^ context->gpr[9];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_1110_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[9] = context->gpr[14] | context->gpr[9];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_1110_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[14] ^ context->gpr[9];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_1110_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[14] << 16;
	context->gpr[9] = context->gpr[9] >> 16;
	context->gpr[9] = context->scratch1 | context->gpr[9];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_1110_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[9] & 65535)) * ((uint32_t)(context->gpr[14] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_1110_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[9])) * ((int32_t)((int16_t)context->gpr[14])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_1111_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[9] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[9], context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_1111_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[9] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[9], context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_1111_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[9] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[9], context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_1111_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[9] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->gpr[9] = context->gpr[9] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_1111_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[9] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->gpr[9] = context->gpr[9] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_1111_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[9] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->gpr[9] = context->gpr[9] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_1111_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[9] >> 31;
	context->m = context->gpr[15] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_1111_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[9] & context->gpr[15];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_1111_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[9] = context->gpr[15] & context->gpr[9];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_1111_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[9] = context->gpr[15] ^ context->gpr[9];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_1111_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[9] = context->gpr[15] | context->gpr[9];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_1111_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[15] ^ context->gpr[9];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_1111_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[15] << 16;
	context->gpr[9] = context->gpr[9] >> 16;
	context->gpr[9] = context->scratch1 | context->gpr[9];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_1111_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[9] & 65535)) * ((uint32_t)(context->gpr[15] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_1111_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[9])) * ((int32_t)((int16_t)context->gpr[15])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_0000_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[10] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[10], context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_0000_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[10] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[10], context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_0000_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[10] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[10], context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_0000_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[10] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->gpr[10] = context->gpr[10] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_0000_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[10] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->gpr[10] = context->gpr[10] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_0000_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[10] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->gpr[10] = context->gpr[10] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_0000_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[10] >> 31;
	context->m = context->gpr[0] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_0000_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[10] & context->gpr[0];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_0000_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[10] = context->gpr[0] & context->gpr[10];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_0000_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[10] = context->gpr[0] ^ context->gpr[10];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_0000_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[10] = context->gpr[0] | context->gpr[10];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_0000_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[0] ^ context->gpr[10];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_0000_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] << 16;
	context->gpr[10] = context->gpr[10] >> 16;
	context->gpr[10] = context->scratch1 | context->gpr[10];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_0000_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[10] & 65535)) * ((uint32_t)(context->gpr[0] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_0000_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[10])) * ((int32_t)((int16_t)context->gpr[0])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_0001_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[10] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[10], context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_0001_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[10] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[10], context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_0001_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[10] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[10], context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_0001_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[10] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->gpr[10] = context->gpr[10] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_0001_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[10] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->gpr[10] = context->gpr[10] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_0001_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[10] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->gpr[10] = context->gpr[10] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_0001_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[10] >> 31;
	context->m = context->gpr[1] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_0001_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[10] & context->gpr[1];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_0001_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[10] = context->gpr[1] & context->gpr[10];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_0001_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[10] = context->gpr[1] ^ context->gpr[10];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_0001_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[10] = context->gpr[1] | context->gpr[10];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_0001_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[1] ^ context->gpr[10];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_0001_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[1] << 16;
	context->gpr[10] = context->gpr[10] >> 16;
	context->gpr[10] = context->scratch1 | context->gpr[10];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_0001_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[10] & 65535)) * ((uint32_t)(context->gpr[1] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_0001_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[10])) * ((int32_t)((int16_t)context->gpr[1])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_0010_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[10] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[10], context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_0010_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[10] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[10], context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_0010_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[10] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[10], context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_0010_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[10] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->gpr[10] = context->gpr[10] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_0010_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[10] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->gpr[10] = context->gpr[10] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_0010_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[10] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->gpr[10] = context->gpr[10] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_0010_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[10] >> 31;
	context->m = context->gpr[2] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_0010_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[10] & context->gpr[2];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_0010_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[10] = context->gpr[2] & context->gpr[10];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_0010_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[10] = context->gpr[2] ^ context->gpr[10];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_0010_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[10] = context->gpr[2] | context->gpr[10];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_0010_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[2] ^ context->gpr[10];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_0010_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[2] << 16;
	context->gpr[10] = context->gpr[10] >> 16;
	context->gpr[10] = context->scratch1 | context->gpr[10];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_0010_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[10] & 65535)) * ((uint32_t)(context->gpr[2] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_0010_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[10])) * ((int32_t)((int16_t)context->gpr[2])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_0011_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[10] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[10], context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_0011_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[10] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[10], context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_0011_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[10] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[10], context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_0011_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[10] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->gpr[10] = context->gpr[10] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_0011_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[10] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->gpr[10] = context->gpr[10] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_0011_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[10] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->gpr[10] = context->gpr[10] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_0011_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[10] >> 31;
	context->m = context->gpr[3] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_0011_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[10] & context->gpr[3];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_0011_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[10] = context->gpr[3] & context->gpr[10];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_0011_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[10] = context->gpr[3] ^ context->gpr[10];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_0011_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[10] = context->gpr[3] | context->gpr[10];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_0011_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[3] ^ context->gpr[10];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_0011_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[3] << 16;
	context->gpr[10] = context->gpr[10] >> 16;
	context->gpr[10] = context->scratch1 | context->gpr[10];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_0011_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[10] & 65535)) * ((uint32_t)(context->gpr[3] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_0011_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[10])) * ((int32_t)((int16_t)context->gpr[3])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_0100_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[10] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[10], context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_0100_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[10] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[10], context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_0100_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[10] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[10], context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_0100_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[10] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->gpr[10] = context->gpr[10] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_0100_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[10] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->gpr[10] = context->gpr[10] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_0100_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[10] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->gpr[10] = context->gpr[10] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_0100_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[10] >> 31;
	context->m = context->gpr[4] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_0100_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[10] & context->gpr[4];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_0100_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[10] = context->gpr[4] & context->gpr[10];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_0100_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[10] = context->gpr[4] ^ context->gpr[10];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_0100_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[10] = context->gpr[4] | context->gpr[10];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_0100_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[4] ^ context->gpr[10];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_0100_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[4] << 16;
	context->gpr[10] = context->gpr[10] >> 16;
	context->gpr[10] = context->scratch1 | context->gpr[10];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_0100_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[10] & 65535)) * ((uint32_t)(context->gpr[4] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_0100_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[10])) * ((int32_t)((int16_t)context->gpr[4])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_0101_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[10] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[10], context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_0101_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[10] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[10], context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_0101_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[10] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[10], context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_0101_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[10] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->gpr[10] = context->gpr[10] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_0101_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[10] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->gpr[10] = context->gpr[10] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_0101_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[10] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->gpr[10] = context->gpr[10] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_0101_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[10] >> 31;
	context->m = context->gpr[5] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_0101_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[10] & context->gpr[5];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_0101_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[10] = context->gpr[5] & context->gpr[10];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_0101_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[10] = context->gpr[5] ^ context->gpr[10];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_0101_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[10] = context->gpr[5] | context->gpr[10];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_0101_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[5] ^ context->gpr[10];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_0101_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[5] << 16;
	context->gpr[10] = context->gpr[10] >> 16;
	context->gpr[10] = context->scratch1 | context->gpr[10];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_0101_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[10] & 65535)) * ((uint32_t)(context->gpr[5] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_0101_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[10])) * ((int32_t)((int16_t)context->gpr[5])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_0110_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[10] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[10], context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_0110_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[10] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[10], context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_0110_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[10] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[10], context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_0110_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[10] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->gpr[10] = context->gpr[10] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_0110_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[10] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->gpr[10] = context->gpr[10] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_0110_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[10] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->gpr[10] = context->gpr[10] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_0110_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[10] >> 31;
	context->m = context->gpr[6] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_0110_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[10] & context->gpr[6];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_0110_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[10] = context->gpr[6] & context->gpr[10];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_0110_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[10] = context->gpr[6] ^ context->gpr[10];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_0110_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[10] = context->gpr[6] | context->gpr[10];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_0110_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[6] ^ context->gpr[10];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_0110_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[6] << 16;
	context->gpr[10] = context->gpr[10] >> 16;
	context->gpr[10] = context->scratch1 | context->gpr[10];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_0110_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[10] & 65535)) * ((uint32_t)(context->gpr[6] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_0110_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[10])) * ((int32_t)((int16_t)context->gpr[6])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_0111_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[10] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[10], context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_0111_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[10] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[10], context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_0111_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[10] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[10], context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_0111_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[10] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->gpr[10] = context->gpr[10] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_0111_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[10] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->gpr[10] = context->gpr[10] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_0111_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[10] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->gpr[10] = context->gpr[10] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_0111_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[10] >> 31;
	context->m = context->gpr[7] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_0111_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[10] & context->gpr[7];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_0111_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[10] = context->gpr[7] & context->gpr[10];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_0111_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[10] = context->gpr[7] ^ context->gpr[10];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_0111_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[10] = context->gpr[7] | context->gpr[10];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_0111_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[7] ^ context->gpr[10];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_0111_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[7] << 16;
	context->gpr[10] = context->gpr[10] >> 16;
	context->gpr[10] = context->scratch1 | context->gpr[10];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_0111_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[10] & 65535)) * ((uint32_t)(context->gpr[7] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_0111_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[10])) * ((int32_t)((int16_t)context->gpr[7])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_1000_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[10] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[10], context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_1000_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[10] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[10], context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_1000_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[10] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[10], context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_1000_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[10] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->gpr[10] = context->gpr[10] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_1000_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[10] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->gpr[10] = context->gpr[10] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_1000_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[10] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->gpr[10] = context->gpr[10] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_1000_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[10] >> 31;
	context->m = context->gpr[8] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_1000_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[10] & context->gpr[8];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_1000_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[10] = context->gpr[8] & context->gpr[10];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_1000_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[10] = context->gpr[8] ^ context->gpr[10];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_1000_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[10] = context->gpr[8] | context->gpr[10];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_1000_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[8] ^ context->gpr[10];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_1000_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[8] << 16;
	context->gpr[10] = context->gpr[10] >> 16;
	context->gpr[10] = context->scratch1 | context->gpr[10];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_1000_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[10] & 65535)) * ((uint32_t)(context->gpr[8] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_1000_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[10])) * ((int32_t)((int16_t)context->gpr[8])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_1001_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[10] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[10], context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_1001_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[10] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[10], context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_1001_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[10] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[10], context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_1001_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[10] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->gpr[10] = context->gpr[10] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_1001_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[10] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->gpr[10] = context->gpr[10] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_1001_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[10] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->gpr[10] = context->gpr[10] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_1001_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[10] >> 31;
	context->m = context->gpr[9] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_1001_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[10] & context->gpr[9];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_1001_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[10] = context->gpr[9] & context->gpr[10];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_1001_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[10] = context->gpr[9] ^ context->gpr[10];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_1001_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[10] = context->gpr[9] | context->gpr[10];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_1001_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[9] ^ context->gpr[10];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_1001_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[9] << 16;
	context->gpr[10] = context->gpr[10] >> 16;
	context->gpr[10] = context->scratch1 | context->gpr[10];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_1001_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[10] & 65535)) * ((uint32_t)(context->gpr[9] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_1001_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[10])) * ((int32_t)((int16_t)context->gpr[9])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_1010_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[10] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[10], context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_1010_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[10] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[10], context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_1010_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[10] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[10], context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_1010_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[10] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->gpr[10] = context->gpr[10] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_1010_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[10] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->gpr[10] = context->gpr[10] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_1010_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[10] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->gpr[10] = context->gpr[10] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_1010_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[10] >> 31;
	context->m = context->gpr[10] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_1010_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[10] & context->gpr[10];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_1010_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[10] = context->gpr[10] & context->gpr[10];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_1010_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[10] = context->gpr[10] ^ context->gpr[10];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_1010_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[10] = context->gpr[10] | context->gpr[10];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_1010_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[10] ^ context->gpr[10];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_1010_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[10] << 16;
	context->gpr[10] = context->gpr[10] >> 16;
	context->gpr[10] = context->scratch1 | context->gpr[10];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_1010_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[10] & 65535)) * ((uint32_t)(context->gpr[10] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_1010_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[10])) * ((int32_t)((int16_t)context->gpr[10])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_1011_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[10] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[10], context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_1011_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[10] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[10], context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_1011_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[10] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[10], context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_1011_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[10] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->gpr[10] = context->gpr[10] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_1011_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[10] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->gpr[10] = context->gpr[10] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_1011_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[10] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->gpr[10] = context->gpr[10] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_1011_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[10] >> 31;
	context->m = context->gpr[11] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_1011_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[10] & context->gpr[11];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_1011_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[10] = context->gpr[11] & context->gpr[10];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_1011_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[10] = context->gpr[11] ^ context->gpr[10];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_1011_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[10] = context->gpr[11] | context->gpr[10];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_1011_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[11] ^ context->gpr[10];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_1011_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[11] << 16;
	context->gpr[10] = context->gpr[10] >> 16;
	context->gpr[10] = context->scratch1 | context->gpr[10];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_1011_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[10] & 65535)) * ((uint32_t)(context->gpr[11] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_1011_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[10])) * ((int32_t)((int16_t)context->gpr[11])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_1100_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[10] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[10], context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_1100_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[10] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[10], context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_1100_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[10] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[10], context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_1100_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[10] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->gpr[10] = context->gpr[10] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_1100_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[10] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->gpr[10] = context->gpr[10] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_1100_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[10] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->gpr[10] = context->gpr[10] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_1100_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[10] >> 31;
	context->m = context->gpr[12] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_1100_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[10] & context->gpr[12];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_1100_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[10] = context->gpr[12] & context->gpr[10];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_1100_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[10] = context->gpr[12] ^ context->gpr[10];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_1100_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[10] = context->gpr[12] | context->gpr[10];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_1100_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[12] ^ context->gpr[10];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_1100_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[12] << 16;
	context->gpr[10] = context->gpr[10] >> 16;
	context->gpr[10] = context->scratch1 | context->gpr[10];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_1100_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[10] & 65535)) * ((uint32_t)(context->gpr[12] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_1100_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[10])) * ((int32_t)((int16_t)context->gpr[12])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_1101_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[10] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[10], context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_1101_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[10] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[10], context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_1101_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[10] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[10], context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_1101_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[10] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->gpr[10] = context->gpr[10] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_1101_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[10] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->gpr[10] = context->gpr[10] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_1101_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[10] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->gpr[10] = context->gpr[10] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_1101_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[10] >> 31;
	context->m = context->gpr[13] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_1101_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[10] & context->gpr[13];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_1101_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[10] = context->gpr[13] & context->gpr[10];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_1101_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[10] = context->gpr[13] ^ context->gpr[10];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_1101_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[10] = context->gpr[13] | context->gpr[10];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_1101_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[13] ^ context->gpr[10];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_1101_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[13] << 16;
	context->gpr[10] = context->gpr[10] >> 16;
	context->gpr[10] = context->scratch1 | context->gpr[10];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_1101_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[10] & 65535)) * ((uint32_t)(context->gpr[13] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_1101_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[10])) * ((int32_t)((int16_t)context->gpr[13])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_1110_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[10] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[10], context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_1110_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[10] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[10], context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_1110_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[10] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[10], context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_1110_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[10] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->gpr[10] = context->gpr[10] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_1110_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[10] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->gpr[10] = context->gpr[10] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_1110_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[10] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->gpr[10] = context->gpr[10] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_1110_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[10] >> 31;
	context->m = context->gpr[14] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_1110_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[10] & context->gpr[14];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_1110_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[10] = context->gpr[14] & context->gpr[10];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_1110_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[10] = context->gpr[14] ^ context->gpr[10];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_1110_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[10] = context->gpr[14] | context->gpr[10];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_1110_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[14] ^ context->gpr[10];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_1110_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[14] << 16;
	context->gpr[10] = context->gpr[10] >> 16;
	context->gpr[10] = context->scratch1 | context->gpr[10];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_1110_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[10] & 65535)) * ((uint32_t)(context->gpr[14] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_1110_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[10])) * ((int32_t)((int16_t)context->gpr[14])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_1111_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[10] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[10], context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_1111_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[10] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[10], context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_1111_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[10] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[10], context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_1111_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[10] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->gpr[10] = context->gpr[10] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_1111_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[10] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->gpr[10] = context->gpr[10] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_1111_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[10] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->gpr[10] = context->gpr[10] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_1111_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[10] >> 31;
	context->m = context->gpr[15] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_1111_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[10] & context->gpr[15];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_1111_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[10] = context->gpr[15] & context->gpr[10];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_1111_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[10] = context->gpr[15] ^ context->gpr[10];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_1111_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[10] = context->gpr[15] | context->gpr[10];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_1111_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[15] ^ context->gpr[10];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_1111_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[15] << 16;
	context->gpr[10] = context->gpr[10] >> 16;
	context->gpr[10] = context->scratch1 | context->gpr[10];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_1111_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[10] & 65535)) * ((uint32_t)(context->gpr[15] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_1111_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[10])) * ((int32_t)((int16_t)context->gpr[15])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_0000_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[11] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[11], context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_0000_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[11] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[11], context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_0000_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[11] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[11], context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_0000_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[11] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->gpr[11] = context->gpr[11] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_0000_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[11] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->gpr[11] = context->gpr[11] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_0000_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[11] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->gpr[11] = context->gpr[11] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_0000_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[11] >> 31;
	context->m = context->gpr[0] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_0000_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[11] & context->gpr[0];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_0000_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[11] = context->gpr[0] & context->gpr[11];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_0000_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[11] = context->gpr[0] ^ context->gpr[11];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_0000_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[11] = context->gpr[0] | context->gpr[11];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_0000_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[0] ^ context->gpr[11];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_0000_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] << 16;
	context->gpr[11] = context->gpr[11] >> 16;
	context->gpr[11] = context->scratch1 | context->gpr[11];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_0000_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[11] & 65535)) * ((uint32_t)(context->gpr[0] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_0000_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[11])) * ((int32_t)((int16_t)context->gpr[0])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_0001_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[11] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[11], context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_0001_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[11] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[11], context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_0001_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[11] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[11], context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_0001_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[11] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->gpr[11] = context->gpr[11] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_0001_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[11] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->gpr[11] = context->gpr[11] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_0001_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[11] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->gpr[11] = context->gpr[11] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_0001_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[11] >> 31;
	context->m = context->gpr[1] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_0001_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[11] & context->gpr[1];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_0001_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[11] = context->gpr[1] & context->gpr[11];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_0001_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[11] = context->gpr[1] ^ context->gpr[11];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_0001_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[11] = context->gpr[1] | context->gpr[11];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_0001_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[1] ^ context->gpr[11];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_0001_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[1] << 16;
	context->gpr[11] = context->gpr[11] >> 16;
	context->gpr[11] = context->scratch1 | context->gpr[11];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_0001_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[11] & 65535)) * ((uint32_t)(context->gpr[1] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_0001_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[11])) * ((int32_t)((int16_t)context->gpr[1])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_0010_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[11] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[11], context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_0010_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[11] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[11], context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_0010_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[11] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[11], context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_0010_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[11] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->gpr[11] = context->gpr[11] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_0010_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[11] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->gpr[11] = context->gpr[11] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_0010_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[11] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->gpr[11] = context->gpr[11] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_0010_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[11] >> 31;
	context->m = context->gpr[2] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_0010_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[11] & context->gpr[2];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_0010_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[11] = context->gpr[2] & context->gpr[11];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_0010_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[11] = context->gpr[2] ^ context->gpr[11];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_0010_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[11] = context->gpr[2] | context->gpr[11];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_0010_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[2] ^ context->gpr[11];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_0010_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[2] << 16;
	context->gpr[11] = context->gpr[11] >> 16;
	context->gpr[11] = context->scratch1 | context->gpr[11];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_0010_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[11] & 65535)) * ((uint32_t)(context->gpr[2] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_0010_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[11])) * ((int32_t)((int16_t)context->gpr[2])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_0011_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[11] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[11], context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_0011_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[11] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[11], context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_0011_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[11] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[11], context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_0011_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[11] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->gpr[11] = context->gpr[11] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_0011_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[11] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->gpr[11] = context->gpr[11] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_0011_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[11] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->gpr[11] = context->gpr[11] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_0011_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[11] >> 31;
	context->m = context->gpr[3] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_0011_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[11] & context->gpr[3];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_0011_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[11] = context->gpr[3] & context->gpr[11];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_0011_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[11] = context->gpr[3] ^ context->gpr[11];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_0011_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[11] = context->gpr[3] | context->gpr[11];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_0011_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[3] ^ context->gpr[11];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_0011_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[3] << 16;
	context->gpr[11] = context->gpr[11] >> 16;
	context->gpr[11] = context->scratch1 | context->gpr[11];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_0011_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[11] & 65535)) * ((uint32_t)(context->gpr[3] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_0011_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[11])) * ((int32_t)((int16_t)context->gpr[3])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_0100_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[11] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[11], context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_0100_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[11] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[11], context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_0100_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[11] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[11], context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_0100_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[11] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->gpr[11] = context->gpr[11] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_0100_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[11] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->gpr[11] = context->gpr[11] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_0100_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[11] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->gpr[11] = context->gpr[11] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_0100_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[11] >> 31;
	context->m = context->gpr[4] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_0100_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[11] & context->gpr[4];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_0100_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[11] = context->gpr[4] & context->gpr[11];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_0100_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[11] = context->gpr[4] ^ context->gpr[11];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_0100_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[11] = context->gpr[4] | context->gpr[11];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_0100_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[4] ^ context->gpr[11];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_0100_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[4] << 16;
	context->gpr[11] = context->gpr[11] >> 16;
	context->gpr[11] = context->scratch1 | context->gpr[11];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_0100_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[11] & 65535)) * ((uint32_t)(context->gpr[4] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_0100_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[11])) * ((int32_t)((int16_t)context->gpr[4])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_0101_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[11] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[11], context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_0101_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[11] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[11], context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_0101_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[11] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[11], context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_0101_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[11] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->gpr[11] = context->gpr[11] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_0101_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[11] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->gpr[11] = context->gpr[11] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_0101_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[11] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->gpr[11] = context->gpr[11] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_0101_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[11] >> 31;
	context->m = context->gpr[5] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_0101_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[11] & context->gpr[5];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_0101_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[11] = context->gpr[5] & context->gpr[11];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_0101_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[11] = context->gpr[5] ^ context->gpr[11];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_0101_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[11] = context->gpr[5] | context->gpr[11];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_0101_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[5] ^ context->gpr[11];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_0101_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[5] << 16;
	context->gpr[11] = context->gpr[11] >> 16;
	context->gpr[11] = context->scratch1 | context->gpr[11];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_0101_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[11] & 65535)) * ((uint32_t)(context->gpr[5] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_0101_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[11])) * ((int32_t)((int16_t)context->gpr[5])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_0110_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[11] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[11], context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_0110_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[11] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[11], context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_0110_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[11] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[11], context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_0110_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[11] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->gpr[11] = context->gpr[11] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_0110_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[11] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->gpr[11] = context->gpr[11] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_0110_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[11] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->gpr[11] = context->gpr[11] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_0110_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[11] >> 31;
	context->m = context->gpr[6] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_0110_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[11] & context->gpr[6];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_0110_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[11] = context->gpr[6] & context->gpr[11];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_0110_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[11] = context->gpr[6] ^ context->gpr[11];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_0110_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[11] = context->gpr[6] | context->gpr[11];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_0110_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[6] ^ context->gpr[11];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_0110_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[6] << 16;
	context->gpr[11] = context->gpr[11] >> 16;
	context->gpr[11] = context->scratch1 | context->gpr[11];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_0110_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[11] & 65535)) * ((uint32_t)(context->gpr[6] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_0110_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[11])) * ((int32_t)((int16_t)context->gpr[6])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_0111_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[11] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[11], context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_0111_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[11] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[11], context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_0111_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[11] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[11], context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_0111_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[11] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->gpr[11] = context->gpr[11] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_0111_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[11] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->gpr[11] = context->gpr[11] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_0111_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[11] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->gpr[11] = context->gpr[11] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_0111_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[11] >> 31;
	context->m = context->gpr[7] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_0111_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[11] & context->gpr[7];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_0111_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[11] = context->gpr[7] & context->gpr[11];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_0111_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[11] = context->gpr[7] ^ context->gpr[11];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_0111_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[11] = context->gpr[7] | context->gpr[11];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_0111_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[7] ^ context->gpr[11];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_0111_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[7] << 16;
	context->gpr[11] = context->gpr[11] >> 16;
	context->gpr[11] = context->scratch1 | context->gpr[11];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_0111_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[11] & 65535)) * ((uint32_t)(context->gpr[7] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_0111_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[11])) * ((int32_t)((int16_t)context->gpr[7])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_1000_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[11] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[11], context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_1000_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[11] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[11], context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_1000_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[11] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[11], context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_1000_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[11] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->gpr[11] = context->gpr[11] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_1000_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[11] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->gpr[11] = context->gpr[11] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_1000_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[11] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->gpr[11] = context->gpr[11] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_1000_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[11] >> 31;
	context->m = context->gpr[8] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_1000_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[11] & context->gpr[8];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_1000_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[11] = context->gpr[8] & context->gpr[11];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_1000_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[11] = context->gpr[8] ^ context->gpr[11];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_1000_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[11] = context->gpr[8] | context->gpr[11];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_1000_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[8] ^ context->gpr[11];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_1000_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[8] << 16;
	context->gpr[11] = context->gpr[11] >> 16;
	context->gpr[11] = context->scratch1 | context->gpr[11];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_1000_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[11] & 65535)) * ((uint32_t)(context->gpr[8] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_1000_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[11])) * ((int32_t)((int16_t)context->gpr[8])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_1001_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[11] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[11], context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_1001_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[11] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[11], context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_1001_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[11] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[11], context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_1001_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[11] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->gpr[11] = context->gpr[11] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_1001_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[11] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->gpr[11] = context->gpr[11] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_1001_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[11] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->gpr[11] = context->gpr[11] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_1001_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[11] >> 31;
	context->m = context->gpr[9] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_1001_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[11] & context->gpr[9];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_1001_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[11] = context->gpr[9] & context->gpr[11];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_1001_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[11] = context->gpr[9] ^ context->gpr[11];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_1001_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[11] = context->gpr[9] | context->gpr[11];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_1001_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[9] ^ context->gpr[11];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_1001_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[9] << 16;
	context->gpr[11] = context->gpr[11] >> 16;
	context->gpr[11] = context->scratch1 | context->gpr[11];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_1001_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[11] & 65535)) * ((uint32_t)(context->gpr[9] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_1001_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[11])) * ((int32_t)((int16_t)context->gpr[9])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_1010_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[11] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[11], context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_1010_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[11] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[11], context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_1010_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[11] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[11], context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_1010_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[11] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->gpr[11] = context->gpr[11] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_1010_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[11] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->gpr[11] = context->gpr[11] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_1010_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[11] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->gpr[11] = context->gpr[11] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_1010_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[11] >> 31;
	context->m = context->gpr[10] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_1010_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[11] & context->gpr[10];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_1010_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[11] = context->gpr[10] & context->gpr[11];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_1010_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[11] = context->gpr[10] ^ context->gpr[11];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_1010_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[11] = context->gpr[10] | context->gpr[11];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_1010_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[10] ^ context->gpr[11];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_1010_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[10] << 16;
	context->gpr[11] = context->gpr[11] >> 16;
	context->gpr[11] = context->scratch1 | context->gpr[11];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_1010_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[11] & 65535)) * ((uint32_t)(context->gpr[10] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_1010_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[11])) * ((int32_t)((int16_t)context->gpr[10])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_1011_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[11] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[11], context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_1011_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[11] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[11], context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_1011_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[11] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[11], context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_1011_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[11] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->gpr[11] = context->gpr[11] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_1011_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[11] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->gpr[11] = context->gpr[11] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_1011_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[11] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->gpr[11] = context->gpr[11] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_1011_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[11] >> 31;
	context->m = context->gpr[11] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_1011_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[11] & context->gpr[11];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_1011_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[11] = context->gpr[11] & context->gpr[11];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_1011_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[11] = context->gpr[11] ^ context->gpr[11];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_1011_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[11] = context->gpr[11] | context->gpr[11];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_1011_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[11] ^ context->gpr[11];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_1011_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[11] << 16;
	context->gpr[11] = context->gpr[11] >> 16;
	context->gpr[11] = context->scratch1 | context->gpr[11];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_1011_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[11] & 65535)) * ((uint32_t)(context->gpr[11] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_1011_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[11])) * ((int32_t)((int16_t)context->gpr[11])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_1100_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[11] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[11], context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_1100_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[11] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[11], context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_1100_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[11] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[11], context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_1100_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[11] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->gpr[11] = context->gpr[11] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_1100_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[11] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->gpr[11] = context->gpr[11] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_1100_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[11] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->gpr[11] = context->gpr[11] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_1100_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[11] >> 31;
	context->m = context->gpr[12] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_1100_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[11] & context->gpr[12];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_1100_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[11] = context->gpr[12] & context->gpr[11];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_1100_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[11] = context->gpr[12] ^ context->gpr[11];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_1100_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[11] = context->gpr[12] | context->gpr[11];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_1100_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[12] ^ context->gpr[11];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_1100_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[12] << 16;
	context->gpr[11] = context->gpr[11] >> 16;
	context->gpr[11] = context->scratch1 | context->gpr[11];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_1100_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[11] & 65535)) * ((uint32_t)(context->gpr[12] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_1100_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[11])) * ((int32_t)((int16_t)context->gpr[12])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_1101_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[11] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[11], context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_1101_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[11] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[11], context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_1101_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[11] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[11], context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_1101_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[11] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->gpr[11] = context->gpr[11] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_1101_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[11] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->gpr[11] = context->gpr[11] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_1101_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[11] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->gpr[11] = context->gpr[11] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_1101_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[11] >> 31;
	context->m = context->gpr[13] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_1101_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[11] & context->gpr[13];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_1101_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[11] = context->gpr[13] & context->gpr[11];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_1101_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[11] = context->gpr[13] ^ context->gpr[11];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_1101_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[11] = context->gpr[13] | context->gpr[11];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_1101_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[13] ^ context->gpr[11];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_1101_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[13] << 16;
	context->gpr[11] = context->gpr[11] >> 16;
	context->gpr[11] = context->scratch1 | context->gpr[11];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_1101_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[11] & 65535)) * ((uint32_t)(context->gpr[13] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_1101_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[11])) * ((int32_t)((int16_t)context->gpr[13])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_1110_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[11] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[11], context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_1110_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[11] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[11], context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_1110_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[11] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[11], context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_1110_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[11] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->gpr[11] = context->gpr[11] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_1110_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[11] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->gpr[11] = context->gpr[11] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_1110_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[11] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->gpr[11] = context->gpr[11] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_1110_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[11] >> 31;
	context->m = context->gpr[14] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_1110_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[11] & context->gpr[14];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_1110_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[11] = context->gpr[14] & context->gpr[11];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_1110_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[11] = context->gpr[14] ^ context->gpr[11];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_1110_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[11] = context->gpr[14] | context->gpr[11];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_1110_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[14] ^ context->gpr[11];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_1110_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[14] << 16;
	context->gpr[11] = context->gpr[11] >> 16;
	context->gpr[11] = context->scratch1 | context->gpr[11];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_1110_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[11] & 65535)) * ((uint32_t)(context->gpr[14] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_1110_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[11])) * ((int32_t)((int16_t)context->gpr[14])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_1111_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[11] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[11], context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_1111_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[11] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[11], context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_1111_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[11] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[11], context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_1111_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[11] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->gpr[11] = context->gpr[11] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_1111_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[11] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->gpr[11] = context->gpr[11] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_1111_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[11] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->gpr[11] = context->gpr[11] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_1111_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[11] >> 31;
	context->m = context->gpr[15] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_1111_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[11] & context->gpr[15];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_1111_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[11] = context->gpr[15] & context->gpr[11];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_1111_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[11] = context->gpr[15] ^ context->gpr[11];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_1111_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[11] = context->gpr[15] | context->gpr[11];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_1111_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[15] ^ context->gpr[11];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_1111_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[15] << 16;
	context->gpr[11] = context->gpr[11] >> 16;
	context->gpr[11] = context->scratch1 | context->gpr[11];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_1111_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[11] & 65535)) * ((uint32_t)(context->gpr[15] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_1111_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[11])) * ((int32_t)((int16_t)context->gpr[15])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_0000_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[12] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[12], context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_0000_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[12] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[12], context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_0000_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[12] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[12], context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_0000_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[12] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->gpr[12] = context->gpr[12] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_0000_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[12] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->gpr[12] = context->gpr[12] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_0000_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[12] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->gpr[12] = context->gpr[12] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_0000_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[12] >> 31;
	context->m = context->gpr[0] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_0000_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[12] & context->gpr[0];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_0000_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[12] = context->gpr[0] & context->gpr[12];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_0000_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[12] = context->gpr[0] ^ context->gpr[12];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_0000_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[12] = context->gpr[0] | context->gpr[12];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_0000_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[0] ^ context->gpr[12];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_0000_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] << 16;
	context->gpr[12] = context->gpr[12] >> 16;
	context->gpr[12] = context->scratch1 | context->gpr[12];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_0000_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[12] & 65535)) * ((uint32_t)(context->gpr[0] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_0000_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[12])) * ((int32_t)((int16_t)context->gpr[0])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_0001_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[12] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[12], context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_0001_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[12] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[12], context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_0001_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[12] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[12], context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_0001_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[12] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->gpr[12] = context->gpr[12] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_0001_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[12] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->gpr[12] = context->gpr[12] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_0001_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[12] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->gpr[12] = context->gpr[12] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_0001_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[12] >> 31;
	context->m = context->gpr[1] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_0001_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[12] & context->gpr[1];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_0001_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[12] = context->gpr[1] & context->gpr[12];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_0001_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[12] = context->gpr[1] ^ context->gpr[12];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_0001_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[12] = context->gpr[1] | context->gpr[12];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_0001_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[1] ^ context->gpr[12];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_0001_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[1] << 16;
	context->gpr[12] = context->gpr[12] >> 16;
	context->gpr[12] = context->scratch1 | context->gpr[12];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_0001_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[12] & 65535)) * ((uint32_t)(context->gpr[1] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_0001_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[12])) * ((int32_t)((int16_t)context->gpr[1])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_0010_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[12] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[12], context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_0010_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[12] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[12], context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_0010_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[12] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[12], context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_0010_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[12] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->gpr[12] = context->gpr[12] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_0010_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[12] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->gpr[12] = context->gpr[12] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_0010_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[12] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->gpr[12] = context->gpr[12] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_0010_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[12] >> 31;
	context->m = context->gpr[2] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_0010_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[12] & context->gpr[2];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_0010_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[12] = context->gpr[2] & context->gpr[12];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_0010_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[12] = context->gpr[2] ^ context->gpr[12];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_0010_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[12] = context->gpr[2] | context->gpr[12];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_0010_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[2] ^ context->gpr[12];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_0010_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[2] << 16;
	context->gpr[12] = context->gpr[12] >> 16;
	context->gpr[12] = context->scratch1 | context->gpr[12];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_0010_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[12] & 65535)) * ((uint32_t)(context->gpr[2] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_0010_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[12])) * ((int32_t)((int16_t)context->gpr[2])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_0011_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[12] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[12], context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_0011_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[12] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[12], context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_0011_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[12] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[12], context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_0011_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[12] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->gpr[12] = context->gpr[12] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_0011_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[12] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->gpr[12] = context->gpr[12] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_0011_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[12] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->gpr[12] = context->gpr[12] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_0011_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[12] >> 31;
	context->m = context->gpr[3] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_0011_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[12] & context->gpr[3];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_0011_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[12] = context->gpr[3] & context->gpr[12];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_0011_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[12] = context->gpr[3] ^ context->gpr[12];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_0011_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[12] = context->gpr[3] | context->gpr[12];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_0011_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[3] ^ context->gpr[12];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_0011_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[3] << 16;
	context->gpr[12] = context->gpr[12] >> 16;
	context->gpr[12] = context->scratch1 | context->gpr[12];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_0011_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[12] & 65535)) * ((uint32_t)(context->gpr[3] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_0011_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[12])) * ((int32_t)((int16_t)context->gpr[3])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_0100_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[12] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[12], context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_0100_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[12] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[12], context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_0100_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[12] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[12], context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_0100_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[12] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->gpr[12] = context->gpr[12] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_0100_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[12] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->gpr[12] = context->gpr[12] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_0100_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[12] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->gpr[12] = context->gpr[12] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_0100_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[12] >> 31;
	context->m = context->gpr[4] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_0100_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[12] & context->gpr[4];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_0100_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[12] = context->gpr[4] & context->gpr[12];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_0100_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[12] = context->gpr[4] ^ context->gpr[12];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_0100_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[12] = context->gpr[4] | context->gpr[12];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_0100_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[4] ^ context->gpr[12];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_0100_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[4] << 16;
	context->gpr[12] = context->gpr[12] >> 16;
	context->gpr[12] = context->scratch1 | context->gpr[12];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_0100_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[12] & 65535)) * ((uint32_t)(context->gpr[4] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_0100_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[12])) * ((int32_t)((int16_t)context->gpr[4])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_0101_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[12] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[12], context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_0101_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[12] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[12], context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_0101_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[12] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[12], context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_0101_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[12] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->gpr[12] = context->gpr[12] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_0101_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[12] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->gpr[12] = context->gpr[12] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_0101_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[12] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->gpr[12] = context->gpr[12] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_0101_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[12] >> 31;
	context->m = context->gpr[5] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_0101_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[12] & context->gpr[5];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_0101_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[12] = context->gpr[5] & context->gpr[12];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_0101_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[12] = context->gpr[5] ^ context->gpr[12];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_0101_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[12] = context->gpr[5] | context->gpr[12];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_0101_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[5] ^ context->gpr[12];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_0101_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[5] << 16;
	context->gpr[12] = context->gpr[12] >> 16;
	context->gpr[12] = context->scratch1 | context->gpr[12];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_0101_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[12] & 65535)) * ((uint32_t)(context->gpr[5] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_0101_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[12])) * ((int32_t)((int16_t)context->gpr[5])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_0110_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[12] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[12], context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_0110_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[12] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[12], context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_0110_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[12] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[12], context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_0110_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[12] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->gpr[12] = context->gpr[12] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_0110_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[12] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->gpr[12] = context->gpr[12] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_0110_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[12] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->gpr[12] = context->gpr[12] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_0110_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[12] >> 31;
	context->m = context->gpr[6] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_0110_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[12] & context->gpr[6];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_0110_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[12] = context->gpr[6] & context->gpr[12];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_0110_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[12] = context->gpr[6] ^ context->gpr[12];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_0110_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[12] = context->gpr[6] | context->gpr[12];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_0110_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[6] ^ context->gpr[12];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_0110_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[6] << 16;
	context->gpr[12] = context->gpr[12] >> 16;
	context->gpr[12] = context->scratch1 | context->gpr[12];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_0110_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[12] & 65535)) * ((uint32_t)(context->gpr[6] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_0110_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[12])) * ((int32_t)((int16_t)context->gpr[6])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_0111_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[12] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[12], context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_0111_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[12] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[12], context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_0111_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[12] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[12], context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_0111_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[12] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->gpr[12] = context->gpr[12] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_0111_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[12] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->gpr[12] = context->gpr[12] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_0111_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[12] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->gpr[12] = context->gpr[12] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_0111_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[12] >> 31;
	context->m = context->gpr[7] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_0111_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[12] & context->gpr[7];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_0111_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[12] = context->gpr[7] & context->gpr[12];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_0111_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[12] = context->gpr[7] ^ context->gpr[12];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_0111_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[12] = context->gpr[7] | context->gpr[12];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_0111_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[7] ^ context->gpr[12];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_0111_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[7] << 16;
	context->gpr[12] = context->gpr[12] >> 16;
	context->gpr[12] = context->scratch1 | context->gpr[12];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_0111_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[12] & 65535)) * ((uint32_t)(context->gpr[7] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_0111_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[12])) * ((int32_t)((int16_t)context->gpr[7])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_1000_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[12] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[12], context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_1000_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[12] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[12], context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_1000_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[12] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[12], context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_1000_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[12] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->gpr[12] = context->gpr[12] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_1000_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[12] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->gpr[12] = context->gpr[12] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_1000_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[12] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->gpr[12] = context->gpr[12] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_1000_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[12] >> 31;
	context->m = context->gpr[8] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_1000_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[12] & context->gpr[8];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_1000_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[12] = context->gpr[8] & context->gpr[12];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_1000_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[12] = context->gpr[8] ^ context->gpr[12];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_1000_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[12] = context->gpr[8] | context->gpr[12];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_1000_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[8] ^ context->gpr[12];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_1000_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[8] << 16;
	context->gpr[12] = context->gpr[12] >> 16;
	context->gpr[12] = context->scratch1 | context->gpr[12];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_1000_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[12] & 65535)) * ((uint32_t)(context->gpr[8] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_1000_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[12])) * ((int32_t)((int16_t)context->gpr[8])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_1001_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[12] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[12], context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_1001_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[12] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[12], context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_1001_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[12] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[12], context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_1001_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[12] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->gpr[12] = context->gpr[12] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_1001_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[12] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->gpr[12] = context->gpr[12] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_1001_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[12] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->gpr[12] = context->gpr[12] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_1001_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[12] >> 31;
	context->m = context->gpr[9] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_1001_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[12] & context->gpr[9];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_1001_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[12] = context->gpr[9] & context->gpr[12];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_1001_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[12] = context->gpr[9] ^ context->gpr[12];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_1001_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[12] = context->gpr[9] | context->gpr[12];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_1001_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[9] ^ context->gpr[12];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_1001_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[9] << 16;
	context->gpr[12] = context->gpr[12] >> 16;
	context->gpr[12] = context->scratch1 | context->gpr[12];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_1001_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[12] & 65535)) * ((uint32_t)(context->gpr[9] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_1001_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[12])) * ((int32_t)((int16_t)context->gpr[9])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_1010_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[12] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[12], context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_1010_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[12] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[12], context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_1010_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[12] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[12], context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_1010_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[12] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->gpr[12] = context->gpr[12] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_1010_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[12] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->gpr[12] = context->gpr[12] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_1010_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[12] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->gpr[12] = context->gpr[12] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_1010_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[12] >> 31;
	context->m = context->gpr[10] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_1010_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[12] & context->gpr[10];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_1010_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[12] = context->gpr[10] & context->gpr[12];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_1010_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[12] = context->gpr[10] ^ context->gpr[12];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_1010_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[12] = context->gpr[10] | context->gpr[12];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_1010_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[10] ^ context->gpr[12];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_1010_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[10] << 16;
	context->gpr[12] = context->gpr[12] >> 16;
	context->gpr[12] = context->scratch1 | context->gpr[12];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_1010_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[12] & 65535)) * ((uint32_t)(context->gpr[10] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_1010_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[12])) * ((int32_t)((int16_t)context->gpr[10])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_1011_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[12] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[12], context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_1011_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[12] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[12], context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_1011_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[12] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[12], context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_1011_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[12] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->gpr[12] = context->gpr[12] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_1011_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[12] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->gpr[12] = context->gpr[12] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_1011_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[12] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->gpr[12] = context->gpr[12] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_1011_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[12] >> 31;
	context->m = context->gpr[11] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_1011_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[12] & context->gpr[11];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_1011_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[12] = context->gpr[11] & context->gpr[12];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_1011_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[12] = context->gpr[11] ^ context->gpr[12];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_1011_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[12] = context->gpr[11] | context->gpr[12];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_1011_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[11] ^ context->gpr[12];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_1011_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[11] << 16;
	context->gpr[12] = context->gpr[12] >> 16;
	context->gpr[12] = context->scratch1 | context->gpr[12];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_1011_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[12] & 65535)) * ((uint32_t)(context->gpr[11] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_1011_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[12])) * ((int32_t)((int16_t)context->gpr[11])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_1100_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[12] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[12], context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_1100_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[12] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[12], context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_1100_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[12] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[12], context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_1100_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[12] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->gpr[12] = context->gpr[12] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_1100_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[12] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->gpr[12] = context->gpr[12] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_1100_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[12] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->gpr[12] = context->gpr[12] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_1100_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[12] >> 31;
	context->m = context->gpr[12] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_1100_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[12] & context->gpr[12];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_1100_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[12] = context->gpr[12] & context->gpr[12];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_1100_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[12] = context->gpr[12] ^ context->gpr[12];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_1100_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[12] = context->gpr[12] | context->gpr[12];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_1100_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[12] ^ context->gpr[12];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_1100_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[12] << 16;
	context->gpr[12] = context->gpr[12] >> 16;
	context->gpr[12] = context->scratch1 | context->gpr[12];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_1100_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[12] & 65535)) * ((uint32_t)(context->gpr[12] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_1100_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[12])) * ((int32_t)((int16_t)context->gpr[12])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_1101_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[12] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[12], context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_1101_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[12] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[12], context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_1101_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[12] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[12], context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_1101_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[12] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->gpr[12] = context->gpr[12] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_1101_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[12] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->gpr[12] = context->gpr[12] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_1101_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[12] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->gpr[12] = context->gpr[12] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_1101_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[12] >> 31;
	context->m = context->gpr[13] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_1101_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[12] & context->gpr[13];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_1101_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[12] = context->gpr[13] & context->gpr[12];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_1101_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[12] = context->gpr[13] ^ context->gpr[12];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_1101_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[12] = context->gpr[13] | context->gpr[12];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_1101_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[13] ^ context->gpr[12];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_1101_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[13] << 16;
	context->gpr[12] = context->gpr[12] >> 16;
	context->gpr[12] = context->scratch1 | context->gpr[12];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_1101_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[12] & 65535)) * ((uint32_t)(context->gpr[13] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_1101_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[12])) * ((int32_t)((int16_t)context->gpr[13])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_1110_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[12] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[12], context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_1110_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[12] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[12], context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_1110_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[12] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[12], context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_1110_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[12] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->gpr[12] = context->gpr[12] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_1110_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[12] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->gpr[12] = context->gpr[12] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_1110_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[12] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->gpr[12] = context->gpr[12] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_1110_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[12] >> 31;
	context->m = context->gpr[14] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_1110_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[12] & context->gpr[14];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_1110_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[12] = context->gpr[14] & context->gpr[12];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_1110_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[12] = context->gpr[14] ^ context->gpr[12];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_1110_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[12] = context->gpr[14] | context->gpr[12];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_1110_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[14] ^ context->gpr[12];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_1110_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[14] << 16;
	context->gpr[12] = context->gpr[12] >> 16;
	context->gpr[12] = context->scratch1 | context->gpr[12];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_1110_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[12] & 65535)) * ((uint32_t)(context->gpr[14] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_1110_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[12])) * ((int32_t)((int16_t)context->gpr[14])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_1111_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[12] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[12], context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_1111_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[12] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[12], context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_1111_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[12] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[12], context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_1111_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[12] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->gpr[12] = context->gpr[12] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_1111_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[12] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->gpr[12] = context->gpr[12] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_1111_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[12] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->gpr[12] = context->gpr[12] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_1111_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[12] >> 31;
	context->m = context->gpr[15] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_1111_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[12] & context->gpr[15];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_1111_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[12] = context->gpr[15] & context->gpr[12];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_1111_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[12] = context->gpr[15] ^ context->gpr[12];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_1111_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[12] = context->gpr[15] | context->gpr[12];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_1111_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[15] ^ context->gpr[12];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_1111_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[15] << 16;
	context->gpr[12] = context->gpr[12] >> 16;
	context->gpr[12] = context->scratch1 | context->gpr[12];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_1111_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[12] & 65535)) * ((uint32_t)(context->gpr[15] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_1111_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[12])) * ((int32_t)((int16_t)context->gpr[15])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_0000_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[13] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[13], context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_0000_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[13] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[13], context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_0000_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[13] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[13], context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_0000_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[13] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->gpr[13] = context->gpr[13] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_0000_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[13] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->gpr[13] = context->gpr[13] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_0000_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[13] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->gpr[13] = context->gpr[13] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_0000_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[13] >> 31;
	context->m = context->gpr[0] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_0000_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[13] & context->gpr[0];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_0000_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[13] = context->gpr[0] & context->gpr[13];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_0000_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[13] = context->gpr[0] ^ context->gpr[13];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_0000_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[13] = context->gpr[0] | context->gpr[13];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_0000_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[0] ^ context->gpr[13];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_0000_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] << 16;
	context->gpr[13] = context->gpr[13] >> 16;
	context->gpr[13] = context->scratch1 | context->gpr[13];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_0000_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[13] & 65535)) * ((uint32_t)(context->gpr[0] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_0000_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[13])) * ((int32_t)((int16_t)context->gpr[0])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_0001_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[13] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[13], context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_0001_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[13] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[13], context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_0001_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[13] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[13], context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_0001_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[13] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->gpr[13] = context->gpr[13] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_0001_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[13] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->gpr[13] = context->gpr[13] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_0001_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[13] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->gpr[13] = context->gpr[13] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_0001_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[13] >> 31;
	context->m = context->gpr[1] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_0001_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[13] & context->gpr[1];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_0001_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[13] = context->gpr[1] & context->gpr[13];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_0001_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[13] = context->gpr[1] ^ context->gpr[13];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_0001_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[13] = context->gpr[1] | context->gpr[13];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_0001_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[1] ^ context->gpr[13];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_0001_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[1] << 16;
	context->gpr[13] = context->gpr[13] >> 16;
	context->gpr[13] = context->scratch1 | context->gpr[13];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_0001_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[13] & 65535)) * ((uint32_t)(context->gpr[1] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_0001_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[13])) * ((int32_t)((int16_t)context->gpr[1])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_0010_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[13] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[13], context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_0010_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[13] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[13], context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_0010_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[13] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[13], context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_0010_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[13] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->gpr[13] = context->gpr[13] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_0010_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[13] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->gpr[13] = context->gpr[13] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_0010_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[13] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->gpr[13] = context->gpr[13] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_0010_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[13] >> 31;
	context->m = context->gpr[2] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_0010_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[13] & context->gpr[2];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_0010_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[13] = context->gpr[2] & context->gpr[13];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_0010_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[13] = context->gpr[2] ^ context->gpr[13];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_0010_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[13] = context->gpr[2] | context->gpr[13];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_0010_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[2] ^ context->gpr[13];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_0010_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[2] << 16;
	context->gpr[13] = context->gpr[13] >> 16;
	context->gpr[13] = context->scratch1 | context->gpr[13];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_0010_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[13] & 65535)) * ((uint32_t)(context->gpr[2] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_0010_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[13])) * ((int32_t)((int16_t)context->gpr[2])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_0011_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[13] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[13], context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_0011_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[13] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[13], context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_0011_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[13] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[13], context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_0011_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[13] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->gpr[13] = context->gpr[13] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_0011_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[13] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->gpr[13] = context->gpr[13] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_0011_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[13] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->gpr[13] = context->gpr[13] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_0011_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[13] >> 31;
	context->m = context->gpr[3] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_0011_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[13] & context->gpr[3];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_0011_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[13] = context->gpr[3] & context->gpr[13];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_0011_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[13] = context->gpr[3] ^ context->gpr[13];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_0011_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[13] = context->gpr[3] | context->gpr[13];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_0011_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[3] ^ context->gpr[13];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_0011_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[3] << 16;
	context->gpr[13] = context->gpr[13] >> 16;
	context->gpr[13] = context->scratch1 | context->gpr[13];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_0011_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[13] & 65535)) * ((uint32_t)(context->gpr[3] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_0011_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[13])) * ((int32_t)((int16_t)context->gpr[3])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_0100_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[13] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[13], context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_0100_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[13] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[13], context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_0100_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[13] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[13], context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_0100_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[13] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->gpr[13] = context->gpr[13] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_0100_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[13] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->gpr[13] = context->gpr[13] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_0100_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[13] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->gpr[13] = context->gpr[13] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_0100_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[13] >> 31;
	context->m = context->gpr[4] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_0100_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[13] & context->gpr[4];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_0100_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[13] = context->gpr[4] & context->gpr[13];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_0100_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[13] = context->gpr[4] ^ context->gpr[13];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_0100_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[13] = context->gpr[4] | context->gpr[13];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_0100_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[4] ^ context->gpr[13];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_0100_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[4] << 16;
	context->gpr[13] = context->gpr[13] >> 16;
	context->gpr[13] = context->scratch1 | context->gpr[13];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_0100_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[13] & 65535)) * ((uint32_t)(context->gpr[4] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_0100_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[13])) * ((int32_t)((int16_t)context->gpr[4])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_0101_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[13] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[13], context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_0101_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[13] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[13], context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_0101_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[13] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[13], context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_0101_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[13] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->gpr[13] = context->gpr[13] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_0101_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[13] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->gpr[13] = context->gpr[13] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_0101_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[13] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->gpr[13] = context->gpr[13] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_0101_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[13] >> 31;
	context->m = context->gpr[5] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_0101_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[13] & context->gpr[5];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_0101_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[13] = context->gpr[5] & context->gpr[13];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_0101_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[13] = context->gpr[5] ^ context->gpr[13];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_0101_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[13] = context->gpr[5] | context->gpr[13];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_0101_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[5] ^ context->gpr[13];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_0101_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[5] << 16;
	context->gpr[13] = context->gpr[13] >> 16;
	context->gpr[13] = context->scratch1 | context->gpr[13];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_0101_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[13] & 65535)) * ((uint32_t)(context->gpr[5] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_0101_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[13])) * ((int32_t)((int16_t)context->gpr[5])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_0110_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[13] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[13], context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_0110_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[13] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[13], context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_0110_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[13] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[13], context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_0110_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[13] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->gpr[13] = context->gpr[13] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_0110_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[13] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->gpr[13] = context->gpr[13] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_0110_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[13] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->gpr[13] = context->gpr[13] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_0110_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[13] >> 31;
	context->m = context->gpr[6] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_0110_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[13] & context->gpr[6];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_0110_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[13] = context->gpr[6] & context->gpr[13];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_0110_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[13] = context->gpr[6] ^ context->gpr[13];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_0110_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[13] = context->gpr[6] | context->gpr[13];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_0110_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[6] ^ context->gpr[13];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_0110_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[6] << 16;
	context->gpr[13] = context->gpr[13] >> 16;
	context->gpr[13] = context->scratch1 | context->gpr[13];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_0110_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[13] & 65535)) * ((uint32_t)(context->gpr[6] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_0110_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[13])) * ((int32_t)((int16_t)context->gpr[6])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_0111_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[13] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[13], context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_0111_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[13] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[13], context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_0111_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[13] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[13], context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_0111_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[13] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->gpr[13] = context->gpr[13] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_0111_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[13] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->gpr[13] = context->gpr[13] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_0111_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[13] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->gpr[13] = context->gpr[13] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_0111_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[13] >> 31;
	context->m = context->gpr[7] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_0111_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[13] & context->gpr[7];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_0111_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[13] = context->gpr[7] & context->gpr[13];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_0111_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[13] = context->gpr[7] ^ context->gpr[13];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_0111_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[13] = context->gpr[7] | context->gpr[13];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_0111_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[7] ^ context->gpr[13];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_0111_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[7] << 16;
	context->gpr[13] = context->gpr[13] >> 16;
	context->gpr[13] = context->scratch1 | context->gpr[13];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_0111_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[13] & 65535)) * ((uint32_t)(context->gpr[7] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_0111_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[13])) * ((int32_t)((int16_t)context->gpr[7])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_1000_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[13] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[13], context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_1000_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[13] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[13], context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_1000_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[13] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[13], context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_1000_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[13] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->gpr[13] = context->gpr[13] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_1000_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[13] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->gpr[13] = context->gpr[13] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_1000_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[13] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->gpr[13] = context->gpr[13] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_1000_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[13] >> 31;
	context->m = context->gpr[8] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_1000_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[13] & context->gpr[8];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_1000_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[13] = context->gpr[8] & context->gpr[13];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_1000_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[13] = context->gpr[8] ^ context->gpr[13];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_1000_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[13] = context->gpr[8] | context->gpr[13];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_1000_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[8] ^ context->gpr[13];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_1000_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[8] << 16;
	context->gpr[13] = context->gpr[13] >> 16;
	context->gpr[13] = context->scratch1 | context->gpr[13];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_1000_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[13] & 65535)) * ((uint32_t)(context->gpr[8] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_1000_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[13])) * ((int32_t)((int16_t)context->gpr[8])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_1001_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[13] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[13], context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_1001_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[13] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[13], context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_1001_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[13] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[13], context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_1001_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[13] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->gpr[13] = context->gpr[13] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_1001_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[13] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->gpr[13] = context->gpr[13] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_1001_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[13] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->gpr[13] = context->gpr[13] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_1001_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[13] >> 31;
	context->m = context->gpr[9] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_1001_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[13] & context->gpr[9];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_1001_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[13] = context->gpr[9] & context->gpr[13];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_1001_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[13] = context->gpr[9] ^ context->gpr[13];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_1001_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[13] = context->gpr[9] | context->gpr[13];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_1001_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[9] ^ context->gpr[13];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_1001_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[9] << 16;
	context->gpr[13] = context->gpr[13] >> 16;
	context->gpr[13] = context->scratch1 | context->gpr[13];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_1001_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[13] & 65535)) * ((uint32_t)(context->gpr[9] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_1001_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[13])) * ((int32_t)((int16_t)context->gpr[9])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_1010_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[13] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[13], context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_1010_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[13] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[13], context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_1010_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[13] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[13], context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_1010_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[13] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->gpr[13] = context->gpr[13] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_1010_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[13] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->gpr[13] = context->gpr[13] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_1010_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[13] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->gpr[13] = context->gpr[13] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_1010_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[13] >> 31;
	context->m = context->gpr[10] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_1010_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[13] & context->gpr[10];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_1010_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[13] = context->gpr[10] & context->gpr[13];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_1010_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[13] = context->gpr[10] ^ context->gpr[13];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_1010_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[13] = context->gpr[10] | context->gpr[13];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_1010_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[10] ^ context->gpr[13];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_1010_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[10] << 16;
	context->gpr[13] = context->gpr[13] >> 16;
	context->gpr[13] = context->scratch1 | context->gpr[13];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_1010_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[13] & 65535)) * ((uint32_t)(context->gpr[10] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_1010_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[13])) * ((int32_t)((int16_t)context->gpr[10])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_1011_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[13] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[13], context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_1011_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[13] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[13], context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_1011_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[13] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[13], context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_1011_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[13] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->gpr[13] = context->gpr[13] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_1011_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[13] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->gpr[13] = context->gpr[13] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_1011_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[13] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->gpr[13] = context->gpr[13] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_1011_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[13] >> 31;
	context->m = context->gpr[11] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_1011_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[13] & context->gpr[11];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_1011_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[13] = context->gpr[11] & context->gpr[13];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_1011_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[13] = context->gpr[11] ^ context->gpr[13];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_1011_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[13] = context->gpr[11] | context->gpr[13];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_1011_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[11] ^ context->gpr[13];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_1011_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[11] << 16;
	context->gpr[13] = context->gpr[13] >> 16;
	context->gpr[13] = context->scratch1 | context->gpr[13];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_1011_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[13] & 65535)) * ((uint32_t)(context->gpr[11] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_1011_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[13])) * ((int32_t)((int16_t)context->gpr[11])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_1100_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[13] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[13], context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_1100_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[13] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[13], context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_1100_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[13] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[13], context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_1100_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[13] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->gpr[13] = context->gpr[13] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_1100_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[13] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->gpr[13] = context->gpr[13] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_1100_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[13] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->gpr[13] = context->gpr[13] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_1100_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[13] >> 31;
	context->m = context->gpr[12] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_1100_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[13] & context->gpr[12];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_1100_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[13] = context->gpr[12] & context->gpr[13];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_1100_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[13] = context->gpr[12] ^ context->gpr[13];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_1100_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[13] = context->gpr[12] | context->gpr[13];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_1100_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[12] ^ context->gpr[13];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_1100_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[12] << 16;
	context->gpr[13] = context->gpr[13] >> 16;
	context->gpr[13] = context->scratch1 | context->gpr[13];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_1100_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[13] & 65535)) * ((uint32_t)(context->gpr[12] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_1100_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[13])) * ((int32_t)((int16_t)context->gpr[12])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_1101_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[13] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[13], context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_1101_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[13] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[13], context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_1101_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[13] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[13], context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_1101_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[13] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->gpr[13] = context->gpr[13] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_1101_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[13] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->gpr[13] = context->gpr[13] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_1101_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[13] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->gpr[13] = context->gpr[13] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_1101_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[13] >> 31;
	context->m = context->gpr[13] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_1101_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[13] & context->gpr[13];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_1101_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[13] = context->gpr[13] & context->gpr[13];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_1101_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[13] = context->gpr[13] ^ context->gpr[13];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_1101_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[13] = context->gpr[13] | context->gpr[13];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_1101_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[13] ^ context->gpr[13];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_1101_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[13] << 16;
	context->gpr[13] = context->gpr[13] >> 16;
	context->gpr[13] = context->scratch1 | context->gpr[13];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_1101_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[13] & 65535)) * ((uint32_t)(context->gpr[13] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_1101_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[13])) * ((int32_t)((int16_t)context->gpr[13])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_1110_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[13] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[13], context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_1110_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[13] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[13], context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_1110_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[13] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[13], context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_1110_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[13] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->gpr[13] = context->gpr[13] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_1110_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[13] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->gpr[13] = context->gpr[13] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_1110_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[13] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->gpr[13] = context->gpr[13] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_1110_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[13] >> 31;
	context->m = context->gpr[14] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_1110_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[13] & context->gpr[14];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_1110_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[13] = context->gpr[14] & context->gpr[13];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_1110_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[13] = context->gpr[14] ^ context->gpr[13];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_1110_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[13] = context->gpr[14] | context->gpr[13];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_1110_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[14] ^ context->gpr[13];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_1110_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[14] << 16;
	context->gpr[13] = context->gpr[13] >> 16;
	context->gpr[13] = context->scratch1 | context->gpr[13];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_1110_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[13] & 65535)) * ((uint32_t)(context->gpr[14] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_1110_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[13])) * ((int32_t)((int16_t)context->gpr[14])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_1111_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[13] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[13], context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_1111_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[13] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[13], context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_1111_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[13] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[13], context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_1111_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[13] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->gpr[13] = context->gpr[13] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_1111_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[13] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->gpr[13] = context->gpr[13] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_1111_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[13] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->gpr[13] = context->gpr[13] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_1111_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[13] >> 31;
	context->m = context->gpr[15] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_1111_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[13] & context->gpr[15];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_1111_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[13] = context->gpr[15] & context->gpr[13];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_1111_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[13] = context->gpr[15] ^ context->gpr[13];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_1111_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[13] = context->gpr[15] | context->gpr[13];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_1111_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[15] ^ context->gpr[13];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_1111_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[15] << 16;
	context->gpr[13] = context->gpr[13] >> 16;
	context->gpr[13] = context->scratch1 | context->gpr[13];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_1111_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[13] & 65535)) * ((uint32_t)(context->gpr[15] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_1111_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[13])) * ((int32_t)((int16_t)context->gpr[15])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_0000_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[14] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[14], context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_0000_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[14] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[14], context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_0000_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[14] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[14], context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_0000_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[14] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->gpr[14] = context->gpr[14] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_0000_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[14] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->gpr[14] = context->gpr[14] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_0000_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[14] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->gpr[14] = context->gpr[14] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_0000_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[14] >> 31;
	context->m = context->gpr[0] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_0000_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[14] & context->gpr[0];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_0000_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[14] = context->gpr[0] & context->gpr[14];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_0000_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[14] = context->gpr[0] ^ context->gpr[14];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_0000_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[14] = context->gpr[0] | context->gpr[14];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_0000_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[0] ^ context->gpr[14];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_0000_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] << 16;
	context->gpr[14] = context->gpr[14] >> 16;
	context->gpr[14] = context->scratch1 | context->gpr[14];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_0000_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[14] & 65535)) * ((uint32_t)(context->gpr[0] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_0000_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[14])) * ((int32_t)((int16_t)context->gpr[0])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_0001_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[14] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[14], context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_0001_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[14] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[14], context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_0001_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[14] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[14], context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_0001_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[14] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->gpr[14] = context->gpr[14] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_0001_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[14] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->gpr[14] = context->gpr[14] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_0001_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[14] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->gpr[14] = context->gpr[14] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_0001_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[14] >> 31;
	context->m = context->gpr[1] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_0001_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[14] & context->gpr[1];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_0001_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[14] = context->gpr[1] & context->gpr[14];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_0001_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[14] = context->gpr[1] ^ context->gpr[14];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_0001_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[14] = context->gpr[1] | context->gpr[14];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_0001_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[1] ^ context->gpr[14];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_0001_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[1] << 16;
	context->gpr[14] = context->gpr[14] >> 16;
	context->gpr[14] = context->scratch1 | context->gpr[14];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_0001_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[14] & 65535)) * ((uint32_t)(context->gpr[1] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_0001_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[14])) * ((int32_t)((int16_t)context->gpr[1])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_0010_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[14] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[14], context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_0010_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[14] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[14], context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_0010_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[14] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[14], context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_0010_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[14] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->gpr[14] = context->gpr[14] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_0010_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[14] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->gpr[14] = context->gpr[14] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_0010_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[14] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->gpr[14] = context->gpr[14] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_0010_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[14] >> 31;
	context->m = context->gpr[2] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_0010_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[14] & context->gpr[2];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_0010_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[14] = context->gpr[2] & context->gpr[14];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_0010_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[14] = context->gpr[2] ^ context->gpr[14];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_0010_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[14] = context->gpr[2] | context->gpr[14];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_0010_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[2] ^ context->gpr[14];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_0010_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[2] << 16;
	context->gpr[14] = context->gpr[14] >> 16;
	context->gpr[14] = context->scratch1 | context->gpr[14];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_0010_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[14] & 65535)) * ((uint32_t)(context->gpr[2] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_0010_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[14])) * ((int32_t)((int16_t)context->gpr[2])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_0011_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[14] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[14], context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_0011_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[14] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[14], context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_0011_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[14] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[14], context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_0011_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[14] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->gpr[14] = context->gpr[14] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_0011_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[14] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->gpr[14] = context->gpr[14] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_0011_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[14] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->gpr[14] = context->gpr[14] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_0011_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[14] >> 31;
	context->m = context->gpr[3] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_0011_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[14] & context->gpr[3];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_0011_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[14] = context->gpr[3] & context->gpr[14];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_0011_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[14] = context->gpr[3] ^ context->gpr[14];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_0011_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[14] = context->gpr[3] | context->gpr[14];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_0011_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[3] ^ context->gpr[14];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_0011_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[3] << 16;
	context->gpr[14] = context->gpr[14] >> 16;
	context->gpr[14] = context->scratch1 | context->gpr[14];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_0011_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[14] & 65535)) * ((uint32_t)(context->gpr[3] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_0011_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[14])) * ((int32_t)((int16_t)context->gpr[3])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_0100_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[14] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[14], context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_0100_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[14] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[14], context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_0100_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[14] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[14], context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_0100_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[14] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->gpr[14] = context->gpr[14] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_0100_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[14] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->gpr[14] = context->gpr[14] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_0100_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[14] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->gpr[14] = context->gpr[14] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_0100_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[14] >> 31;
	context->m = context->gpr[4] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_0100_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[14] & context->gpr[4];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_0100_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[14] = context->gpr[4] & context->gpr[14];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_0100_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[14] = context->gpr[4] ^ context->gpr[14];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_0100_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[14] = context->gpr[4] | context->gpr[14];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_0100_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[4] ^ context->gpr[14];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_0100_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[4] << 16;
	context->gpr[14] = context->gpr[14] >> 16;
	context->gpr[14] = context->scratch1 | context->gpr[14];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_0100_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[14] & 65535)) * ((uint32_t)(context->gpr[4] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_0100_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[14])) * ((int32_t)((int16_t)context->gpr[4])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_0101_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[14] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[14], context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_0101_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[14] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[14], context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_0101_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[14] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[14], context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_0101_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[14] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->gpr[14] = context->gpr[14] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_0101_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[14] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->gpr[14] = context->gpr[14] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_0101_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[14] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->gpr[14] = context->gpr[14] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_0101_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[14] >> 31;
	context->m = context->gpr[5] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_0101_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[14] & context->gpr[5];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_0101_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[14] = context->gpr[5] & context->gpr[14];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_0101_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[14] = context->gpr[5] ^ context->gpr[14];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_0101_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[14] = context->gpr[5] | context->gpr[14];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_0101_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[5] ^ context->gpr[14];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_0101_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[5] << 16;
	context->gpr[14] = context->gpr[14] >> 16;
	context->gpr[14] = context->scratch1 | context->gpr[14];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_0101_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[14] & 65535)) * ((uint32_t)(context->gpr[5] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_0101_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[14])) * ((int32_t)((int16_t)context->gpr[5])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_0110_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[14] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[14], context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_0110_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[14] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[14], context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_0110_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[14] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[14], context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_0110_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[14] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->gpr[14] = context->gpr[14] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_0110_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[14] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->gpr[14] = context->gpr[14] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_0110_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[14] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->gpr[14] = context->gpr[14] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_0110_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[14] >> 31;
	context->m = context->gpr[6] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_0110_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[14] & context->gpr[6];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_0110_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[14] = context->gpr[6] & context->gpr[14];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_0110_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[14] = context->gpr[6] ^ context->gpr[14];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_0110_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[14] = context->gpr[6] | context->gpr[14];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_0110_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[6] ^ context->gpr[14];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_0110_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[6] << 16;
	context->gpr[14] = context->gpr[14] >> 16;
	context->gpr[14] = context->scratch1 | context->gpr[14];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_0110_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[14] & 65535)) * ((uint32_t)(context->gpr[6] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_0110_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[14])) * ((int32_t)((int16_t)context->gpr[6])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_0111_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[14] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[14], context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_0111_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[14] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[14], context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_0111_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[14] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[14], context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_0111_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[14] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->gpr[14] = context->gpr[14] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_0111_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[14] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->gpr[14] = context->gpr[14] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_0111_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[14] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->gpr[14] = context->gpr[14] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_0111_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[14] >> 31;
	context->m = context->gpr[7] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_0111_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[14] & context->gpr[7];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_0111_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[14] = context->gpr[7] & context->gpr[14];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_0111_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[14] = context->gpr[7] ^ context->gpr[14];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_0111_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[14] = context->gpr[7] | context->gpr[14];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_0111_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[7] ^ context->gpr[14];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_0111_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[7] << 16;
	context->gpr[14] = context->gpr[14] >> 16;
	context->gpr[14] = context->scratch1 | context->gpr[14];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_0111_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[14] & 65535)) * ((uint32_t)(context->gpr[7] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_0111_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[14])) * ((int32_t)((int16_t)context->gpr[7])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_1000_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[14] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[14], context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_1000_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[14] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[14], context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_1000_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[14] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[14], context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_1000_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[14] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->gpr[14] = context->gpr[14] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_1000_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[14] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->gpr[14] = context->gpr[14] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_1000_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[14] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->gpr[14] = context->gpr[14] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_1000_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[14] >> 31;
	context->m = context->gpr[8] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_1000_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[14] & context->gpr[8];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_1000_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[14] = context->gpr[8] & context->gpr[14];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_1000_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[14] = context->gpr[8] ^ context->gpr[14];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_1000_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[14] = context->gpr[8] | context->gpr[14];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_1000_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[8] ^ context->gpr[14];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_1000_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[8] << 16;
	context->gpr[14] = context->gpr[14] >> 16;
	context->gpr[14] = context->scratch1 | context->gpr[14];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_1000_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[14] & 65535)) * ((uint32_t)(context->gpr[8] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_1000_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[14])) * ((int32_t)((int16_t)context->gpr[8])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_1001_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[14] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[14], context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_1001_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[14] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[14], context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_1001_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[14] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[14], context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_1001_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[14] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->gpr[14] = context->gpr[14] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_1001_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[14] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->gpr[14] = context->gpr[14] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_1001_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[14] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->gpr[14] = context->gpr[14] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_1001_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[14] >> 31;
	context->m = context->gpr[9] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_1001_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[14] & context->gpr[9];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_1001_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[14] = context->gpr[9] & context->gpr[14];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_1001_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[14] = context->gpr[9] ^ context->gpr[14];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_1001_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[14] = context->gpr[9] | context->gpr[14];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_1001_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[9] ^ context->gpr[14];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_1001_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[9] << 16;
	context->gpr[14] = context->gpr[14] >> 16;
	context->gpr[14] = context->scratch1 | context->gpr[14];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_1001_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[14] & 65535)) * ((uint32_t)(context->gpr[9] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_1001_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[14])) * ((int32_t)((int16_t)context->gpr[9])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_1010_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[14] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[14], context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_1010_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[14] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[14], context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_1010_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[14] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[14], context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_1010_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[14] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->gpr[14] = context->gpr[14] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_1010_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[14] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->gpr[14] = context->gpr[14] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_1010_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[14] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->gpr[14] = context->gpr[14] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_1010_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[14] >> 31;
	context->m = context->gpr[10] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_1010_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[14] & context->gpr[10];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_1010_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[14] = context->gpr[10] & context->gpr[14];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_1010_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[14] = context->gpr[10] ^ context->gpr[14];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_1010_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[14] = context->gpr[10] | context->gpr[14];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_1010_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[10] ^ context->gpr[14];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_1010_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[10] << 16;
	context->gpr[14] = context->gpr[14] >> 16;
	context->gpr[14] = context->scratch1 | context->gpr[14];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_1010_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[14] & 65535)) * ((uint32_t)(context->gpr[10] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_1010_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[14])) * ((int32_t)((int16_t)context->gpr[10])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_1011_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[14] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[14], context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_1011_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[14] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[14], context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_1011_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[14] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[14], context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_1011_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[14] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->gpr[14] = context->gpr[14] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_1011_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[14] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->gpr[14] = context->gpr[14] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_1011_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[14] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->gpr[14] = context->gpr[14] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_1011_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[14] >> 31;
	context->m = context->gpr[11] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_1011_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[14] & context->gpr[11];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_1011_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[14] = context->gpr[11] & context->gpr[14];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_1011_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[14] = context->gpr[11] ^ context->gpr[14];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_1011_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[14] = context->gpr[11] | context->gpr[14];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_1011_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[11] ^ context->gpr[14];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_1011_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[11] << 16;
	context->gpr[14] = context->gpr[14] >> 16;
	context->gpr[14] = context->scratch1 | context->gpr[14];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_1011_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[14] & 65535)) * ((uint32_t)(context->gpr[11] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_1011_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[14])) * ((int32_t)((int16_t)context->gpr[11])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_1100_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[14] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[14], context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_1100_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[14] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[14], context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_1100_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[14] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[14], context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_1100_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[14] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->gpr[14] = context->gpr[14] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_1100_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[14] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->gpr[14] = context->gpr[14] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_1100_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[14] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->gpr[14] = context->gpr[14] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_1100_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[14] >> 31;
	context->m = context->gpr[12] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_1100_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[14] & context->gpr[12];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_1100_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[14] = context->gpr[12] & context->gpr[14];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_1100_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[14] = context->gpr[12] ^ context->gpr[14];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_1100_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[14] = context->gpr[12] | context->gpr[14];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_1100_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[12] ^ context->gpr[14];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_1100_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[12] << 16;
	context->gpr[14] = context->gpr[14] >> 16;
	context->gpr[14] = context->scratch1 | context->gpr[14];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_1100_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[14] & 65535)) * ((uint32_t)(context->gpr[12] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_1100_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[14])) * ((int32_t)((int16_t)context->gpr[12])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_1101_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[14] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[14], context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_1101_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[14] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[14], context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_1101_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[14] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[14], context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_1101_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[14] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->gpr[14] = context->gpr[14] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_1101_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[14] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->gpr[14] = context->gpr[14] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_1101_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[14] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->gpr[14] = context->gpr[14] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_1101_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[14] >> 31;
	context->m = context->gpr[13] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_1101_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[14] & context->gpr[13];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_1101_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[14] = context->gpr[13] & context->gpr[14];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_1101_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[14] = context->gpr[13] ^ context->gpr[14];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_1101_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[14] = context->gpr[13] | context->gpr[14];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_1101_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[13] ^ context->gpr[14];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_1101_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[13] << 16;
	context->gpr[14] = context->gpr[14] >> 16;
	context->gpr[14] = context->scratch1 | context->gpr[14];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_1101_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[14] & 65535)) * ((uint32_t)(context->gpr[13] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_1101_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[14])) * ((int32_t)((int16_t)context->gpr[13])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_1110_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[14] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[14], context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_1110_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[14] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[14], context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_1110_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[14] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[14], context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_1110_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[14] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->gpr[14] = context->gpr[14] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_1110_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[14] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->gpr[14] = context->gpr[14] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_1110_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[14] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->gpr[14] = context->gpr[14] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_1110_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[14] >> 31;
	context->m = context->gpr[14] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_1110_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[14] & context->gpr[14];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_1110_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[14] = context->gpr[14] & context->gpr[14];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_1110_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[14] = context->gpr[14] ^ context->gpr[14];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_1110_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[14] = context->gpr[14] | context->gpr[14];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_1110_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[14] ^ context->gpr[14];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_1110_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[14] << 16;
	context->gpr[14] = context->gpr[14] >> 16;
	context->gpr[14] = context->scratch1 | context->gpr[14];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_1110_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[14] & 65535)) * ((uint32_t)(context->gpr[14] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_1110_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[14])) * ((int32_t)((int16_t)context->gpr[14])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_1111_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[14] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[14], context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_1111_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[14] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[14], context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_1111_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[14] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[14], context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_1111_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[14] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->gpr[14] = context->gpr[14] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_1111_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[14] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->gpr[14] = context->gpr[14] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_1111_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[14] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->gpr[14] = context->gpr[14] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_1111_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[14] >> 31;
	context->m = context->gpr[15] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_1111_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[14] & context->gpr[15];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_1111_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[14] = context->gpr[15] & context->gpr[14];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_1111_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[14] = context->gpr[15] ^ context->gpr[14];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_1111_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[14] = context->gpr[15] | context->gpr[14];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_1111_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[15] ^ context->gpr[14];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_1111_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[15] << 16;
	context->gpr[14] = context->gpr[14] >> 16;
	context->gpr[14] = context->scratch1 | context->gpr[14];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_1111_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[14] & 65535)) * ((uint32_t)(context->gpr[15] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_1111_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[14])) * ((int32_t)((int16_t)context->gpr[15])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_0000_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[15] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[15], context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_0000_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[15] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[15], context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_0000_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[15] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[15], context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_0000_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[15] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->gpr[15] = context->gpr[15] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_0000_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[15] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->gpr[15] = context->gpr[15] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_0000_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[15] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->gpr[15] = context->gpr[15] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_0000_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[15] >> 31;
	context->m = context->gpr[0] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_0000_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[15] & context->gpr[0];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_0000_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[15] = context->gpr[0] & context->gpr[15];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_0000_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[15] = context->gpr[0] ^ context->gpr[15];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_0000_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[15] = context->gpr[0] | context->gpr[15];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_0000_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[0] ^ context->gpr[15];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_0000_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] << 16;
	context->gpr[15] = context->gpr[15] >> 16;
	context->gpr[15] = context->scratch1 | context->gpr[15];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_0000_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[15] & 65535)) * ((uint32_t)(context->gpr[0] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_0000_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[15])) * ((int32_t)((int16_t)context->gpr[0])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_0001_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[15] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[15], context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_0001_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[15] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[15], context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_0001_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[15] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[15], context, context->gpr[1]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_0001_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[15] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->gpr[15] = context->gpr[15] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_0001_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[15] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->gpr[15] = context->gpr[15] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_0001_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[15] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[1]);
	context->did_mem = 1;
	context->gpr[15] = context->gpr[15] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_0001_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[15] >> 31;
	context->m = context->gpr[1] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_0001_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[15] & context->gpr[1];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_0001_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[15] = context->gpr[1] & context->gpr[15];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_0001_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[15] = context->gpr[1] ^ context->gpr[15];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_0001_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[15] = context->gpr[1] | context->gpr[15];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_0001_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[1] ^ context->gpr[15];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_0001_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[1] << 16;
	context->gpr[15] = context->gpr[15] >> 16;
	context->gpr[15] = context->scratch1 | context->gpr[15];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_0001_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[15] & 65535)) * ((uint32_t)(context->gpr[1] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_0001_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[15])) * ((int32_t)((int16_t)context->gpr[1])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_0010_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[15] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[15], context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_0010_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[15] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[15], context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_0010_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[15] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[15], context, context->gpr[2]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_0010_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[15] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->gpr[15] = context->gpr[15] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_0010_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[15] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->gpr[15] = context->gpr[15] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_0010_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[15] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[2]);
	context->did_mem = 1;
	context->gpr[15] = context->gpr[15] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_0010_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[15] >> 31;
	context->m = context->gpr[2] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_0010_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[15] & context->gpr[2];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_0010_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[15] = context->gpr[2] & context->gpr[15];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_0010_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[15] = context->gpr[2] ^ context->gpr[15];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_0010_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[15] = context->gpr[2] | context->gpr[15];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_0010_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[2] ^ context->gpr[15];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_0010_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[2] << 16;
	context->gpr[15] = context->gpr[15] >> 16;
	context->gpr[15] = context->scratch1 | context->gpr[15];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_0010_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[15] & 65535)) * ((uint32_t)(context->gpr[2] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_0010_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[15])) * ((int32_t)((int16_t)context->gpr[2])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_0011_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[15] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[15], context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_0011_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[15] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[15], context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_0011_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[15] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[15], context, context->gpr[3]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_0011_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[15] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->gpr[15] = context->gpr[15] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_0011_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[15] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->gpr[15] = context->gpr[15] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_0011_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[15] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[3]);
	context->did_mem = 1;
	context->gpr[15] = context->gpr[15] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_0011_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[15] >> 31;
	context->m = context->gpr[3] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_0011_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[15] & context->gpr[3];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_0011_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[15] = context->gpr[3] & context->gpr[15];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_0011_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[15] = context->gpr[3] ^ context->gpr[15];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_0011_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[15] = context->gpr[3] | context->gpr[15];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_0011_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[3] ^ context->gpr[15];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_0011_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[3] << 16;
	context->gpr[15] = context->gpr[15] >> 16;
	context->gpr[15] = context->scratch1 | context->gpr[15];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_0011_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[15] & 65535)) * ((uint32_t)(context->gpr[3] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_0011_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[15])) * ((int32_t)((int16_t)context->gpr[3])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_0100_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[15] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[15], context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_0100_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[15] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[15], context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_0100_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[15] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[15], context, context->gpr[4]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_0100_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[15] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->gpr[15] = context->gpr[15] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_0100_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[15] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->gpr[15] = context->gpr[15] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_0100_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[15] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[4]);
	context->did_mem = 1;
	context->gpr[15] = context->gpr[15] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_0100_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[15] >> 31;
	context->m = context->gpr[4] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_0100_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[15] & context->gpr[4];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_0100_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[15] = context->gpr[4] & context->gpr[15];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_0100_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[15] = context->gpr[4] ^ context->gpr[15];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_0100_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[15] = context->gpr[4] | context->gpr[15];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_0100_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[4] ^ context->gpr[15];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_0100_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[4] << 16;
	context->gpr[15] = context->gpr[15] >> 16;
	context->gpr[15] = context->scratch1 | context->gpr[15];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_0100_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[15] & 65535)) * ((uint32_t)(context->gpr[4] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_0100_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[15])) * ((int32_t)((int16_t)context->gpr[4])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_0101_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[15] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[15], context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_0101_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[15] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[15], context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_0101_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[15] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[15], context, context->gpr[5]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_0101_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[15] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->gpr[15] = context->gpr[15] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_0101_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[15] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->gpr[15] = context->gpr[15] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_0101_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[15] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[5]);
	context->did_mem = 1;
	context->gpr[15] = context->gpr[15] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_0101_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[15] >> 31;
	context->m = context->gpr[5] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_0101_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[15] & context->gpr[5];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_0101_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[15] = context->gpr[5] & context->gpr[15];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_0101_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[15] = context->gpr[5] ^ context->gpr[15];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_0101_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[15] = context->gpr[5] | context->gpr[15];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_0101_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[5] ^ context->gpr[15];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_0101_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[5] << 16;
	context->gpr[15] = context->gpr[15] >> 16;
	context->gpr[15] = context->scratch1 | context->gpr[15];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_0101_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[15] & 65535)) * ((uint32_t)(context->gpr[5] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_0101_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[15])) * ((int32_t)((int16_t)context->gpr[5])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_0110_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[15] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[15], context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_0110_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[15] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[15], context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_0110_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[15] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[15], context, context->gpr[6]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_0110_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[15] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->gpr[15] = context->gpr[15] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_0110_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[15] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->gpr[15] = context->gpr[15] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_0110_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[15] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[6]);
	context->did_mem = 1;
	context->gpr[15] = context->gpr[15] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_0110_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[15] >> 31;
	context->m = context->gpr[6] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_0110_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[15] & context->gpr[6];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_0110_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[15] = context->gpr[6] & context->gpr[15];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_0110_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[15] = context->gpr[6] ^ context->gpr[15];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_0110_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[15] = context->gpr[6] | context->gpr[15];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_0110_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[6] ^ context->gpr[15];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_0110_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[6] << 16;
	context->gpr[15] = context->gpr[15] >> 16;
	context->gpr[15] = context->scratch1 | context->gpr[15];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_0110_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[15] & 65535)) * ((uint32_t)(context->gpr[6] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_0110_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[15])) * ((int32_t)((int16_t)context->gpr[6])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_0111_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[15] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[15], context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_0111_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[15] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[15], context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_0111_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[15] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[15], context, context->gpr[7]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_0111_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[15] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->gpr[15] = context->gpr[15] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_0111_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[15] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->gpr[15] = context->gpr[15] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_0111_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[15] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[7]);
	context->did_mem = 1;
	context->gpr[15] = context->gpr[15] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_0111_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[15] >> 31;
	context->m = context->gpr[7] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_0111_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[15] & context->gpr[7];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_0111_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[15] = context->gpr[7] & context->gpr[15];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_0111_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[15] = context->gpr[7] ^ context->gpr[15];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_0111_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[15] = context->gpr[7] | context->gpr[15];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_0111_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[7] ^ context->gpr[15];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_0111_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[7] << 16;
	context->gpr[15] = context->gpr[15] >> 16;
	context->gpr[15] = context->scratch1 | context->gpr[15];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_0111_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[15] & 65535)) * ((uint32_t)(context->gpr[7] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_0111_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[15])) * ((int32_t)((int16_t)context->gpr[7])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_1000_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[15] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[15], context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_1000_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[15] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[15], context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_1000_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[15] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[15], context, context->gpr[8]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_1000_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[15] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->gpr[15] = context->gpr[15] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_1000_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[15] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->gpr[15] = context->gpr[15] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_1000_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[15] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[8]);
	context->did_mem = 1;
	context->gpr[15] = context->gpr[15] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_1000_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[15] >> 31;
	context->m = context->gpr[8] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_1000_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[15] & context->gpr[8];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_1000_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[15] = context->gpr[8] & context->gpr[15];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_1000_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[15] = context->gpr[8] ^ context->gpr[15];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_1000_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[15] = context->gpr[8] | context->gpr[15];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_1000_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[8] ^ context->gpr[15];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_1000_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[8] << 16;
	context->gpr[15] = context->gpr[15] >> 16;
	context->gpr[15] = context->scratch1 | context->gpr[15];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_1000_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[15] & 65535)) * ((uint32_t)(context->gpr[8] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_1000_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[15])) * ((int32_t)((int16_t)context->gpr[8])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_1001_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[15] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[15], context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_1001_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[15] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[15], context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_1001_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[15] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[15], context, context->gpr[9]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_1001_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[15] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->gpr[15] = context->gpr[15] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_1001_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[15] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->gpr[15] = context->gpr[15] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_1001_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[15] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[9]);
	context->did_mem = 1;
	context->gpr[15] = context->gpr[15] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_1001_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[15] >> 31;
	context->m = context->gpr[9] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_1001_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[15] & context->gpr[9];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_1001_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[15] = context->gpr[9] & context->gpr[15];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_1001_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[15] = context->gpr[9] ^ context->gpr[15];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_1001_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[15] = context->gpr[9] | context->gpr[15];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_1001_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[9] ^ context->gpr[15];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_1001_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[9] << 16;
	context->gpr[15] = context->gpr[15] >> 16;
	context->gpr[15] = context->scratch1 | context->gpr[15];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_1001_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[15] & 65535)) * ((uint32_t)(context->gpr[9] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_1001_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[15])) * ((int32_t)((int16_t)context->gpr[9])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_1010_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[15] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[15], context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_1010_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[15] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[15], context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_1010_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[15] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[15], context, context->gpr[10]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_1010_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[15] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->gpr[15] = context->gpr[15] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_1010_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[15] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->gpr[15] = context->gpr[15] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_1010_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[15] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[10]);
	context->did_mem = 1;
	context->gpr[15] = context->gpr[15] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_1010_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[15] >> 31;
	context->m = context->gpr[10] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_1010_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[15] & context->gpr[10];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_1010_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[15] = context->gpr[10] & context->gpr[15];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_1010_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[15] = context->gpr[10] ^ context->gpr[15];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_1010_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[15] = context->gpr[10] | context->gpr[15];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_1010_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[10] ^ context->gpr[15];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_1010_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[10] << 16;
	context->gpr[15] = context->gpr[15] >> 16;
	context->gpr[15] = context->scratch1 | context->gpr[15];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_1010_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[15] & 65535)) * ((uint32_t)(context->gpr[10] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_1010_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[15])) * ((int32_t)((int16_t)context->gpr[10])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_1011_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[15] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[15], context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_1011_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[15] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[15], context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_1011_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[15] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[15], context, context->gpr[11]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_1011_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[15] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->gpr[15] = context->gpr[15] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_1011_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[15] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->gpr[15] = context->gpr[15] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_1011_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[15] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[11]);
	context->did_mem = 1;
	context->gpr[15] = context->gpr[15] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_1011_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[15] >> 31;
	context->m = context->gpr[11] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_1011_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[15] & context->gpr[11];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_1011_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[15] = context->gpr[11] & context->gpr[15];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_1011_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[15] = context->gpr[11] ^ context->gpr[15];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_1011_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[15] = context->gpr[11] | context->gpr[15];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_1011_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[11] ^ context->gpr[15];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_1011_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[11] << 16;
	context->gpr[15] = context->gpr[15] >> 16;
	context->gpr[15] = context->scratch1 | context->gpr[15];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_1011_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[15] & 65535)) * ((uint32_t)(context->gpr[11] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_1011_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[15])) * ((int32_t)((int16_t)context->gpr[11])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_1100_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[15] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[15], context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_1100_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[15] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[15], context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_1100_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[15] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[15], context, context->gpr[12]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_1100_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[15] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->gpr[15] = context->gpr[15] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_1100_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[15] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->gpr[15] = context->gpr[15] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_1100_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[15] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[12]);
	context->did_mem = 1;
	context->gpr[15] = context->gpr[15] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_1100_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[15] >> 31;
	context->m = context->gpr[12] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_1100_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[15] & context->gpr[12];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_1100_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[15] = context->gpr[12] & context->gpr[15];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_1100_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[15] = context->gpr[12] ^ context->gpr[15];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_1100_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[15] = context->gpr[12] | context->gpr[15];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_1100_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[12] ^ context->gpr[15];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_1100_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[12] << 16;
	context->gpr[15] = context->gpr[15] >> 16;
	context->gpr[15] = context->scratch1 | context->gpr[15];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_1100_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[15] & 65535)) * ((uint32_t)(context->gpr[12] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_1100_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[15])) * ((int32_t)((int16_t)context->gpr[12])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_1101_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[15] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[15], context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_1101_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[15] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[15], context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_1101_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[15] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[15], context, context->gpr[13]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_1101_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[15] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->gpr[15] = context->gpr[15] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_1101_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[15] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->gpr[15] = context->gpr[15] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_1101_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[15] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[13]);
	context->did_mem = 1;
	context->gpr[15] = context->gpr[15] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_1101_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[15] >> 31;
	context->m = context->gpr[13] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_1101_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[15] & context->gpr[13];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_1101_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[15] = context->gpr[13] & context->gpr[15];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_1101_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[15] = context->gpr[13] ^ context->gpr[15];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_1101_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[15] = context->gpr[13] | context->gpr[15];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_1101_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[13] ^ context->gpr[15];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_1101_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[13] << 16;
	context->gpr[15] = context->gpr[15] >> 16;
	context->gpr[15] = context->scratch1 | context->gpr[15];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_1101_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[15] & 65535)) * ((uint32_t)(context->gpr[13] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_1101_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[15])) * ((int32_t)((int16_t)context->gpr[13])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_1110_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[15] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[15], context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_1110_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[15] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[15], context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_1110_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[15] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[15], context, context->gpr[14]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_1110_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[15] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->gpr[15] = context->gpr[15] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_1110_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[15] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->gpr[15] = context->gpr[15] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_1110_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[15] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[14]);
	context->did_mem = 1;
	context->gpr[15] = context->gpr[15] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_1110_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[15] >> 31;
	context->m = context->gpr[14] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_1110_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[15] & context->gpr[14];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_1110_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[15] = context->gpr[14] & context->gpr[15];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_1110_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[15] = context->gpr[14] ^ context->gpr[15];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_1110_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[15] = context->gpr[14] | context->gpr[15];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_1110_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[14] ^ context->gpr[15];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_1110_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[14] << 16;
	context->gpr[15] = context->gpr[15] >> 16;
	context->gpr[15] = context->scratch1 | context->gpr[15];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_1110_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[15] & 65535)) * ((uint32_t)(context->gpr[14] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_1110_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[15])) * ((int32_t)((int16_t)context->gpr[14])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_b_M_1111_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write8_tmp = context->gpr[15] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[15], context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_w_M_1111_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write16_tmp = context->gpr[15] >> 29;
	context->write16[sh2_write16_tmp](context->gpr[15], context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_rm_rn_l_M_1111_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	sh2_write32_tmp = context->gpr[15] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[15], context, context->gpr[15]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_b_M_1111_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[15] - 1;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->gpr[15] = context->gpr[15] - 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_w_M_1111_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[15] - 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->gpr[15] = context->gpr[15] - 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_predec_rm_rn_l_M_1111_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[15] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[15]);
	context->did_mem = 1;
	context->gpr[15] = context->gpr[15] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div0s_M_1111_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->q = context->gpr[15] >> 31;
	context->m = context->gpr[15] >> 31;
	context->t = context->m ^ context->q;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_rm_rn_M_1111_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[15] & context->gpr[15];
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void and_rm_rn_M_1111_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[15] = context->gpr[15] & context->gpr[15];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_rm_rn_M_1111_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[15] = context->gpr[15] ^ context->gpr[15];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_rm_rn_M_1111_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[15] = context->gpr[15] | context->gpr[15];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpstr_rm_rn_M_1111_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint32_t hh;
	uint32_t hl;
	uint32_t lh;
	uint32_t ll;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[15] ^ context->gpr[15];
	hh = temp >> 24;
	hh = 255 & hh;
	hl = temp >> 16;
	hl = 255 & hl;
	lh = temp >> 8;
	lh = 255 & lh;
	ll = temp & 255;
	hh = !hh;
	hl = !hl;
	lh = !lh;
	ll = !ll;
	context->t = hh | hl;
	context->t = lh | context->t;
	context->t = ll | context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xtrct_M_1111_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[15] << 16;
	context->gpr[15] = context->gpr[15] >> 16;
	context->gpr[15] = context->scratch1 | context->gpr[15];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mulu_w_M_1111_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = ((uint32_t)(context->gpr[15] & 65535)) * ((uint32_t)(context->gpr[15] & 65535));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void muls_w_M_1111_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->macl = (int32_t)(((int32_t)((int16_t)context->gpr[15])) * ((int32_t)((int16_t)context->gpr[15])));
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_0000_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t cmp_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[0] - context->gpr[0];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_0000_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t cmp_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[0] >= context->gpr[0]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_0000_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t cmp_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[0]) >= ((int32_t)context->gpr[0])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_0000_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint8_t cmp_tmp8__;
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[0]) << 1 | ((uint64_t)context->gpr[0]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[0] >> 24 & 128U;
	context->gpr[0] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[0]) - ((uint64_t)context->gpr[0]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[0] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[0]) + ((uint64_t)context->gpr[0]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[0] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_0000_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[0] & 4294967295)) * ((uint64_t)(context->gpr[0] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_0000_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint64_t cmp_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[0]) - ((uint64_t)context->gpr[0]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_0000_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t cmp_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[0]) >= ((int32_t)context->gpr[0])) {
	if (context->gpr[0] == context->gpr[0]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_0000_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[0] = context->gpr[0] - context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_0000_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[0]) - ((uint64_t)context->gpr[0]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[0] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_0000_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[0] - context->gpr[0];
	context->t = (((context->gpr[0] ^ context->gpr[0])) & (context->gpr[0] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[0] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_0000_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[0] = context->gpr[0] + context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_0000_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[0])) * ((int64_t)((int32_t)context->gpr[0])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_0000_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[0]) + ((uint64_t)context->gpr[0]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[0] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_0000_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[0] + context->gpr[0];
	context->t = (((context->gpr[0] ^ (~context->gpr[0]))) & (context->gpr[0] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[0] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_0001_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[0] - context->gpr[1];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_0001_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[0] >= context->gpr[1]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_0001_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[0]) >= ((int32_t)context->gpr[1])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_0001_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[0]) << 1 | ((uint64_t)context->gpr[0]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[0] >> 24 & 128U;
	context->gpr[0] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[0]) - ((uint64_t)context->gpr[1]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[0] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[1]) + ((uint64_t)context->gpr[0]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[0] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_0001_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[0] & 4294967295)) * ((uint64_t)(context->gpr[1] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_0001_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[1]) - ((uint64_t)context->gpr[0]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_0001_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[0]) >= ((int32_t)context->gpr[1])) {
	if (context->gpr[0] == context->gpr[1]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_0001_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[0] = context->gpr[0] - context->gpr[1];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_0001_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[0]) - ((uint64_t)context->gpr[1]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[0] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_0001_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[0] - context->gpr[1];
	context->t = (((context->gpr[0] ^ context->gpr[1])) & (context->gpr[0] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[0] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_0001_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[0] = context->gpr[1] + context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_0001_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[0])) * ((int64_t)((int32_t)context->gpr[1])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_0001_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[1]) + ((uint64_t)context->gpr[0]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[0] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_0001_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[1] + context->gpr[0];
	context->t = (((context->gpr[1] ^ (~context->gpr[0]))) & (context->gpr[1] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[0] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_0010_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[0] - context->gpr[2];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_0010_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[0] >= context->gpr[2]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_0010_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[0]) >= ((int32_t)context->gpr[2])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_0010_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[0]) << 1 | ((uint64_t)context->gpr[0]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[0] >> 24 & 128U;
	context->gpr[0] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[0]) - ((uint64_t)context->gpr[2]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[0] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[2]) + ((uint64_t)context->gpr[0]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[0] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_0010_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[0] & 4294967295)) * ((uint64_t)(context->gpr[2] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_0010_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[2]) - ((uint64_t)context->gpr[0]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_0010_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[0]) >= ((int32_t)context->gpr[2])) {
	if (context->gpr[0] == context->gpr[2]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_0010_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[0] = context->gpr[0] - context->gpr[2];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_0010_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[0]) - ((uint64_t)context->gpr[2]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[0] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_0010_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[0] - context->gpr[2];
	context->t = (((context->gpr[0] ^ context->gpr[2])) & (context->gpr[0] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[0] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_0010_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[0] = context->gpr[2] + context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_0010_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[0])) * ((int64_t)((int32_t)context->gpr[2])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_0010_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[2]) + ((uint64_t)context->gpr[0]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[0] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_0010_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[2] + context->gpr[0];
	context->t = (((context->gpr[2] ^ (~context->gpr[0]))) & (context->gpr[2] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[0] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_0011_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[0] - context->gpr[3];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_0011_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[0] >= context->gpr[3]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_0011_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[0]) >= ((int32_t)context->gpr[3])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_0011_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[0]) << 1 | ((uint64_t)context->gpr[0]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[0] >> 24 & 128U;
	context->gpr[0] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[0]) - ((uint64_t)context->gpr[3]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[0] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[3]) + ((uint64_t)context->gpr[0]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[0] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_0011_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[0] & 4294967295)) * ((uint64_t)(context->gpr[3] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_0011_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[3]) - ((uint64_t)context->gpr[0]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_0011_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[0]) >= ((int32_t)context->gpr[3])) {
	if (context->gpr[0] == context->gpr[3]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_0011_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[0] = context->gpr[0] - context->gpr[3];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_0011_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[0]) - ((uint64_t)context->gpr[3]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[0] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_0011_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[0] - context->gpr[3];
	context->t = (((context->gpr[0] ^ context->gpr[3])) & (context->gpr[0] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[0] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_0011_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[0] = context->gpr[3] + context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_0011_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[0])) * ((int64_t)((int32_t)context->gpr[3])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_0011_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[3]) + ((uint64_t)context->gpr[0]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[0] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_0011_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[3] + context->gpr[0];
	context->t = (((context->gpr[3] ^ (~context->gpr[0]))) & (context->gpr[3] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[0] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_0100_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[0] - context->gpr[4];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_0100_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[0] >= context->gpr[4]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_0100_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[0]) >= ((int32_t)context->gpr[4])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_0100_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[0]) << 1 | ((uint64_t)context->gpr[0]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[0] >> 24 & 128U;
	context->gpr[0] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[0]) - ((uint64_t)context->gpr[4]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[0] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[4]) + ((uint64_t)context->gpr[0]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[0] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_0100_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[0] & 4294967295)) * ((uint64_t)(context->gpr[4] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_0100_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[4]) - ((uint64_t)context->gpr[0]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_0100_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[0]) >= ((int32_t)context->gpr[4])) {
	if (context->gpr[0] == context->gpr[4]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_0100_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[0] = context->gpr[0] - context->gpr[4];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_0100_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[0]) - ((uint64_t)context->gpr[4]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[0] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_0100_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[0] - context->gpr[4];
	context->t = (((context->gpr[0] ^ context->gpr[4])) & (context->gpr[0] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[0] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_0100_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[0] = context->gpr[4] + context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_0100_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[0])) * ((int64_t)((int32_t)context->gpr[4])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_0100_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[4]) + ((uint64_t)context->gpr[0]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[0] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_0100_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[4] + context->gpr[0];
	context->t = (((context->gpr[4] ^ (~context->gpr[0]))) & (context->gpr[4] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[0] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_0101_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[0] - context->gpr[5];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_0101_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[0] >= context->gpr[5]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_0101_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[0]) >= ((int32_t)context->gpr[5])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_0101_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[0]) << 1 | ((uint64_t)context->gpr[0]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[0] >> 24 & 128U;
	context->gpr[0] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[0]) - ((uint64_t)context->gpr[5]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[0] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[5]) + ((uint64_t)context->gpr[0]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[0] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_0101_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[0] & 4294967295)) * ((uint64_t)(context->gpr[5] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_0101_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[5]) - ((uint64_t)context->gpr[0]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_0101_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[0]) >= ((int32_t)context->gpr[5])) {
	if (context->gpr[0] == context->gpr[5]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_0101_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[0] = context->gpr[0] - context->gpr[5];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_0101_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[0]) - ((uint64_t)context->gpr[5]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[0] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_0101_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[0] - context->gpr[5];
	context->t = (((context->gpr[0] ^ context->gpr[5])) & (context->gpr[0] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[0] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_0101_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[0] = context->gpr[5] + context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_0101_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[0])) * ((int64_t)((int32_t)context->gpr[5])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_0101_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[5]) + ((uint64_t)context->gpr[0]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[0] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_0101_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[5] + context->gpr[0];
	context->t = (((context->gpr[5] ^ (~context->gpr[0]))) & (context->gpr[5] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[0] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_0110_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[0] - context->gpr[6];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_0110_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[0] >= context->gpr[6]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_0110_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[0]) >= ((int32_t)context->gpr[6])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_0110_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[0]) << 1 | ((uint64_t)context->gpr[0]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[0] >> 24 & 128U;
	context->gpr[0] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[0]) - ((uint64_t)context->gpr[6]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[0] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[6]) + ((uint64_t)context->gpr[0]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[0] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_0110_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[0] & 4294967295)) * ((uint64_t)(context->gpr[6] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_0110_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[6]) - ((uint64_t)context->gpr[0]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_0110_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[0]) >= ((int32_t)context->gpr[6])) {
	if (context->gpr[0] == context->gpr[6]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_0110_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[0] = context->gpr[0] - context->gpr[6];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_0110_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[0]) - ((uint64_t)context->gpr[6]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[0] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_0110_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[0] - context->gpr[6];
	context->t = (((context->gpr[0] ^ context->gpr[6])) & (context->gpr[0] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[0] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_0110_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[0] = context->gpr[6] + context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_0110_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[0])) * ((int64_t)((int32_t)context->gpr[6])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_0110_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[6]) + ((uint64_t)context->gpr[0]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[0] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_0110_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[6] + context->gpr[0];
	context->t = (((context->gpr[6] ^ (~context->gpr[0]))) & (context->gpr[6] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[0] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_0111_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[0] - context->gpr[7];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_0111_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[0] >= context->gpr[7]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_0111_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[0]) >= ((int32_t)context->gpr[7])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_0111_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[0]) << 1 | ((uint64_t)context->gpr[0]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[0] >> 24 & 128U;
	context->gpr[0] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[0]) - ((uint64_t)context->gpr[7]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[0] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[7]) + ((uint64_t)context->gpr[0]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[0] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_0111_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[0] & 4294967295)) * ((uint64_t)(context->gpr[7] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_0111_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[7]) - ((uint64_t)context->gpr[0]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_0111_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[0]) >= ((int32_t)context->gpr[7])) {
	if (context->gpr[0] == context->gpr[7]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_0111_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[0] = context->gpr[0] - context->gpr[7];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_0111_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[0]) - ((uint64_t)context->gpr[7]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[0] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_0111_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[0] - context->gpr[7];
	context->t = (((context->gpr[0] ^ context->gpr[7])) & (context->gpr[0] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[0] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_0111_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[0] = context->gpr[7] + context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_0111_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[0])) * ((int64_t)((int32_t)context->gpr[7])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_0111_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[7]) + ((uint64_t)context->gpr[0]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[0] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_0111_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[7] + context->gpr[0];
	context->t = (((context->gpr[7] ^ (~context->gpr[0]))) & (context->gpr[7] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[0] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_1000_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[0] - context->gpr[8];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_1000_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[0] >= context->gpr[8]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_1000_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[0]) >= ((int32_t)context->gpr[8])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_1000_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[0]) << 1 | ((uint64_t)context->gpr[0]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[0] >> 24 & 128U;
	context->gpr[0] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[0]) - ((uint64_t)context->gpr[8]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[0] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[8]) + ((uint64_t)context->gpr[0]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[0] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_1000_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[0] & 4294967295)) * ((uint64_t)(context->gpr[8] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_1000_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[8]) - ((uint64_t)context->gpr[0]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_1000_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[0]) >= ((int32_t)context->gpr[8])) {
	if (context->gpr[0] == context->gpr[8]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_1000_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[0] = context->gpr[0] - context->gpr[8];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_1000_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[0]) - ((uint64_t)context->gpr[8]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[0] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_1000_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[0] - context->gpr[8];
	context->t = (((context->gpr[0] ^ context->gpr[8])) & (context->gpr[0] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[0] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_1000_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[0] = context->gpr[8] + context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_1000_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[0])) * ((int64_t)((int32_t)context->gpr[8])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_1000_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[8]) + ((uint64_t)context->gpr[0]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[0] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_1000_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[8] + context->gpr[0];
	context->t = (((context->gpr[8] ^ (~context->gpr[0]))) & (context->gpr[8] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[0] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_1001_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[0] - context->gpr[9];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_1001_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[0] >= context->gpr[9]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_1001_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[0]) >= ((int32_t)context->gpr[9])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_1001_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[0]) << 1 | ((uint64_t)context->gpr[0]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[0] >> 24 & 128U;
	context->gpr[0] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[0]) - ((uint64_t)context->gpr[9]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[0] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[9]) + ((uint64_t)context->gpr[0]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[0] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_1001_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[0] & 4294967295)) * ((uint64_t)(context->gpr[9] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_1001_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[9]) - ((uint64_t)context->gpr[0]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_1001_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[0]) >= ((int32_t)context->gpr[9])) {
	if (context->gpr[0] == context->gpr[9]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_1001_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[0] = context->gpr[0] - context->gpr[9];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_1001_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[0]) - ((uint64_t)context->gpr[9]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[0] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_1001_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[0] - context->gpr[9];
	context->t = (((context->gpr[0] ^ context->gpr[9])) & (context->gpr[0] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[0] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_1001_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[0] = context->gpr[9] + context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_1001_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[0])) * ((int64_t)((int32_t)context->gpr[9])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_1001_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[9]) + ((uint64_t)context->gpr[0]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[0] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_1001_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[9] + context->gpr[0];
	context->t = (((context->gpr[9] ^ (~context->gpr[0]))) & (context->gpr[9] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[0] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_1010_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[0] - context->gpr[10];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_1010_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[0] >= context->gpr[10]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_1010_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[0]) >= ((int32_t)context->gpr[10])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_1010_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[0]) << 1 | ((uint64_t)context->gpr[0]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[0] >> 24 & 128U;
	context->gpr[0] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[0]) - ((uint64_t)context->gpr[10]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[0] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[10]) + ((uint64_t)context->gpr[0]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[0] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_1010_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[0] & 4294967295)) * ((uint64_t)(context->gpr[10] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_1010_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[10]) - ((uint64_t)context->gpr[0]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_1010_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[0]) >= ((int32_t)context->gpr[10])) {
	if (context->gpr[0] == context->gpr[10]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_1010_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[0] = context->gpr[0] - context->gpr[10];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_1010_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[0]) - ((uint64_t)context->gpr[10]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[0] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_1010_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[0] - context->gpr[10];
	context->t = (((context->gpr[0] ^ context->gpr[10])) & (context->gpr[0] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[0] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_1010_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[0] = context->gpr[10] + context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_1010_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[0])) * ((int64_t)((int32_t)context->gpr[10])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_1010_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[10]) + ((uint64_t)context->gpr[0]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[0] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_1010_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[10] + context->gpr[0];
	context->t = (((context->gpr[10] ^ (~context->gpr[0]))) & (context->gpr[10] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[0] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_1011_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[0] - context->gpr[11];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_1011_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[0] >= context->gpr[11]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_1011_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[0]) >= ((int32_t)context->gpr[11])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_1011_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[0]) << 1 | ((uint64_t)context->gpr[0]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[0] >> 24 & 128U;
	context->gpr[0] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[0]) - ((uint64_t)context->gpr[11]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[0] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[11]) + ((uint64_t)context->gpr[0]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[0] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_1011_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[0] & 4294967295)) * ((uint64_t)(context->gpr[11] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_1011_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[11]) - ((uint64_t)context->gpr[0]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_1011_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[0]) >= ((int32_t)context->gpr[11])) {
	if (context->gpr[0] == context->gpr[11]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_1011_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[0] = context->gpr[0] - context->gpr[11];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_1011_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[0]) - ((uint64_t)context->gpr[11]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[0] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_1011_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[0] - context->gpr[11];
	context->t = (((context->gpr[0] ^ context->gpr[11])) & (context->gpr[0] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[0] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_1011_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[0] = context->gpr[11] + context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_1011_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[0])) * ((int64_t)((int32_t)context->gpr[11])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_1011_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[11]) + ((uint64_t)context->gpr[0]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[0] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_1011_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[11] + context->gpr[0];
	context->t = (((context->gpr[11] ^ (~context->gpr[0]))) & (context->gpr[11] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[0] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_1100_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[0] - context->gpr[12];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_1100_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[0] >= context->gpr[12]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_1100_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[0]) >= ((int32_t)context->gpr[12])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_1100_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[0]) << 1 | ((uint64_t)context->gpr[0]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[0] >> 24 & 128U;
	context->gpr[0] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[0]) - ((uint64_t)context->gpr[12]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[0] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[12]) + ((uint64_t)context->gpr[0]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[0] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_1100_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[0] & 4294967295)) * ((uint64_t)(context->gpr[12] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_1100_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[12]) - ((uint64_t)context->gpr[0]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_1100_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[0]) >= ((int32_t)context->gpr[12])) {
	if (context->gpr[0] == context->gpr[12]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_1100_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[0] = context->gpr[0] - context->gpr[12];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_1100_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[0]) - ((uint64_t)context->gpr[12]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[0] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_1100_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[0] - context->gpr[12];
	context->t = (((context->gpr[0] ^ context->gpr[12])) & (context->gpr[0] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[0] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_1100_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[0] = context->gpr[12] + context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_1100_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[0])) * ((int64_t)((int32_t)context->gpr[12])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_1100_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[12]) + ((uint64_t)context->gpr[0]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[0] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_1100_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[12] + context->gpr[0];
	context->t = (((context->gpr[12] ^ (~context->gpr[0]))) & (context->gpr[12] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[0] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_1101_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[0] - context->gpr[13];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_1101_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[0] >= context->gpr[13]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_1101_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[0]) >= ((int32_t)context->gpr[13])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_1101_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[0]) << 1 | ((uint64_t)context->gpr[0]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[0] >> 24 & 128U;
	context->gpr[0] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[0]) - ((uint64_t)context->gpr[13]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[0] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[13]) + ((uint64_t)context->gpr[0]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[0] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_1101_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[0] & 4294967295)) * ((uint64_t)(context->gpr[13] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_1101_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[13]) - ((uint64_t)context->gpr[0]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_1101_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[0]) >= ((int32_t)context->gpr[13])) {
	if (context->gpr[0] == context->gpr[13]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_1101_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[0] = context->gpr[0] - context->gpr[13];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_1101_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[0]) - ((uint64_t)context->gpr[13]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[0] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_1101_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[0] - context->gpr[13];
	context->t = (((context->gpr[0] ^ context->gpr[13])) & (context->gpr[0] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[0] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_1101_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[0] = context->gpr[13] + context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_1101_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[0])) * ((int64_t)((int32_t)context->gpr[13])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_1101_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[13]) + ((uint64_t)context->gpr[0]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[0] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_1101_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[13] + context->gpr[0];
	context->t = (((context->gpr[13] ^ (~context->gpr[0]))) & (context->gpr[13] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[0] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_1110_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[0] - context->gpr[14];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_1110_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[0] >= context->gpr[14]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_1110_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[0]) >= ((int32_t)context->gpr[14])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_1110_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[0]) << 1 | ((uint64_t)context->gpr[0]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[0] >> 24 & 128U;
	context->gpr[0] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[0]) - ((uint64_t)context->gpr[14]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[0] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[14]) + ((uint64_t)context->gpr[0]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[0] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_1110_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[0] & 4294967295)) * ((uint64_t)(context->gpr[14] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_1110_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[14]) - ((uint64_t)context->gpr[0]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_1110_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[0]) >= ((int32_t)context->gpr[14])) {
	if (context->gpr[0] == context->gpr[14]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_1110_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[0] = context->gpr[0] - context->gpr[14];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_1110_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[0]) - ((uint64_t)context->gpr[14]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[0] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_1110_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[0] - context->gpr[14];
	context->t = (((context->gpr[0] ^ context->gpr[14])) & (context->gpr[0] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[0] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_1110_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[0] = context->gpr[14] + context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_1110_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[0])) * ((int64_t)((int32_t)context->gpr[14])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_1110_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[14]) + ((uint64_t)context->gpr[0]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[0] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_1110_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[14] + context->gpr[0];
	context->t = (((context->gpr[14] ^ (~context->gpr[0]))) & (context->gpr[14] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[0] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_1111_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[0] - context->gpr[15];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_1111_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[0] >= context->gpr[15]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_1111_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[0]) >= ((int32_t)context->gpr[15])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_1111_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[0]) << 1 | ((uint64_t)context->gpr[0]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[0] >> 24 & 128U;
	context->gpr[0] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[0]) - ((uint64_t)context->gpr[15]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[0] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[15]) + ((uint64_t)context->gpr[0]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[0] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_1111_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[0] & 4294967295)) * ((uint64_t)(context->gpr[15] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_1111_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[15]) - ((uint64_t)context->gpr[0]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_1111_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[0]) >= ((int32_t)context->gpr[15])) {
	if (context->gpr[0] == context->gpr[15]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_1111_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[0] = context->gpr[0] - context->gpr[15];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_1111_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[0]) - ((uint64_t)context->gpr[15]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[0] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_1111_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[0] - context->gpr[15];
	context->t = (((context->gpr[0] ^ context->gpr[15])) & (context->gpr[0] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[0] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_1111_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[0] = context->gpr[15] + context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_1111_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[0])) * ((int64_t)((int32_t)context->gpr[15])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_1111_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[15]) + ((uint64_t)context->gpr[0]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[0] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_1111_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[15] + context->gpr[0];
	context->t = (((context->gpr[15] ^ (~context->gpr[0]))) & (context->gpr[15] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[0] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_0000_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[1] - context->gpr[0];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_0000_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[1] >= context->gpr[0]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_0000_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[1]) >= ((int32_t)context->gpr[0])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_0000_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[1]) << 1 | ((uint64_t)context->gpr[1]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[1] >> 24 & 128U;
	context->gpr[1] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[1]) - ((uint64_t)context->gpr[0]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[1] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[0]) + ((uint64_t)context->gpr[1]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[1] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_0000_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[1] & 4294967295)) * ((uint64_t)(context->gpr[0] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_0000_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[0]) - ((uint64_t)context->gpr[1]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_0000_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[1]) >= ((int32_t)context->gpr[0])) {
	if (context->gpr[1] == context->gpr[0]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_0000_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[1] = context->gpr[1] - context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_0000_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[1]) - ((uint64_t)context->gpr[0]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[1] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_0000_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[1] - context->gpr[0];
	context->t = (((context->gpr[1] ^ context->gpr[0])) & (context->gpr[1] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[1] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_0000_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[1] = context->gpr[0] + context->gpr[1];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_0000_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[1])) * ((int64_t)((int32_t)context->gpr[0])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_0000_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[0]) + ((uint64_t)context->gpr[1]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[1] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_0000_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[0] + context->gpr[1];
	context->t = (((context->gpr[0] ^ (~context->gpr[1]))) & (context->gpr[0] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[1] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_0001_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[1] - context->gpr[1];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_0001_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[1] >= context->gpr[1]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_0001_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[1]) >= ((int32_t)context->gpr[1])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_0001_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[1]) << 1 | ((uint64_t)context->gpr[1]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[1] >> 24 & 128U;
	context->gpr[1] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[1]) - ((uint64_t)context->gpr[1]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[1] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[1]) + ((uint64_t)context->gpr[1]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[1] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_0001_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[1] & 4294967295)) * ((uint64_t)(context->gpr[1] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_0001_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[1]) - ((uint64_t)context->gpr[1]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_0001_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[1]) >= ((int32_t)context->gpr[1])) {
	if (context->gpr[1] == context->gpr[1]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_0001_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[1] = context->gpr[1] - context->gpr[1];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_0001_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[1]) - ((uint64_t)context->gpr[1]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[1] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_0001_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[1] - context->gpr[1];
	context->t = (((context->gpr[1] ^ context->gpr[1])) & (context->gpr[1] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[1] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_0001_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[1] = context->gpr[1] + context->gpr[1];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_0001_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[1])) * ((int64_t)((int32_t)context->gpr[1])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_0001_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[1]) + ((uint64_t)context->gpr[1]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[1] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_0001_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[1] + context->gpr[1];
	context->t = (((context->gpr[1] ^ (~context->gpr[1]))) & (context->gpr[1] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[1] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_0010_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[1] - context->gpr[2];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_0010_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[1] >= context->gpr[2]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_0010_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[1]) >= ((int32_t)context->gpr[2])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_0010_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[1]) << 1 | ((uint64_t)context->gpr[1]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[1] >> 24 & 128U;
	context->gpr[1] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[1]) - ((uint64_t)context->gpr[2]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[1] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[2]) + ((uint64_t)context->gpr[1]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[1] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_0010_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[1] & 4294967295)) * ((uint64_t)(context->gpr[2] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_0010_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[2]) - ((uint64_t)context->gpr[1]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_0010_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[1]) >= ((int32_t)context->gpr[2])) {
	if (context->gpr[1] == context->gpr[2]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_0010_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[1] = context->gpr[1] - context->gpr[2];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_0010_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[1]) - ((uint64_t)context->gpr[2]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[1] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_0010_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[1] - context->gpr[2];
	context->t = (((context->gpr[1] ^ context->gpr[2])) & (context->gpr[1] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[1] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_0010_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[1] = context->gpr[2] + context->gpr[1];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_0010_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[1])) * ((int64_t)((int32_t)context->gpr[2])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_0010_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[2]) + ((uint64_t)context->gpr[1]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[1] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_0010_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[2] + context->gpr[1];
	context->t = (((context->gpr[2] ^ (~context->gpr[1]))) & (context->gpr[2] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[1] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_0011_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[1] - context->gpr[3];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_0011_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[1] >= context->gpr[3]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_0011_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[1]) >= ((int32_t)context->gpr[3])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_0011_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[1]) << 1 | ((uint64_t)context->gpr[1]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[1] >> 24 & 128U;
	context->gpr[1] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[1]) - ((uint64_t)context->gpr[3]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[1] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[3]) + ((uint64_t)context->gpr[1]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[1] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_0011_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[1] & 4294967295)) * ((uint64_t)(context->gpr[3] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_0011_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[3]) - ((uint64_t)context->gpr[1]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_0011_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[1]) >= ((int32_t)context->gpr[3])) {
	if (context->gpr[1] == context->gpr[3]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_0011_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[1] = context->gpr[1] - context->gpr[3];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_0011_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[1]) - ((uint64_t)context->gpr[3]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[1] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_0011_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[1] - context->gpr[3];
	context->t = (((context->gpr[1] ^ context->gpr[3])) & (context->gpr[1] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[1] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_0011_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[1] = context->gpr[3] + context->gpr[1];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_0011_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[1])) * ((int64_t)((int32_t)context->gpr[3])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_0011_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[3]) + ((uint64_t)context->gpr[1]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[1] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_0011_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[3] + context->gpr[1];
	context->t = (((context->gpr[3] ^ (~context->gpr[1]))) & (context->gpr[3] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[1] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_0100_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[1] - context->gpr[4];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_0100_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[1] >= context->gpr[4]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_0100_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[1]) >= ((int32_t)context->gpr[4])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_0100_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[1]) << 1 | ((uint64_t)context->gpr[1]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[1] >> 24 & 128U;
	context->gpr[1] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[1]) - ((uint64_t)context->gpr[4]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[1] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[4]) + ((uint64_t)context->gpr[1]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[1] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_0100_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[1] & 4294967295)) * ((uint64_t)(context->gpr[4] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_0100_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[4]) - ((uint64_t)context->gpr[1]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_0100_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[1]) >= ((int32_t)context->gpr[4])) {
	if (context->gpr[1] == context->gpr[4]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_0100_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[1] = context->gpr[1] - context->gpr[4];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_0100_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[1]) - ((uint64_t)context->gpr[4]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[1] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_0100_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[1] - context->gpr[4];
	context->t = (((context->gpr[1] ^ context->gpr[4])) & (context->gpr[1] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[1] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_0100_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[1] = context->gpr[4] + context->gpr[1];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_0100_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[1])) * ((int64_t)((int32_t)context->gpr[4])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_0100_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[4]) + ((uint64_t)context->gpr[1]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[1] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_0100_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[4] + context->gpr[1];
	context->t = (((context->gpr[4] ^ (~context->gpr[1]))) & (context->gpr[4] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[1] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_0101_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[1] - context->gpr[5];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_0101_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[1] >= context->gpr[5]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_0101_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[1]) >= ((int32_t)context->gpr[5])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_0101_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[1]) << 1 | ((uint64_t)context->gpr[1]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[1] >> 24 & 128U;
	context->gpr[1] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[1]) - ((uint64_t)context->gpr[5]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[1] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[5]) + ((uint64_t)context->gpr[1]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[1] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_0101_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[1] & 4294967295)) * ((uint64_t)(context->gpr[5] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_0101_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[5]) - ((uint64_t)context->gpr[1]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_0101_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[1]) >= ((int32_t)context->gpr[5])) {
	if (context->gpr[1] == context->gpr[5]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_0101_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[1] = context->gpr[1] - context->gpr[5];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_0101_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[1]) - ((uint64_t)context->gpr[5]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[1] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_0101_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[1] - context->gpr[5];
	context->t = (((context->gpr[1] ^ context->gpr[5])) & (context->gpr[1] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[1] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_0101_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[1] = context->gpr[5] + context->gpr[1];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_0101_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[1])) * ((int64_t)((int32_t)context->gpr[5])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_0101_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[5]) + ((uint64_t)context->gpr[1]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[1] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_0101_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[5] + context->gpr[1];
	context->t = (((context->gpr[5] ^ (~context->gpr[1]))) & (context->gpr[5] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[1] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_0110_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[1] - context->gpr[6];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_0110_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[1] >= context->gpr[6]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_0110_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[1]) >= ((int32_t)context->gpr[6])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_0110_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[1]) << 1 | ((uint64_t)context->gpr[1]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[1] >> 24 & 128U;
	context->gpr[1] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[1]) - ((uint64_t)context->gpr[6]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[1] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[6]) + ((uint64_t)context->gpr[1]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[1] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_0110_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[1] & 4294967295)) * ((uint64_t)(context->gpr[6] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_0110_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[6]) - ((uint64_t)context->gpr[1]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_0110_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[1]) >= ((int32_t)context->gpr[6])) {
	if (context->gpr[1] == context->gpr[6]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_0110_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[1] = context->gpr[1] - context->gpr[6];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_0110_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[1]) - ((uint64_t)context->gpr[6]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[1] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_0110_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[1] - context->gpr[6];
	context->t = (((context->gpr[1] ^ context->gpr[6])) & (context->gpr[1] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[1] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_0110_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[1] = context->gpr[6] + context->gpr[1];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_0110_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[1])) * ((int64_t)((int32_t)context->gpr[6])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_0110_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[6]) + ((uint64_t)context->gpr[1]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[1] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_0110_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[6] + context->gpr[1];
	context->t = (((context->gpr[6] ^ (~context->gpr[1]))) & (context->gpr[6] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[1] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_0111_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[1] - context->gpr[7];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_0111_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[1] >= context->gpr[7]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_0111_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[1]) >= ((int32_t)context->gpr[7])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_0111_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[1]) << 1 | ((uint64_t)context->gpr[1]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[1] >> 24 & 128U;
	context->gpr[1] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[1]) - ((uint64_t)context->gpr[7]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[1] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[7]) + ((uint64_t)context->gpr[1]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[1] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_0111_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[1] & 4294967295)) * ((uint64_t)(context->gpr[7] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_0111_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[7]) - ((uint64_t)context->gpr[1]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_0111_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[1]) >= ((int32_t)context->gpr[7])) {
	if (context->gpr[1] == context->gpr[7]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_0111_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[1] = context->gpr[1] - context->gpr[7];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_0111_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[1]) - ((uint64_t)context->gpr[7]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[1] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_0111_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[1] - context->gpr[7];
	context->t = (((context->gpr[1] ^ context->gpr[7])) & (context->gpr[1] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[1] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_0111_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[1] = context->gpr[7] + context->gpr[1];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_0111_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[1])) * ((int64_t)((int32_t)context->gpr[7])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_0111_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[7]) + ((uint64_t)context->gpr[1]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[1] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_0111_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[7] + context->gpr[1];
	context->t = (((context->gpr[7] ^ (~context->gpr[1]))) & (context->gpr[7] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[1] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_1000_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[1] - context->gpr[8];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_1000_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[1] >= context->gpr[8]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_1000_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[1]) >= ((int32_t)context->gpr[8])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_1000_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[1]) << 1 | ((uint64_t)context->gpr[1]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[1] >> 24 & 128U;
	context->gpr[1] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[1]) - ((uint64_t)context->gpr[8]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[1] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[8]) + ((uint64_t)context->gpr[1]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[1] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_1000_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[1] & 4294967295)) * ((uint64_t)(context->gpr[8] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_1000_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[8]) - ((uint64_t)context->gpr[1]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_1000_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[1]) >= ((int32_t)context->gpr[8])) {
	if (context->gpr[1] == context->gpr[8]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_1000_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[1] = context->gpr[1] - context->gpr[8];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_1000_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[1]) - ((uint64_t)context->gpr[8]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[1] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_1000_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[1] - context->gpr[8];
	context->t = (((context->gpr[1] ^ context->gpr[8])) & (context->gpr[1] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[1] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_1000_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[1] = context->gpr[8] + context->gpr[1];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_1000_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[1])) * ((int64_t)((int32_t)context->gpr[8])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_1000_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[8]) + ((uint64_t)context->gpr[1]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[1] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_1000_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[8] + context->gpr[1];
	context->t = (((context->gpr[8] ^ (~context->gpr[1]))) & (context->gpr[8] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[1] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_1001_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[1] - context->gpr[9];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_1001_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[1] >= context->gpr[9]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_1001_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[1]) >= ((int32_t)context->gpr[9])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_1001_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[1]) << 1 | ((uint64_t)context->gpr[1]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[1] >> 24 & 128U;
	context->gpr[1] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[1]) - ((uint64_t)context->gpr[9]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[1] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[9]) + ((uint64_t)context->gpr[1]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[1] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_1001_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[1] & 4294967295)) * ((uint64_t)(context->gpr[9] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_1001_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[9]) - ((uint64_t)context->gpr[1]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_1001_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[1]) >= ((int32_t)context->gpr[9])) {
	if (context->gpr[1] == context->gpr[9]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_1001_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[1] = context->gpr[1] - context->gpr[9];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_1001_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[1]) - ((uint64_t)context->gpr[9]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[1] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_1001_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[1] - context->gpr[9];
	context->t = (((context->gpr[1] ^ context->gpr[9])) & (context->gpr[1] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[1] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_1001_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[1] = context->gpr[9] + context->gpr[1];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_1001_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[1])) * ((int64_t)((int32_t)context->gpr[9])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_1001_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[9]) + ((uint64_t)context->gpr[1]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[1] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_1001_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[9] + context->gpr[1];
	context->t = (((context->gpr[9] ^ (~context->gpr[1]))) & (context->gpr[9] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[1] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_1010_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[1] - context->gpr[10];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_1010_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[1] >= context->gpr[10]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_1010_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[1]) >= ((int32_t)context->gpr[10])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_1010_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[1]) << 1 | ((uint64_t)context->gpr[1]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[1] >> 24 & 128U;
	context->gpr[1] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[1]) - ((uint64_t)context->gpr[10]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[1] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[10]) + ((uint64_t)context->gpr[1]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[1] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_1010_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[1] & 4294967295)) * ((uint64_t)(context->gpr[10] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_1010_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[10]) - ((uint64_t)context->gpr[1]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_1010_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[1]) >= ((int32_t)context->gpr[10])) {
	if (context->gpr[1] == context->gpr[10]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_1010_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[1] = context->gpr[1] - context->gpr[10];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_1010_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[1]) - ((uint64_t)context->gpr[10]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[1] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_1010_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[1] - context->gpr[10];
	context->t = (((context->gpr[1] ^ context->gpr[10])) & (context->gpr[1] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[1] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_1010_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[1] = context->gpr[10] + context->gpr[1];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_1010_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[1])) * ((int64_t)((int32_t)context->gpr[10])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_1010_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[10]) + ((uint64_t)context->gpr[1]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[1] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_1010_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[10] + context->gpr[1];
	context->t = (((context->gpr[10] ^ (~context->gpr[1]))) & (context->gpr[10] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[1] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_1011_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[1] - context->gpr[11];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_1011_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[1] >= context->gpr[11]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_1011_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[1]) >= ((int32_t)context->gpr[11])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_1011_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[1]) << 1 | ((uint64_t)context->gpr[1]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[1] >> 24 & 128U;
	context->gpr[1] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[1]) - ((uint64_t)context->gpr[11]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[1] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[11]) + ((uint64_t)context->gpr[1]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[1] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_1011_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[1] & 4294967295)) * ((uint64_t)(context->gpr[11] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_1011_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[11]) - ((uint64_t)context->gpr[1]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_1011_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[1]) >= ((int32_t)context->gpr[11])) {
	if (context->gpr[1] == context->gpr[11]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_1011_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[1] = context->gpr[1] - context->gpr[11];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_1011_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[1]) - ((uint64_t)context->gpr[11]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[1] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_1011_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[1] - context->gpr[11];
	context->t = (((context->gpr[1] ^ context->gpr[11])) & (context->gpr[1] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[1] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_1011_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[1] = context->gpr[11] + context->gpr[1];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_1011_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[1])) * ((int64_t)((int32_t)context->gpr[11])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_1011_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[11]) + ((uint64_t)context->gpr[1]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[1] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_1011_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[11] + context->gpr[1];
	context->t = (((context->gpr[11] ^ (~context->gpr[1]))) & (context->gpr[11] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[1] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_1100_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[1] - context->gpr[12];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_1100_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[1] >= context->gpr[12]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_1100_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[1]) >= ((int32_t)context->gpr[12])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_1100_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[1]) << 1 | ((uint64_t)context->gpr[1]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[1] >> 24 & 128U;
	context->gpr[1] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[1]) - ((uint64_t)context->gpr[12]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[1] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[12]) + ((uint64_t)context->gpr[1]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[1] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_1100_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[1] & 4294967295)) * ((uint64_t)(context->gpr[12] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_1100_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[12]) - ((uint64_t)context->gpr[1]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_1100_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[1]) >= ((int32_t)context->gpr[12])) {
	if (context->gpr[1] == context->gpr[12]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_1100_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[1] = context->gpr[1] - context->gpr[12];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_1100_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[1]) - ((uint64_t)context->gpr[12]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[1] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_1100_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[1] - context->gpr[12];
	context->t = (((context->gpr[1] ^ context->gpr[12])) & (context->gpr[1] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[1] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_1100_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[1] = context->gpr[12] + context->gpr[1];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_1100_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[1])) * ((int64_t)((int32_t)context->gpr[12])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_1100_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[12]) + ((uint64_t)context->gpr[1]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[1] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_1100_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[12] + context->gpr[1];
	context->t = (((context->gpr[12] ^ (~context->gpr[1]))) & (context->gpr[12] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[1] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_1101_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[1] - context->gpr[13];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_1101_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[1] >= context->gpr[13]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_1101_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[1]) >= ((int32_t)context->gpr[13])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_1101_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[1]) << 1 | ((uint64_t)context->gpr[1]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[1] >> 24 & 128U;
	context->gpr[1] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[1]) - ((uint64_t)context->gpr[13]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[1] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[13]) + ((uint64_t)context->gpr[1]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[1] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_1101_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[1] & 4294967295)) * ((uint64_t)(context->gpr[13] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_1101_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[13]) - ((uint64_t)context->gpr[1]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_1101_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[1]) >= ((int32_t)context->gpr[13])) {
	if (context->gpr[1] == context->gpr[13]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_1101_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[1] = context->gpr[1] - context->gpr[13];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_1101_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[1]) - ((uint64_t)context->gpr[13]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[1] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_1101_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[1] - context->gpr[13];
	context->t = (((context->gpr[1] ^ context->gpr[13])) & (context->gpr[1] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[1] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_1101_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[1] = context->gpr[13] + context->gpr[1];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_1101_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[1])) * ((int64_t)((int32_t)context->gpr[13])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_1101_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[13]) + ((uint64_t)context->gpr[1]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[1] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_1101_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[13] + context->gpr[1];
	context->t = (((context->gpr[13] ^ (~context->gpr[1]))) & (context->gpr[13] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[1] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_1110_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[1] - context->gpr[14];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_1110_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[1] >= context->gpr[14]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_1110_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[1]) >= ((int32_t)context->gpr[14])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_1110_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[1]) << 1 | ((uint64_t)context->gpr[1]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[1] >> 24 & 128U;
	context->gpr[1] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[1]) - ((uint64_t)context->gpr[14]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[1] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[14]) + ((uint64_t)context->gpr[1]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[1] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_1110_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[1] & 4294967295)) * ((uint64_t)(context->gpr[14] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_1110_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[14]) - ((uint64_t)context->gpr[1]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_1110_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[1]) >= ((int32_t)context->gpr[14])) {
	if (context->gpr[1] == context->gpr[14]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_1110_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[1] = context->gpr[1] - context->gpr[14];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_1110_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[1]) - ((uint64_t)context->gpr[14]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[1] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_1110_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[1] - context->gpr[14];
	context->t = (((context->gpr[1] ^ context->gpr[14])) & (context->gpr[1] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[1] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_1110_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[1] = context->gpr[14] + context->gpr[1];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_1110_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[1])) * ((int64_t)((int32_t)context->gpr[14])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_1110_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[14]) + ((uint64_t)context->gpr[1]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[1] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_1110_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[14] + context->gpr[1];
	context->t = (((context->gpr[14] ^ (~context->gpr[1]))) & (context->gpr[14] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[1] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_1111_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[1] - context->gpr[15];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_1111_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[1] >= context->gpr[15]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_1111_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[1]) >= ((int32_t)context->gpr[15])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_1111_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[1]) << 1 | ((uint64_t)context->gpr[1]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[1] >> 24 & 128U;
	context->gpr[1] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[1]) - ((uint64_t)context->gpr[15]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[1] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[15]) + ((uint64_t)context->gpr[1]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[1] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_1111_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[1] & 4294967295)) * ((uint64_t)(context->gpr[15] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_1111_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[15]) - ((uint64_t)context->gpr[1]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_1111_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[1]) >= ((int32_t)context->gpr[15])) {
	if (context->gpr[1] == context->gpr[15]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_1111_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[1] = context->gpr[1] - context->gpr[15];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_1111_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[1]) - ((uint64_t)context->gpr[15]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[1] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_1111_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[1] - context->gpr[15];
	context->t = (((context->gpr[1] ^ context->gpr[15])) & (context->gpr[1] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[1] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_1111_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[1] = context->gpr[15] + context->gpr[1];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_1111_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[1])) * ((int64_t)((int32_t)context->gpr[15])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_1111_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[15]) + ((uint64_t)context->gpr[1]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[1] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_1111_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[15] + context->gpr[1];
	context->t = (((context->gpr[15] ^ (~context->gpr[1]))) & (context->gpr[15] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[1] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_0000_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[2] - context->gpr[0];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_0000_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[2] >= context->gpr[0]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_0000_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[2]) >= ((int32_t)context->gpr[0])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_0000_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[2]) << 1 | ((uint64_t)context->gpr[2]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[2] >> 24 & 128U;
	context->gpr[2] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[2]) - ((uint64_t)context->gpr[0]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[2] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[0]) + ((uint64_t)context->gpr[2]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[2] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_0000_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[2] & 4294967295)) * ((uint64_t)(context->gpr[0] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_0000_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[0]) - ((uint64_t)context->gpr[2]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_0000_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[2]) >= ((int32_t)context->gpr[0])) {
	if (context->gpr[2] == context->gpr[0]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_0000_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[2] = context->gpr[2] - context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_0000_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[2]) - ((uint64_t)context->gpr[0]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[2] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_0000_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[2] - context->gpr[0];
	context->t = (((context->gpr[2] ^ context->gpr[0])) & (context->gpr[2] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[2] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_0000_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[2] = context->gpr[0] + context->gpr[2];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_0000_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[2])) * ((int64_t)((int32_t)context->gpr[0])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_0000_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[0]) + ((uint64_t)context->gpr[2]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[2] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_0000_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[0] + context->gpr[2];
	context->t = (((context->gpr[0] ^ (~context->gpr[2]))) & (context->gpr[0] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[2] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_0001_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[2] - context->gpr[1];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_0001_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[2] >= context->gpr[1]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_0001_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[2]) >= ((int32_t)context->gpr[1])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_0001_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[2]) << 1 | ((uint64_t)context->gpr[2]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[2] >> 24 & 128U;
	context->gpr[2] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[2]) - ((uint64_t)context->gpr[1]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[2] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[1]) + ((uint64_t)context->gpr[2]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[2] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_0001_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[2] & 4294967295)) * ((uint64_t)(context->gpr[1] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_0001_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[1]) - ((uint64_t)context->gpr[2]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_0001_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[2]) >= ((int32_t)context->gpr[1])) {
	if (context->gpr[2] == context->gpr[1]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_0001_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[2] = context->gpr[2] - context->gpr[1];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_0001_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[2]) - ((uint64_t)context->gpr[1]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[2] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_0001_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[2] - context->gpr[1];
	context->t = (((context->gpr[2] ^ context->gpr[1])) & (context->gpr[2] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[2] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_0001_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[2] = context->gpr[1] + context->gpr[2];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_0001_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[2])) * ((int64_t)((int32_t)context->gpr[1])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_0001_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[1]) + ((uint64_t)context->gpr[2]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[2] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_0001_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[1] + context->gpr[2];
	context->t = (((context->gpr[1] ^ (~context->gpr[2]))) & (context->gpr[1] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[2] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_0010_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[2] - context->gpr[2];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_0010_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[2] >= context->gpr[2]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_0010_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[2]) >= ((int32_t)context->gpr[2])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_0010_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[2]) << 1 | ((uint64_t)context->gpr[2]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[2] >> 24 & 128U;
	context->gpr[2] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[2]) - ((uint64_t)context->gpr[2]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[2] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[2]) + ((uint64_t)context->gpr[2]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[2] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_0010_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[2] & 4294967295)) * ((uint64_t)(context->gpr[2] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_0010_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[2]) - ((uint64_t)context->gpr[2]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_0010_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[2]) >= ((int32_t)context->gpr[2])) {
	if (context->gpr[2] == context->gpr[2]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_0010_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[2] = context->gpr[2] - context->gpr[2];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_0010_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[2]) - ((uint64_t)context->gpr[2]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[2] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_0010_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[2] - context->gpr[2];
	context->t = (((context->gpr[2] ^ context->gpr[2])) & (context->gpr[2] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[2] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_0010_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[2] = context->gpr[2] + context->gpr[2];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_0010_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[2])) * ((int64_t)((int32_t)context->gpr[2])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_0010_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[2]) + ((uint64_t)context->gpr[2]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[2] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_0010_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[2] + context->gpr[2];
	context->t = (((context->gpr[2] ^ (~context->gpr[2]))) & (context->gpr[2] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[2] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_0011_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[2] - context->gpr[3];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_0011_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[2] >= context->gpr[3]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_0011_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[2]) >= ((int32_t)context->gpr[3])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_0011_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[2]) << 1 | ((uint64_t)context->gpr[2]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[2] >> 24 & 128U;
	context->gpr[2] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[2]) - ((uint64_t)context->gpr[3]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[2] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[3]) + ((uint64_t)context->gpr[2]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[2] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_0011_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[2] & 4294967295)) * ((uint64_t)(context->gpr[3] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_0011_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[3]) - ((uint64_t)context->gpr[2]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_0011_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[2]) >= ((int32_t)context->gpr[3])) {
	if (context->gpr[2] == context->gpr[3]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_0011_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[2] = context->gpr[2] - context->gpr[3];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_0011_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[2]) - ((uint64_t)context->gpr[3]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[2] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_0011_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[2] - context->gpr[3];
	context->t = (((context->gpr[2] ^ context->gpr[3])) & (context->gpr[2] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[2] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_0011_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[2] = context->gpr[3] + context->gpr[2];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_0011_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[2])) * ((int64_t)((int32_t)context->gpr[3])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_0011_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[3]) + ((uint64_t)context->gpr[2]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[2] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_0011_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[3] + context->gpr[2];
	context->t = (((context->gpr[3] ^ (~context->gpr[2]))) & (context->gpr[3] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[2] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_0100_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[2] - context->gpr[4];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_0100_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[2] >= context->gpr[4]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_0100_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[2]) >= ((int32_t)context->gpr[4])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_0100_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[2]) << 1 | ((uint64_t)context->gpr[2]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[2] >> 24 & 128U;
	context->gpr[2] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[2]) - ((uint64_t)context->gpr[4]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[2] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[4]) + ((uint64_t)context->gpr[2]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[2] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_0100_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[2] & 4294967295)) * ((uint64_t)(context->gpr[4] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_0100_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[4]) - ((uint64_t)context->gpr[2]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_0100_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[2]) >= ((int32_t)context->gpr[4])) {
	if (context->gpr[2] == context->gpr[4]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_0100_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[2] = context->gpr[2] - context->gpr[4];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_0100_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[2]) - ((uint64_t)context->gpr[4]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[2] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_0100_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[2] - context->gpr[4];
	context->t = (((context->gpr[2] ^ context->gpr[4])) & (context->gpr[2] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[2] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_0100_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[2] = context->gpr[4] + context->gpr[2];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_0100_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[2])) * ((int64_t)((int32_t)context->gpr[4])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_0100_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[4]) + ((uint64_t)context->gpr[2]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[2] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_0100_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[4] + context->gpr[2];
	context->t = (((context->gpr[4] ^ (~context->gpr[2]))) & (context->gpr[4] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[2] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_0101_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[2] - context->gpr[5];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_0101_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[2] >= context->gpr[5]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_0101_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[2]) >= ((int32_t)context->gpr[5])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_0101_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[2]) << 1 | ((uint64_t)context->gpr[2]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[2] >> 24 & 128U;
	context->gpr[2] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[2]) - ((uint64_t)context->gpr[5]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[2] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[5]) + ((uint64_t)context->gpr[2]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[2] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_0101_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[2] & 4294967295)) * ((uint64_t)(context->gpr[5] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_0101_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[5]) - ((uint64_t)context->gpr[2]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_0101_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[2]) >= ((int32_t)context->gpr[5])) {
	if (context->gpr[2] == context->gpr[5]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_0101_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[2] = context->gpr[2] - context->gpr[5];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_0101_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[2]) - ((uint64_t)context->gpr[5]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[2] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_0101_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[2] - context->gpr[5];
	context->t = (((context->gpr[2] ^ context->gpr[5])) & (context->gpr[2] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[2] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_0101_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[2] = context->gpr[5] + context->gpr[2];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_0101_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[2])) * ((int64_t)((int32_t)context->gpr[5])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_0101_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[5]) + ((uint64_t)context->gpr[2]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[2] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_0101_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[5] + context->gpr[2];
	context->t = (((context->gpr[5] ^ (~context->gpr[2]))) & (context->gpr[5] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[2] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_0110_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[2] - context->gpr[6];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_0110_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[2] >= context->gpr[6]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_0110_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[2]) >= ((int32_t)context->gpr[6])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_0110_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[2]) << 1 | ((uint64_t)context->gpr[2]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[2] >> 24 & 128U;
	context->gpr[2] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[2]) - ((uint64_t)context->gpr[6]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[2] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[6]) + ((uint64_t)context->gpr[2]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[2] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_0110_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[2] & 4294967295)) * ((uint64_t)(context->gpr[6] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_0110_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[6]) - ((uint64_t)context->gpr[2]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_0110_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[2]) >= ((int32_t)context->gpr[6])) {
	if (context->gpr[2] == context->gpr[6]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_0110_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[2] = context->gpr[2] - context->gpr[6];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_0110_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[2]) - ((uint64_t)context->gpr[6]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[2] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_0110_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[2] - context->gpr[6];
	context->t = (((context->gpr[2] ^ context->gpr[6])) & (context->gpr[2] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[2] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_0110_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[2] = context->gpr[6] + context->gpr[2];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_0110_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[2])) * ((int64_t)((int32_t)context->gpr[6])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_0110_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[6]) + ((uint64_t)context->gpr[2]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[2] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_0110_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[6] + context->gpr[2];
	context->t = (((context->gpr[6] ^ (~context->gpr[2]))) & (context->gpr[6] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[2] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_0111_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[2] - context->gpr[7];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_0111_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[2] >= context->gpr[7]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_0111_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[2]) >= ((int32_t)context->gpr[7])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_0111_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[2]) << 1 | ((uint64_t)context->gpr[2]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[2] >> 24 & 128U;
	context->gpr[2] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[2]) - ((uint64_t)context->gpr[7]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[2] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[7]) + ((uint64_t)context->gpr[2]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[2] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_0111_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[2] & 4294967295)) * ((uint64_t)(context->gpr[7] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_0111_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[7]) - ((uint64_t)context->gpr[2]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_0111_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[2]) >= ((int32_t)context->gpr[7])) {
	if (context->gpr[2] == context->gpr[7]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_0111_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[2] = context->gpr[2] - context->gpr[7];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_0111_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[2]) - ((uint64_t)context->gpr[7]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[2] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_0111_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[2] - context->gpr[7];
	context->t = (((context->gpr[2] ^ context->gpr[7])) & (context->gpr[2] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[2] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_0111_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[2] = context->gpr[7] + context->gpr[2];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_0111_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[2])) * ((int64_t)((int32_t)context->gpr[7])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_0111_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[7]) + ((uint64_t)context->gpr[2]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[2] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_0111_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[7] + context->gpr[2];
	context->t = (((context->gpr[7] ^ (~context->gpr[2]))) & (context->gpr[7] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[2] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_1000_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[2] - context->gpr[8];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_1000_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[2] >= context->gpr[8]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_1000_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[2]) >= ((int32_t)context->gpr[8])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_1000_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[2]) << 1 | ((uint64_t)context->gpr[2]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[2] >> 24 & 128U;
	context->gpr[2] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[2]) - ((uint64_t)context->gpr[8]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[2] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[8]) + ((uint64_t)context->gpr[2]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[2] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_1000_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[2] & 4294967295)) * ((uint64_t)(context->gpr[8] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_1000_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[8]) - ((uint64_t)context->gpr[2]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_1000_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[2]) >= ((int32_t)context->gpr[8])) {
	if (context->gpr[2] == context->gpr[8]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_1000_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[2] = context->gpr[2] - context->gpr[8];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_1000_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[2]) - ((uint64_t)context->gpr[8]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[2] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_1000_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[2] - context->gpr[8];
	context->t = (((context->gpr[2] ^ context->gpr[8])) & (context->gpr[2] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[2] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_1000_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[2] = context->gpr[8] + context->gpr[2];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_1000_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[2])) * ((int64_t)((int32_t)context->gpr[8])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_1000_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[8]) + ((uint64_t)context->gpr[2]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[2] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_1000_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[8] + context->gpr[2];
	context->t = (((context->gpr[8] ^ (~context->gpr[2]))) & (context->gpr[8] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[2] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_1001_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[2] - context->gpr[9];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_1001_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[2] >= context->gpr[9]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_1001_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[2]) >= ((int32_t)context->gpr[9])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_1001_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[2]) << 1 | ((uint64_t)context->gpr[2]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[2] >> 24 & 128U;
	context->gpr[2] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[2]) - ((uint64_t)context->gpr[9]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[2] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[9]) + ((uint64_t)context->gpr[2]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[2] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_1001_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[2] & 4294967295)) * ((uint64_t)(context->gpr[9] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_1001_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[9]) - ((uint64_t)context->gpr[2]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_1001_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[2]) >= ((int32_t)context->gpr[9])) {
	if (context->gpr[2] == context->gpr[9]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_1001_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[2] = context->gpr[2] - context->gpr[9];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_1001_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[2]) - ((uint64_t)context->gpr[9]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[2] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_1001_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[2] - context->gpr[9];
	context->t = (((context->gpr[2] ^ context->gpr[9])) & (context->gpr[2] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[2] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_1001_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[2] = context->gpr[9] + context->gpr[2];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_1001_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[2])) * ((int64_t)((int32_t)context->gpr[9])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_1001_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[9]) + ((uint64_t)context->gpr[2]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[2] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_1001_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[9] + context->gpr[2];
	context->t = (((context->gpr[9] ^ (~context->gpr[2]))) & (context->gpr[9] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[2] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_1010_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[2] - context->gpr[10];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_1010_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[2] >= context->gpr[10]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_1010_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[2]) >= ((int32_t)context->gpr[10])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_1010_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[2]) << 1 | ((uint64_t)context->gpr[2]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[2] >> 24 & 128U;
	context->gpr[2] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[2]) - ((uint64_t)context->gpr[10]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[2] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[10]) + ((uint64_t)context->gpr[2]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[2] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_1010_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[2] & 4294967295)) * ((uint64_t)(context->gpr[10] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_1010_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[10]) - ((uint64_t)context->gpr[2]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_1010_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[2]) >= ((int32_t)context->gpr[10])) {
	if (context->gpr[2] == context->gpr[10]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_1010_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[2] = context->gpr[2] - context->gpr[10];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_1010_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[2]) - ((uint64_t)context->gpr[10]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[2] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_1010_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[2] - context->gpr[10];
	context->t = (((context->gpr[2] ^ context->gpr[10])) & (context->gpr[2] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[2] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_1010_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[2] = context->gpr[10] + context->gpr[2];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_1010_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[2])) * ((int64_t)((int32_t)context->gpr[10])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_1010_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[10]) + ((uint64_t)context->gpr[2]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[2] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_1010_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[10] + context->gpr[2];
	context->t = (((context->gpr[10] ^ (~context->gpr[2]))) & (context->gpr[10] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[2] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_1011_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[2] - context->gpr[11];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_1011_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[2] >= context->gpr[11]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_1011_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[2]) >= ((int32_t)context->gpr[11])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_1011_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[2]) << 1 | ((uint64_t)context->gpr[2]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[2] >> 24 & 128U;
	context->gpr[2] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[2]) - ((uint64_t)context->gpr[11]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[2] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[11]) + ((uint64_t)context->gpr[2]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[2] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_1011_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[2] & 4294967295)) * ((uint64_t)(context->gpr[11] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_1011_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[11]) - ((uint64_t)context->gpr[2]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_1011_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[2]) >= ((int32_t)context->gpr[11])) {
	if (context->gpr[2] == context->gpr[11]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_1011_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[2] = context->gpr[2] - context->gpr[11];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_1011_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[2]) - ((uint64_t)context->gpr[11]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[2] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_1011_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[2] - context->gpr[11];
	context->t = (((context->gpr[2] ^ context->gpr[11])) & (context->gpr[2] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[2] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_1011_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[2] = context->gpr[11] + context->gpr[2];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_1011_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[2])) * ((int64_t)((int32_t)context->gpr[11])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_1011_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[11]) + ((uint64_t)context->gpr[2]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[2] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_1011_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[11] + context->gpr[2];
	context->t = (((context->gpr[11] ^ (~context->gpr[2]))) & (context->gpr[11] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[2] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_1100_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[2] - context->gpr[12];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_1100_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[2] >= context->gpr[12]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_1100_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[2]) >= ((int32_t)context->gpr[12])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_1100_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[2]) << 1 | ((uint64_t)context->gpr[2]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[2] >> 24 & 128U;
	context->gpr[2] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[2]) - ((uint64_t)context->gpr[12]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[2] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[12]) + ((uint64_t)context->gpr[2]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[2] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_1100_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[2] & 4294967295)) * ((uint64_t)(context->gpr[12] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_1100_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[12]) - ((uint64_t)context->gpr[2]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_1100_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[2]) >= ((int32_t)context->gpr[12])) {
	if (context->gpr[2] == context->gpr[12]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_1100_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[2] = context->gpr[2] - context->gpr[12];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_1100_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[2]) - ((uint64_t)context->gpr[12]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[2] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_1100_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[2] - context->gpr[12];
	context->t = (((context->gpr[2] ^ context->gpr[12])) & (context->gpr[2] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[2] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_1100_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[2] = context->gpr[12] + context->gpr[2];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_1100_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[2])) * ((int64_t)((int32_t)context->gpr[12])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_1100_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[12]) + ((uint64_t)context->gpr[2]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[2] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_1100_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[12] + context->gpr[2];
	context->t = (((context->gpr[12] ^ (~context->gpr[2]))) & (context->gpr[12] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[2] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_1101_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[2] - context->gpr[13];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_1101_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[2] >= context->gpr[13]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_1101_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[2]) >= ((int32_t)context->gpr[13])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_1101_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[2]) << 1 | ((uint64_t)context->gpr[2]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[2] >> 24 & 128U;
	context->gpr[2] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[2]) - ((uint64_t)context->gpr[13]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[2] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[13]) + ((uint64_t)context->gpr[2]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[2] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_1101_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[2] & 4294967295)) * ((uint64_t)(context->gpr[13] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_1101_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[13]) - ((uint64_t)context->gpr[2]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_1101_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[2]) >= ((int32_t)context->gpr[13])) {
	if (context->gpr[2] == context->gpr[13]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_1101_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[2] = context->gpr[2] - context->gpr[13];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_1101_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[2]) - ((uint64_t)context->gpr[13]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[2] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_1101_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[2] - context->gpr[13];
	context->t = (((context->gpr[2] ^ context->gpr[13])) & (context->gpr[2] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[2] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_1101_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[2] = context->gpr[13] + context->gpr[2];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_1101_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[2])) * ((int64_t)((int32_t)context->gpr[13])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_1101_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[13]) + ((uint64_t)context->gpr[2]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[2] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_1101_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[13] + context->gpr[2];
	context->t = (((context->gpr[13] ^ (~context->gpr[2]))) & (context->gpr[13] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[2] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_1110_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[2] - context->gpr[14];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_1110_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[2] >= context->gpr[14]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_1110_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[2]) >= ((int32_t)context->gpr[14])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_1110_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[2]) << 1 | ((uint64_t)context->gpr[2]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[2] >> 24 & 128U;
	context->gpr[2] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[2]) - ((uint64_t)context->gpr[14]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[2] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[14]) + ((uint64_t)context->gpr[2]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[2] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_1110_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[2] & 4294967295)) * ((uint64_t)(context->gpr[14] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_1110_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[14]) - ((uint64_t)context->gpr[2]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_1110_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[2]) >= ((int32_t)context->gpr[14])) {
	if (context->gpr[2] == context->gpr[14]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_1110_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[2] = context->gpr[2] - context->gpr[14];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_1110_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[2]) - ((uint64_t)context->gpr[14]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[2] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_1110_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[2] - context->gpr[14];
	context->t = (((context->gpr[2] ^ context->gpr[14])) & (context->gpr[2] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[2] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_1110_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[2] = context->gpr[14] + context->gpr[2];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_1110_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[2])) * ((int64_t)((int32_t)context->gpr[14])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_1110_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[14]) + ((uint64_t)context->gpr[2]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[2] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_1110_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[14] + context->gpr[2];
	context->t = (((context->gpr[14] ^ (~context->gpr[2]))) & (context->gpr[14] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[2] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_1111_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[2] - context->gpr[15];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_1111_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[2] >= context->gpr[15]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_1111_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[2]) >= ((int32_t)context->gpr[15])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_1111_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[2]) << 1 | ((uint64_t)context->gpr[2]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[2] >> 24 & 128U;
	context->gpr[2] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[2]) - ((uint64_t)context->gpr[15]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[2] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[15]) + ((uint64_t)context->gpr[2]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[2] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_1111_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[2] & 4294967295)) * ((uint64_t)(context->gpr[15] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_1111_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[15]) - ((uint64_t)context->gpr[2]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_1111_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[2]) >= ((int32_t)context->gpr[15])) {
	if (context->gpr[2] == context->gpr[15]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_1111_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[2] = context->gpr[2] - context->gpr[15];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_1111_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[2]) - ((uint64_t)context->gpr[15]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[2] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_1111_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[2] - context->gpr[15];
	context->t = (((context->gpr[2] ^ context->gpr[15])) & (context->gpr[2] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[2] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_1111_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[2] = context->gpr[15] + context->gpr[2];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_1111_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[2])) * ((int64_t)((int32_t)context->gpr[15])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_1111_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[15]) + ((uint64_t)context->gpr[2]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[2] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_1111_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[15] + context->gpr[2];
	context->t = (((context->gpr[15] ^ (~context->gpr[2]))) & (context->gpr[15] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[2] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_0000_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[3] - context->gpr[0];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_0000_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[3] >= context->gpr[0]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_0000_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[3]) >= ((int32_t)context->gpr[0])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_0000_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[3]) << 1 | ((uint64_t)context->gpr[3]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[3] >> 24 & 128U;
	context->gpr[3] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[3]) - ((uint64_t)context->gpr[0]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[3] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[0]) + ((uint64_t)context->gpr[3]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[3] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_0000_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[3] & 4294967295)) * ((uint64_t)(context->gpr[0] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_0000_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[0]) - ((uint64_t)context->gpr[3]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_0000_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[3]) >= ((int32_t)context->gpr[0])) {
	if (context->gpr[3] == context->gpr[0]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_0000_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[3] = context->gpr[3] - context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_0000_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[3]) - ((uint64_t)context->gpr[0]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[3] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_0000_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[3] - context->gpr[0];
	context->t = (((context->gpr[3] ^ context->gpr[0])) & (context->gpr[3] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[3] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_0000_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[3] = context->gpr[0] + context->gpr[3];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_0000_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[3])) * ((int64_t)((int32_t)context->gpr[0])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_0000_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[0]) + ((uint64_t)context->gpr[3]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[3] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_0000_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[0] + context->gpr[3];
	context->t = (((context->gpr[0] ^ (~context->gpr[3]))) & (context->gpr[0] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[3] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_0001_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[3] - context->gpr[1];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_0001_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[3] >= context->gpr[1]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_0001_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[3]) >= ((int32_t)context->gpr[1])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_0001_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[3]) << 1 | ((uint64_t)context->gpr[3]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[3] >> 24 & 128U;
	context->gpr[3] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[3]) - ((uint64_t)context->gpr[1]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[3] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[1]) + ((uint64_t)context->gpr[3]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[3] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_0001_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[3] & 4294967295)) * ((uint64_t)(context->gpr[1] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_0001_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[1]) - ((uint64_t)context->gpr[3]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_0001_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[3]) >= ((int32_t)context->gpr[1])) {
	if (context->gpr[3] == context->gpr[1]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_0001_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[3] = context->gpr[3] - context->gpr[1];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_0001_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[3]) - ((uint64_t)context->gpr[1]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[3] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_0001_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[3] - context->gpr[1];
	context->t = (((context->gpr[3] ^ context->gpr[1])) & (context->gpr[3] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[3] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_0001_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[3] = context->gpr[1] + context->gpr[3];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_0001_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[3])) * ((int64_t)((int32_t)context->gpr[1])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_0001_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[1]) + ((uint64_t)context->gpr[3]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[3] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_0001_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[1] + context->gpr[3];
	context->t = (((context->gpr[1] ^ (~context->gpr[3]))) & (context->gpr[1] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[3] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_0010_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[3] - context->gpr[2];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_0010_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[3] >= context->gpr[2]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_0010_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[3]) >= ((int32_t)context->gpr[2])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_0010_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[3]) << 1 | ((uint64_t)context->gpr[3]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[3] >> 24 & 128U;
	context->gpr[3] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[3]) - ((uint64_t)context->gpr[2]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[3] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[2]) + ((uint64_t)context->gpr[3]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[3] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_0010_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[3] & 4294967295)) * ((uint64_t)(context->gpr[2] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_0010_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[2]) - ((uint64_t)context->gpr[3]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_0010_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[3]) >= ((int32_t)context->gpr[2])) {
	if (context->gpr[3] == context->gpr[2]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_0010_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[3] = context->gpr[3] - context->gpr[2];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_0010_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[3]) - ((uint64_t)context->gpr[2]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[3] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_0010_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[3] - context->gpr[2];
	context->t = (((context->gpr[3] ^ context->gpr[2])) & (context->gpr[3] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[3] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_0010_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[3] = context->gpr[2] + context->gpr[3];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_0010_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[3])) * ((int64_t)((int32_t)context->gpr[2])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_0010_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[2]) + ((uint64_t)context->gpr[3]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[3] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_0010_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[2] + context->gpr[3];
	context->t = (((context->gpr[2] ^ (~context->gpr[3]))) & (context->gpr[2] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[3] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_0011_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[3] - context->gpr[3];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_0011_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[3] >= context->gpr[3]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_0011_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[3]) >= ((int32_t)context->gpr[3])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_0011_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[3]) << 1 | ((uint64_t)context->gpr[3]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[3] >> 24 & 128U;
	context->gpr[3] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[3]) - ((uint64_t)context->gpr[3]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[3] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[3]) + ((uint64_t)context->gpr[3]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[3] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_0011_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[3] & 4294967295)) * ((uint64_t)(context->gpr[3] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_0011_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[3]) - ((uint64_t)context->gpr[3]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_0011_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[3]) >= ((int32_t)context->gpr[3])) {
	if (context->gpr[3] == context->gpr[3]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_0011_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[3] = context->gpr[3] - context->gpr[3];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_0011_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[3]) - ((uint64_t)context->gpr[3]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[3] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_0011_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[3] - context->gpr[3];
	context->t = (((context->gpr[3] ^ context->gpr[3])) & (context->gpr[3] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[3] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_0011_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[3] = context->gpr[3] + context->gpr[3];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_0011_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[3])) * ((int64_t)((int32_t)context->gpr[3])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_0011_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[3]) + ((uint64_t)context->gpr[3]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[3] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_0011_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[3] + context->gpr[3];
	context->t = (((context->gpr[3] ^ (~context->gpr[3]))) & (context->gpr[3] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[3] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_0100_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[3] - context->gpr[4];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_0100_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[3] >= context->gpr[4]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_0100_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[3]) >= ((int32_t)context->gpr[4])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_0100_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[3]) << 1 | ((uint64_t)context->gpr[3]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[3] >> 24 & 128U;
	context->gpr[3] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[3]) - ((uint64_t)context->gpr[4]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[3] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[4]) + ((uint64_t)context->gpr[3]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[3] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_0100_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[3] & 4294967295)) * ((uint64_t)(context->gpr[4] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_0100_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[4]) - ((uint64_t)context->gpr[3]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_0100_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[3]) >= ((int32_t)context->gpr[4])) {
	if (context->gpr[3] == context->gpr[4]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_0100_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[3] = context->gpr[3] - context->gpr[4];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_0100_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[3]) - ((uint64_t)context->gpr[4]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[3] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_0100_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[3] - context->gpr[4];
	context->t = (((context->gpr[3] ^ context->gpr[4])) & (context->gpr[3] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[3] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_0100_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[3] = context->gpr[4] + context->gpr[3];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_0100_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[3])) * ((int64_t)((int32_t)context->gpr[4])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_0100_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[4]) + ((uint64_t)context->gpr[3]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[3] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_0100_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[4] + context->gpr[3];
	context->t = (((context->gpr[4] ^ (~context->gpr[3]))) & (context->gpr[4] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[3] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_0101_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[3] - context->gpr[5];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_0101_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[3] >= context->gpr[5]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_0101_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[3]) >= ((int32_t)context->gpr[5])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_0101_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[3]) << 1 | ((uint64_t)context->gpr[3]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[3] >> 24 & 128U;
	context->gpr[3] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[3]) - ((uint64_t)context->gpr[5]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[3] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[5]) + ((uint64_t)context->gpr[3]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[3] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_0101_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[3] & 4294967295)) * ((uint64_t)(context->gpr[5] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_0101_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[5]) - ((uint64_t)context->gpr[3]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_0101_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[3]) >= ((int32_t)context->gpr[5])) {
	if (context->gpr[3] == context->gpr[5]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_0101_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[3] = context->gpr[3] - context->gpr[5];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_0101_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[3]) - ((uint64_t)context->gpr[5]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[3] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_0101_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[3] - context->gpr[5];
	context->t = (((context->gpr[3] ^ context->gpr[5])) & (context->gpr[3] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[3] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_0101_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[3] = context->gpr[5] + context->gpr[3];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_0101_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[3])) * ((int64_t)((int32_t)context->gpr[5])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_0101_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[5]) + ((uint64_t)context->gpr[3]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[3] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_0101_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[5] + context->gpr[3];
	context->t = (((context->gpr[5] ^ (~context->gpr[3]))) & (context->gpr[5] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[3] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_0110_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[3] - context->gpr[6];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_0110_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[3] >= context->gpr[6]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_0110_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[3]) >= ((int32_t)context->gpr[6])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_0110_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[3]) << 1 | ((uint64_t)context->gpr[3]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[3] >> 24 & 128U;
	context->gpr[3] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[3]) - ((uint64_t)context->gpr[6]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[3] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[6]) + ((uint64_t)context->gpr[3]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[3] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_0110_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[3] & 4294967295)) * ((uint64_t)(context->gpr[6] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_0110_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[6]) - ((uint64_t)context->gpr[3]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_0110_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[3]) >= ((int32_t)context->gpr[6])) {
	if (context->gpr[3] == context->gpr[6]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_0110_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[3] = context->gpr[3] - context->gpr[6];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_0110_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[3]) - ((uint64_t)context->gpr[6]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[3] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_0110_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[3] - context->gpr[6];
	context->t = (((context->gpr[3] ^ context->gpr[6])) & (context->gpr[3] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[3] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_0110_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[3] = context->gpr[6] + context->gpr[3];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_0110_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[3])) * ((int64_t)((int32_t)context->gpr[6])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_0110_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[6]) + ((uint64_t)context->gpr[3]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[3] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_0110_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[6] + context->gpr[3];
	context->t = (((context->gpr[6] ^ (~context->gpr[3]))) & (context->gpr[6] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[3] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_0111_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[3] - context->gpr[7];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_0111_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[3] >= context->gpr[7]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_0111_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[3]) >= ((int32_t)context->gpr[7])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_0111_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[3]) << 1 | ((uint64_t)context->gpr[3]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[3] >> 24 & 128U;
	context->gpr[3] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[3]) - ((uint64_t)context->gpr[7]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[3] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[7]) + ((uint64_t)context->gpr[3]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[3] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_0111_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[3] & 4294967295)) * ((uint64_t)(context->gpr[7] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_0111_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[7]) - ((uint64_t)context->gpr[3]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_0111_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[3]) >= ((int32_t)context->gpr[7])) {
	if (context->gpr[3] == context->gpr[7]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_0111_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[3] = context->gpr[3] - context->gpr[7];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_0111_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[3]) - ((uint64_t)context->gpr[7]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[3] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_0111_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[3] - context->gpr[7];
	context->t = (((context->gpr[3] ^ context->gpr[7])) & (context->gpr[3] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[3] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_0111_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[3] = context->gpr[7] + context->gpr[3];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_0111_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[3])) * ((int64_t)((int32_t)context->gpr[7])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_0111_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[7]) + ((uint64_t)context->gpr[3]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[3] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_0111_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[7] + context->gpr[3];
	context->t = (((context->gpr[7] ^ (~context->gpr[3]))) & (context->gpr[7] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[3] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_1000_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[3] - context->gpr[8];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_1000_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[3] >= context->gpr[8]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_1000_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[3]) >= ((int32_t)context->gpr[8])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_1000_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[3]) << 1 | ((uint64_t)context->gpr[3]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[3] >> 24 & 128U;
	context->gpr[3] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[3]) - ((uint64_t)context->gpr[8]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[3] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[8]) + ((uint64_t)context->gpr[3]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[3] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_1000_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[3] & 4294967295)) * ((uint64_t)(context->gpr[8] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_1000_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[8]) - ((uint64_t)context->gpr[3]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_1000_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[3]) >= ((int32_t)context->gpr[8])) {
	if (context->gpr[3] == context->gpr[8]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_1000_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[3] = context->gpr[3] - context->gpr[8];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_1000_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[3]) - ((uint64_t)context->gpr[8]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[3] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_1000_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[3] - context->gpr[8];
	context->t = (((context->gpr[3] ^ context->gpr[8])) & (context->gpr[3] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[3] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_1000_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[3] = context->gpr[8] + context->gpr[3];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_1000_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[3])) * ((int64_t)((int32_t)context->gpr[8])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_1000_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[8]) + ((uint64_t)context->gpr[3]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[3] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_1000_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[8] + context->gpr[3];
	context->t = (((context->gpr[8] ^ (~context->gpr[3]))) & (context->gpr[8] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[3] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_1001_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[3] - context->gpr[9];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_1001_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[3] >= context->gpr[9]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_1001_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[3]) >= ((int32_t)context->gpr[9])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_1001_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[3]) << 1 | ((uint64_t)context->gpr[3]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[3] >> 24 & 128U;
	context->gpr[3] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[3]) - ((uint64_t)context->gpr[9]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[3] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[9]) + ((uint64_t)context->gpr[3]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[3] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_1001_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[3] & 4294967295)) * ((uint64_t)(context->gpr[9] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_1001_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[9]) - ((uint64_t)context->gpr[3]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_1001_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[3]) >= ((int32_t)context->gpr[9])) {
	if (context->gpr[3] == context->gpr[9]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_1001_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[3] = context->gpr[3] - context->gpr[9];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_1001_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[3]) - ((uint64_t)context->gpr[9]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[3] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_1001_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[3] - context->gpr[9];
	context->t = (((context->gpr[3] ^ context->gpr[9])) & (context->gpr[3] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[3] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_1001_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[3] = context->gpr[9] + context->gpr[3];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_1001_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[3])) * ((int64_t)((int32_t)context->gpr[9])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_1001_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[9]) + ((uint64_t)context->gpr[3]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[3] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_1001_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[9] + context->gpr[3];
	context->t = (((context->gpr[9] ^ (~context->gpr[3]))) & (context->gpr[9] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[3] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_1010_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[3] - context->gpr[10];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_1010_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[3] >= context->gpr[10]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_1010_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[3]) >= ((int32_t)context->gpr[10])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_1010_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[3]) << 1 | ((uint64_t)context->gpr[3]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[3] >> 24 & 128U;
	context->gpr[3] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[3]) - ((uint64_t)context->gpr[10]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[3] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[10]) + ((uint64_t)context->gpr[3]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[3] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_1010_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[3] & 4294967295)) * ((uint64_t)(context->gpr[10] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_1010_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[10]) - ((uint64_t)context->gpr[3]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_1010_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[3]) >= ((int32_t)context->gpr[10])) {
	if (context->gpr[3] == context->gpr[10]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_1010_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[3] = context->gpr[3] - context->gpr[10];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_1010_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[3]) - ((uint64_t)context->gpr[10]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[3] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_1010_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[3] - context->gpr[10];
	context->t = (((context->gpr[3] ^ context->gpr[10])) & (context->gpr[3] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[3] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_1010_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[3] = context->gpr[10] + context->gpr[3];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_1010_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[3])) * ((int64_t)((int32_t)context->gpr[10])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_1010_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[10]) + ((uint64_t)context->gpr[3]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[3] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_1010_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[10] + context->gpr[3];
	context->t = (((context->gpr[10] ^ (~context->gpr[3]))) & (context->gpr[10] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[3] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_1011_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[3] - context->gpr[11];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_1011_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[3] >= context->gpr[11]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_1011_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[3]) >= ((int32_t)context->gpr[11])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_1011_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[3]) << 1 | ((uint64_t)context->gpr[3]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[3] >> 24 & 128U;
	context->gpr[3] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[3]) - ((uint64_t)context->gpr[11]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[3] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[11]) + ((uint64_t)context->gpr[3]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[3] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_1011_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[3] & 4294967295)) * ((uint64_t)(context->gpr[11] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_1011_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[11]) - ((uint64_t)context->gpr[3]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_1011_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[3]) >= ((int32_t)context->gpr[11])) {
	if (context->gpr[3] == context->gpr[11]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_1011_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[3] = context->gpr[3] - context->gpr[11];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_1011_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[3]) - ((uint64_t)context->gpr[11]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[3] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_1011_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[3] - context->gpr[11];
	context->t = (((context->gpr[3] ^ context->gpr[11])) & (context->gpr[3] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[3] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_1011_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[3] = context->gpr[11] + context->gpr[3];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_1011_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[3])) * ((int64_t)((int32_t)context->gpr[11])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_1011_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[11]) + ((uint64_t)context->gpr[3]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[3] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_1011_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[11] + context->gpr[3];
	context->t = (((context->gpr[11] ^ (~context->gpr[3]))) & (context->gpr[11] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[3] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_1100_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[3] - context->gpr[12];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_1100_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[3] >= context->gpr[12]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_1100_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[3]) >= ((int32_t)context->gpr[12])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_1100_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[3]) << 1 | ((uint64_t)context->gpr[3]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[3] >> 24 & 128U;
	context->gpr[3] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[3]) - ((uint64_t)context->gpr[12]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[3] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[12]) + ((uint64_t)context->gpr[3]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[3] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_1100_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[3] & 4294967295)) * ((uint64_t)(context->gpr[12] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_1100_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[12]) - ((uint64_t)context->gpr[3]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_1100_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[3]) >= ((int32_t)context->gpr[12])) {
	if (context->gpr[3] == context->gpr[12]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_1100_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[3] = context->gpr[3] - context->gpr[12];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_1100_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[3]) - ((uint64_t)context->gpr[12]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[3] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_1100_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[3] - context->gpr[12];
	context->t = (((context->gpr[3] ^ context->gpr[12])) & (context->gpr[3] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[3] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_1100_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[3] = context->gpr[12] + context->gpr[3];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_1100_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[3])) * ((int64_t)((int32_t)context->gpr[12])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_1100_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[12]) + ((uint64_t)context->gpr[3]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[3] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_1100_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[12] + context->gpr[3];
	context->t = (((context->gpr[12] ^ (~context->gpr[3]))) & (context->gpr[12] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[3] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_1101_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[3] - context->gpr[13];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_1101_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[3] >= context->gpr[13]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_1101_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[3]) >= ((int32_t)context->gpr[13])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_1101_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[3]) << 1 | ((uint64_t)context->gpr[3]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[3] >> 24 & 128U;
	context->gpr[3] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[3]) - ((uint64_t)context->gpr[13]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[3] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[13]) + ((uint64_t)context->gpr[3]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[3] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_1101_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[3] & 4294967295)) * ((uint64_t)(context->gpr[13] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_1101_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[13]) - ((uint64_t)context->gpr[3]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_1101_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[3]) >= ((int32_t)context->gpr[13])) {
	if (context->gpr[3] == context->gpr[13]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_1101_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[3] = context->gpr[3] - context->gpr[13];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_1101_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[3]) - ((uint64_t)context->gpr[13]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[3] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_1101_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[3] - context->gpr[13];
	context->t = (((context->gpr[3] ^ context->gpr[13])) & (context->gpr[3] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[3] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_1101_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[3] = context->gpr[13] + context->gpr[3];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_1101_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[3])) * ((int64_t)((int32_t)context->gpr[13])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_1101_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[13]) + ((uint64_t)context->gpr[3]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[3] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_1101_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[13] + context->gpr[3];
	context->t = (((context->gpr[13] ^ (~context->gpr[3]))) & (context->gpr[13] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[3] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_1110_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[3] - context->gpr[14];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_1110_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[3] >= context->gpr[14]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_1110_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[3]) >= ((int32_t)context->gpr[14])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_1110_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[3]) << 1 | ((uint64_t)context->gpr[3]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[3] >> 24 & 128U;
	context->gpr[3] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[3]) - ((uint64_t)context->gpr[14]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[3] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[14]) + ((uint64_t)context->gpr[3]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[3] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_1110_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[3] & 4294967295)) * ((uint64_t)(context->gpr[14] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_1110_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[14]) - ((uint64_t)context->gpr[3]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_1110_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[3]) >= ((int32_t)context->gpr[14])) {
	if (context->gpr[3] == context->gpr[14]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_1110_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[3] = context->gpr[3] - context->gpr[14];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_1110_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[3]) - ((uint64_t)context->gpr[14]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[3] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_1110_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[3] - context->gpr[14];
	context->t = (((context->gpr[3] ^ context->gpr[14])) & (context->gpr[3] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[3] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_1110_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[3] = context->gpr[14] + context->gpr[3];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_1110_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[3])) * ((int64_t)((int32_t)context->gpr[14])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_1110_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[14]) + ((uint64_t)context->gpr[3]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[3] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_1110_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[14] + context->gpr[3];
	context->t = (((context->gpr[14] ^ (~context->gpr[3]))) & (context->gpr[14] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[3] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_1111_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[3] - context->gpr[15];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_1111_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[3] >= context->gpr[15]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_1111_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[3]) >= ((int32_t)context->gpr[15])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_1111_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[3]) << 1 | ((uint64_t)context->gpr[3]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[3] >> 24 & 128U;
	context->gpr[3] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[3]) - ((uint64_t)context->gpr[15]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[3] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[15]) + ((uint64_t)context->gpr[3]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[3] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_1111_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[3] & 4294967295)) * ((uint64_t)(context->gpr[15] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_1111_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[15]) - ((uint64_t)context->gpr[3]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_1111_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[3]) >= ((int32_t)context->gpr[15])) {
	if (context->gpr[3] == context->gpr[15]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_1111_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[3] = context->gpr[3] - context->gpr[15];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_1111_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[3]) - ((uint64_t)context->gpr[15]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[3] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_1111_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[3] - context->gpr[15];
	context->t = (((context->gpr[3] ^ context->gpr[15])) & (context->gpr[3] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[3] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_1111_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[3] = context->gpr[15] + context->gpr[3];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_1111_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[3])) * ((int64_t)((int32_t)context->gpr[15])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_1111_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[15]) + ((uint64_t)context->gpr[3]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[3] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_1111_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[15] + context->gpr[3];
	context->t = (((context->gpr[15] ^ (~context->gpr[3]))) & (context->gpr[15] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[3] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_0000_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[4] - context->gpr[0];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_0000_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[4] >= context->gpr[0]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_0000_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[4]) >= ((int32_t)context->gpr[0])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_0000_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[4]) << 1 | ((uint64_t)context->gpr[4]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[4] >> 24 & 128U;
	context->gpr[4] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[4]) - ((uint64_t)context->gpr[0]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[4] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[0]) + ((uint64_t)context->gpr[4]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[4] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_0000_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[4] & 4294967295)) * ((uint64_t)(context->gpr[0] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_0000_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[0]) - ((uint64_t)context->gpr[4]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_0000_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[4]) >= ((int32_t)context->gpr[0])) {
	if (context->gpr[4] == context->gpr[0]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_0000_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[4] = context->gpr[4] - context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_0000_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[4]) - ((uint64_t)context->gpr[0]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[4] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_0000_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[4] - context->gpr[0];
	context->t = (((context->gpr[4] ^ context->gpr[0])) & (context->gpr[4] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[4] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_0000_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[4] = context->gpr[0] + context->gpr[4];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_0000_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[4])) * ((int64_t)((int32_t)context->gpr[0])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_0000_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[0]) + ((uint64_t)context->gpr[4]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[4] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_0000_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[0] + context->gpr[4];
	context->t = (((context->gpr[0] ^ (~context->gpr[4]))) & (context->gpr[0] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[4] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_0001_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[4] - context->gpr[1];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_0001_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[4] >= context->gpr[1]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_0001_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[4]) >= ((int32_t)context->gpr[1])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_0001_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[4]) << 1 | ((uint64_t)context->gpr[4]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[4] >> 24 & 128U;
	context->gpr[4] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[4]) - ((uint64_t)context->gpr[1]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[4] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[1]) + ((uint64_t)context->gpr[4]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[4] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_0001_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[4] & 4294967295)) * ((uint64_t)(context->gpr[1] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_0001_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[1]) - ((uint64_t)context->gpr[4]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_0001_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[4]) >= ((int32_t)context->gpr[1])) {
	if (context->gpr[4] == context->gpr[1]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_0001_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[4] = context->gpr[4] - context->gpr[1];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_0001_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[4]) - ((uint64_t)context->gpr[1]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[4] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_0001_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[4] - context->gpr[1];
	context->t = (((context->gpr[4] ^ context->gpr[1])) & (context->gpr[4] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[4] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_0001_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[4] = context->gpr[1] + context->gpr[4];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_0001_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[4])) * ((int64_t)((int32_t)context->gpr[1])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_0001_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[1]) + ((uint64_t)context->gpr[4]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[4] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_0001_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[1] + context->gpr[4];
	context->t = (((context->gpr[1] ^ (~context->gpr[4]))) & (context->gpr[1] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[4] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_0010_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[4] - context->gpr[2];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_0010_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[4] >= context->gpr[2]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_0010_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[4]) >= ((int32_t)context->gpr[2])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_0010_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[4]) << 1 | ((uint64_t)context->gpr[4]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[4] >> 24 & 128U;
	context->gpr[4] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[4]) - ((uint64_t)context->gpr[2]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[4] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[2]) + ((uint64_t)context->gpr[4]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[4] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_0010_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[4] & 4294967295)) * ((uint64_t)(context->gpr[2] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_0010_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[2]) - ((uint64_t)context->gpr[4]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_0010_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[4]) >= ((int32_t)context->gpr[2])) {
	if (context->gpr[4] == context->gpr[2]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_0010_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[4] = context->gpr[4] - context->gpr[2];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_0010_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[4]) - ((uint64_t)context->gpr[2]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[4] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_0010_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[4] - context->gpr[2];
	context->t = (((context->gpr[4] ^ context->gpr[2])) & (context->gpr[4] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[4] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_0010_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[4] = context->gpr[2] + context->gpr[4];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_0010_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[4])) * ((int64_t)((int32_t)context->gpr[2])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_0010_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[2]) + ((uint64_t)context->gpr[4]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[4] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_0010_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[2] + context->gpr[4];
	context->t = (((context->gpr[2] ^ (~context->gpr[4]))) & (context->gpr[2] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[4] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_0011_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[4] - context->gpr[3];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_0011_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[4] >= context->gpr[3]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_0011_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[4]) >= ((int32_t)context->gpr[3])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_0011_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[4]) << 1 | ((uint64_t)context->gpr[4]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[4] >> 24 & 128U;
	context->gpr[4] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[4]) - ((uint64_t)context->gpr[3]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[4] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[3]) + ((uint64_t)context->gpr[4]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[4] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_0011_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[4] & 4294967295)) * ((uint64_t)(context->gpr[3] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_0011_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[3]) - ((uint64_t)context->gpr[4]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_0011_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[4]) >= ((int32_t)context->gpr[3])) {
	if (context->gpr[4] == context->gpr[3]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_0011_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[4] = context->gpr[4] - context->gpr[3];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_0011_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[4]) - ((uint64_t)context->gpr[3]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[4] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_0011_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[4] - context->gpr[3];
	context->t = (((context->gpr[4] ^ context->gpr[3])) & (context->gpr[4] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[4] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_0011_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[4] = context->gpr[3] + context->gpr[4];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_0011_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[4])) * ((int64_t)((int32_t)context->gpr[3])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_0011_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[3]) + ((uint64_t)context->gpr[4]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[4] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_0011_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[3] + context->gpr[4];
	context->t = (((context->gpr[3] ^ (~context->gpr[4]))) & (context->gpr[3] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[4] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_0100_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[4] - context->gpr[4];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_0100_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[4] >= context->gpr[4]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_0100_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[4]) >= ((int32_t)context->gpr[4])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_0100_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[4]) << 1 | ((uint64_t)context->gpr[4]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[4] >> 24 & 128U;
	context->gpr[4] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[4]) - ((uint64_t)context->gpr[4]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[4] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[4]) + ((uint64_t)context->gpr[4]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[4] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_0100_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[4] & 4294967295)) * ((uint64_t)(context->gpr[4] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_0100_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[4]) - ((uint64_t)context->gpr[4]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_0100_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[4]) >= ((int32_t)context->gpr[4])) {
	if (context->gpr[4] == context->gpr[4]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_0100_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[4] = context->gpr[4] - context->gpr[4];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_0100_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[4]) - ((uint64_t)context->gpr[4]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[4] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_0100_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[4] - context->gpr[4];
	context->t = (((context->gpr[4] ^ context->gpr[4])) & (context->gpr[4] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[4] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_0100_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[4] = context->gpr[4] + context->gpr[4];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_0100_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[4])) * ((int64_t)((int32_t)context->gpr[4])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_0100_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[4]) + ((uint64_t)context->gpr[4]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[4] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_0100_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[4] + context->gpr[4];
	context->t = (((context->gpr[4] ^ (~context->gpr[4]))) & (context->gpr[4] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[4] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_0101_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[4] - context->gpr[5];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_0101_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[4] >= context->gpr[5]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_0101_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[4]) >= ((int32_t)context->gpr[5])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_0101_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[4]) << 1 | ((uint64_t)context->gpr[4]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[4] >> 24 & 128U;
	context->gpr[4] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[4]) - ((uint64_t)context->gpr[5]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[4] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[5]) + ((uint64_t)context->gpr[4]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[4] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_0101_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[4] & 4294967295)) * ((uint64_t)(context->gpr[5] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_0101_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[5]) - ((uint64_t)context->gpr[4]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_0101_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[4]) >= ((int32_t)context->gpr[5])) {
	if (context->gpr[4] == context->gpr[5]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_0101_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[4] = context->gpr[4] - context->gpr[5];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_0101_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[4]) - ((uint64_t)context->gpr[5]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[4] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_0101_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[4] - context->gpr[5];
	context->t = (((context->gpr[4] ^ context->gpr[5])) & (context->gpr[4] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[4] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_0101_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[4] = context->gpr[5] + context->gpr[4];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_0101_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[4])) * ((int64_t)((int32_t)context->gpr[5])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_0101_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[5]) + ((uint64_t)context->gpr[4]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[4] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_0101_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[5] + context->gpr[4];
	context->t = (((context->gpr[5] ^ (~context->gpr[4]))) & (context->gpr[5] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[4] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_0110_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[4] - context->gpr[6];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_0110_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[4] >= context->gpr[6]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_0110_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[4]) >= ((int32_t)context->gpr[6])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_0110_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[4]) << 1 | ((uint64_t)context->gpr[4]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[4] >> 24 & 128U;
	context->gpr[4] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[4]) - ((uint64_t)context->gpr[6]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[4] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[6]) + ((uint64_t)context->gpr[4]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[4] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_0110_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[4] & 4294967295)) * ((uint64_t)(context->gpr[6] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_0110_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[6]) - ((uint64_t)context->gpr[4]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_0110_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[4]) >= ((int32_t)context->gpr[6])) {
	if (context->gpr[4] == context->gpr[6]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_0110_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[4] = context->gpr[4] - context->gpr[6];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_0110_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[4]) - ((uint64_t)context->gpr[6]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[4] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_0110_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[4] - context->gpr[6];
	context->t = (((context->gpr[4] ^ context->gpr[6])) & (context->gpr[4] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[4] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_0110_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[4] = context->gpr[6] + context->gpr[4];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_0110_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[4])) * ((int64_t)((int32_t)context->gpr[6])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_0110_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[6]) + ((uint64_t)context->gpr[4]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[4] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_0110_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[6] + context->gpr[4];
	context->t = (((context->gpr[6] ^ (~context->gpr[4]))) & (context->gpr[6] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[4] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_0111_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[4] - context->gpr[7];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_0111_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[4] >= context->gpr[7]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_0111_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[4]) >= ((int32_t)context->gpr[7])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_0111_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[4]) << 1 | ((uint64_t)context->gpr[4]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[4] >> 24 & 128U;
	context->gpr[4] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[4]) - ((uint64_t)context->gpr[7]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[4] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[7]) + ((uint64_t)context->gpr[4]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[4] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_0111_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[4] & 4294967295)) * ((uint64_t)(context->gpr[7] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_0111_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[7]) - ((uint64_t)context->gpr[4]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_0111_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[4]) >= ((int32_t)context->gpr[7])) {
	if (context->gpr[4] == context->gpr[7]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_0111_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[4] = context->gpr[4] - context->gpr[7];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_0111_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[4]) - ((uint64_t)context->gpr[7]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[4] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_0111_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[4] - context->gpr[7];
	context->t = (((context->gpr[4] ^ context->gpr[7])) & (context->gpr[4] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[4] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_0111_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[4] = context->gpr[7] + context->gpr[4];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_0111_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[4])) * ((int64_t)((int32_t)context->gpr[7])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_0111_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[7]) + ((uint64_t)context->gpr[4]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[4] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_0111_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[7] + context->gpr[4];
	context->t = (((context->gpr[7] ^ (~context->gpr[4]))) & (context->gpr[7] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[4] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_1000_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[4] - context->gpr[8];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_1000_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[4] >= context->gpr[8]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_1000_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[4]) >= ((int32_t)context->gpr[8])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_1000_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[4]) << 1 | ((uint64_t)context->gpr[4]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[4] >> 24 & 128U;
	context->gpr[4] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[4]) - ((uint64_t)context->gpr[8]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[4] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[8]) + ((uint64_t)context->gpr[4]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[4] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_1000_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[4] & 4294967295)) * ((uint64_t)(context->gpr[8] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_1000_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[8]) - ((uint64_t)context->gpr[4]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_1000_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[4]) >= ((int32_t)context->gpr[8])) {
	if (context->gpr[4] == context->gpr[8]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_1000_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[4] = context->gpr[4] - context->gpr[8];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_1000_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[4]) - ((uint64_t)context->gpr[8]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[4] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_1000_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[4] - context->gpr[8];
	context->t = (((context->gpr[4] ^ context->gpr[8])) & (context->gpr[4] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[4] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_1000_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[4] = context->gpr[8] + context->gpr[4];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_1000_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[4])) * ((int64_t)((int32_t)context->gpr[8])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_1000_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[8]) + ((uint64_t)context->gpr[4]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[4] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_1000_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[8] + context->gpr[4];
	context->t = (((context->gpr[8] ^ (~context->gpr[4]))) & (context->gpr[8] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[4] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_1001_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[4] - context->gpr[9];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_1001_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[4] >= context->gpr[9]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_1001_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[4]) >= ((int32_t)context->gpr[9])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_1001_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[4]) << 1 | ((uint64_t)context->gpr[4]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[4] >> 24 & 128U;
	context->gpr[4] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[4]) - ((uint64_t)context->gpr[9]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[4] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[9]) + ((uint64_t)context->gpr[4]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[4] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_1001_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[4] & 4294967295)) * ((uint64_t)(context->gpr[9] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_1001_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[9]) - ((uint64_t)context->gpr[4]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_1001_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[4]) >= ((int32_t)context->gpr[9])) {
	if (context->gpr[4] == context->gpr[9]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_1001_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[4] = context->gpr[4] - context->gpr[9];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_1001_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[4]) - ((uint64_t)context->gpr[9]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[4] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_1001_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[4] - context->gpr[9];
	context->t = (((context->gpr[4] ^ context->gpr[9])) & (context->gpr[4] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[4] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_1001_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[4] = context->gpr[9] + context->gpr[4];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_1001_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[4])) * ((int64_t)((int32_t)context->gpr[9])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_1001_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[9]) + ((uint64_t)context->gpr[4]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[4] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_1001_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[9] + context->gpr[4];
	context->t = (((context->gpr[9] ^ (~context->gpr[4]))) & (context->gpr[9] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[4] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_1010_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[4] - context->gpr[10];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_1010_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[4] >= context->gpr[10]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_1010_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[4]) >= ((int32_t)context->gpr[10])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_1010_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[4]) << 1 | ((uint64_t)context->gpr[4]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[4] >> 24 & 128U;
	context->gpr[4] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[4]) - ((uint64_t)context->gpr[10]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[4] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[10]) + ((uint64_t)context->gpr[4]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[4] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_1010_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[4] & 4294967295)) * ((uint64_t)(context->gpr[10] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_1010_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[10]) - ((uint64_t)context->gpr[4]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_1010_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[4]) >= ((int32_t)context->gpr[10])) {
	if (context->gpr[4] == context->gpr[10]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_1010_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[4] = context->gpr[4] - context->gpr[10];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_1010_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[4]) - ((uint64_t)context->gpr[10]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[4] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_1010_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[4] - context->gpr[10];
	context->t = (((context->gpr[4] ^ context->gpr[10])) & (context->gpr[4] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[4] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_1010_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[4] = context->gpr[10] + context->gpr[4];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_1010_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[4])) * ((int64_t)((int32_t)context->gpr[10])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_1010_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[10]) + ((uint64_t)context->gpr[4]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[4] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_1010_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[10] + context->gpr[4];
	context->t = (((context->gpr[10] ^ (~context->gpr[4]))) & (context->gpr[10] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[4] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_1011_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[4] - context->gpr[11];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_1011_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[4] >= context->gpr[11]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_1011_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[4]) >= ((int32_t)context->gpr[11])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_1011_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[4]) << 1 | ((uint64_t)context->gpr[4]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[4] >> 24 & 128U;
	context->gpr[4] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[4]) - ((uint64_t)context->gpr[11]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[4] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[11]) + ((uint64_t)context->gpr[4]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[4] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_1011_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[4] & 4294967295)) * ((uint64_t)(context->gpr[11] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_1011_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[11]) - ((uint64_t)context->gpr[4]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_1011_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[4]) >= ((int32_t)context->gpr[11])) {
	if (context->gpr[4] == context->gpr[11]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_1011_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[4] = context->gpr[4] - context->gpr[11];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_1011_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[4]) - ((uint64_t)context->gpr[11]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[4] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_1011_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[4] - context->gpr[11];
	context->t = (((context->gpr[4] ^ context->gpr[11])) & (context->gpr[4] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[4] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_1011_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[4] = context->gpr[11] + context->gpr[4];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_1011_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[4])) * ((int64_t)((int32_t)context->gpr[11])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_1011_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[11]) + ((uint64_t)context->gpr[4]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[4] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_1011_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[11] + context->gpr[4];
	context->t = (((context->gpr[11] ^ (~context->gpr[4]))) & (context->gpr[11] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[4] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_1100_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[4] - context->gpr[12];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_1100_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[4] >= context->gpr[12]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_1100_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[4]) >= ((int32_t)context->gpr[12])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_1100_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[4]) << 1 | ((uint64_t)context->gpr[4]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[4] >> 24 & 128U;
	context->gpr[4] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[4]) - ((uint64_t)context->gpr[12]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[4] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[12]) + ((uint64_t)context->gpr[4]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[4] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_1100_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[4] & 4294967295)) * ((uint64_t)(context->gpr[12] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_1100_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[12]) - ((uint64_t)context->gpr[4]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_1100_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[4]) >= ((int32_t)context->gpr[12])) {
	if (context->gpr[4] == context->gpr[12]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_1100_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[4] = context->gpr[4] - context->gpr[12];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_1100_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[4]) - ((uint64_t)context->gpr[12]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[4] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_1100_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[4] - context->gpr[12];
	context->t = (((context->gpr[4] ^ context->gpr[12])) & (context->gpr[4] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[4] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_1100_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[4] = context->gpr[12] + context->gpr[4];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_1100_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[4])) * ((int64_t)((int32_t)context->gpr[12])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_1100_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[12]) + ((uint64_t)context->gpr[4]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[4] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_1100_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[12] + context->gpr[4];
	context->t = (((context->gpr[12] ^ (~context->gpr[4]))) & (context->gpr[12] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[4] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_1101_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[4] - context->gpr[13];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_1101_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[4] >= context->gpr[13]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_1101_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[4]) >= ((int32_t)context->gpr[13])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_1101_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[4]) << 1 | ((uint64_t)context->gpr[4]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[4] >> 24 & 128U;
	context->gpr[4] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[4]) - ((uint64_t)context->gpr[13]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[4] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[13]) + ((uint64_t)context->gpr[4]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[4] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_1101_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[4] & 4294967295)) * ((uint64_t)(context->gpr[13] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_1101_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[13]) - ((uint64_t)context->gpr[4]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_1101_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[4]) >= ((int32_t)context->gpr[13])) {
	if (context->gpr[4] == context->gpr[13]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_1101_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[4] = context->gpr[4] - context->gpr[13];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_1101_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[4]) - ((uint64_t)context->gpr[13]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[4] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_1101_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[4] - context->gpr[13];
	context->t = (((context->gpr[4] ^ context->gpr[13])) & (context->gpr[4] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[4] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_1101_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[4] = context->gpr[13] + context->gpr[4];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_1101_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[4])) * ((int64_t)((int32_t)context->gpr[13])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_1101_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[13]) + ((uint64_t)context->gpr[4]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[4] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_1101_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[13] + context->gpr[4];
	context->t = (((context->gpr[13] ^ (~context->gpr[4]))) & (context->gpr[13] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[4] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_1110_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[4] - context->gpr[14];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_1110_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[4] >= context->gpr[14]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_1110_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[4]) >= ((int32_t)context->gpr[14])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_1110_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[4]) << 1 | ((uint64_t)context->gpr[4]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[4] >> 24 & 128U;
	context->gpr[4] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[4]) - ((uint64_t)context->gpr[14]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[4] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[14]) + ((uint64_t)context->gpr[4]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[4] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_1110_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[4] & 4294967295)) * ((uint64_t)(context->gpr[14] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_1110_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[14]) - ((uint64_t)context->gpr[4]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_1110_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[4]) >= ((int32_t)context->gpr[14])) {
	if (context->gpr[4] == context->gpr[14]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_1110_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[4] = context->gpr[4] - context->gpr[14];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_1110_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[4]) - ((uint64_t)context->gpr[14]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[4] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_1110_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[4] - context->gpr[14];
	context->t = (((context->gpr[4] ^ context->gpr[14])) & (context->gpr[4] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[4] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_1110_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[4] = context->gpr[14] + context->gpr[4];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_1110_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[4])) * ((int64_t)((int32_t)context->gpr[14])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_1110_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[14]) + ((uint64_t)context->gpr[4]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[4] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_1110_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[14] + context->gpr[4];
	context->t = (((context->gpr[14] ^ (~context->gpr[4]))) & (context->gpr[14] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[4] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_1111_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[4] - context->gpr[15];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_1111_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[4] >= context->gpr[15]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_1111_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[4]) >= ((int32_t)context->gpr[15])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_1111_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[4]) << 1 | ((uint64_t)context->gpr[4]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[4] >> 24 & 128U;
	context->gpr[4] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[4]) - ((uint64_t)context->gpr[15]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[4] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[15]) + ((uint64_t)context->gpr[4]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[4] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_1111_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[4] & 4294967295)) * ((uint64_t)(context->gpr[15] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_1111_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[15]) - ((uint64_t)context->gpr[4]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_1111_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[4]) >= ((int32_t)context->gpr[15])) {
	if (context->gpr[4] == context->gpr[15]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_1111_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[4] = context->gpr[4] - context->gpr[15];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_1111_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[4]) - ((uint64_t)context->gpr[15]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[4] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_1111_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[4] - context->gpr[15];
	context->t = (((context->gpr[4] ^ context->gpr[15])) & (context->gpr[4] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[4] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_1111_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[4] = context->gpr[15] + context->gpr[4];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_1111_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[4])) * ((int64_t)((int32_t)context->gpr[15])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_1111_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[15]) + ((uint64_t)context->gpr[4]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[4] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_1111_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[15] + context->gpr[4];
	context->t = (((context->gpr[15] ^ (~context->gpr[4]))) & (context->gpr[15] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[4] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_0000_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[5] - context->gpr[0];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_0000_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[5] >= context->gpr[0]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_0000_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[5]) >= ((int32_t)context->gpr[0])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_0000_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[5]) << 1 | ((uint64_t)context->gpr[5]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[5] >> 24 & 128U;
	context->gpr[5] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[5]) - ((uint64_t)context->gpr[0]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[5] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[0]) + ((uint64_t)context->gpr[5]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[5] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_0000_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[5] & 4294967295)) * ((uint64_t)(context->gpr[0] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_0000_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[0]) - ((uint64_t)context->gpr[5]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_0000_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[5]) >= ((int32_t)context->gpr[0])) {
	if (context->gpr[5] == context->gpr[0]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_0000_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[5] = context->gpr[5] - context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_0000_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[5]) - ((uint64_t)context->gpr[0]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[5] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_0000_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[5] - context->gpr[0];
	context->t = (((context->gpr[5] ^ context->gpr[0])) & (context->gpr[5] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[5] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_0000_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[5] = context->gpr[0] + context->gpr[5];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_0000_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[5])) * ((int64_t)((int32_t)context->gpr[0])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_0000_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[0]) + ((uint64_t)context->gpr[5]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[5] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_0000_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[0] + context->gpr[5];
	context->t = (((context->gpr[0] ^ (~context->gpr[5]))) & (context->gpr[0] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[5] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_0001_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[5] - context->gpr[1];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_0001_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[5] >= context->gpr[1]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_0001_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[5]) >= ((int32_t)context->gpr[1])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_0001_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[5]) << 1 | ((uint64_t)context->gpr[5]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[5] >> 24 & 128U;
	context->gpr[5] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[5]) - ((uint64_t)context->gpr[1]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[5] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[1]) + ((uint64_t)context->gpr[5]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[5] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_0001_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[5] & 4294967295)) * ((uint64_t)(context->gpr[1] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_0001_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[1]) - ((uint64_t)context->gpr[5]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_0001_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[5]) >= ((int32_t)context->gpr[1])) {
	if (context->gpr[5] == context->gpr[1]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_0001_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[5] = context->gpr[5] - context->gpr[1];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_0001_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[5]) - ((uint64_t)context->gpr[1]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[5] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_0001_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[5] - context->gpr[1];
	context->t = (((context->gpr[5] ^ context->gpr[1])) & (context->gpr[5] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[5] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_0001_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[5] = context->gpr[1] + context->gpr[5];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_0001_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[5])) * ((int64_t)((int32_t)context->gpr[1])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_0001_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[1]) + ((uint64_t)context->gpr[5]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[5] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_0001_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[1] + context->gpr[5];
	context->t = (((context->gpr[1] ^ (~context->gpr[5]))) & (context->gpr[1] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[5] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_0010_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[5] - context->gpr[2];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_0010_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[5] >= context->gpr[2]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_0010_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[5]) >= ((int32_t)context->gpr[2])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_0010_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[5]) << 1 | ((uint64_t)context->gpr[5]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[5] >> 24 & 128U;
	context->gpr[5] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[5]) - ((uint64_t)context->gpr[2]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[5] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[2]) + ((uint64_t)context->gpr[5]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[5] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_0010_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[5] & 4294967295)) * ((uint64_t)(context->gpr[2] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_0010_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[2]) - ((uint64_t)context->gpr[5]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_0010_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[5]) >= ((int32_t)context->gpr[2])) {
	if (context->gpr[5] == context->gpr[2]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_0010_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[5] = context->gpr[5] - context->gpr[2];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_0010_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[5]) - ((uint64_t)context->gpr[2]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[5] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_0010_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[5] - context->gpr[2];
	context->t = (((context->gpr[5] ^ context->gpr[2])) & (context->gpr[5] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[5] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_0010_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[5] = context->gpr[2] + context->gpr[5];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_0010_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[5])) * ((int64_t)((int32_t)context->gpr[2])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_0010_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[2]) + ((uint64_t)context->gpr[5]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[5] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_0010_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[2] + context->gpr[5];
	context->t = (((context->gpr[2] ^ (~context->gpr[5]))) & (context->gpr[2] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[5] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_0011_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[5] - context->gpr[3];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_0011_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[5] >= context->gpr[3]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_0011_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[5]) >= ((int32_t)context->gpr[3])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_0011_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[5]) << 1 | ((uint64_t)context->gpr[5]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[5] >> 24 & 128U;
	context->gpr[5] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[5]) - ((uint64_t)context->gpr[3]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[5] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[3]) + ((uint64_t)context->gpr[5]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[5] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_0011_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[5] & 4294967295)) * ((uint64_t)(context->gpr[3] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_0011_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[3]) - ((uint64_t)context->gpr[5]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_0011_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[5]) >= ((int32_t)context->gpr[3])) {
	if (context->gpr[5] == context->gpr[3]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_0011_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[5] = context->gpr[5] - context->gpr[3];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_0011_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[5]) - ((uint64_t)context->gpr[3]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[5] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_0011_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[5] - context->gpr[3];
	context->t = (((context->gpr[5] ^ context->gpr[3])) & (context->gpr[5] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[5] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_0011_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[5] = context->gpr[3] + context->gpr[5];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_0011_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[5])) * ((int64_t)((int32_t)context->gpr[3])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_0011_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[3]) + ((uint64_t)context->gpr[5]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[5] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_0011_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[3] + context->gpr[5];
	context->t = (((context->gpr[3] ^ (~context->gpr[5]))) & (context->gpr[3] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[5] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_0100_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[5] - context->gpr[4];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_0100_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[5] >= context->gpr[4]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_0100_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[5]) >= ((int32_t)context->gpr[4])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_0100_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[5]) << 1 | ((uint64_t)context->gpr[5]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[5] >> 24 & 128U;
	context->gpr[5] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[5]) - ((uint64_t)context->gpr[4]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[5] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[4]) + ((uint64_t)context->gpr[5]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[5] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_0100_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[5] & 4294967295)) * ((uint64_t)(context->gpr[4] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_0100_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[4]) - ((uint64_t)context->gpr[5]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_0100_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[5]) >= ((int32_t)context->gpr[4])) {
	if (context->gpr[5] == context->gpr[4]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_0100_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[5] = context->gpr[5] - context->gpr[4];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_0100_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[5]) - ((uint64_t)context->gpr[4]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[5] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_0100_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[5] - context->gpr[4];
	context->t = (((context->gpr[5] ^ context->gpr[4])) & (context->gpr[5] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[5] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_0100_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[5] = context->gpr[4] + context->gpr[5];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_0100_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[5])) * ((int64_t)((int32_t)context->gpr[4])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_0100_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[4]) + ((uint64_t)context->gpr[5]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[5] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_0100_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[4] + context->gpr[5];
	context->t = (((context->gpr[4] ^ (~context->gpr[5]))) & (context->gpr[4] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[5] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_0101_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[5] - context->gpr[5];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_0101_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[5] >= context->gpr[5]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_0101_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[5]) >= ((int32_t)context->gpr[5])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_0101_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[5]) << 1 | ((uint64_t)context->gpr[5]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[5] >> 24 & 128U;
	context->gpr[5] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[5]) - ((uint64_t)context->gpr[5]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[5] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[5]) + ((uint64_t)context->gpr[5]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[5] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_0101_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[5] & 4294967295)) * ((uint64_t)(context->gpr[5] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_0101_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[5]) - ((uint64_t)context->gpr[5]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_0101_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[5]) >= ((int32_t)context->gpr[5])) {
	if (context->gpr[5] == context->gpr[5]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_0101_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[5] = context->gpr[5] - context->gpr[5];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_0101_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[5]) - ((uint64_t)context->gpr[5]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[5] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_0101_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[5] - context->gpr[5];
	context->t = (((context->gpr[5] ^ context->gpr[5])) & (context->gpr[5] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[5] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_0101_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[5] = context->gpr[5] + context->gpr[5];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_0101_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[5])) * ((int64_t)((int32_t)context->gpr[5])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_0101_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[5]) + ((uint64_t)context->gpr[5]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[5] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_0101_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[5] + context->gpr[5];
	context->t = (((context->gpr[5] ^ (~context->gpr[5]))) & (context->gpr[5] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[5] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_0110_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[5] - context->gpr[6];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_0110_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[5] >= context->gpr[6]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_0110_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[5]) >= ((int32_t)context->gpr[6])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_0110_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[5]) << 1 | ((uint64_t)context->gpr[5]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[5] >> 24 & 128U;
	context->gpr[5] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[5]) - ((uint64_t)context->gpr[6]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[5] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[6]) + ((uint64_t)context->gpr[5]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[5] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_0110_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[5] & 4294967295)) * ((uint64_t)(context->gpr[6] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_0110_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[6]) - ((uint64_t)context->gpr[5]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_0110_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[5]) >= ((int32_t)context->gpr[6])) {
	if (context->gpr[5] == context->gpr[6]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_0110_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[5] = context->gpr[5] - context->gpr[6];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_0110_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[5]) - ((uint64_t)context->gpr[6]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[5] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_0110_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[5] - context->gpr[6];
	context->t = (((context->gpr[5] ^ context->gpr[6])) & (context->gpr[5] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[5] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_0110_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[5] = context->gpr[6] + context->gpr[5];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_0110_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[5])) * ((int64_t)((int32_t)context->gpr[6])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_0110_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[6]) + ((uint64_t)context->gpr[5]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[5] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_0110_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[6] + context->gpr[5];
	context->t = (((context->gpr[6] ^ (~context->gpr[5]))) & (context->gpr[6] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[5] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_0111_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[5] - context->gpr[7];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_0111_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[5] >= context->gpr[7]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_0111_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[5]) >= ((int32_t)context->gpr[7])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_0111_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[5]) << 1 | ((uint64_t)context->gpr[5]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[5] >> 24 & 128U;
	context->gpr[5] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[5]) - ((uint64_t)context->gpr[7]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[5] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[7]) + ((uint64_t)context->gpr[5]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[5] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_0111_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[5] & 4294967295)) * ((uint64_t)(context->gpr[7] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_0111_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[7]) - ((uint64_t)context->gpr[5]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_0111_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[5]) >= ((int32_t)context->gpr[7])) {
	if (context->gpr[5] == context->gpr[7]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_0111_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[5] = context->gpr[5] - context->gpr[7];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_0111_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[5]) - ((uint64_t)context->gpr[7]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[5] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_0111_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[5] - context->gpr[7];
	context->t = (((context->gpr[5] ^ context->gpr[7])) & (context->gpr[5] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[5] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_0111_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[5] = context->gpr[7] + context->gpr[5];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_0111_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[5])) * ((int64_t)((int32_t)context->gpr[7])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_0111_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[7]) + ((uint64_t)context->gpr[5]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[5] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_0111_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[7] + context->gpr[5];
	context->t = (((context->gpr[7] ^ (~context->gpr[5]))) & (context->gpr[7] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[5] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_1000_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[5] - context->gpr[8];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_1000_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[5] >= context->gpr[8]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_1000_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[5]) >= ((int32_t)context->gpr[8])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_1000_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[5]) << 1 | ((uint64_t)context->gpr[5]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[5] >> 24 & 128U;
	context->gpr[5] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[5]) - ((uint64_t)context->gpr[8]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[5] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[8]) + ((uint64_t)context->gpr[5]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[5] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_1000_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[5] & 4294967295)) * ((uint64_t)(context->gpr[8] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_1000_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[8]) - ((uint64_t)context->gpr[5]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_1000_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[5]) >= ((int32_t)context->gpr[8])) {
	if (context->gpr[5] == context->gpr[8]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_1000_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[5] = context->gpr[5] - context->gpr[8];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_1000_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[5]) - ((uint64_t)context->gpr[8]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[5] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_1000_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[5] - context->gpr[8];
	context->t = (((context->gpr[5] ^ context->gpr[8])) & (context->gpr[5] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[5] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_1000_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[5] = context->gpr[8] + context->gpr[5];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_1000_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[5])) * ((int64_t)((int32_t)context->gpr[8])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_1000_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[8]) + ((uint64_t)context->gpr[5]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[5] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_1000_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[8] + context->gpr[5];
	context->t = (((context->gpr[8] ^ (~context->gpr[5]))) & (context->gpr[8] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[5] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_1001_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[5] - context->gpr[9];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_1001_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[5] >= context->gpr[9]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_1001_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[5]) >= ((int32_t)context->gpr[9])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_1001_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[5]) << 1 | ((uint64_t)context->gpr[5]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[5] >> 24 & 128U;
	context->gpr[5] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[5]) - ((uint64_t)context->gpr[9]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[5] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[9]) + ((uint64_t)context->gpr[5]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[5] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_1001_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[5] & 4294967295)) * ((uint64_t)(context->gpr[9] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_1001_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[9]) - ((uint64_t)context->gpr[5]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_1001_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[5]) >= ((int32_t)context->gpr[9])) {
	if (context->gpr[5] == context->gpr[9]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_1001_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[5] = context->gpr[5] - context->gpr[9];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_1001_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[5]) - ((uint64_t)context->gpr[9]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[5] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_1001_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[5] - context->gpr[9];
	context->t = (((context->gpr[5] ^ context->gpr[9])) & (context->gpr[5] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[5] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_1001_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[5] = context->gpr[9] + context->gpr[5];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_1001_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[5])) * ((int64_t)((int32_t)context->gpr[9])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_1001_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[9]) + ((uint64_t)context->gpr[5]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[5] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_1001_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[9] + context->gpr[5];
	context->t = (((context->gpr[9] ^ (~context->gpr[5]))) & (context->gpr[9] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[5] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_1010_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[5] - context->gpr[10];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_1010_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[5] >= context->gpr[10]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_1010_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[5]) >= ((int32_t)context->gpr[10])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_1010_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[5]) << 1 | ((uint64_t)context->gpr[5]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[5] >> 24 & 128U;
	context->gpr[5] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[5]) - ((uint64_t)context->gpr[10]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[5] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[10]) + ((uint64_t)context->gpr[5]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[5] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_1010_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[5] & 4294967295)) * ((uint64_t)(context->gpr[10] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_1010_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[10]) - ((uint64_t)context->gpr[5]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_1010_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[5]) >= ((int32_t)context->gpr[10])) {
	if (context->gpr[5] == context->gpr[10]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_1010_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[5] = context->gpr[5] - context->gpr[10];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_1010_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[5]) - ((uint64_t)context->gpr[10]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[5] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_1010_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[5] - context->gpr[10];
	context->t = (((context->gpr[5] ^ context->gpr[10])) & (context->gpr[5] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[5] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_1010_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[5] = context->gpr[10] + context->gpr[5];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_1010_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[5])) * ((int64_t)((int32_t)context->gpr[10])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_1010_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[10]) + ((uint64_t)context->gpr[5]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[5] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_1010_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[10] + context->gpr[5];
	context->t = (((context->gpr[10] ^ (~context->gpr[5]))) & (context->gpr[10] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[5] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_1011_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[5] - context->gpr[11];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_1011_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[5] >= context->gpr[11]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_1011_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[5]) >= ((int32_t)context->gpr[11])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_1011_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[5]) << 1 | ((uint64_t)context->gpr[5]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[5] >> 24 & 128U;
	context->gpr[5] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[5]) - ((uint64_t)context->gpr[11]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[5] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[11]) + ((uint64_t)context->gpr[5]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[5] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_1011_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[5] & 4294967295)) * ((uint64_t)(context->gpr[11] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_1011_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[11]) - ((uint64_t)context->gpr[5]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_1011_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[5]) >= ((int32_t)context->gpr[11])) {
	if (context->gpr[5] == context->gpr[11]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_1011_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[5] = context->gpr[5] - context->gpr[11];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_1011_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[5]) - ((uint64_t)context->gpr[11]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[5] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_1011_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[5] - context->gpr[11];
	context->t = (((context->gpr[5] ^ context->gpr[11])) & (context->gpr[5] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[5] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_1011_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[5] = context->gpr[11] + context->gpr[5];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_1011_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[5])) * ((int64_t)((int32_t)context->gpr[11])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_1011_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[11]) + ((uint64_t)context->gpr[5]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[5] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_1011_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[11] + context->gpr[5];
	context->t = (((context->gpr[11] ^ (~context->gpr[5]))) & (context->gpr[11] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[5] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_1100_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[5] - context->gpr[12];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_1100_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[5] >= context->gpr[12]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_1100_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[5]) >= ((int32_t)context->gpr[12])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_1100_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[5]) << 1 | ((uint64_t)context->gpr[5]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[5] >> 24 & 128U;
	context->gpr[5] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[5]) - ((uint64_t)context->gpr[12]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[5] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[12]) + ((uint64_t)context->gpr[5]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[5] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_1100_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[5] & 4294967295)) * ((uint64_t)(context->gpr[12] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_1100_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[12]) - ((uint64_t)context->gpr[5]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_1100_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[5]) >= ((int32_t)context->gpr[12])) {
	if (context->gpr[5] == context->gpr[12]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_1100_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[5] = context->gpr[5] - context->gpr[12];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_1100_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[5]) - ((uint64_t)context->gpr[12]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[5] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_1100_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[5] - context->gpr[12];
	context->t = (((context->gpr[5] ^ context->gpr[12])) & (context->gpr[5] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[5] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_1100_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[5] = context->gpr[12] + context->gpr[5];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_1100_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[5])) * ((int64_t)((int32_t)context->gpr[12])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_1100_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[12]) + ((uint64_t)context->gpr[5]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[5] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_1100_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[12] + context->gpr[5];
	context->t = (((context->gpr[12] ^ (~context->gpr[5]))) & (context->gpr[12] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[5] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_1101_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[5] - context->gpr[13];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_1101_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[5] >= context->gpr[13]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_1101_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[5]) >= ((int32_t)context->gpr[13])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_1101_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[5]) << 1 | ((uint64_t)context->gpr[5]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[5] >> 24 & 128U;
	context->gpr[5] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[5]) - ((uint64_t)context->gpr[13]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[5] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[13]) + ((uint64_t)context->gpr[5]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[5] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_1101_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[5] & 4294967295)) * ((uint64_t)(context->gpr[13] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_1101_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[13]) - ((uint64_t)context->gpr[5]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_1101_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[5]) >= ((int32_t)context->gpr[13])) {
	if (context->gpr[5] == context->gpr[13]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_1101_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[5] = context->gpr[5] - context->gpr[13];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_1101_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[5]) - ((uint64_t)context->gpr[13]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[5] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_1101_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[5] - context->gpr[13];
	context->t = (((context->gpr[5] ^ context->gpr[13])) & (context->gpr[5] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[5] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_1101_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[5] = context->gpr[13] + context->gpr[5];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_1101_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[5])) * ((int64_t)((int32_t)context->gpr[13])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_1101_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[13]) + ((uint64_t)context->gpr[5]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[5] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_1101_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[13] + context->gpr[5];
	context->t = (((context->gpr[13] ^ (~context->gpr[5]))) & (context->gpr[13] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[5] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_1110_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[5] - context->gpr[14];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_1110_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[5] >= context->gpr[14]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_1110_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[5]) >= ((int32_t)context->gpr[14])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_1110_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[5]) << 1 | ((uint64_t)context->gpr[5]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[5] >> 24 & 128U;
	context->gpr[5] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[5]) - ((uint64_t)context->gpr[14]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[5] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[14]) + ((uint64_t)context->gpr[5]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[5] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_1110_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[5] & 4294967295)) * ((uint64_t)(context->gpr[14] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_1110_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[14]) - ((uint64_t)context->gpr[5]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_1110_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[5]) >= ((int32_t)context->gpr[14])) {
	if (context->gpr[5] == context->gpr[14]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_1110_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[5] = context->gpr[5] - context->gpr[14];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_1110_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[5]) - ((uint64_t)context->gpr[14]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[5] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_1110_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[5] - context->gpr[14];
	context->t = (((context->gpr[5] ^ context->gpr[14])) & (context->gpr[5] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[5] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_1110_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[5] = context->gpr[14] + context->gpr[5];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_1110_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[5])) * ((int64_t)((int32_t)context->gpr[14])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_1110_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[14]) + ((uint64_t)context->gpr[5]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[5] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_1110_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[14] + context->gpr[5];
	context->t = (((context->gpr[14] ^ (~context->gpr[5]))) & (context->gpr[14] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[5] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_1111_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[5] - context->gpr[15];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_1111_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[5] >= context->gpr[15]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_1111_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[5]) >= ((int32_t)context->gpr[15])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_1111_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[5]) << 1 | ((uint64_t)context->gpr[5]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[5] >> 24 & 128U;
	context->gpr[5] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[5]) - ((uint64_t)context->gpr[15]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[5] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[15]) + ((uint64_t)context->gpr[5]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[5] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_1111_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[5] & 4294967295)) * ((uint64_t)(context->gpr[15] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_1111_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[15]) - ((uint64_t)context->gpr[5]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_1111_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[5]) >= ((int32_t)context->gpr[15])) {
	if (context->gpr[5] == context->gpr[15]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_1111_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[5] = context->gpr[5] - context->gpr[15];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_1111_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[5]) - ((uint64_t)context->gpr[15]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[5] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_1111_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[5] - context->gpr[15];
	context->t = (((context->gpr[5] ^ context->gpr[15])) & (context->gpr[5] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[5] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_1111_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[5] = context->gpr[15] + context->gpr[5];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_1111_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[5])) * ((int64_t)((int32_t)context->gpr[15])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_1111_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[15]) + ((uint64_t)context->gpr[5]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[5] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_1111_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[15] + context->gpr[5];
	context->t = (((context->gpr[15] ^ (~context->gpr[5]))) & (context->gpr[15] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[5] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_0000_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[6] - context->gpr[0];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_0000_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[6] >= context->gpr[0]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_0000_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[6]) >= ((int32_t)context->gpr[0])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_0000_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[6]) << 1 | ((uint64_t)context->gpr[6]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[6] >> 24 & 128U;
	context->gpr[6] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[6]) - ((uint64_t)context->gpr[0]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[6] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[0]) + ((uint64_t)context->gpr[6]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[6] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_0000_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[6] & 4294967295)) * ((uint64_t)(context->gpr[0] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_0000_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[0]) - ((uint64_t)context->gpr[6]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_0000_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[6]) >= ((int32_t)context->gpr[0])) {
	if (context->gpr[6] == context->gpr[0]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_0000_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[6] = context->gpr[6] - context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_0000_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[6]) - ((uint64_t)context->gpr[0]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[6] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_0000_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[6] - context->gpr[0];
	context->t = (((context->gpr[6] ^ context->gpr[0])) & (context->gpr[6] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[6] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_0000_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[6] = context->gpr[0] + context->gpr[6];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_0000_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[6])) * ((int64_t)((int32_t)context->gpr[0])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_0000_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[0]) + ((uint64_t)context->gpr[6]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[6] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_0000_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[0] + context->gpr[6];
	context->t = (((context->gpr[0] ^ (~context->gpr[6]))) & (context->gpr[0] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[6] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_0001_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[6] - context->gpr[1];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_0001_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[6] >= context->gpr[1]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_0001_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[6]) >= ((int32_t)context->gpr[1])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_0001_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[6]) << 1 | ((uint64_t)context->gpr[6]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[6] >> 24 & 128U;
	context->gpr[6] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[6]) - ((uint64_t)context->gpr[1]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[6] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[1]) + ((uint64_t)context->gpr[6]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[6] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_0001_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[6] & 4294967295)) * ((uint64_t)(context->gpr[1] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_0001_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[1]) - ((uint64_t)context->gpr[6]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_0001_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[6]) >= ((int32_t)context->gpr[1])) {
	if (context->gpr[6] == context->gpr[1]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_0001_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[6] = context->gpr[6] - context->gpr[1];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_0001_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[6]) - ((uint64_t)context->gpr[1]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[6] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_0001_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[6] - context->gpr[1];
	context->t = (((context->gpr[6] ^ context->gpr[1])) & (context->gpr[6] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[6] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_0001_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[6] = context->gpr[1] + context->gpr[6];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_0001_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[6])) * ((int64_t)((int32_t)context->gpr[1])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_0001_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[1]) + ((uint64_t)context->gpr[6]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[6] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_0001_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[1] + context->gpr[6];
	context->t = (((context->gpr[1] ^ (~context->gpr[6]))) & (context->gpr[1] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[6] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_0010_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[6] - context->gpr[2];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_0010_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[6] >= context->gpr[2]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_0010_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[6]) >= ((int32_t)context->gpr[2])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_0010_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[6]) << 1 | ((uint64_t)context->gpr[6]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[6] >> 24 & 128U;
	context->gpr[6] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[6]) - ((uint64_t)context->gpr[2]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[6] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[2]) + ((uint64_t)context->gpr[6]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[6] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_0010_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[6] & 4294967295)) * ((uint64_t)(context->gpr[2] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_0010_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[2]) - ((uint64_t)context->gpr[6]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_0010_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[6]) >= ((int32_t)context->gpr[2])) {
	if (context->gpr[6] == context->gpr[2]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_0010_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[6] = context->gpr[6] - context->gpr[2];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_0010_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[6]) - ((uint64_t)context->gpr[2]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[6] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_0010_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[6] - context->gpr[2];
	context->t = (((context->gpr[6] ^ context->gpr[2])) & (context->gpr[6] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[6] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_0010_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[6] = context->gpr[2] + context->gpr[6];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_0010_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[6])) * ((int64_t)((int32_t)context->gpr[2])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_0010_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[2]) + ((uint64_t)context->gpr[6]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[6] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_0010_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[2] + context->gpr[6];
	context->t = (((context->gpr[2] ^ (~context->gpr[6]))) & (context->gpr[2] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[6] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_0011_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[6] - context->gpr[3];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_0011_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[6] >= context->gpr[3]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_0011_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[6]) >= ((int32_t)context->gpr[3])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_0011_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[6]) << 1 | ((uint64_t)context->gpr[6]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[6] >> 24 & 128U;
	context->gpr[6] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[6]) - ((uint64_t)context->gpr[3]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[6] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[3]) + ((uint64_t)context->gpr[6]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[6] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_0011_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[6] & 4294967295)) * ((uint64_t)(context->gpr[3] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_0011_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[3]) - ((uint64_t)context->gpr[6]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_0011_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[6]) >= ((int32_t)context->gpr[3])) {
	if (context->gpr[6] == context->gpr[3]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_0011_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[6] = context->gpr[6] - context->gpr[3];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_0011_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[6]) - ((uint64_t)context->gpr[3]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[6] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_0011_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[6] - context->gpr[3];
	context->t = (((context->gpr[6] ^ context->gpr[3])) & (context->gpr[6] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[6] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_0011_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[6] = context->gpr[3] + context->gpr[6];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_0011_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[6])) * ((int64_t)((int32_t)context->gpr[3])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_0011_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[3]) + ((uint64_t)context->gpr[6]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[6] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_0011_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[3] + context->gpr[6];
	context->t = (((context->gpr[3] ^ (~context->gpr[6]))) & (context->gpr[3] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[6] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_0100_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[6] - context->gpr[4];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_0100_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[6] >= context->gpr[4]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_0100_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[6]) >= ((int32_t)context->gpr[4])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_0100_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[6]) << 1 | ((uint64_t)context->gpr[6]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[6] >> 24 & 128U;
	context->gpr[6] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[6]) - ((uint64_t)context->gpr[4]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[6] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[4]) + ((uint64_t)context->gpr[6]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[6] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_0100_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[6] & 4294967295)) * ((uint64_t)(context->gpr[4] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_0100_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[4]) - ((uint64_t)context->gpr[6]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_0100_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[6]) >= ((int32_t)context->gpr[4])) {
	if (context->gpr[6] == context->gpr[4]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_0100_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[6] = context->gpr[6] - context->gpr[4];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_0100_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[6]) - ((uint64_t)context->gpr[4]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[6] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_0100_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[6] - context->gpr[4];
	context->t = (((context->gpr[6] ^ context->gpr[4])) & (context->gpr[6] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[6] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_0100_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[6] = context->gpr[4] + context->gpr[6];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_0100_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[6])) * ((int64_t)((int32_t)context->gpr[4])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_0100_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[4]) + ((uint64_t)context->gpr[6]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[6] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_0100_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[4] + context->gpr[6];
	context->t = (((context->gpr[4] ^ (~context->gpr[6]))) & (context->gpr[4] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[6] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_0101_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[6] - context->gpr[5];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_0101_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[6] >= context->gpr[5]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_0101_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[6]) >= ((int32_t)context->gpr[5])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_0101_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[6]) << 1 | ((uint64_t)context->gpr[6]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[6] >> 24 & 128U;
	context->gpr[6] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[6]) - ((uint64_t)context->gpr[5]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[6] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[5]) + ((uint64_t)context->gpr[6]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[6] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_0101_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[6] & 4294967295)) * ((uint64_t)(context->gpr[5] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_0101_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[5]) - ((uint64_t)context->gpr[6]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_0101_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[6]) >= ((int32_t)context->gpr[5])) {
	if (context->gpr[6] == context->gpr[5]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_0101_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[6] = context->gpr[6] - context->gpr[5];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_0101_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[6]) - ((uint64_t)context->gpr[5]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[6] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_0101_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[6] - context->gpr[5];
	context->t = (((context->gpr[6] ^ context->gpr[5])) & (context->gpr[6] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[6] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_0101_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[6] = context->gpr[5] + context->gpr[6];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_0101_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[6])) * ((int64_t)((int32_t)context->gpr[5])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_0101_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[5]) + ((uint64_t)context->gpr[6]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[6] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_0101_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[5] + context->gpr[6];
	context->t = (((context->gpr[5] ^ (~context->gpr[6]))) & (context->gpr[5] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[6] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_0110_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[6] - context->gpr[6];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_0110_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[6] >= context->gpr[6]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_0110_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[6]) >= ((int32_t)context->gpr[6])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_0110_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[6]) << 1 | ((uint64_t)context->gpr[6]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[6] >> 24 & 128U;
	context->gpr[6] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[6]) - ((uint64_t)context->gpr[6]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[6] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[6]) + ((uint64_t)context->gpr[6]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[6] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_0110_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[6] & 4294967295)) * ((uint64_t)(context->gpr[6] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_0110_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[6]) - ((uint64_t)context->gpr[6]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_0110_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[6]) >= ((int32_t)context->gpr[6])) {
	if (context->gpr[6] == context->gpr[6]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_0110_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[6] = context->gpr[6] - context->gpr[6];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_0110_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[6]) - ((uint64_t)context->gpr[6]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[6] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_0110_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[6] - context->gpr[6];
	context->t = (((context->gpr[6] ^ context->gpr[6])) & (context->gpr[6] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[6] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_0110_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[6] = context->gpr[6] + context->gpr[6];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_0110_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[6])) * ((int64_t)((int32_t)context->gpr[6])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_0110_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[6]) + ((uint64_t)context->gpr[6]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[6] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_0110_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[6] + context->gpr[6];
	context->t = (((context->gpr[6] ^ (~context->gpr[6]))) & (context->gpr[6] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[6] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_0111_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[6] - context->gpr[7];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_0111_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[6] >= context->gpr[7]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_0111_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[6]) >= ((int32_t)context->gpr[7])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_0111_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[6]) << 1 | ((uint64_t)context->gpr[6]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[6] >> 24 & 128U;
	context->gpr[6] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[6]) - ((uint64_t)context->gpr[7]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[6] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[7]) + ((uint64_t)context->gpr[6]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[6] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_0111_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[6] & 4294967295)) * ((uint64_t)(context->gpr[7] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_0111_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[7]) - ((uint64_t)context->gpr[6]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_0111_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[6]) >= ((int32_t)context->gpr[7])) {
	if (context->gpr[6] == context->gpr[7]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_0111_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[6] = context->gpr[6] - context->gpr[7];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_0111_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[6]) - ((uint64_t)context->gpr[7]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[6] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_0111_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[6] - context->gpr[7];
	context->t = (((context->gpr[6] ^ context->gpr[7])) & (context->gpr[6] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[6] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_0111_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[6] = context->gpr[7] + context->gpr[6];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_0111_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[6])) * ((int64_t)((int32_t)context->gpr[7])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_0111_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[7]) + ((uint64_t)context->gpr[6]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[6] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_0111_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[7] + context->gpr[6];
	context->t = (((context->gpr[7] ^ (~context->gpr[6]))) & (context->gpr[7] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[6] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_1000_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[6] - context->gpr[8];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_1000_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[6] >= context->gpr[8]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_1000_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[6]) >= ((int32_t)context->gpr[8])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_1000_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[6]) << 1 | ((uint64_t)context->gpr[6]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[6] >> 24 & 128U;
	context->gpr[6] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[6]) - ((uint64_t)context->gpr[8]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[6] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[8]) + ((uint64_t)context->gpr[6]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[6] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_1000_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[6] & 4294967295)) * ((uint64_t)(context->gpr[8] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_1000_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[8]) - ((uint64_t)context->gpr[6]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_1000_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[6]) >= ((int32_t)context->gpr[8])) {
	if (context->gpr[6] == context->gpr[8]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_1000_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[6] = context->gpr[6] - context->gpr[8];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_1000_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[6]) - ((uint64_t)context->gpr[8]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[6] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_1000_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[6] - context->gpr[8];
	context->t = (((context->gpr[6] ^ context->gpr[8])) & (context->gpr[6] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[6] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_1000_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[6] = context->gpr[8] + context->gpr[6];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_1000_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[6])) * ((int64_t)((int32_t)context->gpr[8])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_1000_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[8]) + ((uint64_t)context->gpr[6]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[6] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_1000_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[8] + context->gpr[6];
	context->t = (((context->gpr[8] ^ (~context->gpr[6]))) & (context->gpr[8] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[6] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_1001_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[6] - context->gpr[9];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_1001_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[6] >= context->gpr[9]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_1001_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[6]) >= ((int32_t)context->gpr[9])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_1001_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[6]) << 1 | ((uint64_t)context->gpr[6]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[6] >> 24 & 128U;
	context->gpr[6] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[6]) - ((uint64_t)context->gpr[9]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[6] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[9]) + ((uint64_t)context->gpr[6]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[6] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_1001_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[6] & 4294967295)) * ((uint64_t)(context->gpr[9] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_1001_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[9]) - ((uint64_t)context->gpr[6]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_1001_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[6]) >= ((int32_t)context->gpr[9])) {
	if (context->gpr[6] == context->gpr[9]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_1001_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[6] = context->gpr[6] - context->gpr[9];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_1001_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[6]) - ((uint64_t)context->gpr[9]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[6] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_1001_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[6] - context->gpr[9];
	context->t = (((context->gpr[6] ^ context->gpr[9])) & (context->gpr[6] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[6] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_1001_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[6] = context->gpr[9] + context->gpr[6];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_1001_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[6])) * ((int64_t)((int32_t)context->gpr[9])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_1001_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[9]) + ((uint64_t)context->gpr[6]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[6] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_1001_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[9] + context->gpr[6];
	context->t = (((context->gpr[9] ^ (~context->gpr[6]))) & (context->gpr[9] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[6] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_1010_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[6] - context->gpr[10];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_1010_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[6] >= context->gpr[10]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_1010_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[6]) >= ((int32_t)context->gpr[10])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_1010_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[6]) << 1 | ((uint64_t)context->gpr[6]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[6] >> 24 & 128U;
	context->gpr[6] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[6]) - ((uint64_t)context->gpr[10]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[6] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[10]) + ((uint64_t)context->gpr[6]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[6] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_1010_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[6] & 4294967295)) * ((uint64_t)(context->gpr[10] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_1010_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[10]) - ((uint64_t)context->gpr[6]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_1010_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[6]) >= ((int32_t)context->gpr[10])) {
	if (context->gpr[6] == context->gpr[10]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_1010_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[6] = context->gpr[6] - context->gpr[10];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_1010_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[6]) - ((uint64_t)context->gpr[10]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[6] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_1010_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[6] - context->gpr[10];
	context->t = (((context->gpr[6] ^ context->gpr[10])) & (context->gpr[6] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[6] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_1010_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[6] = context->gpr[10] + context->gpr[6];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_1010_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[6])) * ((int64_t)((int32_t)context->gpr[10])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_1010_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[10]) + ((uint64_t)context->gpr[6]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[6] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_1010_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[10] + context->gpr[6];
	context->t = (((context->gpr[10] ^ (~context->gpr[6]))) & (context->gpr[10] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[6] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_1011_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[6] - context->gpr[11];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_1011_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[6] >= context->gpr[11]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_1011_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[6]) >= ((int32_t)context->gpr[11])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_1011_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[6]) << 1 | ((uint64_t)context->gpr[6]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[6] >> 24 & 128U;
	context->gpr[6] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[6]) - ((uint64_t)context->gpr[11]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[6] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[11]) + ((uint64_t)context->gpr[6]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[6] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_1011_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[6] & 4294967295)) * ((uint64_t)(context->gpr[11] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_1011_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[11]) - ((uint64_t)context->gpr[6]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_1011_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[6]) >= ((int32_t)context->gpr[11])) {
	if (context->gpr[6] == context->gpr[11]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_1011_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[6] = context->gpr[6] - context->gpr[11];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_1011_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[6]) - ((uint64_t)context->gpr[11]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[6] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_1011_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[6] - context->gpr[11];
	context->t = (((context->gpr[6] ^ context->gpr[11])) & (context->gpr[6] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[6] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_1011_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[6] = context->gpr[11] + context->gpr[6];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_1011_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[6])) * ((int64_t)((int32_t)context->gpr[11])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_1011_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[11]) + ((uint64_t)context->gpr[6]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[6] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_1011_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[11] + context->gpr[6];
	context->t = (((context->gpr[11] ^ (~context->gpr[6]))) & (context->gpr[11] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[6] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_1100_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[6] - context->gpr[12];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_1100_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[6] >= context->gpr[12]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_1100_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[6]) >= ((int32_t)context->gpr[12])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_1100_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[6]) << 1 | ((uint64_t)context->gpr[6]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[6] >> 24 & 128U;
	context->gpr[6] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[6]) - ((uint64_t)context->gpr[12]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[6] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[12]) + ((uint64_t)context->gpr[6]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[6] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_1100_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[6] & 4294967295)) * ((uint64_t)(context->gpr[12] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_1100_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[12]) - ((uint64_t)context->gpr[6]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_1100_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[6]) >= ((int32_t)context->gpr[12])) {
	if (context->gpr[6] == context->gpr[12]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_1100_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[6] = context->gpr[6] - context->gpr[12];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_1100_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[6]) - ((uint64_t)context->gpr[12]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[6] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_1100_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[6] - context->gpr[12];
	context->t = (((context->gpr[6] ^ context->gpr[12])) & (context->gpr[6] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[6] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_1100_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[6] = context->gpr[12] + context->gpr[6];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_1100_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[6])) * ((int64_t)((int32_t)context->gpr[12])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_1100_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[12]) + ((uint64_t)context->gpr[6]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[6] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_1100_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[12] + context->gpr[6];
	context->t = (((context->gpr[12] ^ (~context->gpr[6]))) & (context->gpr[12] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[6] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_1101_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[6] - context->gpr[13];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_1101_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[6] >= context->gpr[13]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_1101_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[6]) >= ((int32_t)context->gpr[13])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_1101_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[6]) << 1 | ((uint64_t)context->gpr[6]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[6] >> 24 & 128U;
	context->gpr[6] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[6]) - ((uint64_t)context->gpr[13]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[6] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[13]) + ((uint64_t)context->gpr[6]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[6] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_1101_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[6] & 4294967295)) * ((uint64_t)(context->gpr[13] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_1101_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[13]) - ((uint64_t)context->gpr[6]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_1101_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[6]) >= ((int32_t)context->gpr[13])) {
	if (context->gpr[6] == context->gpr[13]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_1101_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[6] = context->gpr[6] - context->gpr[13];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_1101_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[6]) - ((uint64_t)context->gpr[13]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[6] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_1101_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[6] - context->gpr[13];
	context->t = (((context->gpr[6] ^ context->gpr[13])) & (context->gpr[6] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[6] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_1101_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[6] = context->gpr[13] + context->gpr[6];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_1101_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[6])) * ((int64_t)((int32_t)context->gpr[13])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_1101_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[13]) + ((uint64_t)context->gpr[6]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[6] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_1101_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[13] + context->gpr[6];
	context->t = (((context->gpr[13] ^ (~context->gpr[6]))) & (context->gpr[13] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[6] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_1110_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[6] - context->gpr[14];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_1110_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[6] >= context->gpr[14]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_1110_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[6]) >= ((int32_t)context->gpr[14])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_1110_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[6]) << 1 | ((uint64_t)context->gpr[6]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[6] >> 24 & 128U;
	context->gpr[6] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[6]) - ((uint64_t)context->gpr[14]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[6] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[14]) + ((uint64_t)context->gpr[6]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[6] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_1110_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[6] & 4294967295)) * ((uint64_t)(context->gpr[14] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_1110_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[14]) - ((uint64_t)context->gpr[6]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_1110_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[6]) >= ((int32_t)context->gpr[14])) {
	if (context->gpr[6] == context->gpr[14]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_1110_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[6] = context->gpr[6] - context->gpr[14];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_1110_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[6]) - ((uint64_t)context->gpr[14]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[6] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_1110_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[6] - context->gpr[14];
	context->t = (((context->gpr[6] ^ context->gpr[14])) & (context->gpr[6] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[6] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_1110_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[6] = context->gpr[14] + context->gpr[6];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_1110_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[6])) * ((int64_t)((int32_t)context->gpr[14])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_1110_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[14]) + ((uint64_t)context->gpr[6]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[6] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_1110_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[14] + context->gpr[6];
	context->t = (((context->gpr[14] ^ (~context->gpr[6]))) & (context->gpr[14] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[6] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_1111_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[6] - context->gpr[15];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_1111_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[6] >= context->gpr[15]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_1111_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[6]) >= ((int32_t)context->gpr[15])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_1111_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[6]) << 1 | ((uint64_t)context->gpr[6]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[6] >> 24 & 128U;
	context->gpr[6] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[6]) - ((uint64_t)context->gpr[15]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[6] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[15]) + ((uint64_t)context->gpr[6]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[6] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_1111_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[6] & 4294967295)) * ((uint64_t)(context->gpr[15] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_1111_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[15]) - ((uint64_t)context->gpr[6]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_1111_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[6]) >= ((int32_t)context->gpr[15])) {
	if (context->gpr[6] == context->gpr[15]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_1111_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[6] = context->gpr[6] - context->gpr[15];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_1111_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[6]) - ((uint64_t)context->gpr[15]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[6] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_1111_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[6] - context->gpr[15];
	context->t = (((context->gpr[6] ^ context->gpr[15])) & (context->gpr[6] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[6] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_1111_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[6] = context->gpr[15] + context->gpr[6];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_1111_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[6])) * ((int64_t)((int32_t)context->gpr[15])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_1111_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[15]) + ((uint64_t)context->gpr[6]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[6] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_1111_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[15] + context->gpr[6];
	context->t = (((context->gpr[15] ^ (~context->gpr[6]))) & (context->gpr[15] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[6] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_0000_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[7] - context->gpr[0];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_0000_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[7] >= context->gpr[0]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_0000_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[7]) >= ((int32_t)context->gpr[0])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_0000_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[7]) << 1 | ((uint64_t)context->gpr[7]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[7] >> 24 & 128U;
	context->gpr[7] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[7]) - ((uint64_t)context->gpr[0]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[7] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[0]) + ((uint64_t)context->gpr[7]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[7] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_0000_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[7] & 4294967295)) * ((uint64_t)(context->gpr[0] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_0000_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[0]) - ((uint64_t)context->gpr[7]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_0000_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[7]) >= ((int32_t)context->gpr[0])) {
	if (context->gpr[7] == context->gpr[0]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_0000_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[7] = context->gpr[7] - context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_0000_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[7]) - ((uint64_t)context->gpr[0]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[7] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_0000_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[7] - context->gpr[0];
	context->t = (((context->gpr[7] ^ context->gpr[0])) & (context->gpr[7] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[7] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_0000_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[7] = context->gpr[0] + context->gpr[7];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_0000_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[7])) * ((int64_t)((int32_t)context->gpr[0])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_0000_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[0]) + ((uint64_t)context->gpr[7]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[7] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_0000_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[0] + context->gpr[7];
	context->t = (((context->gpr[0] ^ (~context->gpr[7]))) & (context->gpr[0] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[7] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_0001_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[7] - context->gpr[1];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_0001_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[7] >= context->gpr[1]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_0001_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[7]) >= ((int32_t)context->gpr[1])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_0001_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[7]) << 1 | ((uint64_t)context->gpr[7]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[7] >> 24 & 128U;
	context->gpr[7] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[7]) - ((uint64_t)context->gpr[1]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[7] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[1]) + ((uint64_t)context->gpr[7]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[7] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_0001_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[7] & 4294967295)) * ((uint64_t)(context->gpr[1] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_0001_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[1]) - ((uint64_t)context->gpr[7]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_0001_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[7]) >= ((int32_t)context->gpr[1])) {
	if (context->gpr[7] == context->gpr[1]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_0001_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[7] = context->gpr[7] - context->gpr[1];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_0001_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[7]) - ((uint64_t)context->gpr[1]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[7] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_0001_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[7] - context->gpr[1];
	context->t = (((context->gpr[7] ^ context->gpr[1])) & (context->gpr[7] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[7] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_0001_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[7] = context->gpr[1] + context->gpr[7];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_0001_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[7])) * ((int64_t)((int32_t)context->gpr[1])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_0001_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[1]) + ((uint64_t)context->gpr[7]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[7] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_0001_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[1] + context->gpr[7];
	context->t = (((context->gpr[1] ^ (~context->gpr[7]))) & (context->gpr[1] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[7] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_0010_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[7] - context->gpr[2];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_0010_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[7] >= context->gpr[2]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_0010_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[7]) >= ((int32_t)context->gpr[2])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_0010_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[7]) << 1 | ((uint64_t)context->gpr[7]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[7] >> 24 & 128U;
	context->gpr[7] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[7]) - ((uint64_t)context->gpr[2]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[7] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[2]) + ((uint64_t)context->gpr[7]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[7] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_0010_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[7] & 4294967295)) * ((uint64_t)(context->gpr[2] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_0010_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[2]) - ((uint64_t)context->gpr[7]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_0010_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[7]) >= ((int32_t)context->gpr[2])) {
	if (context->gpr[7] == context->gpr[2]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_0010_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[7] = context->gpr[7] - context->gpr[2];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_0010_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[7]) - ((uint64_t)context->gpr[2]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[7] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_0010_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[7] - context->gpr[2];
	context->t = (((context->gpr[7] ^ context->gpr[2])) & (context->gpr[7] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[7] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_0010_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[7] = context->gpr[2] + context->gpr[7];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_0010_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[7])) * ((int64_t)((int32_t)context->gpr[2])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_0010_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[2]) + ((uint64_t)context->gpr[7]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[7] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_0010_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[2] + context->gpr[7];
	context->t = (((context->gpr[2] ^ (~context->gpr[7]))) & (context->gpr[2] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[7] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_0011_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[7] - context->gpr[3];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_0011_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[7] >= context->gpr[3]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_0011_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[7]) >= ((int32_t)context->gpr[3])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_0011_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[7]) << 1 | ((uint64_t)context->gpr[7]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[7] >> 24 & 128U;
	context->gpr[7] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[7]) - ((uint64_t)context->gpr[3]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[7] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[3]) + ((uint64_t)context->gpr[7]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[7] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_0011_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[7] & 4294967295)) * ((uint64_t)(context->gpr[3] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_0011_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[3]) - ((uint64_t)context->gpr[7]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_0011_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[7]) >= ((int32_t)context->gpr[3])) {
	if (context->gpr[7] == context->gpr[3]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_0011_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[7] = context->gpr[7] - context->gpr[3];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_0011_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[7]) - ((uint64_t)context->gpr[3]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[7] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_0011_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[7] - context->gpr[3];
	context->t = (((context->gpr[7] ^ context->gpr[3])) & (context->gpr[7] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[7] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_0011_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[7] = context->gpr[3] + context->gpr[7];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_0011_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[7])) * ((int64_t)((int32_t)context->gpr[3])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_0011_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[3]) + ((uint64_t)context->gpr[7]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[7] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_0011_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[3] + context->gpr[7];
	context->t = (((context->gpr[3] ^ (~context->gpr[7]))) & (context->gpr[3] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[7] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_0100_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[7] - context->gpr[4];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_0100_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[7] >= context->gpr[4]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_0100_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[7]) >= ((int32_t)context->gpr[4])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_0100_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[7]) << 1 | ((uint64_t)context->gpr[7]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[7] >> 24 & 128U;
	context->gpr[7] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[7]) - ((uint64_t)context->gpr[4]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[7] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[4]) + ((uint64_t)context->gpr[7]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[7] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_0100_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[7] & 4294967295)) * ((uint64_t)(context->gpr[4] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_0100_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[4]) - ((uint64_t)context->gpr[7]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_0100_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[7]) >= ((int32_t)context->gpr[4])) {
	if (context->gpr[7] == context->gpr[4]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_0100_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[7] = context->gpr[7] - context->gpr[4];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_0100_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[7]) - ((uint64_t)context->gpr[4]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[7] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_0100_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[7] - context->gpr[4];
	context->t = (((context->gpr[7] ^ context->gpr[4])) & (context->gpr[7] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[7] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_0100_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[7] = context->gpr[4] + context->gpr[7];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_0100_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[7])) * ((int64_t)((int32_t)context->gpr[4])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_0100_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[4]) + ((uint64_t)context->gpr[7]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[7] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_0100_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[4] + context->gpr[7];
	context->t = (((context->gpr[4] ^ (~context->gpr[7]))) & (context->gpr[4] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[7] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_0101_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[7] - context->gpr[5];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_0101_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[7] >= context->gpr[5]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_0101_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[7]) >= ((int32_t)context->gpr[5])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_0101_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[7]) << 1 | ((uint64_t)context->gpr[7]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[7] >> 24 & 128U;
	context->gpr[7] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[7]) - ((uint64_t)context->gpr[5]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[7] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[5]) + ((uint64_t)context->gpr[7]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[7] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_0101_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[7] & 4294967295)) * ((uint64_t)(context->gpr[5] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_0101_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[5]) - ((uint64_t)context->gpr[7]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_0101_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[7]) >= ((int32_t)context->gpr[5])) {
	if (context->gpr[7] == context->gpr[5]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_0101_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[7] = context->gpr[7] - context->gpr[5];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_0101_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[7]) - ((uint64_t)context->gpr[5]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[7] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_0101_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[7] - context->gpr[5];
	context->t = (((context->gpr[7] ^ context->gpr[5])) & (context->gpr[7] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[7] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_0101_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[7] = context->gpr[5] + context->gpr[7];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_0101_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[7])) * ((int64_t)((int32_t)context->gpr[5])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_0101_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[5]) + ((uint64_t)context->gpr[7]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[7] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_0101_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[5] + context->gpr[7];
	context->t = (((context->gpr[5] ^ (~context->gpr[7]))) & (context->gpr[5] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[7] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_0110_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[7] - context->gpr[6];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_0110_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[7] >= context->gpr[6]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_0110_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[7]) >= ((int32_t)context->gpr[6])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_0110_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[7]) << 1 | ((uint64_t)context->gpr[7]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[7] >> 24 & 128U;
	context->gpr[7] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[7]) - ((uint64_t)context->gpr[6]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[7] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[6]) + ((uint64_t)context->gpr[7]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[7] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_0110_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[7] & 4294967295)) * ((uint64_t)(context->gpr[6] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_0110_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[6]) - ((uint64_t)context->gpr[7]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_0110_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[7]) >= ((int32_t)context->gpr[6])) {
	if (context->gpr[7] == context->gpr[6]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_0110_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[7] = context->gpr[7] - context->gpr[6];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_0110_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[7]) - ((uint64_t)context->gpr[6]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[7] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_0110_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[7] - context->gpr[6];
	context->t = (((context->gpr[7] ^ context->gpr[6])) & (context->gpr[7] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[7] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_0110_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[7] = context->gpr[6] + context->gpr[7];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_0110_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[7])) * ((int64_t)((int32_t)context->gpr[6])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_0110_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[6]) + ((uint64_t)context->gpr[7]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[7] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_0110_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[6] + context->gpr[7];
	context->t = (((context->gpr[6] ^ (~context->gpr[7]))) & (context->gpr[6] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[7] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_0111_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[7] - context->gpr[7];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_0111_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[7] >= context->gpr[7]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_0111_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[7]) >= ((int32_t)context->gpr[7])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_0111_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[7]) << 1 | ((uint64_t)context->gpr[7]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[7] >> 24 & 128U;
	context->gpr[7] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[7]) - ((uint64_t)context->gpr[7]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[7] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[7]) + ((uint64_t)context->gpr[7]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[7] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_0111_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[7] & 4294967295)) * ((uint64_t)(context->gpr[7] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_0111_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[7]) - ((uint64_t)context->gpr[7]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_0111_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[7]) >= ((int32_t)context->gpr[7])) {
	if (context->gpr[7] == context->gpr[7]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_0111_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[7] = context->gpr[7] - context->gpr[7];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_0111_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[7]) - ((uint64_t)context->gpr[7]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[7] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_0111_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[7] - context->gpr[7];
	context->t = (((context->gpr[7] ^ context->gpr[7])) & (context->gpr[7] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[7] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_0111_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[7] = context->gpr[7] + context->gpr[7];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_0111_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[7])) * ((int64_t)((int32_t)context->gpr[7])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_0111_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[7]) + ((uint64_t)context->gpr[7]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[7] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_0111_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[7] + context->gpr[7];
	context->t = (((context->gpr[7] ^ (~context->gpr[7]))) & (context->gpr[7] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[7] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_1000_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[7] - context->gpr[8];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_1000_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[7] >= context->gpr[8]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_1000_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[7]) >= ((int32_t)context->gpr[8])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_1000_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[7]) << 1 | ((uint64_t)context->gpr[7]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[7] >> 24 & 128U;
	context->gpr[7] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[7]) - ((uint64_t)context->gpr[8]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[7] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[8]) + ((uint64_t)context->gpr[7]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[7] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_1000_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[7] & 4294967295)) * ((uint64_t)(context->gpr[8] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_1000_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[8]) - ((uint64_t)context->gpr[7]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_1000_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[7]) >= ((int32_t)context->gpr[8])) {
	if (context->gpr[7] == context->gpr[8]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_1000_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[7] = context->gpr[7] - context->gpr[8];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_1000_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[7]) - ((uint64_t)context->gpr[8]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[7] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_1000_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[7] - context->gpr[8];
	context->t = (((context->gpr[7] ^ context->gpr[8])) & (context->gpr[7] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[7] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_1000_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[7] = context->gpr[8] + context->gpr[7];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_1000_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[7])) * ((int64_t)((int32_t)context->gpr[8])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_1000_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[8]) + ((uint64_t)context->gpr[7]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[7] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_1000_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[8] + context->gpr[7];
	context->t = (((context->gpr[8] ^ (~context->gpr[7]))) & (context->gpr[8] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[7] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_1001_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[7] - context->gpr[9];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_1001_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[7] >= context->gpr[9]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_1001_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[7]) >= ((int32_t)context->gpr[9])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_1001_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[7]) << 1 | ((uint64_t)context->gpr[7]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[7] >> 24 & 128U;
	context->gpr[7] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[7]) - ((uint64_t)context->gpr[9]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[7] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[9]) + ((uint64_t)context->gpr[7]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[7] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_1001_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[7] & 4294967295)) * ((uint64_t)(context->gpr[9] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_1001_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[9]) - ((uint64_t)context->gpr[7]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_1001_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[7]) >= ((int32_t)context->gpr[9])) {
	if (context->gpr[7] == context->gpr[9]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_1001_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[7] = context->gpr[7] - context->gpr[9];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_1001_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[7]) - ((uint64_t)context->gpr[9]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[7] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_1001_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[7] - context->gpr[9];
	context->t = (((context->gpr[7] ^ context->gpr[9])) & (context->gpr[7] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[7] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_1001_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[7] = context->gpr[9] + context->gpr[7];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_1001_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[7])) * ((int64_t)((int32_t)context->gpr[9])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_1001_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[9]) + ((uint64_t)context->gpr[7]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[7] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_1001_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[9] + context->gpr[7];
	context->t = (((context->gpr[9] ^ (~context->gpr[7]))) & (context->gpr[9] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[7] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_1010_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[7] - context->gpr[10];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_1010_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[7] >= context->gpr[10]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_1010_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[7]) >= ((int32_t)context->gpr[10])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_1010_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[7]) << 1 | ((uint64_t)context->gpr[7]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[7] >> 24 & 128U;
	context->gpr[7] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[7]) - ((uint64_t)context->gpr[10]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[7] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[10]) + ((uint64_t)context->gpr[7]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[7] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_1010_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[7] & 4294967295)) * ((uint64_t)(context->gpr[10] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_1010_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[10]) - ((uint64_t)context->gpr[7]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_1010_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[7]) >= ((int32_t)context->gpr[10])) {
	if (context->gpr[7] == context->gpr[10]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_1010_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[7] = context->gpr[7] - context->gpr[10];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_1010_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[7]) - ((uint64_t)context->gpr[10]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[7] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_1010_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[7] - context->gpr[10];
	context->t = (((context->gpr[7] ^ context->gpr[10])) & (context->gpr[7] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[7] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_1010_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[7] = context->gpr[10] + context->gpr[7];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_1010_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[7])) * ((int64_t)((int32_t)context->gpr[10])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_1010_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[10]) + ((uint64_t)context->gpr[7]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[7] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_1010_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[10] + context->gpr[7];
	context->t = (((context->gpr[10] ^ (~context->gpr[7]))) & (context->gpr[10] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[7] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_1011_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[7] - context->gpr[11];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_1011_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[7] >= context->gpr[11]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_1011_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[7]) >= ((int32_t)context->gpr[11])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_1011_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[7]) << 1 | ((uint64_t)context->gpr[7]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[7] >> 24 & 128U;
	context->gpr[7] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[7]) - ((uint64_t)context->gpr[11]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[7] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[11]) + ((uint64_t)context->gpr[7]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[7] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_1011_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[7] & 4294967295)) * ((uint64_t)(context->gpr[11] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_1011_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[11]) - ((uint64_t)context->gpr[7]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_1011_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[7]) >= ((int32_t)context->gpr[11])) {
	if (context->gpr[7] == context->gpr[11]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_1011_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[7] = context->gpr[7] - context->gpr[11];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_1011_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[7]) - ((uint64_t)context->gpr[11]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[7] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_1011_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[7] - context->gpr[11];
	context->t = (((context->gpr[7] ^ context->gpr[11])) & (context->gpr[7] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[7] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_1011_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[7] = context->gpr[11] + context->gpr[7];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_1011_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[7])) * ((int64_t)((int32_t)context->gpr[11])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_1011_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[11]) + ((uint64_t)context->gpr[7]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[7] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_1011_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[11] + context->gpr[7];
	context->t = (((context->gpr[11] ^ (~context->gpr[7]))) & (context->gpr[11] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[7] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_1100_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[7] - context->gpr[12];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_1100_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[7] >= context->gpr[12]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_1100_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[7]) >= ((int32_t)context->gpr[12])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_1100_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[7]) << 1 | ((uint64_t)context->gpr[7]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[7] >> 24 & 128U;
	context->gpr[7] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[7]) - ((uint64_t)context->gpr[12]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[7] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[12]) + ((uint64_t)context->gpr[7]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[7] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_1100_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[7] & 4294967295)) * ((uint64_t)(context->gpr[12] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_1100_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[12]) - ((uint64_t)context->gpr[7]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_1100_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[7]) >= ((int32_t)context->gpr[12])) {
	if (context->gpr[7] == context->gpr[12]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_1100_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[7] = context->gpr[7] - context->gpr[12];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_1100_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[7]) - ((uint64_t)context->gpr[12]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[7] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_1100_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[7] - context->gpr[12];
	context->t = (((context->gpr[7] ^ context->gpr[12])) & (context->gpr[7] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[7] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_1100_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[7] = context->gpr[12] + context->gpr[7];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_1100_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[7])) * ((int64_t)((int32_t)context->gpr[12])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_1100_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[12]) + ((uint64_t)context->gpr[7]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[7] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_1100_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[12] + context->gpr[7];
	context->t = (((context->gpr[12] ^ (~context->gpr[7]))) & (context->gpr[12] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[7] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_1101_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[7] - context->gpr[13];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_1101_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[7] >= context->gpr[13]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_1101_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[7]) >= ((int32_t)context->gpr[13])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_1101_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[7]) << 1 | ((uint64_t)context->gpr[7]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[7] >> 24 & 128U;
	context->gpr[7] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[7]) - ((uint64_t)context->gpr[13]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[7] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[13]) + ((uint64_t)context->gpr[7]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[7] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_1101_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[7] & 4294967295)) * ((uint64_t)(context->gpr[13] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_1101_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[13]) - ((uint64_t)context->gpr[7]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_1101_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[7]) >= ((int32_t)context->gpr[13])) {
	if (context->gpr[7] == context->gpr[13]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_1101_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[7] = context->gpr[7] - context->gpr[13];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_1101_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[7]) - ((uint64_t)context->gpr[13]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[7] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_1101_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[7] - context->gpr[13];
	context->t = (((context->gpr[7] ^ context->gpr[13])) & (context->gpr[7] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[7] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_1101_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[7] = context->gpr[13] + context->gpr[7];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_1101_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[7])) * ((int64_t)((int32_t)context->gpr[13])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_1101_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[13]) + ((uint64_t)context->gpr[7]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[7] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_1101_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[13] + context->gpr[7];
	context->t = (((context->gpr[13] ^ (~context->gpr[7]))) & (context->gpr[13] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[7] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_1110_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[7] - context->gpr[14];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_1110_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[7] >= context->gpr[14]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_1110_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[7]) >= ((int32_t)context->gpr[14])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_1110_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[7]) << 1 | ((uint64_t)context->gpr[7]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[7] >> 24 & 128U;
	context->gpr[7] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[7]) - ((uint64_t)context->gpr[14]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[7] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[14]) + ((uint64_t)context->gpr[7]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[7] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_1110_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[7] & 4294967295)) * ((uint64_t)(context->gpr[14] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_1110_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[14]) - ((uint64_t)context->gpr[7]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_1110_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[7]) >= ((int32_t)context->gpr[14])) {
	if (context->gpr[7] == context->gpr[14]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_1110_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[7] = context->gpr[7] - context->gpr[14];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_1110_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[7]) - ((uint64_t)context->gpr[14]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[7] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_1110_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[7] - context->gpr[14];
	context->t = (((context->gpr[7] ^ context->gpr[14])) & (context->gpr[7] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[7] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_1110_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[7] = context->gpr[14] + context->gpr[7];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_1110_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[7])) * ((int64_t)((int32_t)context->gpr[14])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_1110_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[14]) + ((uint64_t)context->gpr[7]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[7] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_1110_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[14] + context->gpr[7];
	context->t = (((context->gpr[14] ^ (~context->gpr[7]))) & (context->gpr[14] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[7] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_1111_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[7] - context->gpr[15];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_1111_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[7] >= context->gpr[15]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_1111_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[7]) >= ((int32_t)context->gpr[15])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_1111_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[7]) << 1 | ((uint64_t)context->gpr[7]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[7] >> 24 & 128U;
	context->gpr[7] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[7]) - ((uint64_t)context->gpr[15]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[7] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[15]) + ((uint64_t)context->gpr[7]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[7] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_1111_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[7] & 4294967295)) * ((uint64_t)(context->gpr[15] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_1111_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[15]) - ((uint64_t)context->gpr[7]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_1111_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[7]) >= ((int32_t)context->gpr[15])) {
	if (context->gpr[7] == context->gpr[15]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_1111_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[7] = context->gpr[7] - context->gpr[15];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_1111_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[7]) - ((uint64_t)context->gpr[15]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[7] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_1111_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[7] - context->gpr[15];
	context->t = (((context->gpr[7] ^ context->gpr[15])) & (context->gpr[7] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[7] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_1111_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[7] = context->gpr[15] + context->gpr[7];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_1111_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[7])) * ((int64_t)((int32_t)context->gpr[15])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_1111_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[15]) + ((uint64_t)context->gpr[7]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[7] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_1111_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[15] + context->gpr[7];
	context->t = (((context->gpr[15] ^ (~context->gpr[7]))) & (context->gpr[15] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[7] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_0000_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[8] - context->gpr[0];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_0000_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[8] >= context->gpr[0]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_0000_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[8]) >= ((int32_t)context->gpr[0])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_0000_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[8]) << 1 | ((uint64_t)context->gpr[8]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[8] >> 24 & 128U;
	context->gpr[8] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[8]) - ((uint64_t)context->gpr[0]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[8] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[0]) + ((uint64_t)context->gpr[8]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[8] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_0000_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[8] & 4294967295)) * ((uint64_t)(context->gpr[0] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_0000_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[0]) - ((uint64_t)context->gpr[8]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_0000_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[8]) >= ((int32_t)context->gpr[0])) {
	if (context->gpr[8] == context->gpr[0]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_0000_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[8] = context->gpr[8] - context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_0000_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[8]) - ((uint64_t)context->gpr[0]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[8] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_0000_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[8] - context->gpr[0];
	context->t = (((context->gpr[8] ^ context->gpr[0])) & (context->gpr[8] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[8] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_0000_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[8] = context->gpr[0] + context->gpr[8];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_0000_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[8])) * ((int64_t)((int32_t)context->gpr[0])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_0000_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[0]) + ((uint64_t)context->gpr[8]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[8] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_0000_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[0] + context->gpr[8];
	context->t = (((context->gpr[0] ^ (~context->gpr[8]))) & (context->gpr[0] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[8] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_0001_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[8] - context->gpr[1];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_0001_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[8] >= context->gpr[1]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_0001_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[8]) >= ((int32_t)context->gpr[1])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_0001_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[8]) << 1 | ((uint64_t)context->gpr[8]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[8] >> 24 & 128U;
	context->gpr[8] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[8]) - ((uint64_t)context->gpr[1]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[8] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[1]) + ((uint64_t)context->gpr[8]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[8] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_0001_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[8] & 4294967295)) * ((uint64_t)(context->gpr[1] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_0001_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[1]) - ((uint64_t)context->gpr[8]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_0001_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[8]) >= ((int32_t)context->gpr[1])) {
	if (context->gpr[8] == context->gpr[1]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_0001_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[8] = context->gpr[8] - context->gpr[1];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_0001_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[8]) - ((uint64_t)context->gpr[1]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[8] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_0001_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[8] - context->gpr[1];
	context->t = (((context->gpr[8] ^ context->gpr[1])) & (context->gpr[8] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[8] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_0001_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[8] = context->gpr[1] + context->gpr[8];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_0001_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[8])) * ((int64_t)((int32_t)context->gpr[1])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_0001_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[1]) + ((uint64_t)context->gpr[8]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[8] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_0001_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[1] + context->gpr[8];
	context->t = (((context->gpr[1] ^ (~context->gpr[8]))) & (context->gpr[1] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[8] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_0010_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[8] - context->gpr[2];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_0010_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[8] >= context->gpr[2]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_0010_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[8]) >= ((int32_t)context->gpr[2])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_0010_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[8]) << 1 | ((uint64_t)context->gpr[8]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[8] >> 24 & 128U;
	context->gpr[8] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[8]) - ((uint64_t)context->gpr[2]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[8] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[2]) + ((uint64_t)context->gpr[8]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[8] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_0010_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[8] & 4294967295)) * ((uint64_t)(context->gpr[2] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_0010_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[2]) - ((uint64_t)context->gpr[8]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_0010_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[8]) >= ((int32_t)context->gpr[2])) {
	if (context->gpr[8] == context->gpr[2]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_0010_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[8] = context->gpr[8] - context->gpr[2];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_0010_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[8]) - ((uint64_t)context->gpr[2]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[8] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_0010_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[8] - context->gpr[2];
	context->t = (((context->gpr[8] ^ context->gpr[2])) & (context->gpr[8] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[8] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_0010_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[8] = context->gpr[2] + context->gpr[8];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_0010_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[8])) * ((int64_t)((int32_t)context->gpr[2])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_0010_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[2]) + ((uint64_t)context->gpr[8]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[8] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_0010_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[2] + context->gpr[8];
	context->t = (((context->gpr[2] ^ (~context->gpr[8]))) & (context->gpr[2] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[8] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_0011_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[8] - context->gpr[3];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_0011_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[8] >= context->gpr[3]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_0011_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[8]) >= ((int32_t)context->gpr[3])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_0011_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[8]) << 1 | ((uint64_t)context->gpr[8]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[8] >> 24 & 128U;
	context->gpr[8] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[8]) - ((uint64_t)context->gpr[3]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[8] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[3]) + ((uint64_t)context->gpr[8]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[8] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_0011_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[8] & 4294967295)) * ((uint64_t)(context->gpr[3] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_0011_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[3]) - ((uint64_t)context->gpr[8]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_0011_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[8]) >= ((int32_t)context->gpr[3])) {
	if (context->gpr[8] == context->gpr[3]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_0011_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[8] = context->gpr[8] - context->gpr[3];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_0011_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[8]) - ((uint64_t)context->gpr[3]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[8] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_0011_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[8] - context->gpr[3];
	context->t = (((context->gpr[8] ^ context->gpr[3])) & (context->gpr[8] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[8] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_0011_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[8] = context->gpr[3] + context->gpr[8];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_0011_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[8])) * ((int64_t)((int32_t)context->gpr[3])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_0011_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[3]) + ((uint64_t)context->gpr[8]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[8] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_0011_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[3] + context->gpr[8];
	context->t = (((context->gpr[3] ^ (~context->gpr[8]))) & (context->gpr[3] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[8] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_0100_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[8] - context->gpr[4];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_0100_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[8] >= context->gpr[4]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_0100_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[8]) >= ((int32_t)context->gpr[4])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_0100_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[8]) << 1 | ((uint64_t)context->gpr[8]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[8] >> 24 & 128U;
	context->gpr[8] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[8]) - ((uint64_t)context->gpr[4]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[8] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[4]) + ((uint64_t)context->gpr[8]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[8] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_0100_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[8] & 4294967295)) * ((uint64_t)(context->gpr[4] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_0100_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[4]) - ((uint64_t)context->gpr[8]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_0100_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[8]) >= ((int32_t)context->gpr[4])) {
	if (context->gpr[8] == context->gpr[4]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_0100_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[8] = context->gpr[8] - context->gpr[4];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_0100_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[8]) - ((uint64_t)context->gpr[4]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[8] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_0100_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[8] - context->gpr[4];
	context->t = (((context->gpr[8] ^ context->gpr[4])) & (context->gpr[8] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[8] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_0100_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[8] = context->gpr[4] + context->gpr[8];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_0100_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[8])) * ((int64_t)((int32_t)context->gpr[4])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_0100_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[4]) + ((uint64_t)context->gpr[8]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[8] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_0100_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[4] + context->gpr[8];
	context->t = (((context->gpr[4] ^ (~context->gpr[8]))) & (context->gpr[4] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[8] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_0101_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[8] - context->gpr[5];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_0101_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[8] >= context->gpr[5]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_0101_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[8]) >= ((int32_t)context->gpr[5])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_0101_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[8]) << 1 | ((uint64_t)context->gpr[8]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[8] >> 24 & 128U;
	context->gpr[8] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[8]) - ((uint64_t)context->gpr[5]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[8] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[5]) + ((uint64_t)context->gpr[8]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[8] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_0101_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[8] & 4294967295)) * ((uint64_t)(context->gpr[5] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_0101_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[5]) - ((uint64_t)context->gpr[8]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_0101_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[8]) >= ((int32_t)context->gpr[5])) {
	if (context->gpr[8] == context->gpr[5]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_0101_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[8] = context->gpr[8] - context->gpr[5];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_0101_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[8]) - ((uint64_t)context->gpr[5]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[8] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_0101_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[8] - context->gpr[5];
	context->t = (((context->gpr[8] ^ context->gpr[5])) & (context->gpr[8] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[8] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_0101_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[8] = context->gpr[5] + context->gpr[8];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_0101_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[8])) * ((int64_t)((int32_t)context->gpr[5])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_0101_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[5]) + ((uint64_t)context->gpr[8]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[8] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_0101_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[5] + context->gpr[8];
	context->t = (((context->gpr[5] ^ (~context->gpr[8]))) & (context->gpr[5] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[8] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_0110_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[8] - context->gpr[6];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_0110_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[8] >= context->gpr[6]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_0110_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[8]) >= ((int32_t)context->gpr[6])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_0110_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[8]) << 1 | ((uint64_t)context->gpr[8]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[8] >> 24 & 128U;
	context->gpr[8] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[8]) - ((uint64_t)context->gpr[6]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[8] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[6]) + ((uint64_t)context->gpr[8]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[8] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_0110_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[8] & 4294967295)) * ((uint64_t)(context->gpr[6] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_0110_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[6]) - ((uint64_t)context->gpr[8]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_0110_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[8]) >= ((int32_t)context->gpr[6])) {
	if (context->gpr[8] == context->gpr[6]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_0110_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[8] = context->gpr[8] - context->gpr[6];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_0110_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[8]) - ((uint64_t)context->gpr[6]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[8] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_0110_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[8] - context->gpr[6];
	context->t = (((context->gpr[8] ^ context->gpr[6])) & (context->gpr[8] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[8] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_0110_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[8] = context->gpr[6] + context->gpr[8];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_0110_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[8])) * ((int64_t)((int32_t)context->gpr[6])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_0110_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[6]) + ((uint64_t)context->gpr[8]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[8] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_0110_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[6] + context->gpr[8];
	context->t = (((context->gpr[6] ^ (~context->gpr[8]))) & (context->gpr[6] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[8] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_0111_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[8] - context->gpr[7];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_0111_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[8] >= context->gpr[7]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_0111_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[8]) >= ((int32_t)context->gpr[7])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_0111_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[8]) << 1 | ((uint64_t)context->gpr[8]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[8] >> 24 & 128U;
	context->gpr[8] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[8]) - ((uint64_t)context->gpr[7]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[8] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[7]) + ((uint64_t)context->gpr[8]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[8] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_0111_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[8] & 4294967295)) * ((uint64_t)(context->gpr[7] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_0111_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[7]) - ((uint64_t)context->gpr[8]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_0111_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[8]) >= ((int32_t)context->gpr[7])) {
	if (context->gpr[8] == context->gpr[7]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_0111_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[8] = context->gpr[8] - context->gpr[7];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_0111_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[8]) - ((uint64_t)context->gpr[7]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[8] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_0111_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[8] - context->gpr[7];
	context->t = (((context->gpr[8] ^ context->gpr[7])) & (context->gpr[8] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[8] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_0111_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[8] = context->gpr[7] + context->gpr[8];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_0111_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[8])) * ((int64_t)((int32_t)context->gpr[7])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_0111_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[7]) + ((uint64_t)context->gpr[8]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[8] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_0111_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[7] + context->gpr[8];
	context->t = (((context->gpr[7] ^ (~context->gpr[8]))) & (context->gpr[7] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[8] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_1000_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[8] - context->gpr[8];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_1000_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[8] >= context->gpr[8]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_1000_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[8]) >= ((int32_t)context->gpr[8])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_1000_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[8]) << 1 | ((uint64_t)context->gpr[8]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[8] >> 24 & 128U;
	context->gpr[8] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[8]) - ((uint64_t)context->gpr[8]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[8] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[8]) + ((uint64_t)context->gpr[8]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[8] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_1000_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[8] & 4294967295)) * ((uint64_t)(context->gpr[8] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_1000_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[8]) - ((uint64_t)context->gpr[8]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_1000_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[8]) >= ((int32_t)context->gpr[8])) {
	if (context->gpr[8] == context->gpr[8]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_1000_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[8] = context->gpr[8] - context->gpr[8];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_1000_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[8]) - ((uint64_t)context->gpr[8]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[8] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_1000_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[8] - context->gpr[8];
	context->t = (((context->gpr[8] ^ context->gpr[8])) & (context->gpr[8] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[8] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_1000_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[8] = context->gpr[8] + context->gpr[8];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_1000_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[8])) * ((int64_t)((int32_t)context->gpr[8])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_1000_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[8]) + ((uint64_t)context->gpr[8]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[8] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_1000_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[8] + context->gpr[8];
	context->t = (((context->gpr[8] ^ (~context->gpr[8]))) & (context->gpr[8] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[8] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_1001_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[8] - context->gpr[9];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_1001_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[8] >= context->gpr[9]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_1001_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[8]) >= ((int32_t)context->gpr[9])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_1001_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[8]) << 1 | ((uint64_t)context->gpr[8]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[8] >> 24 & 128U;
	context->gpr[8] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[8]) - ((uint64_t)context->gpr[9]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[8] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[9]) + ((uint64_t)context->gpr[8]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[8] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_1001_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[8] & 4294967295)) * ((uint64_t)(context->gpr[9] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_1001_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[9]) - ((uint64_t)context->gpr[8]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_1001_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[8]) >= ((int32_t)context->gpr[9])) {
	if (context->gpr[8] == context->gpr[9]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_1001_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[8] = context->gpr[8] - context->gpr[9];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_1001_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[8]) - ((uint64_t)context->gpr[9]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[8] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_1001_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[8] - context->gpr[9];
	context->t = (((context->gpr[8] ^ context->gpr[9])) & (context->gpr[8] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[8] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_1001_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[8] = context->gpr[9] + context->gpr[8];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_1001_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[8])) * ((int64_t)((int32_t)context->gpr[9])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_1001_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[9]) + ((uint64_t)context->gpr[8]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[8] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_1001_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[9] + context->gpr[8];
	context->t = (((context->gpr[9] ^ (~context->gpr[8]))) & (context->gpr[9] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[8] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_1010_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[8] - context->gpr[10];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_1010_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[8] >= context->gpr[10]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_1010_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[8]) >= ((int32_t)context->gpr[10])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_1010_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[8]) << 1 | ((uint64_t)context->gpr[8]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[8] >> 24 & 128U;
	context->gpr[8] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[8]) - ((uint64_t)context->gpr[10]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[8] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[10]) + ((uint64_t)context->gpr[8]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[8] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_1010_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[8] & 4294967295)) * ((uint64_t)(context->gpr[10] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_1010_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[10]) - ((uint64_t)context->gpr[8]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_1010_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[8]) >= ((int32_t)context->gpr[10])) {
	if (context->gpr[8] == context->gpr[10]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_1010_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[8] = context->gpr[8] - context->gpr[10];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_1010_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[8]) - ((uint64_t)context->gpr[10]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[8] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_1010_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[8] - context->gpr[10];
	context->t = (((context->gpr[8] ^ context->gpr[10])) & (context->gpr[8] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[8] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_1010_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[8] = context->gpr[10] + context->gpr[8];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_1010_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[8])) * ((int64_t)((int32_t)context->gpr[10])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_1010_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[10]) + ((uint64_t)context->gpr[8]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[8] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_1010_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[10] + context->gpr[8];
	context->t = (((context->gpr[10] ^ (~context->gpr[8]))) & (context->gpr[10] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[8] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_1011_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[8] - context->gpr[11];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_1011_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[8] >= context->gpr[11]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_1011_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[8]) >= ((int32_t)context->gpr[11])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_1011_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[8]) << 1 | ((uint64_t)context->gpr[8]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[8] >> 24 & 128U;
	context->gpr[8] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[8]) - ((uint64_t)context->gpr[11]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[8] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[11]) + ((uint64_t)context->gpr[8]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[8] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_1011_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[8] & 4294967295)) * ((uint64_t)(context->gpr[11] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_1011_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[11]) - ((uint64_t)context->gpr[8]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_1011_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[8]) >= ((int32_t)context->gpr[11])) {
	if (context->gpr[8] == context->gpr[11]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_1011_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[8] = context->gpr[8] - context->gpr[11];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_1011_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[8]) - ((uint64_t)context->gpr[11]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[8] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_1011_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[8] - context->gpr[11];
	context->t = (((context->gpr[8] ^ context->gpr[11])) & (context->gpr[8] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[8] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_1011_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[8] = context->gpr[11] + context->gpr[8];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_1011_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[8])) * ((int64_t)((int32_t)context->gpr[11])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_1011_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[11]) + ((uint64_t)context->gpr[8]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[8] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_1011_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[11] + context->gpr[8];
	context->t = (((context->gpr[11] ^ (~context->gpr[8]))) & (context->gpr[11] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[8] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_1100_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[8] - context->gpr[12];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_1100_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[8] >= context->gpr[12]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_1100_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[8]) >= ((int32_t)context->gpr[12])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_1100_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[8]) << 1 | ((uint64_t)context->gpr[8]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[8] >> 24 & 128U;
	context->gpr[8] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[8]) - ((uint64_t)context->gpr[12]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[8] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[12]) + ((uint64_t)context->gpr[8]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[8] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_1100_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[8] & 4294967295)) * ((uint64_t)(context->gpr[12] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_1100_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[12]) - ((uint64_t)context->gpr[8]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_1100_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[8]) >= ((int32_t)context->gpr[12])) {
	if (context->gpr[8] == context->gpr[12]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_1100_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[8] = context->gpr[8] - context->gpr[12];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_1100_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[8]) - ((uint64_t)context->gpr[12]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[8] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_1100_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[8] - context->gpr[12];
	context->t = (((context->gpr[8] ^ context->gpr[12])) & (context->gpr[8] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[8] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_1100_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[8] = context->gpr[12] + context->gpr[8];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_1100_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[8])) * ((int64_t)((int32_t)context->gpr[12])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_1100_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[12]) + ((uint64_t)context->gpr[8]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[8] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_1100_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[12] + context->gpr[8];
	context->t = (((context->gpr[12] ^ (~context->gpr[8]))) & (context->gpr[12] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[8] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_1101_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[8] - context->gpr[13];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_1101_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[8] >= context->gpr[13]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_1101_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[8]) >= ((int32_t)context->gpr[13])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_1101_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[8]) << 1 | ((uint64_t)context->gpr[8]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[8] >> 24 & 128U;
	context->gpr[8] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[8]) - ((uint64_t)context->gpr[13]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[8] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[13]) + ((uint64_t)context->gpr[8]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[8] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_1101_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[8] & 4294967295)) * ((uint64_t)(context->gpr[13] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_1101_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[13]) - ((uint64_t)context->gpr[8]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_1101_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[8]) >= ((int32_t)context->gpr[13])) {
	if (context->gpr[8] == context->gpr[13]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_1101_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[8] = context->gpr[8] - context->gpr[13];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_1101_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[8]) - ((uint64_t)context->gpr[13]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[8] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_1101_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[8] - context->gpr[13];
	context->t = (((context->gpr[8] ^ context->gpr[13])) & (context->gpr[8] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[8] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_1101_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[8] = context->gpr[13] + context->gpr[8];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_1101_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[8])) * ((int64_t)((int32_t)context->gpr[13])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_1101_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[13]) + ((uint64_t)context->gpr[8]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[8] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_1101_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[13] + context->gpr[8];
	context->t = (((context->gpr[13] ^ (~context->gpr[8]))) & (context->gpr[13] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[8] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_1110_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[8] - context->gpr[14];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_1110_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[8] >= context->gpr[14]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_1110_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[8]) >= ((int32_t)context->gpr[14])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_1110_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[8]) << 1 | ((uint64_t)context->gpr[8]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[8] >> 24 & 128U;
	context->gpr[8] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[8]) - ((uint64_t)context->gpr[14]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[8] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[14]) + ((uint64_t)context->gpr[8]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[8] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_1110_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[8] & 4294967295)) * ((uint64_t)(context->gpr[14] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_1110_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[14]) - ((uint64_t)context->gpr[8]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_1110_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[8]) >= ((int32_t)context->gpr[14])) {
	if (context->gpr[8] == context->gpr[14]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_1110_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[8] = context->gpr[8] - context->gpr[14];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_1110_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[8]) - ((uint64_t)context->gpr[14]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[8] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_1110_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[8] - context->gpr[14];
	context->t = (((context->gpr[8] ^ context->gpr[14])) & (context->gpr[8] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[8] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_1110_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[8] = context->gpr[14] + context->gpr[8];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_1110_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[8])) * ((int64_t)((int32_t)context->gpr[14])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_1110_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[14]) + ((uint64_t)context->gpr[8]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[8] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_1110_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[14] + context->gpr[8];
	context->t = (((context->gpr[14] ^ (~context->gpr[8]))) & (context->gpr[14] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[8] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_1111_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[8] - context->gpr[15];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_1111_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[8] >= context->gpr[15]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_1111_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[8]) >= ((int32_t)context->gpr[15])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_1111_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[8]) << 1 | ((uint64_t)context->gpr[8]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[8] >> 24 & 128U;
	context->gpr[8] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[8]) - ((uint64_t)context->gpr[15]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[8] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[15]) + ((uint64_t)context->gpr[8]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[8] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_1111_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[8] & 4294967295)) * ((uint64_t)(context->gpr[15] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_1111_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[15]) - ((uint64_t)context->gpr[8]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_1111_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[8]) >= ((int32_t)context->gpr[15])) {
	if (context->gpr[8] == context->gpr[15]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_1111_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[8] = context->gpr[8] - context->gpr[15];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_1111_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[8]) - ((uint64_t)context->gpr[15]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[8] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_1111_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[8] - context->gpr[15];
	context->t = (((context->gpr[8] ^ context->gpr[15])) & (context->gpr[8] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[8] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_1111_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[8] = context->gpr[15] + context->gpr[8];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_1111_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[8])) * ((int64_t)((int32_t)context->gpr[15])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_1111_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[15]) + ((uint64_t)context->gpr[8]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[8] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_1111_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[15] + context->gpr[8];
	context->t = (((context->gpr[15] ^ (~context->gpr[8]))) & (context->gpr[15] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[8] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_0000_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[9] - context->gpr[0];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_0000_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[9] >= context->gpr[0]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_0000_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[9]) >= ((int32_t)context->gpr[0])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_0000_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[9]) << 1 | ((uint64_t)context->gpr[9]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[9] >> 24 & 128U;
	context->gpr[9] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[9]) - ((uint64_t)context->gpr[0]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[9] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[0]) + ((uint64_t)context->gpr[9]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[9] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_0000_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[9] & 4294967295)) * ((uint64_t)(context->gpr[0] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_0000_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[0]) - ((uint64_t)context->gpr[9]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_0000_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[9]) >= ((int32_t)context->gpr[0])) {
	if (context->gpr[9] == context->gpr[0]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_0000_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[9] = context->gpr[9] - context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_0000_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[9]) - ((uint64_t)context->gpr[0]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[9] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_0000_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[9] - context->gpr[0];
	context->t = (((context->gpr[9] ^ context->gpr[0])) & (context->gpr[9] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[9] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_0000_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[9] = context->gpr[0] + context->gpr[9];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_0000_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[9])) * ((int64_t)((int32_t)context->gpr[0])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_0000_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[0]) + ((uint64_t)context->gpr[9]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[9] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_0000_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[0] + context->gpr[9];
	context->t = (((context->gpr[0] ^ (~context->gpr[9]))) & (context->gpr[0] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[9] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_0001_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[9] - context->gpr[1];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_0001_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[9] >= context->gpr[1]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_0001_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[9]) >= ((int32_t)context->gpr[1])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_0001_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[9]) << 1 | ((uint64_t)context->gpr[9]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[9] >> 24 & 128U;
	context->gpr[9] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[9]) - ((uint64_t)context->gpr[1]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[9] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[1]) + ((uint64_t)context->gpr[9]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[9] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_0001_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[9] & 4294967295)) * ((uint64_t)(context->gpr[1] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_0001_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[1]) - ((uint64_t)context->gpr[9]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_0001_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[9]) >= ((int32_t)context->gpr[1])) {
	if (context->gpr[9] == context->gpr[1]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_0001_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[9] = context->gpr[9] - context->gpr[1];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_0001_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[9]) - ((uint64_t)context->gpr[1]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[9] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_0001_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[9] - context->gpr[1];
	context->t = (((context->gpr[9] ^ context->gpr[1])) & (context->gpr[9] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[9] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_0001_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[9] = context->gpr[1] + context->gpr[9];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_0001_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[9])) * ((int64_t)((int32_t)context->gpr[1])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_0001_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[1]) + ((uint64_t)context->gpr[9]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[9] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_0001_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[1] + context->gpr[9];
	context->t = (((context->gpr[1] ^ (~context->gpr[9]))) & (context->gpr[1] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[9] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_0010_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[9] - context->gpr[2];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_0010_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[9] >= context->gpr[2]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_0010_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[9]) >= ((int32_t)context->gpr[2])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_0010_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[9]) << 1 | ((uint64_t)context->gpr[9]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[9] >> 24 & 128U;
	context->gpr[9] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[9]) - ((uint64_t)context->gpr[2]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[9] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[2]) + ((uint64_t)context->gpr[9]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[9] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_0010_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[9] & 4294967295)) * ((uint64_t)(context->gpr[2] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_0010_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[2]) - ((uint64_t)context->gpr[9]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_0010_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[9]) >= ((int32_t)context->gpr[2])) {
	if (context->gpr[9] == context->gpr[2]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_0010_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[9] = context->gpr[9] - context->gpr[2];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_0010_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[9]) - ((uint64_t)context->gpr[2]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[9] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_0010_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[9] - context->gpr[2];
	context->t = (((context->gpr[9] ^ context->gpr[2])) & (context->gpr[9] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[9] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_0010_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[9] = context->gpr[2] + context->gpr[9];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_0010_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[9])) * ((int64_t)((int32_t)context->gpr[2])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_0010_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[2]) + ((uint64_t)context->gpr[9]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[9] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_0010_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[2] + context->gpr[9];
	context->t = (((context->gpr[2] ^ (~context->gpr[9]))) & (context->gpr[2] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[9] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_0011_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[9] - context->gpr[3];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_0011_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[9] >= context->gpr[3]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_0011_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[9]) >= ((int32_t)context->gpr[3])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_0011_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[9]) << 1 | ((uint64_t)context->gpr[9]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[9] >> 24 & 128U;
	context->gpr[9] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[9]) - ((uint64_t)context->gpr[3]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[9] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[3]) + ((uint64_t)context->gpr[9]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[9] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_0011_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[9] & 4294967295)) * ((uint64_t)(context->gpr[3] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_0011_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[3]) - ((uint64_t)context->gpr[9]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_0011_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[9]) >= ((int32_t)context->gpr[3])) {
	if (context->gpr[9] == context->gpr[3]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_0011_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[9] = context->gpr[9] - context->gpr[3];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_0011_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[9]) - ((uint64_t)context->gpr[3]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[9] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_0011_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[9] - context->gpr[3];
	context->t = (((context->gpr[9] ^ context->gpr[3])) & (context->gpr[9] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[9] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_0011_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[9] = context->gpr[3] + context->gpr[9];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_0011_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[9])) * ((int64_t)((int32_t)context->gpr[3])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_0011_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[3]) + ((uint64_t)context->gpr[9]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[9] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_0011_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[3] + context->gpr[9];
	context->t = (((context->gpr[3] ^ (~context->gpr[9]))) & (context->gpr[3] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[9] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_0100_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[9] - context->gpr[4];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_0100_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[9] >= context->gpr[4]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_0100_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[9]) >= ((int32_t)context->gpr[4])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_0100_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[9]) << 1 | ((uint64_t)context->gpr[9]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[9] >> 24 & 128U;
	context->gpr[9] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[9]) - ((uint64_t)context->gpr[4]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[9] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[4]) + ((uint64_t)context->gpr[9]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[9] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_0100_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[9] & 4294967295)) * ((uint64_t)(context->gpr[4] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_0100_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[4]) - ((uint64_t)context->gpr[9]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_0100_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[9]) >= ((int32_t)context->gpr[4])) {
	if (context->gpr[9] == context->gpr[4]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_0100_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[9] = context->gpr[9] - context->gpr[4];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_0100_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[9]) - ((uint64_t)context->gpr[4]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[9] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_0100_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[9] - context->gpr[4];
	context->t = (((context->gpr[9] ^ context->gpr[4])) & (context->gpr[9] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[9] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_0100_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[9] = context->gpr[4] + context->gpr[9];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_0100_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[9])) * ((int64_t)((int32_t)context->gpr[4])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_0100_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[4]) + ((uint64_t)context->gpr[9]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[9] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_0100_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[4] + context->gpr[9];
	context->t = (((context->gpr[4] ^ (~context->gpr[9]))) & (context->gpr[4] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[9] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_0101_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[9] - context->gpr[5];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_0101_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[9] >= context->gpr[5]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_0101_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[9]) >= ((int32_t)context->gpr[5])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_0101_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[9]) << 1 | ((uint64_t)context->gpr[9]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[9] >> 24 & 128U;
	context->gpr[9] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[9]) - ((uint64_t)context->gpr[5]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[9] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[5]) + ((uint64_t)context->gpr[9]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[9] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_0101_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[9] & 4294967295)) * ((uint64_t)(context->gpr[5] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_0101_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[5]) - ((uint64_t)context->gpr[9]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_0101_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[9]) >= ((int32_t)context->gpr[5])) {
	if (context->gpr[9] == context->gpr[5]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_0101_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[9] = context->gpr[9] - context->gpr[5];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_0101_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[9]) - ((uint64_t)context->gpr[5]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[9] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_0101_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[9] - context->gpr[5];
	context->t = (((context->gpr[9] ^ context->gpr[5])) & (context->gpr[9] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[9] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_0101_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[9] = context->gpr[5] + context->gpr[9];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_0101_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[9])) * ((int64_t)((int32_t)context->gpr[5])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_0101_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[5]) + ((uint64_t)context->gpr[9]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[9] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_0101_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[5] + context->gpr[9];
	context->t = (((context->gpr[5] ^ (~context->gpr[9]))) & (context->gpr[5] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[9] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_0110_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[9] - context->gpr[6];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_0110_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[9] >= context->gpr[6]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_0110_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[9]) >= ((int32_t)context->gpr[6])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_0110_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[9]) << 1 | ((uint64_t)context->gpr[9]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[9] >> 24 & 128U;
	context->gpr[9] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[9]) - ((uint64_t)context->gpr[6]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[9] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[6]) + ((uint64_t)context->gpr[9]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[9] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_0110_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[9] & 4294967295)) * ((uint64_t)(context->gpr[6] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_0110_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[6]) - ((uint64_t)context->gpr[9]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_0110_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[9]) >= ((int32_t)context->gpr[6])) {
	if (context->gpr[9] == context->gpr[6]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_0110_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[9] = context->gpr[9] - context->gpr[6];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_0110_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[9]) - ((uint64_t)context->gpr[6]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[9] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_0110_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[9] - context->gpr[6];
	context->t = (((context->gpr[9] ^ context->gpr[6])) & (context->gpr[9] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[9] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_0110_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[9] = context->gpr[6] + context->gpr[9];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_0110_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[9])) * ((int64_t)((int32_t)context->gpr[6])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_0110_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[6]) + ((uint64_t)context->gpr[9]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[9] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_0110_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[6] + context->gpr[9];
	context->t = (((context->gpr[6] ^ (~context->gpr[9]))) & (context->gpr[6] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[9] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_0111_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[9] - context->gpr[7];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_0111_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[9] >= context->gpr[7]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_0111_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[9]) >= ((int32_t)context->gpr[7])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_0111_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[9]) << 1 | ((uint64_t)context->gpr[9]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[9] >> 24 & 128U;
	context->gpr[9] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[9]) - ((uint64_t)context->gpr[7]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[9] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[7]) + ((uint64_t)context->gpr[9]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[9] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_0111_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[9] & 4294967295)) * ((uint64_t)(context->gpr[7] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_0111_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[7]) - ((uint64_t)context->gpr[9]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_0111_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[9]) >= ((int32_t)context->gpr[7])) {
	if (context->gpr[9] == context->gpr[7]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_0111_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[9] = context->gpr[9] - context->gpr[7];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_0111_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[9]) - ((uint64_t)context->gpr[7]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[9] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_0111_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[9] - context->gpr[7];
	context->t = (((context->gpr[9] ^ context->gpr[7])) & (context->gpr[9] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[9] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_0111_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[9] = context->gpr[7] + context->gpr[9];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_0111_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[9])) * ((int64_t)((int32_t)context->gpr[7])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_0111_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[7]) + ((uint64_t)context->gpr[9]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[9] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_0111_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[7] + context->gpr[9];
	context->t = (((context->gpr[7] ^ (~context->gpr[9]))) & (context->gpr[7] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[9] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_1000_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[9] - context->gpr[8];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_1000_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[9] >= context->gpr[8]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_1000_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[9]) >= ((int32_t)context->gpr[8])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_1000_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[9]) << 1 | ((uint64_t)context->gpr[9]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[9] >> 24 & 128U;
	context->gpr[9] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[9]) - ((uint64_t)context->gpr[8]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[9] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[8]) + ((uint64_t)context->gpr[9]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[9] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_1000_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[9] & 4294967295)) * ((uint64_t)(context->gpr[8] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_1000_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[8]) - ((uint64_t)context->gpr[9]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_1000_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[9]) >= ((int32_t)context->gpr[8])) {
	if (context->gpr[9] == context->gpr[8]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_1000_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[9] = context->gpr[9] - context->gpr[8];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_1000_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[9]) - ((uint64_t)context->gpr[8]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[9] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_1000_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[9] - context->gpr[8];
	context->t = (((context->gpr[9] ^ context->gpr[8])) & (context->gpr[9] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[9] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_1000_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[9] = context->gpr[8] + context->gpr[9];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_1000_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[9])) * ((int64_t)((int32_t)context->gpr[8])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_1000_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[8]) + ((uint64_t)context->gpr[9]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[9] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_1000_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[8] + context->gpr[9];
	context->t = (((context->gpr[8] ^ (~context->gpr[9]))) & (context->gpr[8] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[9] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_1001_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[9] - context->gpr[9];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_1001_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[9] >= context->gpr[9]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_1001_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[9]) >= ((int32_t)context->gpr[9])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_1001_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[9]) << 1 | ((uint64_t)context->gpr[9]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[9] >> 24 & 128U;
	context->gpr[9] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[9]) - ((uint64_t)context->gpr[9]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[9] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[9]) + ((uint64_t)context->gpr[9]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[9] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_1001_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[9] & 4294967295)) * ((uint64_t)(context->gpr[9] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_1001_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[9]) - ((uint64_t)context->gpr[9]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_1001_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[9]) >= ((int32_t)context->gpr[9])) {
	if (context->gpr[9] == context->gpr[9]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_1001_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[9] = context->gpr[9] - context->gpr[9];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_1001_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[9]) - ((uint64_t)context->gpr[9]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[9] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_1001_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[9] - context->gpr[9];
	context->t = (((context->gpr[9] ^ context->gpr[9])) & (context->gpr[9] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[9] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_1001_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[9] = context->gpr[9] + context->gpr[9];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_1001_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[9])) * ((int64_t)((int32_t)context->gpr[9])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_1001_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[9]) + ((uint64_t)context->gpr[9]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[9] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_1001_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[9] + context->gpr[9];
	context->t = (((context->gpr[9] ^ (~context->gpr[9]))) & (context->gpr[9] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[9] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_1010_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[9] - context->gpr[10];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_1010_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[9] >= context->gpr[10]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_1010_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[9]) >= ((int32_t)context->gpr[10])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_1010_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[9]) << 1 | ((uint64_t)context->gpr[9]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[9] >> 24 & 128U;
	context->gpr[9] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[9]) - ((uint64_t)context->gpr[10]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[9] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[10]) + ((uint64_t)context->gpr[9]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[9] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_1010_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[9] & 4294967295)) * ((uint64_t)(context->gpr[10] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_1010_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[10]) - ((uint64_t)context->gpr[9]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_1010_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[9]) >= ((int32_t)context->gpr[10])) {
	if (context->gpr[9] == context->gpr[10]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_1010_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[9] = context->gpr[9] - context->gpr[10];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_1010_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[9]) - ((uint64_t)context->gpr[10]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[9] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_1010_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[9] - context->gpr[10];
	context->t = (((context->gpr[9] ^ context->gpr[10])) & (context->gpr[9] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[9] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_1010_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[9] = context->gpr[10] + context->gpr[9];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_1010_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[9])) * ((int64_t)((int32_t)context->gpr[10])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_1010_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[10]) + ((uint64_t)context->gpr[9]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[9] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_1010_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[10] + context->gpr[9];
	context->t = (((context->gpr[10] ^ (~context->gpr[9]))) & (context->gpr[10] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[9] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_1011_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[9] - context->gpr[11];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_1011_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[9] >= context->gpr[11]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_1011_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[9]) >= ((int32_t)context->gpr[11])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_1011_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[9]) << 1 | ((uint64_t)context->gpr[9]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[9] >> 24 & 128U;
	context->gpr[9] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[9]) - ((uint64_t)context->gpr[11]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[9] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[11]) + ((uint64_t)context->gpr[9]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[9] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_1011_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[9] & 4294967295)) * ((uint64_t)(context->gpr[11] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_1011_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[11]) - ((uint64_t)context->gpr[9]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_1011_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[9]) >= ((int32_t)context->gpr[11])) {
	if (context->gpr[9] == context->gpr[11]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_1011_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[9] = context->gpr[9] - context->gpr[11];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_1011_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[9]) - ((uint64_t)context->gpr[11]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[9] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_1011_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[9] - context->gpr[11];
	context->t = (((context->gpr[9] ^ context->gpr[11])) & (context->gpr[9] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[9] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_1011_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[9] = context->gpr[11] + context->gpr[9];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_1011_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[9])) * ((int64_t)((int32_t)context->gpr[11])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_1011_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[11]) + ((uint64_t)context->gpr[9]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[9] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_1011_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[11] + context->gpr[9];
	context->t = (((context->gpr[11] ^ (~context->gpr[9]))) & (context->gpr[11] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[9] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_1100_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[9] - context->gpr[12];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_1100_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[9] >= context->gpr[12]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_1100_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[9]) >= ((int32_t)context->gpr[12])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_1100_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[9]) << 1 | ((uint64_t)context->gpr[9]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[9] >> 24 & 128U;
	context->gpr[9] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[9]) - ((uint64_t)context->gpr[12]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[9] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[12]) + ((uint64_t)context->gpr[9]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[9] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_1100_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[9] & 4294967295)) * ((uint64_t)(context->gpr[12] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_1100_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[12]) - ((uint64_t)context->gpr[9]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_1100_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[9]) >= ((int32_t)context->gpr[12])) {
	if (context->gpr[9] == context->gpr[12]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_1100_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[9] = context->gpr[9] - context->gpr[12];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_1100_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[9]) - ((uint64_t)context->gpr[12]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[9] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_1100_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[9] - context->gpr[12];
	context->t = (((context->gpr[9] ^ context->gpr[12])) & (context->gpr[9] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[9] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_1100_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[9] = context->gpr[12] + context->gpr[9];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_1100_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[9])) * ((int64_t)((int32_t)context->gpr[12])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_1100_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[12]) + ((uint64_t)context->gpr[9]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[9] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_1100_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[12] + context->gpr[9];
	context->t = (((context->gpr[12] ^ (~context->gpr[9]))) & (context->gpr[12] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[9] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_1101_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[9] - context->gpr[13];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_1101_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[9] >= context->gpr[13]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_1101_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[9]) >= ((int32_t)context->gpr[13])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_1101_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[9]) << 1 | ((uint64_t)context->gpr[9]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[9] >> 24 & 128U;
	context->gpr[9] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[9]) - ((uint64_t)context->gpr[13]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[9] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[13]) + ((uint64_t)context->gpr[9]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[9] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_1101_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[9] & 4294967295)) * ((uint64_t)(context->gpr[13] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_1101_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[13]) - ((uint64_t)context->gpr[9]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_1101_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[9]) >= ((int32_t)context->gpr[13])) {
	if (context->gpr[9] == context->gpr[13]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_1101_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[9] = context->gpr[9] - context->gpr[13];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_1101_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[9]) - ((uint64_t)context->gpr[13]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[9] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_1101_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[9] - context->gpr[13];
	context->t = (((context->gpr[9] ^ context->gpr[13])) & (context->gpr[9] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[9] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_1101_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[9] = context->gpr[13] + context->gpr[9];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_1101_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[9])) * ((int64_t)((int32_t)context->gpr[13])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_1101_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[13]) + ((uint64_t)context->gpr[9]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[9] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_1101_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[13] + context->gpr[9];
	context->t = (((context->gpr[13] ^ (~context->gpr[9]))) & (context->gpr[13] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[9] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_1110_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[9] - context->gpr[14];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_1110_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[9] >= context->gpr[14]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_1110_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[9]) >= ((int32_t)context->gpr[14])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_1110_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[9]) << 1 | ((uint64_t)context->gpr[9]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[9] >> 24 & 128U;
	context->gpr[9] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[9]) - ((uint64_t)context->gpr[14]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[9] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[14]) + ((uint64_t)context->gpr[9]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[9] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_1110_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[9] & 4294967295)) * ((uint64_t)(context->gpr[14] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_1110_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[14]) - ((uint64_t)context->gpr[9]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_1110_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[9]) >= ((int32_t)context->gpr[14])) {
	if (context->gpr[9] == context->gpr[14]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_1110_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[9] = context->gpr[9] - context->gpr[14];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_1110_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[9]) - ((uint64_t)context->gpr[14]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[9] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_1110_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[9] - context->gpr[14];
	context->t = (((context->gpr[9] ^ context->gpr[14])) & (context->gpr[9] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[9] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_1110_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[9] = context->gpr[14] + context->gpr[9];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_1110_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[9])) * ((int64_t)((int32_t)context->gpr[14])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_1110_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[14]) + ((uint64_t)context->gpr[9]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[9] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_1110_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[14] + context->gpr[9];
	context->t = (((context->gpr[14] ^ (~context->gpr[9]))) & (context->gpr[14] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[9] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_1111_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[9] - context->gpr[15];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_1111_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[9] >= context->gpr[15]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_1111_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[9]) >= ((int32_t)context->gpr[15])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_1111_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[9]) << 1 | ((uint64_t)context->gpr[9]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[9] >> 24 & 128U;
	context->gpr[9] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[9]) - ((uint64_t)context->gpr[15]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[9] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[15]) + ((uint64_t)context->gpr[9]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[9] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_1111_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[9] & 4294967295)) * ((uint64_t)(context->gpr[15] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_1111_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[15]) - ((uint64_t)context->gpr[9]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_1111_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[9]) >= ((int32_t)context->gpr[15])) {
	if (context->gpr[9] == context->gpr[15]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_1111_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[9] = context->gpr[9] - context->gpr[15];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_1111_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[9]) - ((uint64_t)context->gpr[15]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[9] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_1111_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[9] - context->gpr[15];
	context->t = (((context->gpr[9] ^ context->gpr[15])) & (context->gpr[9] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[9] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_1111_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[9] = context->gpr[15] + context->gpr[9];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_1111_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[9])) * ((int64_t)((int32_t)context->gpr[15])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_1111_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[15]) + ((uint64_t)context->gpr[9]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[9] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_1111_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[15] + context->gpr[9];
	context->t = (((context->gpr[15] ^ (~context->gpr[9]))) & (context->gpr[15] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[9] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_0000_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[10] - context->gpr[0];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_0000_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[10] >= context->gpr[0]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_0000_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[10]) >= ((int32_t)context->gpr[0])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_0000_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[10]) << 1 | ((uint64_t)context->gpr[10]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[10] >> 24 & 128U;
	context->gpr[10] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[10]) - ((uint64_t)context->gpr[0]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[10] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[0]) + ((uint64_t)context->gpr[10]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[10] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_0000_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[10] & 4294967295)) * ((uint64_t)(context->gpr[0] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_0000_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[0]) - ((uint64_t)context->gpr[10]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_0000_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[10]) >= ((int32_t)context->gpr[0])) {
	if (context->gpr[10] == context->gpr[0]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_0000_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[10] = context->gpr[10] - context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_0000_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[10]) - ((uint64_t)context->gpr[0]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[10] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_0000_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[10] - context->gpr[0];
	context->t = (((context->gpr[10] ^ context->gpr[0])) & (context->gpr[10] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[10] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_0000_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[10] = context->gpr[0] + context->gpr[10];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_0000_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[10])) * ((int64_t)((int32_t)context->gpr[0])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_0000_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[0]) + ((uint64_t)context->gpr[10]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[10] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_0000_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[0] + context->gpr[10];
	context->t = (((context->gpr[0] ^ (~context->gpr[10]))) & (context->gpr[0] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[10] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_0001_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[10] - context->gpr[1];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_0001_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[10] >= context->gpr[1]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_0001_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[10]) >= ((int32_t)context->gpr[1])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_0001_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[10]) << 1 | ((uint64_t)context->gpr[10]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[10] >> 24 & 128U;
	context->gpr[10] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[10]) - ((uint64_t)context->gpr[1]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[10] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[1]) + ((uint64_t)context->gpr[10]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[10] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_0001_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[10] & 4294967295)) * ((uint64_t)(context->gpr[1] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_0001_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[1]) - ((uint64_t)context->gpr[10]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_0001_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[10]) >= ((int32_t)context->gpr[1])) {
	if (context->gpr[10] == context->gpr[1]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_0001_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[10] = context->gpr[10] - context->gpr[1];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_0001_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[10]) - ((uint64_t)context->gpr[1]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[10] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_0001_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[10] - context->gpr[1];
	context->t = (((context->gpr[10] ^ context->gpr[1])) & (context->gpr[10] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[10] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_0001_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[10] = context->gpr[1] + context->gpr[10];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_0001_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[10])) * ((int64_t)((int32_t)context->gpr[1])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_0001_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[1]) + ((uint64_t)context->gpr[10]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[10] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_0001_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[1] + context->gpr[10];
	context->t = (((context->gpr[1] ^ (~context->gpr[10]))) & (context->gpr[1] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[10] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_0010_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[10] - context->gpr[2];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_0010_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[10] >= context->gpr[2]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_0010_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[10]) >= ((int32_t)context->gpr[2])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_0010_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[10]) << 1 | ((uint64_t)context->gpr[10]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[10] >> 24 & 128U;
	context->gpr[10] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[10]) - ((uint64_t)context->gpr[2]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[10] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[2]) + ((uint64_t)context->gpr[10]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[10] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_0010_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[10] & 4294967295)) * ((uint64_t)(context->gpr[2] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_0010_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[2]) - ((uint64_t)context->gpr[10]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_0010_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[10]) >= ((int32_t)context->gpr[2])) {
	if (context->gpr[10] == context->gpr[2]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_0010_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[10] = context->gpr[10] - context->gpr[2];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_0010_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[10]) - ((uint64_t)context->gpr[2]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[10] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_0010_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[10] - context->gpr[2];
	context->t = (((context->gpr[10] ^ context->gpr[2])) & (context->gpr[10] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[10] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_0010_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[10] = context->gpr[2] + context->gpr[10];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_0010_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[10])) * ((int64_t)((int32_t)context->gpr[2])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_0010_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[2]) + ((uint64_t)context->gpr[10]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[10] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_0010_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[2] + context->gpr[10];
	context->t = (((context->gpr[2] ^ (~context->gpr[10]))) & (context->gpr[2] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[10] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_0011_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[10] - context->gpr[3];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_0011_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[10] >= context->gpr[3]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_0011_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[10]) >= ((int32_t)context->gpr[3])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_0011_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[10]) << 1 | ((uint64_t)context->gpr[10]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[10] >> 24 & 128U;
	context->gpr[10] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[10]) - ((uint64_t)context->gpr[3]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[10] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[3]) + ((uint64_t)context->gpr[10]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[10] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_0011_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[10] & 4294967295)) * ((uint64_t)(context->gpr[3] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_0011_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[3]) - ((uint64_t)context->gpr[10]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_0011_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[10]) >= ((int32_t)context->gpr[3])) {
	if (context->gpr[10] == context->gpr[3]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_0011_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[10] = context->gpr[10] - context->gpr[3];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_0011_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[10]) - ((uint64_t)context->gpr[3]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[10] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_0011_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[10] - context->gpr[3];
	context->t = (((context->gpr[10] ^ context->gpr[3])) & (context->gpr[10] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[10] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_0011_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[10] = context->gpr[3] + context->gpr[10];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_0011_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[10])) * ((int64_t)((int32_t)context->gpr[3])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_0011_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[3]) + ((uint64_t)context->gpr[10]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[10] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_0011_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[3] + context->gpr[10];
	context->t = (((context->gpr[3] ^ (~context->gpr[10]))) & (context->gpr[3] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[10] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_0100_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[10] - context->gpr[4];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_0100_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[10] >= context->gpr[4]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_0100_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[10]) >= ((int32_t)context->gpr[4])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_0100_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[10]) << 1 | ((uint64_t)context->gpr[10]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[10] >> 24 & 128U;
	context->gpr[10] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[10]) - ((uint64_t)context->gpr[4]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[10] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[4]) + ((uint64_t)context->gpr[10]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[10] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_0100_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[10] & 4294967295)) * ((uint64_t)(context->gpr[4] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_0100_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[4]) - ((uint64_t)context->gpr[10]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_0100_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[10]) >= ((int32_t)context->gpr[4])) {
	if (context->gpr[10] == context->gpr[4]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_0100_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[10] = context->gpr[10] - context->gpr[4];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_0100_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[10]) - ((uint64_t)context->gpr[4]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[10] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_0100_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[10] - context->gpr[4];
	context->t = (((context->gpr[10] ^ context->gpr[4])) & (context->gpr[10] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[10] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_0100_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[10] = context->gpr[4] + context->gpr[10];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_0100_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[10])) * ((int64_t)((int32_t)context->gpr[4])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_0100_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[4]) + ((uint64_t)context->gpr[10]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[10] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_0100_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[4] + context->gpr[10];
	context->t = (((context->gpr[4] ^ (~context->gpr[10]))) & (context->gpr[4] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[10] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_0101_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[10] - context->gpr[5];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_0101_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[10] >= context->gpr[5]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_0101_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[10]) >= ((int32_t)context->gpr[5])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_0101_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[10]) << 1 | ((uint64_t)context->gpr[10]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[10] >> 24 & 128U;
	context->gpr[10] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[10]) - ((uint64_t)context->gpr[5]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[10] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[5]) + ((uint64_t)context->gpr[10]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[10] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_0101_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[10] & 4294967295)) * ((uint64_t)(context->gpr[5] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_0101_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[5]) - ((uint64_t)context->gpr[10]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_0101_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[10]) >= ((int32_t)context->gpr[5])) {
	if (context->gpr[10] == context->gpr[5]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_0101_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[10] = context->gpr[10] - context->gpr[5];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_0101_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[10]) - ((uint64_t)context->gpr[5]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[10] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_0101_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[10] - context->gpr[5];
	context->t = (((context->gpr[10] ^ context->gpr[5])) & (context->gpr[10] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[10] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_0101_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[10] = context->gpr[5] + context->gpr[10];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_0101_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[10])) * ((int64_t)((int32_t)context->gpr[5])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_0101_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[5]) + ((uint64_t)context->gpr[10]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[10] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_0101_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[5] + context->gpr[10];
	context->t = (((context->gpr[5] ^ (~context->gpr[10]))) & (context->gpr[5] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[10] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_0110_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[10] - context->gpr[6];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_0110_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[10] >= context->gpr[6]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_0110_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[10]) >= ((int32_t)context->gpr[6])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_0110_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[10]) << 1 | ((uint64_t)context->gpr[10]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[10] >> 24 & 128U;
	context->gpr[10] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[10]) - ((uint64_t)context->gpr[6]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[10] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[6]) + ((uint64_t)context->gpr[10]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[10] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_0110_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[10] & 4294967295)) * ((uint64_t)(context->gpr[6] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_0110_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[6]) - ((uint64_t)context->gpr[10]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_0110_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[10]) >= ((int32_t)context->gpr[6])) {
	if (context->gpr[10] == context->gpr[6]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_0110_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[10] = context->gpr[10] - context->gpr[6];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_0110_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[10]) - ((uint64_t)context->gpr[6]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[10] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_0110_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[10] - context->gpr[6];
	context->t = (((context->gpr[10] ^ context->gpr[6])) & (context->gpr[10] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[10] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_0110_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[10] = context->gpr[6] + context->gpr[10];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_0110_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[10])) * ((int64_t)((int32_t)context->gpr[6])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_0110_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[6]) + ((uint64_t)context->gpr[10]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[10] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_0110_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[6] + context->gpr[10];
	context->t = (((context->gpr[6] ^ (~context->gpr[10]))) & (context->gpr[6] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[10] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_0111_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[10] - context->gpr[7];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_0111_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[10] >= context->gpr[7]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_0111_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[10]) >= ((int32_t)context->gpr[7])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_0111_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[10]) << 1 | ((uint64_t)context->gpr[10]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[10] >> 24 & 128U;
	context->gpr[10] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[10]) - ((uint64_t)context->gpr[7]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[10] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[7]) + ((uint64_t)context->gpr[10]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[10] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_0111_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[10] & 4294967295)) * ((uint64_t)(context->gpr[7] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_0111_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[7]) - ((uint64_t)context->gpr[10]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_0111_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[10]) >= ((int32_t)context->gpr[7])) {
	if (context->gpr[10] == context->gpr[7]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_0111_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[10] = context->gpr[10] - context->gpr[7];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_0111_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[10]) - ((uint64_t)context->gpr[7]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[10] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_0111_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[10] - context->gpr[7];
	context->t = (((context->gpr[10] ^ context->gpr[7])) & (context->gpr[10] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[10] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_0111_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[10] = context->gpr[7] + context->gpr[10];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_0111_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[10])) * ((int64_t)((int32_t)context->gpr[7])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_0111_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[7]) + ((uint64_t)context->gpr[10]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[10] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_0111_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[7] + context->gpr[10];
	context->t = (((context->gpr[7] ^ (~context->gpr[10]))) & (context->gpr[7] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[10] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_1000_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[10] - context->gpr[8];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_1000_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[10] >= context->gpr[8]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_1000_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[10]) >= ((int32_t)context->gpr[8])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_1000_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[10]) << 1 | ((uint64_t)context->gpr[10]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[10] >> 24 & 128U;
	context->gpr[10] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[10]) - ((uint64_t)context->gpr[8]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[10] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[8]) + ((uint64_t)context->gpr[10]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[10] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_1000_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[10] & 4294967295)) * ((uint64_t)(context->gpr[8] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_1000_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[8]) - ((uint64_t)context->gpr[10]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_1000_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[10]) >= ((int32_t)context->gpr[8])) {
	if (context->gpr[10] == context->gpr[8]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_1000_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[10] = context->gpr[10] - context->gpr[8];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_1000_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[10]) - ((uint64_t)context->gpr[8]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[10] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_1000_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[10] - context->gpr[8];
	context->t = (((context->gpr[10] ^ context->gpr[8])) & (context->gpr[10] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[10] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_1000_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[10] = context->gpr[8] + context->gpr[10];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_1000_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[10])) * ((int64_t)((int32_t)context->gpr[8])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_1000_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[8]) + ((uint64_t)context->gpr[10]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[10] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_1000_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[8] + context->gpr[10];
	context->t = (((context->gpr[8] ^ (~context->gpr[10]))) & (context->gpr[8] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[10] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_1001_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[10] - context->gpr[9];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_1001_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[10] >= context->gpr[9]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_1001_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[10]) >= ((int32_t)context->gpr[9])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_1001_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[10]) << 1 | ((uint64_t)context->gpr[10]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[10] >> 24 & 128U;
	context->gpr[10] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[10]) - ((uint64_t)context->gpr[9]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[10] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[9]) + ((uint64_t)context->gpr[10]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[10] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_1001_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[10] & 4294967295)) * ((uint64_t)(context->gpr[9] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_1001_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[9]) - ((uint64_t)context->gpr[10]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_1001_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[10]) >= ((int32_t)context->gpr[9])) {
	if (context->gpr[10] == context->gpr[9]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_1001_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[10] = context->gpr[10] - context->gpr[9];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_1001_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[10]) - ((uint64_t)context->gpr[9]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[10] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_1001_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[10] - context->gpr[9];
	context->t = (((context->gpr[10] ^ context->gpr[9])) & (context->gpr[10] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[10] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_1001_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[10] = context->gpr[9] + context->gpr[10];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_1001_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[10])) * ((int64_t)((int32_t)context->gpr[9])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_1001_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[9]) + ((uint64_t)context->gpr[10]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[10] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_1001_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[9] + context->gpr[10];
	context->t = (((context->gpr[9] ^ (~context->gpr[10]))) & (context->gpr[9] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[10] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_1010_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[10] - context->gpr[10];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_1010_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[10] >= context->gpr[10]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_1010_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[10]) >= ((int32_t)context->gpr[10])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_1010_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[10]) << 1 | ((uint64_t)context->gpr[10]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[10] >> 24 & 128U;
	context->gpr[10] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[10]) - ((uint64_t)context->gpr[10]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[10] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[10]) + ((uint64_t)context->gpr[10]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[10] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_1010_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[10] & 4294967295)) * ((uint64_t)(context->gpr[10] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_1010_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[10]) - ((uint64_t)context->gpr[10]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_1010_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[10]) >= ((int32_t)context->gpr[10])) {
	if (context->gpr[10] == context->gpr[10]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_1010_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[10] = context->gpr[10] - context->gpr[10];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_1010_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[10]) - ((uint64_t)context->gpr[10]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[10] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_1010_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[10] - context->gpr[10];
	context->t = (((context->gpr[10] ^ context->gpr[10])) & (context->gpr[10] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[10] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_1010_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[10] = context->gpr[10] + context->gpr[10];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_1010_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[10])) * ((int64_t)((int32_t)context->gpr[10])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_1010_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[10]) + ((uint64_t)context->gpr[10]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[10] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_1010_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[10] + context->gpr[10];
	context->t = (((context->gpr[10] ^ (~context->gpr[10]))) & (context->gpr[10] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[10] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_1011_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[10] - context->gpr[11];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_1011_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[10] >= context->gpr[11]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_1011_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[10]) >= ((int32_t)context->gpr[11])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_1011_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[10]) << 1 | ((uint64_t)context->gpr[10]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[10] >> 24 & 128U;
	context->gpr[10] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[10]) - ((uint64_t)context->gpr[11]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[10] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[11]) + ((uint64_t)context->gpr[10]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[10] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_1011_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[10] & 4294967295)) * ((uint64_t)(context->gpr[11] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_1011_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[11]) - ((uint64_t)context->gpr[10]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_1011_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[10]) >= ((int32_t)context->gpr[11])) {
	if (context->gpr[10] == context->gpr[11]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_1011_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[10] = context->gpr[10] - context->gpr[11];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_1011_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[10]) - ((uint64_t)context->gpr[11]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[10] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_1011_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[10] - context->gpr[11];
	context->t = (((context->gpr[10] ^ context->gpr[11])) & (context->gpr[10] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[10] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_1011_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[10] = context->gpr[11] + context->gpr[10];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_1011_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[10])) * ((int64_t)((int32_t)context->gpr[11])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_1011_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[11]) + ((uint64_t)context->gpr[10]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[10] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_1011_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[11] + context->gpr[10];
	context->t = (((context->gpr[11] ^ (~context->gpr[10]))) & (context->gpr[11] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[10] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_1100_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[10] - context->gpr[12];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_1100_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[10] >= context->gpr[12]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_1100_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[10]) >= ((int32_t)context->gpr[12])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_1100_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[10]) << 1 | ((uint64_t)context->gpr[10]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[10] >> 24 & 128U;
	context->gpr[10] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[10]) - ((uint64_t)context->gpr[12]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[10] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[12]) + ((uint64_t)context->gpr[10]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[10] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_1100_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[10] & 4294967295)) * ((uint64_t)(context->gpr[12] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_1100_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[12]) - ((uint64_t)context->gpr[10]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_1100_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[10]) >= ((int32_t)context->gpr[12])) {
	if (context->gpr[10] == context->gpr[12]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_1100_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[10] = context->gpr[10] - context->gpr[12];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_1100_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[10]) - ((uint64_t)context->gpr[12]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[10] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_1100_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[10] - context->gpr[12];
	context->t = (((context->gpr[10] ^ context->gpr[12])) & (context->gpr[10] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[10] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_1100_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[10] = context->gpr[12] + context->gpr[10];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_1100_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[10])) * ((int64_t)((int32_t)context->gpr[12])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_1100_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[12]) + ((uint64_t)context->gpr[10]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[10] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_1100_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[12] + context->gpr[10];
	context->t = (((context->gpr[12] ^ (~context->gpr[10]))) & (context->gpr[12] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[10] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_1101_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[10] - context->gpr[13];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_1101_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[10] >= context->gpr[13]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_1101_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[10]) >= ((int32_t)context->gpr[13])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_1101_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[10]) << 1 | ((uint64_t)context->gpr[10]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[10] >> 24 & 128U;
	context->gpr[10] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[10]) - ((uint64_t)context->gpr[13]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[10] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[13]) + ((uint64_t)context->gpr[10]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[10] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_1101_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[10] & 4294967295)) * ((uint64_t)(context->gpr[13] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_1101_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[13]) - ((uint64_t)context->gpr[10]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_1101_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[10]) >= ((int32_t)context->gpr[13])) {
	if (context->gpr[10] == context->gpr[13]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_1101_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[10] = context->gpr[10] - context->gpr[13];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_1101_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[10]) - ((uint64_t)context->gpr[13]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[10] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_1101_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[10] - context->gpr[13];
	context->t = (((context->gpr[10] ^ context->gpr[13])) & (context->gpr[10] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[10] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_1101_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[10] = context->gpr[13] + context->gpr[10];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_1101_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[10])) * ((int64_t)((int32_t)context->gpr[13])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_1101_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[13]) + ((uint64_t)context->gpr[10]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[10] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_1101_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[13] + context->gpr[10];
	context->t = (((context->gpr[13] ^ (~context->gpr[10]))) & (context->gpr[13] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[10] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_1110_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[10] - context->gpr[14];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_1110_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[10] >= context->gpr[14]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_1110_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[10]) >= ((int32_t)context->gpr[14])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_1110_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[10]) << 1 | ((uint64_t)context->gpr[10]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[10] >> 24 & 128U;
	context->gpr[10] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[10]) - ((uint64_t)context->gpr[14]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[10] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[14]) + ((uint64_t)context->gpr[10]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[10] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_1110_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[10] & 4294967295)) * ((uint64_t)(context->gpr[14] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_1110_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[14]) - ((uint64_t)context->gpr[10]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_1110_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[10]) >= ((int32_t)context->gpr[14])) {
	if (context->gpr[10] == context->gpr[14]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_1110_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[10] = context->gpr[10] - context->gpr[14];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_1110_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[10]) - ((uint64_t)context->gpr[14]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[10] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_1110_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[10] - context->gpr[14];
	context->t = (((context->gpr[10] ^ context->gpr[14])) & (context->gpr[10] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[10] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_1110_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[10] = context->gpr[14] + context->gpr[10];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_1110_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[10])) * ((int64_t)((int32_t)context->gpr[14])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_1110_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[14]) + ((uint64_t)context->gpr[10]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[10] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_1110_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[14] + context->gpr[10];
	context->t = (((context->gpr[14] ^ (~context->gpr[10]))) & (context->gpr[14] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[10] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_1111_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[10] - context->gpr[15];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_1111_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[10] >= context->gpr[15]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_1111_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[10]) >= ((int32_t)context->gpr[15])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_1111_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[10]) << 1 | ((uint64_t)context->gpr[10]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[10] >> 24 & 128U;
	context->gpr[10] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[10]) - ((uint64_t)context->gpr[15]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[10] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[15]) + ((uint64_t)context->gpr[10]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[10] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_1111_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[10] & 4294967295)) * ((uint64_t)(context->gpr[15] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_1111_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[15]) - ((uint64_t)context->gpr[10]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_1111_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[10]) >= ((int32_t)context->gpr[15])) {
	if (context->gpr[10] == context->gpr[15]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_1111_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[10] = context->gpr[10] - context->gpr[15];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_1111_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[10]) - ((uint64_t)context->gpr[15]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[10] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_1111_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[10] - context->gpr[15];
	context->t = (((context->gpr[10] ^ context->gpr[15])) & (context->gpr[10] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[10] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_1111_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[10] = context->gpr[15] + context->gpr[10];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_1111_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[10])) * ((int64_t)((int32_t)context->gpr[15])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_1111_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[15]) + ((uint64_t)context->gpr[10]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[10] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_1111_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[15] + context->gpr[10];
	context->t = (((context->gpr[15] ^ (~context->gpr[10]))) & (context->gpr[15] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[10] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_0000_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[11] - context->gpr[0];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_0000_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[11] >= context->gpr[0]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_0000_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[11]) >= ((int32_t)context->gpr[0])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_0000_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[11]) << 1 | ((uint64_t)context->gpr[11]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[11] >> 24 & 128U;
	context->gpr[11] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[11]) - ((uint64_t)context->gpr[0]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[11] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[0]) + ((uint64_t)context->gpr[11]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[11] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_0000_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[11] & 4294967295)) * ((uint64_t)(context->gpr[0] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_0000_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[0]) - ((uint64_t)context->gpr[11]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_0000_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[11]) >= ((int32_t)context->gpr[0])) {
	if (context->gpr[11] == context->gpr[0]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_0000_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[11] = context->gpr[11] - context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_0000_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[11]) - ((uint64_t)context->gpr[0]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[11] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_0000_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[11] - context->gpr[0];
	context->t = (((context->gpr[11] ^ context->gpr[0])) & (context->gpr[11] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[11] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_0000_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[11] = context->gpr[0] + context->gpr[11];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_0000_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[11])) * ((int64_t)((int32_t)context->gpr[0])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_0000_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[0]) + ((uint64_t)context->gpr[11]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[11] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_0000_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[0] + context->gpr[11];
	context->t = (((context->gpr[0] ^ (~context->gpr[11]))) & (context->gpr[0] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[11] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_0001_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[11] - context->gpr[1];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_0001_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[11] >= context->gpr[1]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_0001_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[11]) >= ((int32_t)context->gpr[1])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_0001_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[11]) << 1 | ((uint64_t)context->gpr[11]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[11] >> 24 & 128U;
	context->gpr[11] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[11]) - ((uint64_t)context->gpr[1]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[11] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[1]) + ((uint64_t)context->gpr[11]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[11] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_0001_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[11] & 4294967295)) * ((uint64_t)(context->gpr[1] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_0001_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[1]) - ((uint64_t)context->gpr[11]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_0001_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[11]) >= ((int32_t)context->gpr[1])) {
	if (context->gpr[11] == context->gpr[1]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_0001_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[11] = context->gpr[11] - context->gpr[1];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_0001_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[11]) - ((uint64_t)context->gpr[1]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[11] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_0001_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[11] - context->gpr[1];
	context->t = (((context->gpr[11] ^ context->gpr[1])) & (context->gpr[11] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[11] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_0001_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[11] = context->gpr[1] + context->gpr[11];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_0001_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[11])) * ((int64_t)((int32_t)context->gpr[1])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_0001_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[1]) + ((uint64_t)context->gpr[11]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[11] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_0001_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[1] + context->gpr[11];
	context->t = (((context->gpr[1] ^ (~context->gpr[11]))) & (context->gpr[1] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[11] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_0010_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[11] - context->gpr[2];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_0010_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[11] >= context->gpr[2]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_0010_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[11]) >= ((int32_t)context->gpr[2])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_0010_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[11]) << 1 | ((uint64_t)context->gpr[11]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[11] >> 24 & 128U;
	context->gpr[11] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[11]) - ((uint64_t)context->gpr[2]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[11] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[2]) + ((uint64_t)context->gpr[11]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[11] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_0010_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[11] & 4294967295)) * ((uint64_t)(context->gpr[2] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_0010_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[2]) - ((uint64_t)context->gpr[11]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_0010_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[11]) >= ((int32_t)context->gpr[2])) {
	if (context->gpr[11] == context->gpr[2]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_0010_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[11] = context->gpr[11] - context->gpr[2];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_0010_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[11]) - ((uint64_t)context->gpr[2]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[11] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_0010_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[11] - context->gpr[2];
	context->t = (((context->gpr[11] ^ context->gpr[2])) & (context->gpr[11] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[11] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_0010_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[11] = context->gpr[2] + context->gpr[11];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_0010_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[11])) * ((int64_t)((int32_t)context->gpr[2])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_0010_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[2]) + ((uint64_t)context->gpr[11]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[11] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_0010_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[2] + context->gpr[11];
	context->t = (((context->gpr[2] ^ (~context->gpr[11]))) & (context->gpr[2] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[11] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_0011_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[11] - context->gpr[3];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_0011_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[11] >= context->gpr[3]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_0011_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[11]) >= ((int32_t)context->gpr[3])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_0011_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[11]) << 1 | ((uint64_t)context->gpr[11]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[11] >> 24 & 128U;
	context->gpr[11] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[11]) - ((uint64_t)context->gpr[3]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[11] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[3]) + ((uint64_t)context->gpr[11]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[11] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_0011_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[11] & 4294967295)) * ((uint64_t)(context->gpr[3] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_0011_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[3]) - ((uint64_t)context->gpr[11]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_0011_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[11]) >= ((int32_t)context->gpr[3])) {
	if (context->gpr[11] == context->gpr[3]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_0011_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[11] = context->gpr[11] - context->gpr[3];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_0011_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[11]) - ((uint64_t)context->gpr[3]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[11] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_0011_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[11] - context->gpr[3];
	context->t = (((context->gpr[11] ^ context->gpr[3])) & (context->gpr[11] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[11] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_0011_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[11] = context->gpr[3] + context->gpr[11];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_0011_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[11])) * ((int64_t)((int32_t)context->gpr[3])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_0011_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[3]) + ((uint64_t)context->gpr[11]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[11] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_0011_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[3] + context->gpr[11];
	context->t = (((context->gpr[3] ^ (~context->gpr[11]))) & (context->gpr[3] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[11] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_0100_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[11] - context->gpr[4];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_0100_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[11] >= context->gpr[4]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_0100_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[11]) >= ((int32_t)context->gpr[4])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_0100_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[11]) << 1 | ((uint64_t)context->gpr[11]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[11] >> 24 & 128U;
	context->gpr[11] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[11]) - ((uint64_t)context->gpr[4]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[11] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[4]) + ((uint64_t)context->gpr[11]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[11] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_0100_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[11] & 4294967295)) * ((uint64_t)(context->gpr[4] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_0100_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[4]) - ((uint64_t)context->gpr[11]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_0100_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[11]) >= ((int32_t)context->gpr[4])) {
	if (context->gpr[11] == context->gpr[4]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_0100_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[11] = context->gpr[11] - context->gpr[4];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_0100_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[11]) - ((uint64_t)context->gpr[4]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[11] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_0100_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[11] - context->gpr[4];
	context->t = (((context->gpr[11] ^ context->gpr[4])) & (context->gpr[11] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[11] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_0100_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[11] = context->gpr[4] + context->gpr[11];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_0100_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[11])) * ((int64_t)((int32_t)context->gpr[4])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_0100_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[4]) + ((uint64_t)context->gpr[11]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[11] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_0100_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[4] + context->gpr[11];
	context->t = (((context->gpr[4] ^ (~context->gpr[11]))) & (context->gpr[4] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[11] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_0101_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[11] - context->gpr[5];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_0101_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[11] >= context->gpr[5]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_0101_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[11]) >= ((int32_t)context->gpr[5])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_0101_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[11]) << 1 | ((uint64_t)context->gpr[11]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[11] >> 24 & 128U;
	context->gpr[11] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[11]) - ((uint64_t)context->gpr[5]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[11] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[5]) + ((uint64_t)context->gpr[11]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[11] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_0101_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[11] & 4294967295)) * ((uint64_t)(context->gpr[5] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_0101_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[5]) - ((uint64_t)context->gpr[11]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_0101_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[11]) >= ((int32_t)context->gpr[5])) {
	if (context->gpr[11] == context->gpr[5]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_0101_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[11] = context->gpr[11] - context->gpr[5];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_0101_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[11]) - ((uint64_t)context->gpr[5]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[11] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_0101_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[11] - context->gpr[5];
	context->t = (((context->gpr[11] ^ context->gpr[5])) & (context->gpr[11] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[11] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_0101_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[11] = context->gpr[5] + context->gpr[11];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_0101_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[11])) * ((int64_t)((int32_t)context->gpr[5])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_0101_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[5]) + ((uint64_t)context->gpr[11]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[11] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_0101_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[5] + context->gpr[11];
	context->t = (((context->gpr[5] ^ (~context->gpr[11]))) & (context->gpr[5] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[11] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_0110_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[11] - context->gpr[6];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_0110_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[11] >= context->gpr[6]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_0110_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[11]) >= ((int32_t)context->gpr[6])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_0110_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[11]) << 1 | ((uint64_t)context->gpr[11]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[11] >> 24 & 128U;
	context->gpr[11] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[11]) - ((uint64_t)context->gpr[6]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[11] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[6]) + ((uint64_t)context->gpr[11]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[11] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_0110_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[11] & 4294967295)) * ((uint64_t)(context->gpr[6] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_0110_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[6]) - ((uint64_t)context->gpr[11]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_0110_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[11]) >= ((int32_t)context->gpr[6])) {
	if (context->gpr[11] == context->gpr[6]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_0110_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[11] = context->gpr[11] - context->gpr[6];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_0110_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[11]) - ((uint64_t)context->gpr[6]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[11] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_0110_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[11] - context->gpr[6];
	context->t = (((context->gpr[11] ^ context->gpr[6])) & (context->gpr[11] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[11] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_0110_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[11] = context->gpr[6] + context->gpr[11];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_0110_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[11])) * ((int64_t)((int32_t)context->gpr[6])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_0110_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[6]) + ((uint64_t)context->gpr[11]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[11] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_0110_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[6] + context->gpr[11];
	context->t = (((context->gpr[6] ^ (~context->gpr[11]))) & (context->gpr[6] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[11] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_0111_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[11] - context->gpr[7];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_0111_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[11] >= context->gpr[7]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_0111_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[11]) >= ((int32_t)context->gpr[7])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_0111_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[11]) << 1 | ((uint64_t)context->gpr[11]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[11] >> 24 & 128U;
	context->gpr[11] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[11]) - ((uint64_t)context->gpr[7]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[11] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[7]) + ((uint64_t)context->gpr[11]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[11] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_0111_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[11] & 4294967295)) * ((uint64_t)(context->gpr[7] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_0111_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[7]) - ((uint64_t)context->gpr[11]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_0111_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[11]) >= ((int32_t)context->gpr[7])) {
	if (context->gpr[11] == context->gpr[7]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_0111_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[11] = context->gpr[11] - context->gpr[7];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_0111_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[11]) - ((uint64_t)context->gpr[7]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[11] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_0111_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[11] - context->gpr[7];
	context->t = (((context->gpr[11] ^ context->gpr[7])) & (context->gpr[11] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[11] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_0111_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[11] = context->gpr[7] + context->gpr[11];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_0111_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[11])) * ((int64_t)((int32_t)context->gpr[7])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_0111_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[7]) + ((uint64_t)context->gpr[11]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[11] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_0111_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[7] + context->gpr[11];
	context->t = (((context->gpr[7] ^ (~context->gpr[11]))) & (context->gpr[7] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[11] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_1000_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[11] - context->gpr[8];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_1000_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[11] >= context->gpr[8]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_1000_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[11]) >= ((int32_t)context->gpr[8])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_1000_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[11]) << 1 | ((uint64_t)context->gpr[11]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[11] >> 24 & 128U;
	context->gpr[11] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[11]) - ((uint64_t)context->gpr[8]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[11] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[8]) + ((uint64_t)context->gpr[11]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[11] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_1000_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[11] & 4294967295)) * ((uint64_t)(context->gpr[8] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_1000_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[8]) - ((uint64_t)context->gpr[11]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_1000_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[11]) >= ((int32_t)context->gpr[8])) {
	if (context->gpr[11] == context->gpr[8]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_1000_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[11] = context->gpr[11] - context->gpr[8];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_1000_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[11]) - ((uint64_t)context->gpr[8]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[11] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_1000_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[11] - context->gpr[8];
	context->t = (((context->gpr[11] ^ context->gpr[8])) & (context->gpr[11] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[11] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_1000_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[11] = context->gpr[8] + context->gpr[11];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_1000_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[11])) * ((int64_t)((int32_t)context->gpr[8])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_1000_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[8]) + ((uint64_t)context->gpr[11]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[11] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_1000_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[8] + context->gpr[11];
	context->t = (((context->gpr[8] ^ (~context->gpr[11]))) & (context->gpr[8] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[11] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_1001_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[11] - context->gpr[9];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_1001_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[11] >= context->gpr[9]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_1001_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[11]) >= ((int32_t)context->gpr[9])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_1001_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[11]) << 1 | ((uint64_t)context->gpr[11]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[11] >> 24 & 128U;
	context->gpr[11] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[11]) - ((uint64_t)context->gpr[9]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[11] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[9]) + ((uint64_t)context->gpr[11]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[11] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_1001_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[11] & 4294967295)) * ((uint64_t)(context->gpr[9] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_1001_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[9]) - ((uint64_t)context->gpr[11]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_1001_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[11]) >= ((int32_t)context->gpr[9])) {
	if (context->gpr[11] == context->gpr[9]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_1001_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[11] = context->gpr[11] - context->gpr[9];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_1001_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[11]) - ((uint64_t)context->gpr[9]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[11] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_1001_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[11] - context->gpr[9];
	context->t = (((context->gpr[11] ^ context->gpr[9])) & (context->gpr[11] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[11] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_1001_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[11] = context->gpr[9] + context->gpr[11];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_1001_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[11])) * ((int64_t)((int32_t)context->gpr[9])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_1001_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[9]) + ((uint64_t)context->gpr[11]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[11] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_1001_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[9] + context->gpr[11];
	context->t = (((context->gpr[9] ^ (~context->gpr[11]))) & (context->gpr[9] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[11] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_1010_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[11] - context->gpr[10];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_1010_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[11] >= context->gpr[10]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_1010_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[11]) >= ((int32_t)context->gpr[10])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_1010_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[11]) << 1 | ((uint64_t)context->gpr[11]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[11] >> 24 & 128U;
	context->gpr[11] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[11]) - ((uint64_t)context->gpr[10]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[11] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[10]) + ((uint64_t)context->gpr[11]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[11] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_1010_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[11] & 4294967295)) * ((uint64_t)(context->gpr[10] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_1010_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[10]) - ((uint64_t)context->gpr[11]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_1010_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[11]) >= ((int32_t)context->gpr[10])) {
	if (context->gpr[11] == context->gpr[10]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_1010_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[11] = context->gpr[11] - context->gpr[10];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_1010_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[11]) - ((uint64_t)context->gpr[10]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[11] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_1010_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[11] - context->gpr[10];
	context->t = (((context->gpr[11] ^ context->gpr[10])) & (context->gpr[11] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[11] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_1010_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[11] = context->gpr[10] + context->gpr[11];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_1010_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[11])) * ((int64_t)((int32_t)context->gpr[10])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_1010_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[10]) + ((uint64_t)context->gpr[11]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[11] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_1010_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[10] + context->gpr[11];
	context->t = (((context->gpr[10] ^ (~context->gpr[11]))) & (context->gpr[10] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[11] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_1011_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[11] - context->gpr[11];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_1011_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[11] >= context->gpr[11]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_1011_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[11]) >= ((int32_t)context->gpr[11])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_1011_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[11]) << 1 | ((uint64_t)context->gpr[11]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[11] >> 24 & 128U;
	context->gpr[11] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[11]) - ((uint64_t)context->gpr[11]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[11] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[11]) + ((uint64_t)context->gpr[11]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[11] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_1011_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[11] & 4294967295)) * ((uint64_t)(context->gpr[11] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_1011_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[11]) - ((uint64_t)context->gpr[11]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_1011_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[11]) >= ((int32_t)context->gpr[11])) {
	if (context->gpr[11] == context->gpr[11]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_1011_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[11] = context->gpr[11] - context->gpr[11];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_1011_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[11]) - ((uint64_t)context->gpr[11]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[11] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_1011_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[11] - context->gpr[11];
	context->t = (((context->gpr[11] ^ context->gpr[11])) & (context->gpr[11] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[11] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_1011_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[11] = context->gpr[11] + context->gpr[11];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_1011_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[11])) * ((int64_t)((int32_t)context->gpr[11])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_1011_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[11]) + ((uint64_t)context->gpr[11]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[11] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_1011_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[11] + context->gpr[11];
	context->t = (((context->gpr[11] ^ (~context->gpr[11]))) & (context->gpr[11] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[11] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_1100_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[11] - context->gpr[12];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_1100_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[11] >= context->gpr[12]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_1100_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[11]) >= ((int32_t)context->gpr[12])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_1100_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[11]) << 1 | ((uint64_t)context->gpr[11]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[11] >> 24 & 128U;
	context->gpr[11] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[11]) - ((uint64_t)context->gpr[12]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[11] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[12]) + ((uint64_t)context->gpr[11]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[11] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_1100_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[11] & 4294967295)) * ((uint64_t)(context->gpr[12] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_1100_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[12]) - ((uint64_t)context->gpr[11]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_1100_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[11]) >= ((int32_t)context->gpr[12])) {
	if (context->gpr[11] == context->gpr[12]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_1100_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[11] = context->gpr[11] - context->gpr[12];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_1100_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[11]) - ((uint64_t)context->gpr[12]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[11] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_1100_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[11] - context->gpr[12];
	context->t = (((context->gpr[11] ^ context->gpr[12])) & (context->gpr[11] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[11] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_1100_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[11] = context->gpr[12] + context->gpr[11];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_1100_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[11])) * ((int64_t)((int32_t)context->gpr[12])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_1100_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[12]) + ((uint64_t)context->gpr[11]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[11] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_1100_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[12] + context->gpr[11];
	context->t = (((context->gpr[12] ^ (~context->gpr[11]))) & (context->gpr[12] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[11] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_1101_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[11] - context->gpr[13];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_1101_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[11] >= context->gpr[13]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_1101_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[11]) >= ((int32_t)context->gpr[13])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_1101_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[11]) << 1 | ((uint64_t)context->gpr[11]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[11] >> 24 & 128U;
	context->gpr[11] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[11]) - ((uint64_t)context->gpr[13]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[11] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[13]) + ((uint64_t)context->gpr[11]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[11] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_1101_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[11] & 4294967295)) * ((uint64_t)(context->gpr[13] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_1101_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[13]) - ((uint64_t)context->gpr[11]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_1101_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[11]) >= ((int32_t)context->gpr[13])) {
	if (context->gpr[11] == context->gpr[13]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_1101_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[11] = context->gpr[11] - context->gpr[13];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_1101_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[11]) - ((uint64_t)context->gpr[13]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[11] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_1101_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[11] - context->gpr[13];
	context->t = (((context->gpr[11] ^ context->gpr[13])) & (context->gpr[11] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[11] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_1101_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[11] = context->gpr[13] + context->gpr[11];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_1101_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[11])) * ((int64_t)((int32_t)context->gpr[13])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_1101_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[13]) + ((uint64_t)context->gpr[11]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[11] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_1101_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[13] + context->gpr[11];
	context->t = (((context->gpr[13] ^ (~context->gpr[11]))) & (context->gpr[13] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[11] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_1110_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[11] - context->gpr[14];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_1110_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[11] >= context->gpr[14]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_1110_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[11]) >= ((int32_t)context->gpr[14])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_1110_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[11]) << 1 | ((uint64_t)context->gpr[11]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[11] >> 24 & 128U;
	context->gpr[11] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[11]) - ((uint64_t)context->gpr[14]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[11] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[14]) + ((uint64_t)context->gpr[11]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[11] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_1110_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[11] & 4294967295)) * ((uint64_t)(context->gpr[14] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_1110_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[14]) - ((uint64_t)context->gpr[11]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_1110_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[11]) >= ((int32_t)context->gpr[14])) {
	if (context->gpr[11] == context->gpr[14]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_1110_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[11] = context->gpr[11] - context->gpr[14];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_1110_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[11]) - ((uint64_t)context->gpr[14]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[11] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_1110_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[11] - context->gpr[14];
	context->t = (((context->gpr[11] ^ context->gpr[14])) & (context->gpr[11] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[11] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_1110_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[11] = context->gpr[14] + context->gpr[11];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_1110_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[11])) * ((int64_t)((int32_t)context->gpr[14])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_1110_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[14]) + ((uint64_t)context->gpr[11]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[11] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_1110_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[14] + context->gpr[11];
	context->t = (((context->gpr[14] ^ (~context->gpr[11]))) & (context->gpr[14] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[11] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_1111_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[11] - context->gpr[15];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_1111_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[11] >= context->gpr[15]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_1111_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[11]) >= ((int32_t)context->gpr[15])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_1111_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[11]) << 1 | ((uint64_t)context->gpr[11]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[11] >> 24 & 128U;
	context->gpr[11] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[11]) - ((uint64_t)context->gpr[15]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[11] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[15]) + ((uint64_t)context->gpr[11]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[11] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_1111_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[11] & 4294967295)) * ((uint64_t)(context->gpr[15] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_1111_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[15]) - ((uint64_t)context->gpr[11]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_1111_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[11]) >= ((int32_t)context->gpr[15])) {
	if (context->gpr[11] == context->gpr[15]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_1111_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[11] = context->gpr[11] - context->gpr[15];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_1111_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[11]) - ((uint64_t)context->gpr[15]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[11] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_1111_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[11] - context->gpr[15];
	context->t = (((context->gpr[11] ^ context->gpr[15])) & (context->gpr[11] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[11] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_1111_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[11] = context->gpr[15] + context->gpr[11];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_1111_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[11])) * ((int64_t)((int32_t)context->gpr[15])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_1111_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[15]) + ((uint64_t)context->gpr[11]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[11] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_1111_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[15] + context->gpr[11];
	context->t = (((context->gpr[15] ^ (~context->gpr[11]))) & (context->gpr[15] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[11] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_0000_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[12] - context->gpr[0];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_0000_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[12] >= context->gpr[0]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_0000_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[12]) >= ((int32_t)context->gpr[0])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_0000_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[12]) << 1 | ((uint64_t)context->gpr[12]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[12] >> 24 & 128U;
	context->gpr[12] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[12]) - ((uint64_t)context->gpr[0]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[12] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[0]) + ((uint64_t)context->gpr[12]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[12] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_0000_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[12] & 4294967295)) * ((uint64_t)(context->gpr[0] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_0000_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[0]) - ((uint64_t)context->gpr[12]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_0000_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[12]) >= ((int32_t)context->gpr[0])) {
	if (context->gpr[12] == context->gpr[0]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_0000_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[12] = context->gpr[12] - context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_0000_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[12]) - ((uint64_t)context->gpr[0]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[12] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_0000_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[12] - context->gpr[0];
	context->t = (((context->gpr[12] ^ context->gpr[0])) & (context->gpr[12] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[12] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_0000_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[12] = context->gpr[0] + context->gpr[12];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_0000_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[12])) * ((int64_t)((int32_t)context->gpr[0])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_0000_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[0]) + ((uint64_t)context->gpr[12]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[12] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_0000_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[0] + context->gpr[12];
	context->t = (((context->gpr[0] ^ (~context->gpr[12]))) & (context->gpr[0] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[12] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_0001_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[12] - context->gpr[1];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_0001_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[12] >= context->gpr[1]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_0001_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[12]) >= ((int32_t)context->gpr[1])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_0001_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[12]) << 1 | ((uint64_t)context->gpr[12]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[12] >> 24 & 128U;
	context->gpr[12] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[12]) - ((uint64_t)context->gpr[1]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[12] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[1]) + ((uint64_t)context->gpr[12]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[12] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_0001_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[12] & 4294967295)) * ((uint64_t)(context->gpr[1] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_0001_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[1]) - ((uint64_t)context->gpr[12]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_0001_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[12]) >= ((int32_t)context->gpr[1])) {
	if (context->gpr[12] == context->gpr[1]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_0001_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[12] = context->gpr[12] - context->gpr[1];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_0001_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[12]) - ((uint64_t)context->gpr[1]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[12] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_0001_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[12] - context->gpr[1];
	context->t = (((context->gpr[12] ^ context->gpr[1])) & (context->gpr[12] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[12] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_0001_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[12] = context->gpr[1] + context->gpr[12];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_0001_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[12])) * ((int64_t)((int32_t)context->gpr[1])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_0001_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[1]) + ((uint64_t)context->gpr[12]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[12] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_0001_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[1] + context->gpr[12];
	context->t = (((context->gpr[1] ^ (~context->gpr[12]))) & (context->gpr[1] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[12] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_0010_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[12] - context->gpr[2];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_0010_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[12] >= context->gpr[2]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_0010_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[12]) >= ((int32_t)context->gpr[2])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_0010_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[12]) << 1 | ((uint64_t)context->gpr[12]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[12] >> 24 & 128U;
	context->gpr[12] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[12]) - ((uint64_t)context->gpr[2]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[12] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[2]) + ((uint64_t)context->gpr[12]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[12] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_0010_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[12] & 4294967295)) * ((uint64_t)(context->gpr[2] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_0010_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[2]) - ((uint64_t)context->gpr[12]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_0010_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[12]) >= ((int32_t)context->gpr[2])) {
	if (context->gpr[12] == context->gpr[2]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_0010_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[12] = context->gpr[12] - context->gpr[2];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_0010_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[12]) - ((uint64_t)context->gpr[2]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[12] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_0010_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[12] - context->gpr[2];
	context->t = (((context->gpr[12] ^ context->gpr[2])) & (context->gpr[12] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[12] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_0010_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[12] = context->gpr[2] + context->gpr[12];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_0010_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[12])) * ((int64_t)((int32_t)context->gpr[2])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_0010_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[2]) + ((uint64_t)context->gpr[12]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[12] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_0010_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[2] + context->gpr[12];
	context->t = (((context->gpr[2] ^ (~context->gpr[12]))) & (context->gpr[2] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[12] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_0011_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[12] - context->gpr[3];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_0011_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[12] >= context->gpr[3]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_0011_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[12]) >= ((int32_t)context->gpr[3])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_0011_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[12]) << 1 | ((uint64_t)context->gpr[12]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[12] >> 24 & 128U;
	context->gpr[12] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[12]) - ((uint64_t)context->gpr[3]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[12] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[3]) + ((uint64_t)context->gpr[12]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[12] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_0011_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[12] & 4294967295)) * ((uint64_t)(context->gpr[3] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_0011_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[3]) - ((uint64_t)context->gpr[12]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_0011_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[12]) >= ((int32_t)context->gpr[3])) {
	if (context->gpr[12] == context->gpr[3]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_0011_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[12] = context->gpr[12] - context->gpr[3];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_0011_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[12]) - ((uint64_t)context->gpr[3]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[12] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_0011_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[12] - context->gpr[3];
	context->t = (((context->gpr[12] ^ context->gpr[3])) & (context->gpr[12] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[12] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_0011_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[12] = context->gpr[3] + context->gpr[12];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_0011_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[12])) * ((int64_t)((int32_t)context->gpr[3])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_0011_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[3]) + ((uint64_t)context->gpr[12]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[12] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_0011_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[3] + context->gpr[12];
	context->t = (((context->gpr[3] ^ (~context->gpr[12]))) & (context->gpr[3] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[12] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_0100_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[12] - context->gpr[4];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_0100_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[12] >= context->gpr[4]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_0100_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[12]) >= ((int32_t)context->gpr[4])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_0100_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[12]) << 1 | ((uint64_t)context->gpr[12]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[12] >> 24 & 128U;
	context->gpr[12] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[12]) - ((uint64_t)context->gpr[4]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[12] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[4]) + ((uint64_t)context->gpr[12]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[12] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_0100_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[12] & 4294967295)) * ((uint64_t)(context->gpr[4] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_0100_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[4]) - ((uint64_t)context->gpr[12]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_0100_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[12]) >= ((int32_t)context->gpr[4])) {
	if (context->gpr[12] == context->gpr[4]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_0100_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[12] = context->gpr[12] - context->gpr[4];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_0100_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[12]) - ((uint64_t)context->gpr[4]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[12] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_0100_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[12] - context->gpr[4];
	context->t = (((context->gpr[12] ^ context->gpr[4])) & (context->gpr[12] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[12] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_0100_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[12] = context->gpr[4] + context->gpr[12];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_0100_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[12])) * ((int64_t)((int32_t)context->gpr[4])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_0100_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[4]) + ((uint64_t)context->gpr[12]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[12] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_0100_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[4] + context->gpr[12];
	context->t = (((context->gpr[4] ^ (~context->gpr[12]))) & (context->gpr[4] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[12] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_0101_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[12] - context->gpr[5];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_0101_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[12] >= context->gpr[5]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_0101_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[12]) >= ((int32_t)context->gpr[5])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_0101_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[12]) << 1 | ((uint64_t)context->gpr[12]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[12] >> 24 & 128U;
	context->gpr[12] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[12]) - ((uint64_t)context->gpr[5]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[12] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[5]) + ((uint64_t)context->gpr[12]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[12] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_0101_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[12] & 4294967295)) * ((uint64_t)(context->gpr[5] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_0101_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[5]) - ((uint64_t)context->gpr[12]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_0101_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[12]) >= ((int32_t)context->gpr[5])) {
	if (context->gpr[12] == context->gpr[5]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_0101_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[12] = context->gpr[12] - context->gpr[5];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_0101_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[12]) - ((uint64_t)context->gpr[5]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[12] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_0101_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[12] - context->gpr[5];
	context->t = (((context->gpr[12] ^ context->gpr[5])) & (context->gpr[12] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[12] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_0101_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[12] = context->gpr[5] + context->gpr[12];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_0101_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[12])) * ((int64_t)((int32_t)context->gpr[5])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_0101_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[5]) + ((uint64_t)context->gpr[12]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[12] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_0101_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[5] + context->gpr[12];
	context->t = (((context->gpr[5] ^ (~context->gpr[12]))) & (context->gpr[5] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[12] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_0110_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[12] - context->gpr[6];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_0110_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[12] >= context->gpr[6]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_0110_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[12]) >= ((int32_t)context->gpr[6])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_0110_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[12]) << 1 | ((uint64_t)context->gpr[12]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[12] >> 24 & 128U;
	context->gpr[12] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[12]) - ((uint64_t)context->gpr[6]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[12] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[6]) + ((uint64_t)context->gpr[12]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[12] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_0110_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[12] & 4294967295)) * ((uint64_t)(context->gpr[6] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_0110_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[6]) - ((uint64_t)context->gpr[12]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_0110_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[12]) >= ((int32_t)context->gpr[6])) {
	if (context->gpr[12] == context->gpr[6]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_0110_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[12] = context->gpr[12] - context->gpr[6];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_0110_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[12]) - ((uint64_t)context->gpr[6]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[12] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_0110_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[12] - context->gpr[6];
	context->t = (((context->gpr[12] ^ context->gpr[6])) & (context->gpr[12] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[12] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_0110_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[12] = context->gpr[6] + context->gpr[12];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_0110_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[12])) * ((int64_t)((int32_t)context->gpr[6])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_0110_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[6]) + ((uint64_t)context->gpr[12]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[12] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_0110_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[6] + context->gpr[12];
	context->t = (((context->gpr[6] ^ (~context->gpr[12]))) & (context->gpr[6] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[12] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_0111_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[12] - context->gpr[7];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_0111_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[12] >= context->gpr[7]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_0111_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[12]) >= ((int32_t)context->gpr[7])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_0111_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[12]) << 1 | ((uint64_t)context->gpr[12]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[12] >> 24 & 128U;
	context->gpr[12] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[12]) - ((uint64_t)context->gpr[7]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[12] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[7]) + ((uint64_t)context->gpr[12]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[12] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_0111_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[12] & 4294967295)) * ((uint64_t)(context->gpr[7] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_0111_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[7]) - ((uint64_t)context->gpr[12]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_0111_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[12]) >= ((int32_t)context->gpr[7])) {
	if (context->gpr[12] == context->gpr[7]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_0111_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[12] = context->gpr[12] - context->gpr[7];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_0111_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[12]) - ((uint64_t)context->gpr[7]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[12] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_0111_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[12] - context->gpr[7];
	context->t = (((context->gpr[12] ^ context->gpr[7])) & (context->gpr[12] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[12] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_0111_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[12] = context->gpr[7] + context->gpr[12];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_0111_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[12])) * ((int64_t)((int32_t)context->gpr[7])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_0111_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[7]) + ((uint64_t)context->gpr[12]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[12] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_0111_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[7] + context->gpr[12];
	context->t = (((context->gpr[7] ^ (~context->gpr[12]))) & (context->gpr[7] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[12] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_1000_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[12] - context->gpr[8];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_1000_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[12] >= context->gpr[8]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_1000_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[12]) >= ((int32_t)context->gpr[8])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_1000_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[12]) << 1 | ((uint64_t)context->gpr[12]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[12] >> 24 & 128U;
	context->gpr[12] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[12]) - ((uint64_t)context->gpr[8]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[12] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[8]) + ((uint64_t)context->gpr[12]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[12] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_1000_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[12] & 4294967295)) * ((uint64_t)(context->gpr[8] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_1000_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[8]) - ((uint64_t)context->gpr[12]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_1000_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[12]) >= ((int32_t)context->gpr[8])) {
	if (context->gpr[12] == context->gpr[8]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_1000_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[12] = context->gpr[12] - context->gpr[8];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_1000_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[12]) - ((uint64_t)context->gpr[8]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[12] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_1000_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[12] - context->gpr[8];
	context->t = (((context->gpr[12] ^ context->gpr[8])) & (context->gpr[12] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[12] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_1000_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[12] = context->gpr[8] + context->gpr[12];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_1000_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[12])) * ((int64_t)((int32_t)context->gpr[8])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_1000_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[8]) + ((uint64_t)context->gpr[12]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[12] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_1000_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[8] + context->gpr[12];
	context->t = (((context->gpr[8] ^ (~context->gpr[12]))) & (context->gpr[8] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[12] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_1001_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[12] - context->gpr[9];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_1001_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[12] >= context->gpr[9]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_1001_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[12]) >= ((int32_t)context->gpr[9])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_1001_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[12]) << 1 | ((uint64_t)context->gpr[12]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[12] >> 24 & 128U;
	context->gpr[12] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[12]) - ((uint64_t)context->gpr[9]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[12] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[9]) + ((uint64_t)context->gpr[12]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[12] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_1001_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[12] & 4294967295)) * ((uint64_t)(context->gpr[9] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_1001_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[9]) - ((uint64_t)context->gpr[12]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_1001_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[12]) >= ((int32_t)context->gpr[9])) {
	if (context->gpr[12] == context->gpr[9]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_1001_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[12] = context->gpr[12] - context->gpr[9];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_1001_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[12]) - ((uint64_t)context->gpr[9]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[12] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_1001_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[12] - context->gpr[9];
	context->t = (((context->gpr[12] ^ context->gpr[9])) & (context->gpr[12] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[12] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_1001_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[12] = context->gpr[9] + context->gpr[12];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_1001_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[12])) * ((int64_t)((int32_t)context->gpr[9])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_1001_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[9]) + ((uint64_t)context->gpr[12]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[12] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_1001_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[9] + context->gpr[12];
	context->t = (((context->gpr[9] ^ (~context->gpr[12]))) & (context->gpr[9] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[12] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_1010_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[12] - context->gpr[10];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_1010_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[12] >= context->gpr[10]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_1010_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[12]) >= ((int32_t)context->gpr[10])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_1010_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[12]) << 1 | ((uint64_t)context->gpr[12]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[12] >> 24 & 128U;
	context->gpr[12] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[12]) - ((uint64_t)context->gpr[10]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[12] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[10]) + ((uint64_t)context->gpr[12]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[12] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_1010_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[12] & 4294967295)) * ((uint64_t)(context->gpr[10] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_1010_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[10]) - ((uint64_t)context->gpr[12]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_1010_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[12]) >= ((int32_t)context->gpr[10])) {
	if (context->gpr[12] == context->gpr[10]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_1010_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[12] = context->gpr[12] - context->gpr[10];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_1010_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[12]) - ((uint64_t)context->gpr[10]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[12] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_1010_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[12] - context->gpr[10];
	context->t = (((context->gpr[12] ^ context->gpr[10])) & (context->gpr[12] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[12] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_1010_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[12] = context->gpr[10] + context->gpr[12];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_1010_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[12])) * ((int64_t)((int32_t)context->gpr[10])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_1010_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[10]) + ((uint64_t)context->gpr[12]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[12] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_1010_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[10] + context->gpr[12];
	context->t = (((context->gpr[10] ^ (~context->gpr[12]))) & (context->gpr[10] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[12] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_1011_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[12] - context->gpr[11];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_1011_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[12] >= context->gpr[11]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_1011_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[12]) >= ((int32_t)context->gpr[11])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_1011_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[12]) << 1 | ((uint64_t)context->gpr[12]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[12] >> 24 & 128U;
	context->gpr[12] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[12]) - ((uint64_t)context->gpr[11]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[12] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[11]) + ((uint64_t)context->gpr[12]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[12] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_1011_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[12] & 4294967295)) * ((uint64_t)(context->gpr[11] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_1011_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[11]) - ((uint64_t)context->gpr[12]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_1011_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[12]) >= ((int32_t)context->gpr[11])) {
	if (context->gpr[12] == context->gpr[11]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_1011_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[12] = context->gpr[12] - context->gpr[11];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_1011_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[12]) - ((uint64_t)context->gpr[11]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[12] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_1011_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[12] - context->gpr[11];
	context->t = (((context->gpr[12] ^ context->gpr[11])) & (context->gpr[12] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[12] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_1011_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[12] = context->gpr[11] + context->gpr[12];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_1011_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[12])) * ((int64_t)((int32_t)context->gpr[11])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_1011_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[11]) + ((uint64_t)context->gpr[12]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[12] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_1011_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[11] + context->gpr[12];
	context->t = (((context->gpr[11] ^ (~context->gpr[12]))) & (context->gpr[11] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[12] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_1100_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[12] - context->gpr[12];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_1100_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[12] >= context->gpr[12]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_1100_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[12]) >= ((int32_t)context->gpr[12])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_1100_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[12]) << 1 | ((uint64_t)context->gpr[12]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[12] >> 24 & 128U;
	context->gpr[12] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[12]) - ((uint64_t)context->gpr[12]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[12] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[12]) + ((uint64_t)context->gpr[12]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[12] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_1100_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[12] & 4294967295)) * ((uint64_t)(context->gpr[12] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_1100_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[12]) - ((uint64_t)context->gpr[12]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_1100_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[12]) >= ((int32_t)context->gpr[12])) {
	if (context->gpr[12] == context->gpr[12]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_1100_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[12] = context->gpr[12] - context->gpr[12];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_1100_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[12]) - ((uint64_t)context->gpr[12]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[12] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_1100_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[12] - context->gpr[12];
	context->t = (((context->gpr[12] ^ context->gpr[12])) & (context->gpr[12] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[12] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_1100_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[12] = context->gpr[12] + context->gpr[12];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_1100_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[12])) * ((int64_t)((int32_t)context->gpr[12])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_1100_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[12]) + ((uint64_t)context->gpr[12]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[12] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_1100_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[12] + context->gpr[12];
	context->t = (((context->gpr[12] ^ (~context->gpr[12]))) & (context->gpr[12] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[12] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_1101_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[12] - context->gpr[13];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_1101_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[12] >= context->gpr[13]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_1101_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[12]) >= ((int32_t)context->gpr[13])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_1101_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[12]) << 1 | ((uint64_t)context->gpr[12]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[12] >> 24 & 128U;
	context->gpr[12] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[12]) - ((uint64_t)context->gpr[13]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[12] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[13]) + ((uint64_t)context->gpr[12]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[12] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_1101_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[12] & 4294967295)) * ((uint64_t)(context->gpr[13] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_1101_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[13]) - ((uint64_t)context->gpr[12]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_1101_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[12]) >= ((int32_t)context->gpr[13])) {
	if (context->gpr[12] == context->gpr[13]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_1101_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[12] = context->gpr[12] - context->gpr[13];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_1101_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[12]) - ((uint64_t)context->gpr[13]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[12] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_1101_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[12] - context->gpr[13];
	context->t = (((context->gpr[12] ^ context->gpr[13])) & (context->gpr[12] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[12] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_1101_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[12] = context->gpr[13] + context->gpr[12];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_1101_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[12])) * ((int64_t)((int32_t)context->gpr[13])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_1101_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[13]) + ((uint64_t)context->gpr[12]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[12] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_1101_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[13] + context->gpr[12];
	context->t = (((context->gpr[13] ^ (~context->gpr[12]))) & (context->gpr[13] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[12] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_1110_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[12] - context->gpr[14];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_1110_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[12] >= context->gpr[14]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_1110_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[12]) >= ((int32_t)context->gpr[14])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_1110_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[12]) << 1 | ((uint64_t)context->gpr[12]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[12] >> 24 & 128U;
	context->gpr[12] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[12]) - ((uint64_t)context->gpr[14]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[12] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[14]) + ((uint64_t)context->gpr[12]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[12] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_1110_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[12] & 4294967295)) * ((uint64_t)(context->gpr[14] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_1110_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[14]) - ((uint64_t)context->gpr[12]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_1110_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[12]) >= ((int32_t)context->gpr[14])) {
	if (context->gpr[12] == context->gpr[14]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_1110_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[12] = context->gpr[12] - context->gpr[14];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_1110_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[12]) - ((uint64_t)context->gpr[14]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[12] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_1110_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[12] - context->gpr[14];
	context->t = (((context->gpr[12] ^ context->gpr[14])) & (context->gpr[12] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[12] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_1110_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[12] = context->gpr[14] + context->gpr[12];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_1110_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[12])) * ((int64_t)((int32_t)context->gpr[14])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_1110_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[14]) + ((uint64_t)context->gpr[12]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[12] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_1110_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[14] + context->gpr[12];
	context->t = (((context->gpr[14] ^ (~context->gpr[12]))) & (context->gpr[14] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[12] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_1111_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[12] - context->gpr[15];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_1111_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[12] >= context->gpr[15]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_1111_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[12]) >= ((int32_t)context->gpr[15])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_1111_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[12]) << 1 | ((uint64_t)context->gpr[12]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[12] >> 24 & 128U;
	context->gpr[12] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[12]) - ((uint64_t)context->gpr[15]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[12] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[15]) + ((uint64_t)context->gpr[12]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[12] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_1111_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[12] & 4294967295)) * ((uint64_t)(context->gpr[15] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_1111_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[15]) - ((uint64_t)context->gpr[12]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_1111_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[12]) >= ((int32_t)context->gpr[15])) {
	if (context->gpr[12] == context->gpr[15]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_1111_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[12] = context->gpr[12] - context->gpr[15];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_1111_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[12]) - ((uint64_t)context->gpr[15]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[12] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_1111_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[12] - context->gpr[15];
	context->t = (((context->gpr[12] ^ context->gpr[15])) & (context->gpr[12] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[12] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_1111_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[12] = context->gpr[15] + context->gpr[12];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_1111_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[12])) * ((int64_t)((int32_t)context->gpr[15])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_1111_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[15]) + ((uint64_t)context->gpr[12]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[12] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_1111_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[15] + context->gpr[12];
	context->t = (((context->gpr[15] ^ (~context->gpr[12]))) & (context->gpr[15] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[12] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_0000_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[13] - context->gpr[0];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_0000_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[13] >= context->gpr[0]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_0000_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[13]) >= ((int32_t)context->gpr[0])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_0000_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[13]) << 1 | ((uint64_t)context->gpr[13]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[13] >> 24 & 128U;
	context->gpr[13] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[13]) - ((uint64_t)context->gpr[0]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[13] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[0]) + ((uint64_t)context->gpr[13]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[13] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_0000_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[13] & 4294967295)) * ((uint64_t)(context->gpr[0] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_0000_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[0]) - ((uint64_t)context->gpr[13]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_0000_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[13]) >= ((int32_t)context->gpr[0])) {
	if (context->gpr[13] == context->gpr[0]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_0000_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[13] = context->gpr[13] - context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_0000_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[13]) - ((uint64_t)context->gpr[0]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[13] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_0000_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[13] - context->gpr[0];
	context->t = (((context->gpr[13] ^ context->gpr[0])) & (context->gpr[13] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[13] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_0000_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[13] = context->gpr[0] + context->gpr[13];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_0000_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[13])) * ((int64_t)((int32_t)context->gpr[0])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_0000_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[0]) + ((uint64_t)context->gpr[13]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[13] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_0000_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[0] + context->gpr[13];
	context->t = (((context->gpr[0] ^ (~context->gpr[13]))) & (context->gpr[0] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[13] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_0001_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[13] - context->gpr[1];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_0001_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[13] >= context->gpr[1]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_0001_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[13]) >= ((int32_t)context->gpr[1])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_0001_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[13]) << 1 | ((uint64_t)context->gpr[13]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[13] >> 24 & 128U;
	context->gpr[13] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[13]) - ((uint64_t)context->gpr[1]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[13] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[1]) + ((uint64_t)context->gpr[13]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[13] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_0001_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[13] & 4294967295)) * ((uint64_t)(context->gpr[1] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_0001_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[1]) - ((uint64_t)context->gpr[13]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_0001_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[13]) >= ((int32_t)context->gpr[1])) {
	if (context->gpr[13] == context->gpr[1]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_0001_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[13] = context->gpr[13] - context->gpr[1];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_0001_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[13]) - ((uint64_t)context->gpr[1]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[13] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_0001_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[13] - context->gpr[1];
	context->t = (((context->gpr[13] ^ context->gpr[1])) & (context->gpr[13] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[13] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_0001_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[13] = context->gpr[1] + context->gpr[13];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_0001_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[13])) * ((int64_t)((int32_t)context->gpr[1])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_0001_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[1]) + ((uint64_t)context->gpr[13]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[13] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_0001_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[1] + context->gpr[13];
	context->t = (((context->gpr[1] ^ (~context->gpr[13]))) & (context->gpr[1] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[13] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_0010_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[13] - context->gpr[2];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_0010_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[13] >= context->gpr[2]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_0010_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[13]) >= ((int32_t)context->gpr[2])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_0010_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[13]) << 1 | ((uint64_t)context->gpr[13]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[13] >> 24 & 128U;
	context->gpr[13] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[13]) - ((uint64_t)context->gpr[2]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[13] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[2]) + ((uint64_t)context->gpr[13]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[13] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_0010_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[13] & 4294967295)) * ((uint64_t)(context->gpr[2] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_0010_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[2]) - ((uint64_t)context->gpr[13]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_0010_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[13]) >= ((int32_t)context->gpr[2])) {
	if (context->gpr[13] == context->gpr[2]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_0010_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[13] = context->gpr[13] - context->gpr[2];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_0010_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[13]) - ((uint64_t)context->gpr[2]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[13] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_0010_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[13] - context->gpr[2];
	context->t = (((context->gpr[13] ^ context->gpr[2])) & (context->gpr[13] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[13] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_0010_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[13] = context->gpr[2] + context->gpr[13];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_0010_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[13])) * ((int64_t)((int32_t)context->gpr[2])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_0010_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[2]) + ((uint64_t)context->gpr[13]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[13] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_0010_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[2] + context->gpr[13];
	context->t = (((context->gpr[2] ^ (~context->gpr[13]))) & (context->gpr[2] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[13] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_0011_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[13] - context->gpr[3];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_0011_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[13] >= context->gpr[3]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_0011_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[13]) >= ((int32_t)context->gpr[3])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_0011_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[13]) << 1 | ((uint64_t)context->gpr[13]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[13] >> 24 & 128U;
	context->gpr[13] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[13]) - ((uint64_t)context->gpr[3]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[13] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[3]) + ((uint64_t)context->gpr[13]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[13] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_0011_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[13] & 4294967295)) * ((uint64_t)(context->gpr[3] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_0011_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[3]) - ((uint64_t)context->gpr[13]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_0011_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[13]) >= ((int32_t)context->gpr[3])) {
	if (context->gpr[13] == context->gpr[3]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_0011_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[13] = context->gpr[13] - context->gpr[3];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_0011_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[13]) - ((uint64_t)context->gpr[3]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[13] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_0011_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[13] - context->gpr[3];
	context->t = (((context->gpr[13] ^ context->gpr[3])) & (context->gpr[13] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[13] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_0011_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[13] = context->gpr[3] + context->gpr[13];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_0011_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[13])) * ((int64_t)((int32_t)context->gpr[3])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_0011_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[3]) + ((uint64_t)context->gpr[13]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[13] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_0011_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[3] + context->gpr[13];
	context->t = (((context->gpr[3] ^ (~context->gpr[13]))) & (context->gpr[3] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[13] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_0100_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[13] - context->gpr[4];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_0100_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[13] >= context->gpr[4]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_0100_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[13]) >= ((int32_t)context->gpr[4])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_0100_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[13]) << 1 | ((uint64_t)context->gpr[13]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[13] >> 24 & 128U;
	context->gpr[13] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[13]) - ((uint64_t)context->gpr[4]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[13] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[4]) + ((uint64_t)context->gpr[13]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[13] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_0100_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[13] & 4294967295)) * ((uint64_t)(context->gpr[4] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_0100_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[4]) - ((uint64_t)context->gpr[13]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_0100_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[13]) >= ((int32_t)context->gpr[4])) {
	if (context->gpr[13] == context->gpr[4]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_0100_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[13] = context->gpr[13] - context->gpr[4];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_0100_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[13]) - ((uint64_t)context->gpr[4]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[13] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_0100_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[13] - context->gpr[4];
	context->t = (((context->gpr[13] ^ context->gpr[4])) & (context->gpr[13] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[13] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_0100_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[13] = context->gpr[4] + context->gpr[13];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_0100_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[13])) * ((int64_t)((int32_t)context->gpr[4])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_0100_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[4]) + ((uint64_t)context->gpr[13]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[13] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_0100_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[4] + context->gpr[13];
	context->t = (((context->gpr[4] ^ (~context->gpr[13]))) & (context->gpr[4] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[13] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_0101_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[13] - context->gpr[5];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_0101_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[13] >= context->gpr[5]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_0101_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[13]) >= ((int32_t)context->gpr[5])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_0101_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[13]) << 1 | ((uint64_t)context->gpr[13]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[13] >> 24 & 128U;
	context->gpr[13] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[13]) - ((uint64_t)context->gpr[5]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[13] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[5]) + ((uint64_t)context->gpr[13]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[13] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_0101_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[13] & 4294967295)) * ((uint64_t)(context->gpr[5] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_0101_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[5]) - ((uint64_t)context->gpr[13]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_0101_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[13]) >= ((int32_t)context->gpr[5])) {
	if (context->gpr[13] == context->gpr[5]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_0101_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[13] = context->gpr[13] - context->gpr[5];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_0101_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[13]) - ((uint64_t)context->gpr[5]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[13] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_0101_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[13] - context->gpr[5];
	context->t = (((context->gpr[13] ^ context->gpr[5])) & (context->gpr[13] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[13] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_0101_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[13] = context->gpr[5] + context->gpr[13];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_0101_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[13])) * ((int64_t)((int32_t)context->gpr[5])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_0101_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[5]) + ((uint64_t)context->gpr[13]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[13] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_0101_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[5] + context->gpr[13];
	context->t = (((context->gpr[5] ^ (~context->gpr[13]))) & (context->gpr[5] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[13] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_0110_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[13] - context->gpr[6];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_0110_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[13] >= context->gpr[6]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_0110_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[13]) >= ((int32_t)context->gpr[6])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_0110_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[13]) << 1 | ((uint64_t)context->gpr[13]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[13] >> 24 & 128U;
	context->gpr[13] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[13]) - ((uint64_t)context->gpr[6]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[13] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[6]) + ((uint64_t)context->gpr[13]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[13] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_0110_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[13] & 4294967295)) * ((uint64_t)(context->gpr[6] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_0110_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[6]) - ((uint64_t)context->gpr[13]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_0110_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[13]) >= ((int32_t)context->gpr[6])) {
	if (context->gpr[13] == context->gpr[6]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_0110_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[13] = context->gpr[13] - context->gpr[6];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_0110_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[13]) - ((uint64_t)context->gpr[6]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[13] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_0110_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[13] - context->gpr[6];
	context->t = (((context->gpr[13] ^ context->gpr[6])) & (context->gpr[13] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[13] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_0110_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[13] = context->gpr[6] + context->gpr[13];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_0110_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[13])) * ((int64_t)((int32_t)context->gpr[6])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_0110_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[6]) + ((uint64_t)context->gpr[13]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[13] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_0110_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[6] + context->gpr[13];
	context->t = (((context->gpr[6] ^ (~context->gpr[13]))) & (context->gpr[6] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[13] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_0111_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[13] - context->gpr[7];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_0111_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[13] >= context->gpr[7]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_0111_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[13]) >= ((int32_t)context->gpr[7])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_0111_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[13]) << 1 | ((uint64_t)context->gpr[13]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[13] >> 24 & 128U;
	context->gpr[13] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[13]) - ((uint64_t)context->gpr[7]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[13] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[7]) + ((uint64_t)context->gpr[13]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[13] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_0111_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[13] & 4294967295)) * ((uint64_t)(context->gpr[7] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_0111_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[7]) - ((uint64_t)context->gpr[13]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_0111_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[13]) >= ((int32_t)context->gpr[7])) {
	if (context->gpr[13] == context->gpr[7]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_0111_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[13] = context->gpr[13] - context->gpr[7];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_0111_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[13]) - ((uint64_t)context->gpr[7]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[13] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_0111_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[13] - context->gpr[7];
	context->t = (((context->gpr[13] ^ context->gpr[7])) & (context->gpr[13] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[13] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_0111_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[13] = context->gpr[7] + context->gpr[13];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_0111_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[13])) * ((int64_t)((int32_t)context->gpr[7])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_0111_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[7]) + ((uint64_t)context->gpr[13]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[13] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_0111_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[7] + context->gpr[13];
	context->t = (((context->gpr[7] ^ (~context->gpr[13]))) & (context->gpr[7] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[13] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_1000_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[13] - context->gpr[8];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_1000_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[13] >= context->gpr[8]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_1000_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[13]) >= ((int32_t)context->gpr[8])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_1000_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[13]) << 1 | ((uint64_t)context->gpr[13]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[13] >> 24 & 128U;
	context->gpr[13] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[13]) - ((uint64_t)context->gpr[8]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[13] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[8]) + ((uint64_t)context->gpr[13]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[13] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_1000_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[13] & 4294967295)) * ((uint64_t)(context->gpr[8] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_1000_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[8]) - ((uint64_t)context->gpr[13]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_1000_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[13]) >= ((int32_t)context->gpr[8])) {
	if (context->gpr[13] == context->gpr[8]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_1000_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[13] = context->gpr[13] - context->gpr[8];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_1000_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[13]) - ((uint64_t)context->gpr[8]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[13] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_1000_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[13] - context->gpr[8];
	context->t = (((context->gpr[13] ^ context->gpr[8])) & (context->gpr[13] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[13] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_1000_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[13] = context->gpr[8] + context->gpr[13];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_1000_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[13])) * ((int64_t)((int32_t)context->gpr[8])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_1000_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[8]) + ((uint64_t)context->gpr[13]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[13] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_1000_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[8] + context->gpr[13];
	context->t = (((context->gpr[8] ^ (~context->gpr[13]))) & (context->gpr[8] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[13] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_1001_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[13] - context->gpr[9];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_1001_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[13] >= context->gpr[9]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_1001_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[13]) >= ((int32_t)context->gpr[9])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_1001_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[13]) << 1 | ((uint64_t)context->gpr[13]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[13] >> 24 & 128U;
	context->gpr[13] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[13]) - ((uint64_t)context->gpr[9]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[13] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[9]) + ((uint64_t)context->gpr[13]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[13] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_1001_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[13] & 4294967295)) * ((uint64_t)(context->gpr[9] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_1001_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[9]) - ((uint64_t)context->gpr[13]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_1001_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[13]) >= ((int32_t)context->gpr[9])) {
	if (context->gpr[13] == context->gpr[9]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_1001_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[13] = context->gpr[13] - context->gpr[9];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_1001_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[13]) - ((uint64_t)context->gpr[9]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[13] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_1001_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[13] - context->gpr[9];
	context->t = (((context->gpr[13] ^ context->gpr[9])) & (context->gpr[13] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[13] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_1001_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[13] = context->gpr[9] + context->gpr[13];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_1001_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[13])) * ((int64_t)((int32_t)context->gpr[9])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_1001_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[9]) + ((uint64_t)context->gpr[13]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[13] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_1001_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[9] + context->gpr[13];
	context->t = (((context->gpr[9] ^ (~context->gpr[13]))) & (context->gpr[9] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[13] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_1010_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[13] - context->gpr[10];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_1010_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[13] >= context->gpr[10]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_1010_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[13]) >= ((int32_t)context->gpr[10])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_1010_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[13]) << 1 | ((uint64_t)context->gpr[13]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[13] >> 24 & 128U;
	context->gpr[13] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[13]) - ((uint64_t)context->gpr[10]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[13] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[10]) + ((uint64_t)context->gpr[13]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[13] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_1010_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[13] & 4294967295)) * ((uint64_t)(context->gpr[10] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_1010_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[10]) - ((uint64_t)context->gpr[13]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_1010_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[13]) >= ((int32_t)context->gpr[10])) {
	if (context->gpr[13] == context->gpr[10]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_1010_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[13] = context->gpr[13] - context->gpr[10];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_1010_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[13]) - ((uint64_t)context->gpr[10]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[13] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_1010_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[13] - context->gpr[10];
	context->t = (((context->gpr[13] ^ context->gpr[10])) & (context->gpr[13] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[13] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_1010_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[13] = context->gpr[10] + context->gpr[13];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_1010_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[13])) * ((int64_t)((int32_t)context->gpr[10])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_1010_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[10]) + ((uint64_t)context->gpr[13]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[13] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_1010_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[10] + context->gpr[13];
	context->t = (((context->gpr[10] ^ (~context->gpr[13]))) & (context->gpr[10] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[13] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_1011_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[13] - context->gpr[11];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_1011_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[13] >= context->gpr[11]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_1011_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[13]) >= ((int32_t)context->gpr[11])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_1011_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[13]) << 1 | ((uint64_t)context->gpr[13]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[13] >> 24 & 128U;
	context->gpr[13] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[13]) - ((uint64_t)context->gpr[11]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[13] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[11]) + ((uint64_t)context->gpr[13]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[13] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_1011_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[13] & 4294967295)) * ((uint64_t)(context->gpr[11] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_1011_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[11]) - ((uint64_t)context->gpr[13]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_1011_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[13]) >= ((int32_t)context->gpr[11])) {
	if (context->gpr[13] == context->gpr[11]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_1011_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[13] = context->gpr[13] - context->gpr[11];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_1011_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[13]) - ((uint64_t)context->gpr[11]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[13] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_1011_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[13] - context->gpr[11];
	context->t = (((context->gpr[13] ^ context->gpr[11])) & (context->gpr[13] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[13] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_1011_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[13] = context->gpr[11] + context->gpr[13];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_1011_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[13])) * ((int64_t)((int32_t)context->gpr[11])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_1011_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[11]) + ((uint64_t)context->gpr[13]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[13] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_1011_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[11] + context->gpr[13];
	context->t = (((context->gpr[11] ^ (~context->gpr[13]))) & (context->gpr[11] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[13] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_1100_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[13] - context->gpr[12];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_1100_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[13] >= context->gpr[12]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_1100_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[13]) >= ((int32_t)context->gpr[12])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_1100_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[13]) << 1 | ((uint64_t)context->gpr[13]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[13] >> 24 & 128U;
	context->gpr[13] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[13]) - ((uint64_t)context->gpr[12]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[13] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[12]) + ((uint64_t)context->gpr[13]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[13] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_1100_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[13] & 4294967295)) * ((uint64_t)(context->gpr[12] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_1100_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[12]) - ((uint64_t)context->gpr[13]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_1100_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[13]) >= ((int32_t)context->gpr[12])) {
	if (context->gpr[13] == context->gpr[12]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_1100_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[13] = context->gpr[13] - context->gpr[12];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_1100_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[13]) - ((uint64_t)context->gpr[12]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[13] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_1100_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[13] - context->gpr[12];
	context->t = (((context->gpr[13] ^ context->gpr[12])) & (context->gpr[13] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[13] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_1100_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[13] = context->gpr[12] + context->gpr[13];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_1100_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[13])) * ((int64_t)((int32_t)context->gpr[12])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_1100_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[12]) + ((uint64_t)context->gpr[13]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[13] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_1100_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[12] + context->gpr[13];
	context->t = (((context->gpr[12] ^ (~context->gpr[13]))) & (context->gpr[12] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[13] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_1101_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[13] - context->gpr[13];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_1101_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[13] >= context->gpr[13]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_1101_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[13]) >= ((int32_t)context->gpr[13])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_1101_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[13]) << 1 | ((uint64_t)context->gpr[13]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[13] >> 24 & 128U;
	context->gpr[13] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[13]) - ((uint64_t)context->gpr[13]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[13] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[13]) + ((uint64_t)context->gpr[13]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[13] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_1101_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[13] & 4294967295)) * ((uint64_t)(context->gpr[13] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_1101_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[13]) - ((uint64_t)context->gpr[13]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_1101_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[13]) >= ((int32_t)context->gpr[13])) {
	if (context->gpr[13] == context->gpr[13]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_1101_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[13] = context->gpr[13] - context->gpr[13];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_1101_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[13]) - ((uint64_t)context->gpr[13]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[13] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_1101_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[13] - context->gpr[13];
	context->t = (((context->gpr[13] ^ context->gpr[13])) & (context->gpr[13] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[13] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_1101_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[13] = context->gpr[13] + context->gpr[13];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_1101_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[13])) * ((int64_t)((int32_t)context->gpr[13])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_1101_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[13]) + ((uint64_t)context->gpr[13]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[13] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_1101_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[13] + context->gpr[13];
	context->t = (((context->gpr[13] ^ (~context->gpr[13]))) & (context->gpr[13] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[13] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_1110_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[13] - context->gpr[14];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_1110_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[13] >= context->gpr[14]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_1110_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[13]) >= ((int32_t)context->gpr[14])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_1110_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[13]) << 1 | ((uint64_t)context->gpr[13]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[13] >> 24 & 128U;
	context->gpr[13] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[13]) - ((uint64_t)context->gpr[14]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[13] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[14]) + ((uint64_t)context->gpr[13]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[13] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_1110_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[13] & 4294967295)) * ((uint64_t)(context->gpr[14] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_1110_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[14]) - ((uint64_t)context->gpr[13]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_1110_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[13]) >= ((int32_t)context->gpr[14])) {
	if (context->gpr[13] == context->gpr[14]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_1110_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[13] = context->gpr[13] - context->gpr[14];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_1110_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[13]) - ((uint64_t)context->gpr[14]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[13] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_1110_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[13] - context->gpr[14];
	context->t = (((context->gpr[13] ^ context->gpr[14])) & (context->gpr[13] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[13] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_1110_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[13] = context->gpr[14] + context->gpr[13];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_1110_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[13])) * ((int64_t)((int32_t)context->gpr[14])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_1110_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[14]) + ((uint64_t)context->gpr[13]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[13] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_1110_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[14] + context->gpr[13];
	context->t = (((context->gpr[14] ^ (~context->gpr[13]))) & (context->gpr[14] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[13] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_1111_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[13] - context->gpr[15];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_1111_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[13] >= context->gpr[15]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_1111_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[13]) >= ((int32_t)context->gpr[15])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_1111_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[13]) << 1 | ((uint64_t)context->gpr[13]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[13] >> 24 & 128U;
	context->gpr[13] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[13]) - ((uint64_t)context->gpr[15]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[13] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[15]) + ((uint64_t)context->gpr[13]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[13] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_1111_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[13] & 4294967295)) * ((uint64_t)(context->gpr[15] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_1111_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[15]) - ((uint64_t)context->gpr[13]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_1111_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[13]) >= ((int32_t)context->gpr[15])) {
	if (context->gpr[13] == context->gpr[15]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_1111_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[13] = context->gpr[13] - context->gpr[15];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_1111_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[13]) - ((uint64_t)context->gpr[15]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[13] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_1111_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[13] - context->gpr[15];
	context->t = (((context->gpr[13] ^ context->gpr[15])) & (context->gpr[13] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[13] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_1111_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[13] = context->gpr[15] + context->gpr[13];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_1111_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[13])) * ((int64_t)((int32_t)context->gpr[15])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_1111_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[15]) + ((uint64_t)context->gpr[13]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[13] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_1111_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[15] + context->gpr[13];
	context->t = (((context->gpr[15] ^ (~context->gpr[13]))) & (context->gpr[15] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[13] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_0000_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[14] - context->gpr[0];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_0000_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[14] >= context->gpr[0]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_0000_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[14]) >= ((int32_t)context->gpr[0])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_0000_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[14]) << 1 | ((uint64_t)context->gpr[14]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[14] >> 24 & 128U;
	context->gpr[14] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[14]) - ((uint64_t)context->gpr[0]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[14] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[0]) + ((uint64_t)context->gpr[14]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[14] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_0000_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[14] & 4294967295)) * ((uint64_t)(context->gpr[0] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_0000_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[0]) - ((uint64_t)context->gpr[14]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_0000_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[14]) >= ((int32_t)context->gpr[0])) {
	if (context->gpr[14] == context->gpr[0]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_0000_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[14] = context->gpr[14] - context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_0000_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[14]) - ((uint64_t)context->gpr[0]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[14] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_0000_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[14] - context->gpr[0];
	context->t = (((context->gpr[14] ^ context->gpr[0])) & (context->gpr[14] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[14] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_0000_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[14] = context->gpr[0] + context->gpr[14];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_0000_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[14])) * ((int64_t)((int32_t)context->gpr[0])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_0000_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[0]) + ((uint64_t)context->gpr[14]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[14] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_0000_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[0] + context->gpr[14];
	context->t = (((context->gpr[0] ^ (~context->gpr[14]))) & (context->gpr[0] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[14] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_0001_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[14] - context->gpr[1];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_0001_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[14] >= context->gpr[1]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_0001_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[14]) >= ((int32_t)context->gpr[1])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_0001_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[14]) << 1 | ((uint64_t)context->gpr[14]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[14] >> 24 & 128U;
	context->gpr[14] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[14]) - ((uint64_t)context->gpr[1]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[14] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[1]) + ((uint64_t)context->gpr[14]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[14] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_0001_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[14] & 4294967295)) * ((uint64_t)(context->gpr[1] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_0001_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[1]) - ((uint64_t)context->gpr[14]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_0001_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[14]) >= ((int32_t)context->gpr[1])) {
	if (context->gpr[14] == context->gpr[1]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_0001_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[14] = context->gpr[14] - context->gpr[1];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_0001_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[14]) - ((uint64_t)context->gpr[1]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[14] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_0001_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[14] - context->gpr[1];
	context->t = (((context->gpr[14] ^ context->gpr[1])) & (context->gpr[14] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[14] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_0001_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[14] = context->gpr[1] + context->gpr[14];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_0001_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[14])) * ((int64_t)((int32_t)context->gpr[1])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_0001_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[1]) + ((uint64_t)context->gpr[14]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[14] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_0001_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[1] + context->gpr[14];
	context->t = (((context->gpr[1] ^ (~context->gpr[14]))) & (context->gpr[1] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[14] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_0010_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[14] - context->gpr[2];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_0010_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[14] >= context->gpr[2]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_0010_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[14]) >= ((int32_t)context->gpr[2])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_0010_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[14]) << 1 | ((uint64_t)context->gpr[14]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[14] >> 24 & 128U;
	context->gpr[14] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[14]) - ((uint64_t)context->gpr[2]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[14] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[2]) + ((uint64_t)context->gpr[14]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[14] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_0010_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[14] & 4294967295)) * ((uint64_t)(context->gpr[2] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_0010_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[2]) - ((uint64_t)context->gpr[14]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_0010_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[14]) >= ((int32_t)context->gpr[2])) {
	if (context->gpr[14] == context->gpr[2]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_0010_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[14] = context->gpr[14] - context->gpr[2];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_0010_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[14]) - ((uint64_t)context->gpr[2]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[14] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_0010_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[14] - context->gpr[2];
	context->t = (((context->gpr[14] ^ context->gpr[2])) & (context->gpr[14] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[14] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_0010_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[14] = context->gpr[2] + context->gpr[14];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_0010_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[14])) * ((int64_t)((int32_t)context->gpr[2])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_0010_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[2]) + ((uint64_t)context->gpr[14]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[14] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_0010_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[2] + context->gpr[14];
	context->t = (((context->gpr[2] ^ (~context->gpr[14]))) & (context->gpr[2] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[14] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_0011_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[14] - context->gpr[3];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_0011_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[14] >= context->gpr[3]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_0011_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[14]) >= ((int32_t)context->gpr[3])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_0011_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[14]) << 1 | ((uint64_t)context->gpr[14]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[14] >> 24 & 128U;
	context->gpr[14] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[14]) - ((uint64_t)context->gpr[3]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[14] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[3]) + ((uint64_t)context->gpr[14]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[14] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_0011_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[14] & 4294967295)) * ((uint64_t)(context->gpr[3] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_0011_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[3]) - ((uint64_t)context->gpr[14]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_0011_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[14]) >= ((int32_t)context->gpr[3])) {
	if (context->gpr[14] == context->gpr[3]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_0011_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[14] = context->gpr[14] - context->gpr[3];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_0011_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[14]) - ((uint64_t)context->gpr[3]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[14] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_0011_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[14] - context->gpr[3];
	context->t = (((context->gpr[14] ^ context->gpr[3])) & (context->gpr[14] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[14] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_0011_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[14] = context->gpr[3] + context->gpr[14];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_0011_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[14])) * ((int64_t)((int32_t)context->gpr[3])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_0011_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[3]) + ((uint64_t)context->gpr[14]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[14] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_0011_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[3] + context->gpr[14];
	context->t = (((context->gpr[3] ^ (~context->gpr[14]))) & (context->gpr[3] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[14] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_0100_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[14] - context->gpr[4];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_0100_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[14] >= context->gpr[4]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_0100_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[14]) >= ((int32_t)context->gpr[4])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_0100_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[14]) << 1 | ((uint64_t)context->gpr[14]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[14] >> 24 & 128U;
	context->gpr[14] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[14]) - ((uint64_t)context->gpr[4]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[14] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[4]) + ((uint64_t)context->gpr[14]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[14] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_0100_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[14] & 4294967295)) * ((uint64_t)(context->gpr[4] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_0100_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[4]) - ((uint64_t)context->gpr[14]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_0100_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[14]) >= ((int32_t)context->gpr[4])) {
	if (context->gpr[14] == context->gpr[4]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_0100_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[14] = context->gpr[14] - context->gpr[4];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_0100_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[14]) - ((uint64_t)context->gpr[4]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[14] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_0100_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[14] - context->gpr[4];
	context->t = (((context->gpr[14] ^ context->gpr[4])) & (context->gpr[14] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[14] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_0100_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[14] = context->gpr[4] + context->gpr[14];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_0100_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[14])) * ((int64_t)((int32_t)context->gpr[4])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_0100_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[4]) + ((uint64_t)context->gpr[14]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[14] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_0100_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[4] + context->gpr[14];
	context->t = (((context->gpr[4] ^ (~context->gpr[14]))) & (context->gpr[4] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[14] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_0101_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[14] - context->gpr[5];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_0101_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[14] >= context->gpr[5]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_0101_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[14]) >= ((int32_t)context->gpr[5])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_0101_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[14]) << 1 | ((uint64_t)context->gpr[14]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[14] >> 24 & 128U;
	context->gpr[14] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[14]) - ((uint64_t)context->gpr[5]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[14] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[5]) + ((uint64_t)context->gpr[14]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[14] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_0101_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[14] & 4294967295)) * ((uint64_t)(context->gpr[5] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_0101_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[5]) - ((uint64_t)context->gpr[14]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_0101_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[14]) >= ((int32_t)context->gpr[5])) {
	if (context->gpr[14] == context->gpr[5]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_0101_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[14] = context->gpr[14] - context->gpr[5];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_0101_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[14]) - ((uint64_t)context->gpr[5]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[14] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_0101_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[14] - context->gpr[5];
	context->t = (((context->gpr[14] ^ context->gpr[5])) & (context->gpr[14] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[14] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_0101_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[14] = context->gpr[5] + context->gpr[14];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_0101_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[14])) * ((int64_t)((int32_t)context->gpr[5])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_0101_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[5]) + ((uint64_t)context->gpr[14]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[14] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_0101_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[5] + context->gpr[14];
	context->t = (((context->gpr[5] ^ (~context->gpr[14]))) & (context->gpr[5] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[14] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_0110_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[14] - context->gpr[6];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_0110_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[14] >= context->gpr[6]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_0110_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[14]) >= ((int32_t)context->gpr[6])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_0110_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[14]) << 1 | ((uint64_t)context->gpr[14]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[14] >> 24 & 128U;
	context->gpr[14] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[14]) - ((uint64_t)context->gpr[6]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[14] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[6]) + ((uint64_t)context->gpr[14]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[14] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_0110_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[14] & 4294967295)) * ((uint64_t)(context->gpr[6] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_0110_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[6]) - ((uint64_t)context->gpr[14]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_0110_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[14]) >= ((int32_t)context->gpr[6])) {
	if (context->gpr[14] == context->gpr[6]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_0110_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[14] = context->gpr[14] - context->gpr[6];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_0110_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[14]) - ((uint64_t)context->gpr[6]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[14] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_0110_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[14] - context->gpr[6];
	context->t = (((context->gpr[14] ^ context->gpr[6])) & (context->gpr[14] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[14] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_0110_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[14] = context->gpr[6] + context->gpr[14];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_0110_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[14])) * ((int64_t)((int32_t)context->gpr[6])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_0110_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[6]) + ((uint64_t)context->gpr[14]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[14] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_0110_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[6] + context->gpr[14];
	context->t = (((context->gpr[6] ^ (~context->gpr[14]))) & (context->gpr[6] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[14] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_0111_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[14] - context->gpr[7];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_0111_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[14] >= context->gpr[7]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_0111_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[14]) >= ((int32_t)context->gpr[7])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_0111_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[14]) << 1 | ((uint64_t)context->gpr[14]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[14] >> 24 & 128U;
	context->gpr[14] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[14]) - ((uint64_t)context->gpr[7]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[14] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[7]) + ((uint64_t)context->gpr[14]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[14] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_0111_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[14] & 4294967295)) * ((uint64_t)(context->gpr[7] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_0111_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[7]) - ((uint64_t)context->gpr[14]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_0111_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[14]) >= ((int32_t)context->gpr[7])) {
	if (context->gpr[14] == context->gpr[7]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_0111_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[14] = context->gpr[14] - context->gpr[7];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_0111_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[14]) - ((uint64_t)context->gpr[7]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[14] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_0111_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[14] - context->gpr[7];
	context->t = (((context->gpr[14] ^ context->gpr[7])) & (context->gpr[14] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[14] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_0111_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[14] = context->gpr[7] + context->gpr[14];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_0111_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[14])) * ((int64_t)((int32_t)context->gpr[7])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_0111_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[7]) + ((uint64_t)context->gpr[14]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[14] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_0111_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[7] + context->gpr[14];
	context->t = (((context->gpr[7] ^ (~context->gpr[14]))) & (context->gpr[7] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[14] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_1000_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[14] - context->gpr[8];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_1000_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[14] >= context->gpr[8]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_1000_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[14]) >= ((int32_t)context->gpr[8])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_1000_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[14]) << 1 | ((uint64_t)context->gpr[14]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[14] >> 24 & 128U;
	context->gpr[14] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[14]) - ((uint64_t)context->gpr[8]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[14] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[8]) + ((uint64_t)context->gpr[14]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[14] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_1000_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[14] & 4294967295)) * ((uint64_t)(context->gpr[8] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_1000_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[8]) - ((uint64_t)context->gpr[14]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_1000_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[14]) >= ((int32_t)context->gpr[8])) {
	if (context->gpr[14] == context->gpr[8]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_1000_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[14] = context->gpr[14] - context->gpr[8];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_1000_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[14]) - ((uint64_t)context->gpr[8]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[14] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_1000_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[14] - context->gpr[8];
	context->t = (((context->gpr[14] ^ context->gpr[8])) & (context->gpr[14] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[14] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_1000_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[14] = context->gpr[8] + context->gpr[14];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_1000_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[14])) * ((int64_t)((int32_t)context->gpr[8])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_1000_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[8]) + ((uint64_t)context->gpr[14]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[14] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_1000_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[8] + context->gpr[14];
	context->t = (((context->gpr[8] ^ (~context->gpr[14]))) & (context->gpr[8] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[14] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_1001_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[14] - context->gpr[9];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_1001_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[14] >= context->gpr[9]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_1001_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[14]) >= ((int32_t)context->gpr[9])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_1001_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[14]) << 1 | ((uint64_t)context->gpr[14]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[14] >> 24 & 128U;
	context->gpr[14] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[14]) - ((uint64_t)context->gpr[9]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[14] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[9]) + ((uint64_t)context->gpr[14]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[14] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_1001_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[14] & 4294967295)) * ((uint64_t)(context->gpr[9] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_1001_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[9]) - ((uint64_t)context->gpr[14]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_1001_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[14]) >= ((int32_t)context->gpr[9])) {
	if (context->gpr[14] == context->gpr[9]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_1001_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[14] = context->gpr[14] - context->gpr[9];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_1001_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[14]) - ((uint64_t)context->gpr[9]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[14] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_1001_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[14] - context->gpr[9];
	context->t = (((context->gpr[14] ^ context->gpr[9])) & (context->gpr[14] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[14] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_1001_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[14] = context->gpr[9] + context->gpr[14];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_1001_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[14])) * ((int64_t)((int32_t)context->gpr[9])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_1001_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[9]) + ((uint64_t)context->gpr[14]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[14] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_1001_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[9] + context->gpr[14];
	context->t = (((context->gpr[9] ^ (~context->gpr[14]))) & (context->gpr[9] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[14] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_1010_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[14] - context->gpr[10];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_1010_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[14] >= context->gpr[10]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_1010_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[14]) >= ((int32_t)context->gpr[10])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_1010_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[14]) << 1 | ((uint64_t)context->gpr[14]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[14] >> 24 & 128U;
	context->gpr[14] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[14]) - ((uint64_t)context->gpr[10]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[14] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[10]) + ((uint64_t)context->gpr[14]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[14] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_1010_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[14] & 4294967295)) * ((uint64_t)(context->gpr[10] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_1010_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[10]) - ((uint64_t)context->gpr[14]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_1010_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[14]) >= ((int32_t)context->gpr[10])) {
	if (context->gpr[14] == context->gpr[10]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_1010_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[14] = context->gpr[14] - context->gpr[10];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_1010_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[14]) - ((uint64_t)context->gpr[10]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[14] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_1010_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[14] - context->gpr[10];
	context->t = (((context->gpr[14] ^ context->gpr[10])) & (context->gpr[14] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[14] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_1010_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[14] = context->gpr[10] + context->gpr[14];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_1010_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[14])) * ((int64_t)((int32_t)context->gpr[10])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_1010_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[10]) + ((uint64_t)context->gpr[14]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[14] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_1010_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[10] + context->gpr[14];
	context->t = (((context->gpr[10] ^ (~context->gpr[14]))) & (context->gpr[10] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[14] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_1011_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[14] - context->gpr[11];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_1011_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[14] >= context->gpr[11]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_1011_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[14]) >= ((int32_t)context->gpr[11])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_1011_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[14]) << 1 | ((uint64_t)context->gpr[14]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[14] >> 24 & 128U;
	context->gpr[14] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[14]) - ((uint64_t)context->gpr[11]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[14] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[11]) + ((uint64_t)context->gpr[14]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[14] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_1011_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[14] & 4294967295)) * ((uint64_t)(context->gpr[11] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_1011_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[11]) - ((uint64_t)context->gpr[14]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_1011_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[14]) >= ((int32_t)context->gpr[11])) {
	if (context->gpr[14] == context->gpr[11]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_1011_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[14] = context->gpr[14] - context->gpr[11];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_1011_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[14]) - ((uint64_t)context->gpr[11]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[14] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_1011_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[14] - context->gpr[11];
	context->t = (((context->gpr[14] ^ context->gpr[11])) & (context->gpr[14] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[14] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_1011_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[14] = context->gpr[11] + context->gpr[14];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_1011_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[14])) * ((int64_t)((int32_t)context->gpr[11])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_1011_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[11]) + ((uint64_t)context->gpr[14]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[14] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_1011_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[11] + context->gpr[14];
	context->t = (((context->gpr[11] ^ (~context->gpr[14]))) & (context->gpr[11] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[14] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_1100_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[14] - context->gpr[12];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_1100_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[14] >= context->gpr[12]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_1100_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[14]) >= ((int32_t)context->gpr[12])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_1100_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[14]) << 1 | ((uint64_t)context->gpr[14]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[14] >> 24 & 128U;
	context->gpr[14] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[14]) - ((uint64_t)context->gpr[12]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[14] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[12]) + ((uint64_t)context->gpr[14]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[14] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_1100_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[14] & 4294967295)) * ((uint64_t)(context->gpr[12] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_1100_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[12]) - ((uint64_t)context->gpr[14]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_1100_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[14]) >= ((int32_t)context->gpr[12])) {
	if (context->gpr[14] == context->gpr[12]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_1100_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[14] = context->gpr[14] - context->gpr[12];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_1100_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[14]) - ((uint64_t)context->gpr[12]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[14] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_1100_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[14] - context->gpr[12];
	context->t = (((context->gpr[14] ^ context->gpr[12])) & (context->gpr[14] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[14] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_1100_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[14] = context->gpr[12] + context->gpr[14];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_1100_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[14])) * ((int64_t)((int32_t)context->gpr[12])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_1100_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[12]) + ((uint64_t)context->gpr[14]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[14] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_1100_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[12] + context->gpr[14];
	context->t = (((context->gpr[12] ^ (~context->gpr[14]))) & (context->gpr[12] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[14] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_1101_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[14] - context->gpr[13];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_1101_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[14] >= context->gpr[13]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_1101_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[14]) >= ((int32_t)context->gpr[13])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_1101_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[14]) << 1 | ((uint64_t)context->gpr[14]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[14] >> 24 & 128U;
	context->gpr[14] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[14]) - ((uint64_t)context->gpr[13]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[14] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[13]) + ((uint64_t)context->gpr[14]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[14] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_1101_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[14] & 4294967295)) * ((uint64_t)(context->gpr[13] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_1101_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[13]) - ((uint64_t)context->gpr[14]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_1101_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[14]) >= ((int32_t)context->gpr[13])) {
	if (context->gpr[14] == context->gpr[13]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_1101_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[14] = context->gpr[14] - context->gpr[13];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_1101_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[14]) - ((uint64_t)context->gpr[13]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[14] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_1101_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[14] - context->gpr[13];
	context->t = (((context->gpr[14] ^ context->gpr[13])) & (context->gpr[14] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[14] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_1101_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[14] = context->gpr[13] + context->gpr[14];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_1101_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[14])) * ((int64_t)((int32_t)context->gpr[13])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_1101_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[13]) + ((uint64_t)context->gpr[14]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[14] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_1101_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[13] + context->gpr[14];
	context->t = (((context->gpr[13] ^ (~context->gpr[14]))) & (context->gpr[13] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[14] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_1110_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[14] - context->gpr[14];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_1110_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[14] >= context->gpr[14]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_1110_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[14]) >= ((int32_t)context->gpr[14])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_1110_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[14]) << 1 | ((uint64_t)context->gpr[14]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[14] >> 24 & 128U;
	context->gpr[14] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[14]) - ((uint64_t)context->gpr[14]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[14] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[14]) + ((uint64_t)context->gpr[14]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[14] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_1110_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[14] & 4294967295)) * ((uint64_t)(context->gpr[14] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_1110_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[14]) - ((uint64_t)context->gpr[14]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_1110_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[14]) >= ((int32_t)context->gpr[14])) {
	if (context->gpr[14] == context->gpr[14]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_1110_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[14] = context->gpr[14] - context->gpr[14];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_1110_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[14]) - ((uint64_t)context->gpr[14]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[14] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_1110_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[14] - context->gpr[14];
	context->t = (((context->gpr[14] ^ context->gpr[14])) & (context->gpr[14] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[14] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_1110_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[14] = context->gpr[14] + context->gpr[14];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_1110_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[14])) * ((int64_t)((int32_t)context->gpr[14])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_1110_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[14]) + ((uint64_t)context->gpr[14]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[14] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_1110_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[14] + context->gpr[14];
	context->t = (((context->gpr[14] ^ (~context->gpr[14]))) & (context->gpr[14] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[14] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_1111_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[14] - context->gpr[15];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_1111_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[14] >= context->gpr[15]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_1111_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[14]) >= ((int32_t)context->gpr[15])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_1111_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[14]) << 1 | ((uint64_t)context->gpr[14]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[14] >> 24 & 128U;
	context->gpr[14] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[14]) - ((uint64_t)context->gpr[15]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[14] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[15]) + ((uint64_t)context->gpr[14]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[14] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_1111_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[14] & 4294967295)) * ((uint64_t)(context->gpr[15] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_1111_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[15]) - ((uint64_t)context->gpr[14]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_1111_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[14]) >= ((int32_t)context->gpr[15])) {
	if (context->gpr[14] == context->gpr[15]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_1111_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[14] = context->gpr[14] - context->gpr[15];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_1111_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[14]) - ((uint64_t)context->gpr[15]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[14] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_1111_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[14] - context->gpr[15];
	context->t = (((context->gpr[14] ^ context->gpr[15])) & (context->gpr[14] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[14] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_1111_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[14] = context->gpr[15] + context->gpr[14];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_1111_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[14])) * ((int64_t)((int32_t)context->gpr[15])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_1111_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[15]) + ((uint64_t)context->gpr[14]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[14] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_1111_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[15] + context->gpr[14];
	context->t = (((context->gpr[15] ^ (~context->gpr[14]))) & (context->gpr[15] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[14] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_0000_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[15] - context->gpr[0];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_0000_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[15] >= context->gpr[0]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_0000_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[15]) >= ((int32_t)context->gpr[0])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_0000_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[15]) << 1 | ((uint64_t)context->gpr[15]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[15] >> 24 & 128U;
	context->gpr[15] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[15]) - ((uint64_t)context->gpr[0]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[15] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[0]) + ((uint64_t)context->gpr[15]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[15] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_0000_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[15] & 4294967295)) * ((uint64_t)(context->gpr[0] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_0000_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[0]) - ((uint64_t)context->gpr[15]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_0000_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[15]) >= ((int32_t)context->gpr[0])) {
	if (context->gpr[15] == context->gpr[0]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_0000_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[15] = context->gpr[15] - context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_0000_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[15]) - ((uint64_t)context->gpr[0]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[15] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_0000_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[15] - context->gpr[0];
	context->t = (((context->gpr[15] ^ context->gpr[0])) & (context->gpr[15] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[15] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_0000_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[15] = context->gpr[0] + context->gpr[15];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_0000_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[15])) * ((int64_t)((int32_t)context->gpr[0])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_0000_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[0]) + ((uint64_t)context->gpr[15]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[15] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_0000_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[0] + context->gpr[15];
	context->t = (((context->gpr[0] ^ (~context->gpr[15]))) & (context->gpr[0] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[15] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_0001_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[15] - context->gpr[1];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_0001_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[15] >= context->gpr[1]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_0001_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[15]) >= ((int32_t)context->gpr[1])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_0001_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[15]) << 1 | ((uint64_t)context->gpr[15]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[15] >> 24 & 128U;
	context->gpr[15] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[15]) - ((uint64_t)context->gpr[1]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[15] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[1]) + ((uint64_t)context->gpr[15]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[15] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_0001_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[15] & 4294967295)) * ((uint64_t)(context->gpr[1] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_0001_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[1]) - ((uint64_t)context->gpr[15]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_0001_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[15]) >= ((int32_t)context->gpr[1])) {
	if (context->gpr[15] == context->gpr[1]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_0001_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[15] = context->gpr[15] - context->gpr[1];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_0001_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[15]) - ((uint64_t)context->gpr[1]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[15] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_0001_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[15] - context->gpr[1];
	context->t = (((context->gpr[15] ^ context->gpr[1])) & (context->gpr[15] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[15] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_0001_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[15] = context->gpr[1] + context->gpr[15];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_0001_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[15])) * ((int64_t)((int32_t)context->gpr[1])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_0001_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[1]) + ((uint64_t)context->gpr[15]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[15] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_0001_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[1] + context->gpr[15];
	context->t = (((context->gpr[1] ^ (~context->gpr[15]))) & (context->gpr[1] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[15] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_0010_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[15] - context->gpr[2];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_0010_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[15] >= context->gpr[2]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_0010_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[15]) >= ((int32_t)context->gpr[2])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_0010_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[15]) << 1 | ((uint64_t)context->gpr[15]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[15] >> 24 & 128U;
	context->gpr[15] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[15]) - ((uint64_t)context->gpr[2]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[15] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[2]) + ((uint64_t)context->gpr[15]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[15] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_0010_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[15] & 4294967295)) * ((uint64_t)(context->gpr[2] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_0010_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[2]) - ((uint64_t)context->gpr[15]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_0010_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[15]) >= ((int32_t)context->gpr[2])) {
	if (context->gpr[15] == context->gpr[2]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_0010_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[15] = context->gpr[15] - context->gpr[2];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_0010_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[15]) - ((uint64_t)context->gpr[2]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[15] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_0010_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[15] - context->gpr[2];
	context->t = (((context->gpr[15] ^ context->gpr[2])) & (context->gpr[15] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[15] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_0010_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[15] = context->gpr[2] + context->gpr[15];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_0010_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[15])) * ((int64_t)((int32_t)context->gpr[2])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_0010_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[2]) + ((uint64_t)context->gpr[15]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[15] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_0010_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[2] + context->gpr[15];
	context->t = (((context->gpr[2] ^ (~context->gpr[15]))) & (context->gpr[2] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[15] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_0011_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[15] - context->gpr[3];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_0011_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[15] >= context->gpr[3]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_0011_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[15]) >= ((int32_t)context->gpr[3])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_0011_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[15]) << 1 | ((uint64_t)context->gpr[15]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[15] >> 24 & 128U;
	context->gpr[15] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[15]) - ((uint64_t)context->gpr[3]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[15] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[3]) + ((uint64_t)context->gpr[15]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[15] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_0011_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[15] & 4294967295)) * ((uint64_t)(context->gpr[3] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_0011_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[3]) - ((uint64_t)context->gpr[15]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_0011_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[15]) >= ((int32_t)context->gpr[3])) {
	if (context->gpr[15] == context->gpr[3]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_0011_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[15] = context->gpr[15] - context->gpr[3];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_0011_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[15]) - ((uint64_t)context->gpr[3]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[15] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_0011_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[15] - context->gpr[3];
	context->t = (((context->gpr[15] ^ context->gpr[3])) & (context->gpr[15] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[15] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_0011_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[15] = context->gpr[3] + context->gpr[15];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_0011_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[15])) * ((int64_t)((int32_t)context->gpr[3])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_0011_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[3]) + ((uint64_t)context->gpr[15]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[15] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_0011_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[3] + context->gpr[15];
	context->t = (((context->gpr[3] ^ (~context->gpr[15]))) & (context->gpr[3] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[15] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_0100_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[15] - context->gpr[4];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_0100_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[15] >= context->gpr[4]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_0100_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[15]) >= ((int32_t)context->gpr[4])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_0100_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[15]) << 1 | ((uint64_t)context->gpr[15]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[15] >> 24 & 128U;
	context->gpr[15] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[15]) - ((uint64_t)context->gpr[4]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[15] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[4]) + ((uint64_t)context->gpr[15]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[15] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_0100_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[15] & 4294967295)) * ((uint64_t)(context->gpr[4] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_0100_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[4]) - ((uint64_t)context->gpr[15]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_0100_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[15]) >= ((int32_t)context->gpr[4])) {
	if (context->gpr[15] == context->gpr[4]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_0100_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[15] = context->gpr[15] - context->gpr[4];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_0100_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[15]) - ((uint64_t)context->gpr[4]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[15] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_0100_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[15] - context->gpr[4];
	context->t = (((context->gpr[15] ^ context->gpr[4])) & (context->gpr[15] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[15] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_0100_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[15] = context->gpr[4] + context->gpr[15];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_0100_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[15])) * ((int64_t)((int32_t)context->gpr[4])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_0100_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[4]) + ((uint64_t)context->gpr[15]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[15] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_0100_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[4] + context->gpr[15];
	context->t = (((context->gpr[4] ^ (~context->gpr[15]))) & (context->gpr[4] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[15] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_0101_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[15] - context->gpr[5];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_0101_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[15] >= context->gpr[5]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_0101_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[15]) >= ((int32_t)context->gpr[5])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_0101_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[15]) << 1 | ((uint64_t)context->gpr[15]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[15] >> 24 & 128U;
	context->gpr[15] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[15]) - ((uint64_t)context->gpr[5]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[15] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[5]) + ((uint64_t)context->gpr[15]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[15] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_0101_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[15] & 4294967295)) * ((uint64_t)(context->gpr[5] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_0101_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[5]) - ((uint64_t)context->gpr[15]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_0101_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[15]) >= ((int32_t)context->gpr[5])) {
	if (context->gpr[15] == context->gpr[5]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_0101_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[15] = context->gpr[15] - context->gpr[5];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_0101_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[15]) - ((uint64_t)context->gpr[5]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[15] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_0101_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[15] - context->gpr[5];
	context->t = (((context->gpr[15] ^ context->gpr[5])) & (context->gpr[15] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[15] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_0101_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[15] = context->gpr[5] + context->gpr[15];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_0101_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[15])) * ((int64_t)((int32_t)context->gpr[5])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_0101_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[5]) + ((uint64_t)context->gpr[15]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[15] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_0101_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[5] + context->gpr[15];
	context->t = (((context->gpr[5] ^ (~context->gpr[15]))) & (context->gpr[5] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[15] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_0110_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[15] - context->gpr[6];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_0110_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[15] >= context->gpr[6]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_0110_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[15]) >= ((int32_t)context->gpr[6])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_0110_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[15]) << 1 | ((uint64_t)context->gpr[15]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[15] >> 24 & 128U;
	context->gpr[15] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[15]) - ((uint64_t)context->gpr[6]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[15] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[6]) + ((uint64_t)context->gpr[15]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[15] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_0110_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[15] & 4294967295)) * ((uint64_t)(context->gpr[6] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_0110_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[6]) - ((uint64_t)context->gpr[15]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_0110_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[15]) >= ((int32_t)context->gpr[6])) {
	if (context->gpr[15] == context->gpr[6]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_0110_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[15] = context->gpr[15] - context->gpr[6];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_0110_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[15]) - ((uint64_t)context->gpr[6]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[15] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_0110_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[15] - context->gpr[6];
	context->t = (((context->gpr[15] ^ context->gpr[6])) & (context->gpr[15] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[15] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_0110_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[15] = context->gpr[6] + context->gpr[15];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_0110_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[15])) * ((int64_t)((int32_t)context->gpr[6])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_0110_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[6]) + ((uint64_t)context->gpr[15]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[15] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_0110_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[6] + context->gpr[15];
	context->t = (((context->gpr[6] ^ (~context->gpr[15]))) & (context->gpr[6] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[15] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_0111_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[15] - context->gpr[7];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_0111_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[15] >= context->gpr[7]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_0111_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[15]) >= ((int32_t)context->gpr[7])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_0111_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[15]) << 1 | ((uint64_t)context->gpr[15]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[15] >> 24 & 128U;
	context->gpr[15] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[15]) - ((uint64_t)context->gpr[7]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[15] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[7]) + ((uint64_t)context->gpr[15]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[15] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_0111_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[15] & 4294967295)) * ((uint64_t)(context->gpr[7] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_0111_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[7]) - ((uint64_t)context->gpr[15]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_0111_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[15]) >= ((int32_t)context->gpr[7])) {
	if (context->gpr[15] == context->gpr[7]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_0111_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[15] = context->gpr[15] - context->gpr[7];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_0111_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[15]) - ((uint64_t)context->gpr[7]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[15] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_0111_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[15] - context->gpr[7];
	context->t = (((context->gpr[15] ^ context->gpr[7])) & (context->gpr[15] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[15] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_0111_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[15] = context->gpr[7] + context->gpr[15];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_0111_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[15])) * ((int64_t)((int32_t)context->gpr[7])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_0111_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[7]) + ((uint64_t)context->gpr[15]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[15] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_0111_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[7] + context->gpr[15];
	context->t = (((context->gpr[7] ^ (~context->gpr[15]))) & (context->gpr[7] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[15] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_1000_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[15] - context->gpr[8];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_1000_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[15] >= context->gpr[8]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_1000_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[15]) >= ((int32_t)context->gpr[8])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_1000_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[15]) << 1 | ((uint64_t)context->gpr[15]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[15] >> 24 & 128U;
	context->gpr[15] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[15]) - ((uint64_t)context->gpr[8]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[15] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[8]) + ((uint64_t)context->gpr[15]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[15] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_1000_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[15] & 4294967295)) * ((uint64_t)(context->gpr[8] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_1000_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[8]) - ((uint64_t)context->gpr[15]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_1000_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[15]) >= ((int32_t)context->gpr[8])) {
	if (context->gpr[15] == context->gpr[8]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_1000_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[15] = context->gpr[15] - context->gpr[8];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_1000_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[15]) - ((uint64_t)context->gpr[8]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[15] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_1000_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[15] - context->gpr[8];
	context->t = (((context->gpr[15] ^ context->gpr[8])) & (context->gpr[15] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[15] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_1000_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[15] = context->gpr[8] + context->gpr[15];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_1000_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[15])) * ((int64_t)((int32_t)context->gpr[8])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_1000_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[8]) + ((uint64_t)context->gpr[15]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[15] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_1000_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[8] + context->gpr[15];
	context->t = (((context->gpr[8] ^ (~context->gpr[15]))) & (context->gpr[8] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[15] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_1001_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[15] - context->gpr[9];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_1001_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[15] >= context->gpr[9]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_1001_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[15]) >= ((int32_t)context->gpr[9])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_1001_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[15]) << 1 | ((uint64_t)context->gpr[15]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[15] >> 24 & 128U;
	context->gpr[15] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[15]) - ((uint64_t)context->gpr[9]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[15] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[9]) + ((uint64_t)context->gpr[15]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[15] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_1001_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[15] & 4294967295)) * ((uint64_t)(context->gpr[9] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_1001_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[9]) - ((uint64_t)context->gpr[15]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_1001_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[15]) >= ((int32_t)context->gpr[9])) {
	if (context->gpr[15] == context->gpr[9]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_1001_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[15] = context->gpr[15] - context->gpr[9];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_1001_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[15]) - ((uint64_t)context->gpr[9]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[15] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_1001_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[15] - context->gpr[9];
	context->t = (((context->gpr[15] ^ context->gpr[9])) & (context->gpr[15] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[15] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_1001_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[15] = context->gpr[9] + context->gpr[15];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_1001_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[15])) * ((int64_t)((int32_t)context->gpr[9])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_1001_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[9]) + ((uint64_t)context->gpr[15]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[15] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_1001_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[9] + context->gpr[15];
	context->t = (((context->gpr[9] ^ (~context->gpr[15]))) & (context->gpr[9] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[15] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_1010_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[15] - context->gpr[10];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_1010_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[15] >= context->gpr[10]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_1010_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[15]) >= ((int32_t)context->gpr[10])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_1010_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[15]) << 1 | ((uint64_t)context->gpr[15]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[15] >> 24 & 128U;
	context->gpr[15] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[15]) - ((uint64_t)context->gpr[10]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[15] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[10]) + ((uint64_t)context->gpr[15]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[15] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_1010_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[15] & 4294967295)) * ((uint64_t)(context->gpr[10] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_1010_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[10]) - ((uint64_t)context->gpr[15]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_1010_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[15]) >= ((int32_t)context->gpr[10])) {
	if (context->gpr[15] == context->gpr[10]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_1010_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[15] = context->gpr[15] - context->gpr[10];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_1010_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[15]) - ((uint64_t)context->gpr[10]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[15] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_1010_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[15] - context->gpr[10];
	context->t = (((context->gpr[15] ^ context->gpr[10])) & (context->gpr[15] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[15] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_1010_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[15] = context->gpr[10] + context->gpr[15];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_1010_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[15])) * ((int64_t)((int32_t)context->gpr[10])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_1010_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[10]) + ((uint64_t)context->gpr[15]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[15] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_1010_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[10] + context->gpr[15];
	context->t = (((context->gpr[10] ^ (~context->gpr[15]))) & (context->gpr[10] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[15] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_1011_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[15] - context->gpr[11];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_1011_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[15] >= context->gpr[11]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_1011_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[15]) >= ((int32_t)context->gpr[11])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_1011_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[15]) << 1 | ((uint64_t)context->gpr[15]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[15] >> 24 & 128U;
	context->gpr[15] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[15]) - ((uint64_t)context->gpr[11]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[15] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[11]) + ((uint64_t)context->gpr[15]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[15] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_1011_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[15] & 4294967295)) * ((uint64_t)(context->gpr[11] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_1011_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[11]) - ((uint64_t)context->gpr[15]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_1011_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[15]) >= ((int32_t)context->gpr[11])) {
	if (context->gpr[15] == context->gpr[11]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_1011_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[15] = context->gpr[15] - context->gpr[11];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_1011_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[15]) - ((uint64_t)context->gpr[11]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[15] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_1011_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[15] - context->gpr[11];
	context->t = (((context->gpr[15] ^ context->gpr[11])) & (context->gpr[15] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[15] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_1011_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[15] = context->gpr[11] + context->gpr[15];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_1011_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[15])) * ((int64_t)((int32_t)context->gpr[11])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_1011_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[11]) + ((uint64_t)context->gpr[15]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[15] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_1011_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[11] + context->gpr[15];
	context->t = (((context->gpr[11] ^ (~context->gpr[15]))) & (context->gpr[11] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[15] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_1100_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[15] - context->gpr[12];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_1100_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[15] >= context->gpr[12]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_1100_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[15]) >= ((int32_t)context->gpr[12])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_1100_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[15]) << 1 | ((uint64_t)context->gpr[15]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[15] >> 24 & 128U;
	context->gpr[15] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[15]) - ((uint64_t)context->gpr[12]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[15] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[12]) + ((uint64_t)context->gpr[15]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[15] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_1100_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[15] & 4294967295)) * ((uint64_t)(context->gpr[12] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_1100_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[12]) - ((uint64_t)context->gpr[15]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_1100_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[15]) >= ((int32_t)context->gpr[12])) {
	if (context->gpr[15] == context->gpr[12]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_1100_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[15] = context->gpr[15] - context->gpr[12];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_1100_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[15]) - ((uint64_t)context->gpr[12]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[15] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_1100_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[15] - context->gpr[12];
	context->t = (((context->gpr[15] ^ context->gpr[12])) & (context->gpr[15] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[15] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_1100_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[15] = context->gpr[12] + context->gpr[15];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_1100_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[15])) * ((int64_t)((int32_t)context->gpr[12])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_1100_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[12]) + ((uint64_t)context->gpr[15]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[15] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_1100_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[12] + context->gpr[15];
	context->t = (((context->gpr[12] ^ (~context->gpr[15]))) & (context->gpr[12] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[15] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_1101_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[15] - context->gpr[13];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_1101_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[15] >= context->gpr[13]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_1101_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[15]) >= ((int32_t)context->gpr[13])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_1101_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[15]) << 1 | ((uint64_t)context->gpr[15]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[15] >> 24 & 128U;
	context->gpr[15] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[15]) - ((uint64_t)context->gpr[13]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[15] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[13]) + ((uint64_t)context->gpr[15]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[15] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_1101_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[15] & 4294967295)) * ((uint64_t)(context->gpr[13] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_1101_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[13]) - ((uint64_t)context->gpr[15]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_1101_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[15]) >= ((int32_t)context->gpr[13])) {
	if (context->gpr[15] == context->gpr[13]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_1101_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[15] = context->gpr[15] - context->gpr[13];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_1101_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[15]) - ((uint64_t)context->gpr[13]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[15] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_1101_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[15] - context->gpr[13];
	context->t = (((context->gpr[15] ^ context->gpr[13])) & (context->gpr[15] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[15] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_1101_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[15] = context->gpr[13] + context->gpr[15];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_1101_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[15])) * ((int64_t)((int32_t)context->gpr[13])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_1101_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[13]) + ((uint64_t)context->gpr[15]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[15] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_1101_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[13] + context->gpr[15];
	context->t = (((context->gpr[13] ^ (~context->gpr[15]))) & (context->gpr[13] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[15] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_1110_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[15] - context->gpr[14];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_1110_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[15] >= context->gpr[14]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_1110_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[15]) >= ((int32_t)context->gpr[14])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_1110_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[15]) << 1 | ((uint64_t)context->gpr[15]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[15] >> 24 & 128U;
	context->gpr[15] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[15]) - ((uint64_t)context->gpr[14]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[15] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[14]) + ((uint64_t)context->gpr[15]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[15] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_1110_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[15] & 4294967295)) * ((uint64_t)(context->gpr[14] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_1110_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[14]) - ((uint64_t)context->gpr[15]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_1110_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[15]) >= ((int32_t)context->gpr[14])) {
	if (context->gpr[15] == context->gpr[14]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_1110_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[15] = context->gpr[15] - context->gpr[14];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_1110_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[15]) - ((uint64_t)context->gpr[14]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[15] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_1110_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[15] - context->gpr[14];
	context->t = (((context->gpr[15] ^ context->gpr[14])) & (context->gpr[15] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[15] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_1110_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[15] = context->gpr[14] + context->gpr[15];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_1110_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[15])) * ((int64_t)((int32_t)context->gpr[14])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_1110_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[14]) + ((uint64_t)context->gpr[15]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[15] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_1110_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[14] + context->gpr[15];
	context->t = (((context->gpr[14] ^ (~context->gpr[15]))) & (context->gpr[14] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[15] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_rm_rn_M_1111_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp32__ = context->gpr[15] - context->gpr[15];
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphs_rm_rn_M_1111_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->gpr[15] >= context->gpr[15]) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpge_rm_rn_M_1111_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[15]) >= ((int32_t)context->gpr[15])) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void div1_M_1111_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint8_t old_q;
	uint32_t tmp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	old_q = context->q;
	gen_tmp32__ = ((uint64_t)context->gpr[15]) << 1 | ((uint64_t)context->gpr[15]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[15] >> 24 & 128U;
	context->gpr[15] = gen_tmp32__;
	context->q = !context->t;
	context->q = !context->q;
	if (old_q == context->m) {
	gen_tmp64__ = ((uint64_t)context->gpr[15]) - ((uint64_t)context->gpr[15]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[15] = gen_tmp64__;
	} else {
	gen_tmp64__ = ((uint64_t)context->gpr[15]) + ((uint64_t)context->gpr[15]);
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[15] = gen_tmp64__;
	}
	context->t = !context->t;
	context->t = !context->t;
	context->q = context->m ^ context->q;
	context->q = context->t ^ context->q;
	context->t = context->q ^ context->m;
	context->t = !context->t;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmulu_M_1111_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = ((uint64_t)(context->gpr[15] & 4294967295)) * ((uint64_t)(context->gpr[15] & 4294967295));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmphi_rm_rn_M_1111_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t cmp_tmp64__;
	context->cycles += context->opts->gen.clock_divider * 1;
	cmp_tmp64__ = ((uint64_t)context->gpr[15]) - ((uint64_t)context->gpr[15]);
	context->t = cmp_tmp64__ >> 25 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpgt_rm_rn_M_1111_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[15]) >= ((int32_t)context->gpr[15])) {
	if (context->gpr[15] == context->gpr[15]) {
	context->t = 0;
	} else {
	context->t = 1;
	}
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sub_M_1111_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[15] = context->gpr[15] - context->gpr[15];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subc_M_1111_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[15]) - ((uint64_t)context->gpr[15]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[15] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void subv_M_1111_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[15] - context->gpr[15];
	context->t = (((context->gpr[15] ^ context->gpr[15])) & (context->gpr[15] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[15] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_rm_rn_M_1111_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[15] = context->gpr[15] + context->gpr[15];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dmuls_M_1111_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t temp;
	context->cycles += context->opts->gen.clock_divider * 3;
	temp = (int64_t)(((int64_t)((int32_t)context->gpr[15])) * ((int64_t)((int32_t)context->gpr[15])));
	context->macl = temp;
	context->mach = temp >> 32;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addc_rm_rn_M_1111_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[15]) + ((uint64_t)context->gpr[15]) + (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[15] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void addv_rm_rn_M_1111_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[15] + context->gpr[15];
	context->t = (((context->gpr[15] ^ (~context->gpr[15]))) & (context->gpr[15] ^ gen_tmp32__)) >> 24 & 128U;
	context->gpr[15] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void shll_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[0]) << 1ULL;
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[0] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void shlr_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[0] >> 1;
	context->t = context->gpr[0] & 1U;
	context->gpr[0] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sts_mach_rn_predec_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->mach);
	context->did_mem = 1;
	context->gpr[0] = context->gpr[0] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void stc_sr_rn_predec_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->sr = 240 & context->sr;
	if (context->t) {
	context->sr = 1 | context->sr;
	}
	if (context->s) {
	context->sr = 2 | context->sr;
	}
	if (context->q) {
	context->sr = 256 | context->sr;
	}
	if (context->m) {
	context->sr = 512 | context->sr;
	}
	context->scratch2 = context->gpr[0] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->sr);
	context->did_mem = 1;
	context->gpr[0] = context->gpr[0] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void rotl_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[0] = context->gpr[0] << 1 | context->gpr[0] >> (32 - 1);
	context->t = context->gpr[0] & 1U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void rotr_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[0] = context->gpr[0] >> 1 | context->gpr[0] << (32 - 1);
	context->t = context->gpr[0] >> 24 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void lds_rm_postinc_mach_M_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[0] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[0], context);
	context->mach = context->scratch1;
	context->gpr[0] = 4 + context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void ldc_rm_postinc_sr_M_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[0] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[0], context);
	context->cycles += context->opts->gen.clock_divider * 2;
	context->sr = context->scratch1 & 1011;
	context->gpr[0] = 4 + context->gpr[0];
	context->sr = 1011 & context->sr;
	context->t = context->sr & 1;
	context->s = context->sr >> 1;
	context->s = 1 & context->s;
	context->q = context->sr >> 8;
	context->q = 1 & context->q;
	context->m = context->sr >> 9;
	context->m = 1 & context->m;
	sh2_sync_cycle(context, target_cycle);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void shll2_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[0] = context->gpr[0] << 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void shlr2_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[0] = context->gpr[0] >> 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void lds_mach_M_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->mach = context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void jsr_M_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->pr = context->pc + 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = context->gpr[0] - 2;
	context->cycles += context->opts->gen.clock_divider * 1;
}
static void ldc_rm_sr_M_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->sr = context->gpr[0] & 1011;
	context->sr = 1011 & context->sr;
	context->t = context->sr & 1;
	context->s = context->sr >> 1;
	context->s = 1 & context->s;
	context->q = context->sr >> 8;
	context->q = 1 & context->q;
	context->m = context->sr >> 9;
	context->m = 1 & context->m;
	sh2_sync_cycle(context, target_cycle);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void mac_w_M_0000_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[0] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[0], context);
	context->gpr[0] = 2 + context->gpr[0];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[0] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[0], context);
	context->gpr[0] = 2 + context->gpr[0];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dt_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[0] = context->gpr[0] - 1;
	context->t = context->gpr[0] == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmppz_rn_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t cmp_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[0]) >= ((int32_t)0)) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sts_macl_rn_predec_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->macl);
	context->did_mem = 1;
	context->gpr[0] = context->gpr[0] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void stc_gbr_rn_predec_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->scratch2 = context->gpr[0] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gbr);
	context->did_mem = 1;
	context->gpr[0] = context->gpr[0] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void cmppl_rn_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t cmp_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[0]) >= ((int32_t)1)) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void lds_rm_postinc_macl_M_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[0] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[0], context);
	context->macl = context->scratch1;
	context->gpr[0] = 4 + context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void ldc_rm_postinc_gbr_M_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[0] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[0], context);
	context->cycles += context->opts->gen.clock_divider * 2;
	context->gbr = context->scratch1;
	context->gpr[0] = 4 + context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void shll8_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[0] = context->gpr[0] << 8;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void shlr8_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[0] = context->gpr[0] >> 8;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void lds_macl_M_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->macl = context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void tas_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t cmp_tmp32__;
	uint32_t sh2_read8_tmp;
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (536870912 >= context->gpr[0]) {
	context->scratch1 = context->gpr[0] | 536870912;
	} else {
	context->scratch1 = context->gpr[0];
	}
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->cycles += context->opts->gen.clock_divider * 3;
	context->t = !context->scratch1;
	context->scratch1 = 128 | context->scratch1;
	sh2_write8_tmp = context->gpr[0] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[0], context, context->scratch1);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void ldc_rm_gbr_M_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gbr = context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void mac_w_M_0001_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[0] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[0], context);
	context->gpr[0] = 2 + context->gpr[0];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[1] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[1], context);
	context->gpr[1] = 2 + context->gpr[1];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void shal_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[0]) << 1ULL;
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[0] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void shar_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = (context->gpr[0] >> 1) | ((context->gpr[0] & 2147483648) && 1 ? 0xFFFFFFFFU << (32 - 1) : 0);
	context->t = context->gpr[0] & 1U;
	context->gpr[0] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sts_pr_rn_predec_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[0] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->pr);
	context->did_mem = 1;
	context->gpr[0] = context->gpr[0] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void stc_vbr_rn_predec_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->scratch2 = context->gpr[0] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->vbr);
	context->did_mem = 1;
	context->gpr[0] = context->gpr[0] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void rotcl_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = ((uint64_t)context->gpr[0]) << 1 | ((uint64_t)context->gpr[0]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[0] >> 24 & 128U;
	context->gpr[0] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void rotcr_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = ((uint64_t)context->gpr[0]) >> 1 | ((uint64_t)context->gpr[0]) << (32 + 1 - 1) | (context->t ? 1 : 0) << (32-1);
	context->t = context->gpr[0] & 1U;
	context->gpr[0] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void lds_rm_postinc_pr_M_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[0] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[0], context);
	context->pr = context->scratch1;
	context->gpr[0] = 4 + context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void ldc_rm_postinc_vbr_M_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[0] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[0], context);
	context->cycles += context->opts->gen.clock_divider * 2;
	context->vbr = context->scratch1;
	context->gpr[0] = 4 + context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void shll16_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[0] = context->gpr[0] << 16;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void shlr16_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[0] = context->gpr[0] >> 16;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void lds_pr_M_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->pr = context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void jmp_M_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = context->gpr[0] - 2;
	context->cycles += context->opts->gen.clock_divider * 1;
}
static void ldc_rm_vbr_M_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->vbr = context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void mac_w_M_0010_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[0] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[0], context);
	context->gpr[0] = 2 + context->gpr[0];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[2] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[2], context);
	context->gpr[2] = 2 + context->gpr[2];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_w_M_0011_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[0] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[0], context);
	context->gpr[0] = 2 + context->gpr[0];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[3] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[3], context);
	context->gpr[3] = 2 + context->gpr[3];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_w_M_0100_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[0] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[0], context);
	context->gpr[0] = 2 + context->gpr[0];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[4] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[4], context);
	context->gpr[4] = 2 + context->gpr[4];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_w_M_0101_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[0] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[0], context);
	context->gpr[0] = 2 + context->gpr[0];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[5] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[5], context);
	context->gpr[5] = 2 + context->gpr[5];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_w_M_0110_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[0] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[0], context);
	context->gpr[0] = 2 + context->gpr[0];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[6] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[6], context);
	context->gpr[6] = 2 + context->gpr[6];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_w_M_0111_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[0] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[0], context);
	context->gpr[0] = 2 + context->gpr[0];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[7] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[7], context);
	context->gpr[7] = 2 + context->gpr[7];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_w_M_1000_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[0] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[0], context);
	context->gpr[0] = 2 + context->gpr[0];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[8] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[8], context);
	context->gpr[8] = 2 + context->gpr[8];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_w_M_1001_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[0] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[0], context);
	context->gpr[0] = 2 + context->gpr[0];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[9] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[9], context);
	context->gpr[9] = 2 + context->gpr[9];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_w_M_1010_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[0] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[0], context);
	context->gpr[0] = 2 + context->gpr[0];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[10] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[10], context);
	context->gpr[10] = 2 + context->gpr[10];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_w_M_1011_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[0] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[0], context);
	context->gpr[0] = 2 + context->gpr[0];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[11] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[11], context);
	context->gpr[11] = 2 + context->gpr[11];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_w_M_1100_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[0] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[0], context);
	context->gpr[0] = 2 + context->gpr[0];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[12] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[12], context);
	context->gpr[12] = 2 + context->gpr[12];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_w_M_1101_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[0] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[0], context);
	context->gpr[0] = 2 + context->gpr[0];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[13] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[13], context);
	context->gpr[13] = 2 + context->gpr[13];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_w_M_1110_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[0] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[0], context);
	context->gpr[0] = 2 + context->gpr[0];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[14] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[14], context);
	context->gpr[14] = 2 + context->gpr[14];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_w_M_1111_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[0] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[0], context);
	context->gpr[0] = 2 + context->gpr[0];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[15] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[15], context);
	context->gpr[15] = 2 + context->gpr[15];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void shll_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[1]) << 1ULL;
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[1] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void shlr_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[1] >> 1;
	context->t = context->gpr[1] & 1U;
	context->gpr[1] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sts_mach_rn_predec_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[1] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->mach);
	context->did_mem = 1;
	context->gpr[1] = context->gpr[1] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void stc_sr_rn_predec_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->sr = 240 & context->sr;
	if (context->t) {
	context->sr = 1 | context->sr;
	}
	if (context->s) {
	context->sr = 2 | context->sr;
	}
	if (context->q) {
	context->sr = 256 | context->sr;
	}
	if (context->m) {
	context->sr = 512 | context->sr;
	}
	context->scratch2 = context->gpr[1] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->sr);
	context->did_mem = 1;
	context->gpr[1] = context->gpr[1] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void rotl_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[1] = context->gpr[1] << 1 | context->gpr[1] >> (32 - 1);
	context->t = context->gpr[1] & 1U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void rotr_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[1] = context->gpr[1] >> 1 | context->gpr[1] << (32 - 1);
	context->t = context->gpr[1] >> 24 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void lds_rm_postinc_mach_M_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[1] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[1], context);
	context->mach = context->scratch1;
	context->gpr[1] = 4 + context->gpr[1];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void ldc_rm_postinc_sr_M_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[1] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[1], context);
	context->cycles += context->opts->gen.clock_divider * 2;
	context->sr = context->scratch1 & 1011;
	context->gpr[1] = 4 + context->gpr[1];
	context->sr = 1011 & context->sr;
	context->t = context->sr & 1;
	context->s = context->sr >> 1;
	context->s = 1 & context->s;
	context->q = context->sr >> 8;
	context->q = 1 & context->q;
	context->m = context->sr >> 9;
	context->m = 1 & context->m;
	sh2_sync_cycle(context, target_cycle);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void shll2_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[1] = context->gpr[1] << 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void shlr2_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[1] = context->gpr[1] >> 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void lds_mach_M_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->mach = context->gpr[1];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void jsr_M_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->pr = context->pc + 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = context->gpr[1] - 2;
	context->cycles += context->opts->gen.clock_divider * 1;
}
static void ldc_rm_sr_M_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->sr = context->gpr[1] & 1011;
	context->sr = 1011 & context->sr;
	context->t = context->sr & 1;
	context->s = context->sr >> 1;
	context->s = 1 & context->s;
	context->q = context->sr >> 8;
	context->q = 1 & context->q;
	context->m = context->sr >> 9;
	context->m = 1 & context->m;
	sh2_sync_cycle(context, target_cycle);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void mac_w_M_0000_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[1] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[1], context);
	context->gpr[1] = 2 + context->gpr[1];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[0] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[0], context);
	context->gpr[0] = 2 + context->gpr[0];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dt_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[1] = context->gpr[1] - 1;
	context->t = context->gpr[1] == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmppz_rn_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[1]) >= ((int32_t)0)) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sts_macl_rn_predec_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[1] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->macl);
	context->did_mem = 1;
	context->gpr[1] = context->gpr[1] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void stc_gbr_rn_predec_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->scratch2 = context->gpr[1] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gbr);
	context->did_mem = 1;
	context->gpr[1] = context->gpr[1] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void cmppl_rn_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[1]) >= ((int32_t)1)) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void lds_rm_postinc_macl_M_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[1] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[1], context);
	context->macl = context->scratch1;
	context->gpr[1] = 4 + context->gpr[1];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void ldc_rm_postinc_gbr_M_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[1] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[1], context);
	context->cycles += context->opts->gen.clock_divider * 2;
	context->gbr = context->scratch1;
	context->gpr[1] = 4 + context->gpr[1];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void shll8_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[1] = context->gpr[1] << 8;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void shlr8_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[1] = context->gpr[1] >> 8;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void lds_macl_M_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->macl = context->gpr[1];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void tas_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (536870912 >= context->gpr[1]) {
	context->scratch1 = context->gpr[1] | 536870912;
	} else {
	context->scratch1 = context->gpr[1];
	}
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->cycles += context->opts->gen.clock_divider * 3;
	context->t = !context->scratch1;
	context->scratch1 = 128 | context->scratch1;
	sh2_write8_tmp = context->gpr[1] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[1], context, context->scratch1);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void ldc_rm_gbr_M_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gbr = context->gpr[1];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void mac_w_M_0001_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[1] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[1], context);
	context->gpr[1] = 2 + context->gpr[1];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[1] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[1], context);
	context->gpr[1] = 2 + context->gpr[1];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void shal_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[1]) << 1ULL;
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[1] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void shar_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = (context->gpr[1] >> 1) | ((context->gpr[1] & 2147483648) && 1 ? 0xFFFFFFFFU << (32 - 1) : 0);
	context->t = context->gpr[1] & 1U;
	context->gpr[1] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sts_pr_rn_predec_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[1] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->pr);
	context->did_mem = 1;
	context->gpr[1] = context->gpr[1] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void stc_vbr_rn_predec_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->scratch2 = context->gpr[1] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->vbr);
	context->did_mem = 1;
	context->gpr[1] = context->gpr[1] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void rotcl_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = ((uint64_t)context->gpr[1]) << 1 | ((uint64_t)context->gpr[1]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[1] >> 24 & 128U;
	context->gpr[1] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void rotcr_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = ((uint64_t)context->gpr[1]) >> 1 | ((uint64_t)context->gpr[1]) << (32 + 1 - 1) | (context->t ? 1 : 0) << (32-1);
	context->t = context->gpr[1] & 1U;
	context->gpr[1] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void lds_rm_postinc_pr_M_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[1] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[1], context);
	context->pr = context->scratch1;
	context->gpr[1] = 4 + context->gpr[1];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void ldc_rm_postinc_vbr_M_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[1] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[1], context);
	context->cycles += context->opts->gen.clock_divider * 2;
	context->vbr = context->scratch1;
	context->gpr[1] = 4 + context->gpr[1];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void shll16_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[1] = context->gpr[1] << 16;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void shlr16_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[1] = context->gpr[1] >> 16;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void lds_pr_M_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->pr = context->gpr[1];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void jmp_M_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = context->gpr[1] - 2;
	context->cycles += context->opts->gen.clock_divider * 1;
}
static void ldc_rm_vbr_M_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->vbr = context->gpr[1];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void mac_w_M_0010_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[1] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[1], context);
	context->gpr[1] = 2 + context->gpr[1];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[2] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[2], context);
	context->gpr[2] = 2 + context->gpr[2];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_w_M_0011_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[1] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[1], context);
	context->gpr[1] = 2 + context->gpr[1];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[3] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[3], context);
	context->gpr[3] = 2 + context->gpr[3];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_w_M_0100_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[1] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[1], context);
	context->gpr[1] = 2 + context->gpr[1];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[4] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[4], context);
	context->gpr[4] = 2 + context->gpr[4];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_w_M_0101_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[1] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[1], context);
	context->gpr[1] = 2 + context->gpr[1];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[5] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[5], context);
	context->gpr[5] = 2 + context->gpr[5];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_w_M_0110_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[1] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[1], context);
	context->gpr[1] = 2 + context->gpr[1];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[6] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[6], context);
	context->gpr[6] = 2 + context->gpr[6];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_w_M_0111_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[1] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[1], context);
	context->gpr[1] = 2 + context->gpr[1];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[7] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[7], context);
	context->gpr[7] = 2 + context->gpr[7];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_w_M_1000_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[1] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[1], context);
	context->gpr[1] = 2 + context->gpr[1];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[8] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[8], context);
	context->gpr[8] = 2 + context->gpr[8];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_w_M_1001_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[1] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[1], context);
	context->gpr[1] = 2 + context->gpr[1];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[9] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[9], context);
	context->gpr[9] = 2 + context->gpr[9];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_w_M_1010_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[1] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[1], context);
	context->gpr[1] = 2 + context->gpr[1];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[10] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[10], context);
	context->gpr[10] = 2 + context->gpr[10];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_w_M_1011_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[1] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[1], context);
	context->gpr[1] = 2 + context->gpr[1];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[11] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[11], context);
	context->gpr[11] = 2 + context->gpr[11];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_w_M_1100_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[1] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[1], context);
	context->gpr[1] = 2 + context->gpr[1];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[12] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[12], context);
	context->gpr[12] = 2 + context->gpr[12];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_w_M_1101_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[1] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[1], context);
	context->gpr[1] = 2 + context->gpr[1];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[13] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[13], context);
	context->gpr[13] = 2 + context->gpr[13];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_w_M_1110_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[1] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[1], context);
	context->gpr[1] = 2 + context->gpr[1];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[14] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[14], context);
	context->gpr[14] = 2 + context->gpr[14];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_w_M_1111_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[1] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[1], context);
	context->gpr[1] = 2 + context->gpr[1];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[15] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[15], context);
	context->gpr[15] = 2 + context->gpr[15];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void shll_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[2]) << 1ULL;
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[2] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void shlr_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[2] >> 1;
	context->t = context->gpr[2] & 1U;
	context->gpr[2] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sts_mach_rn_predec_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[2] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->mach);
	context->did_mem = 1;
	context->gpr[2] = context->gpr[2] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void stc_sr_rn_predec_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->sr = 240 & context->sr;
	if (context->t) {
	context->sr = 1 | context->sr;
	}
	if (context->s) {
	context->sr = 2 | context->sr;
	}
	if (context->q) {
	context->sr = 256 | context->sr;
	}
	if (context->m) {
	context->sr = 512 | context->sr;
	}
	context->scratch2 = context->gpr[2] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->sr);
	context->did_mem = 1;
	context->gpr[2] = context->gpr[2] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void rotl_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[2] = context->gpr[2] << 1 | context->gpr[2] >> (32 - 1);
	context->t = context->gpr[2] & 1U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void rotr_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[2] = context->gpr[2] >> 1 | context->gpr[2] << (32 - 1);
	context->t = context->gpr[2] >> 24 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void lds_rm_postinc_mach_M_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[2] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[2], context);
	context->mach = context->scratch1;
	context->gpr[2] = 4 + context->gpr[2];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void ldc_rm_postinc_sr_M_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[2] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[2], context);
	context->cycles += context->opts->gen.clock_divider * 2;
	context->sr = context->scratch1 & 1011;
	context->gpr[2] = 4 + context->gpr[2];
	context->sr = 1011 & context->sr;
	context->t = context->sr & 1;
	context->s = context->sr >> 1;
	context->s = 1 & context->s;
	context->q = context->sr >> 8;
	context->q = 1 & context->q;
	context->m = context->sr >> 9;
	context->m = 1 & context->m;
	sh2_sync_cycle(context, target_cycle);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void shll2_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[2] = context->gpr[2] << 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void shlr2_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[2] = context->gpr[2] >> 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void lds_mach_M_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->mach = context->gpr[2];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void jsr_M_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->pr = context->pc + 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = context->gpr[2] - 2;
	context->cycles += context->opts->gen.clock_divider * 1;
}
static void ldc_rm_sr_M_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->sr = context->gpr[2] & 1011;
	context->sr = 1011 & context->sr;
	context->t = context->sr & 1;
	context->s = context->sr >> 1;
	context->s = 1 & context->s;
	context->q = context->sr >> 8;
	context->q = 1 & context->q;
	context->m = context->sr >> 9;
	context->m = 1 & context->m;
	sh2_sync_cycle(context, target_cycle);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void mac_w_M_0000_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[2] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[2], context);
	context->gpr[2] = 2 + context->gpr[2];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[0] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[0], context);
	context->gpr[0] = 2 + context->gpr[0];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dt_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[2] = context->gpr[2] - 1;
	context->t = context->gpr[2] == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmppz_rn_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[2]) >= ((int32_t)0)) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sts_macl_rn_predec_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[2] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->macl);
	context->did_mem = 1;
	context->gpr[2] = context->gpr[2] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void stc_gbr_rn_predec_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->scratch2 = context->gpr[2] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gbr);
	context->did_mem = 1;
	context->gpr[2] = context->gpr[2] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void cmppl_rn_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[2]) >= ((int32_t)1)) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void lds_rm_postinc_macl_M_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[2] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[2], context);
	context->macl = context->scratch1;
	context->gpr[2] = 4 + context->gpr[2];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void ldc_rm_postinc_gbr_M_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[2] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[2], context);
	context->cycles += context->opts->gen.clock_divider * 2;
	context->gbr = context->scratch1;
	context->gpr[2] = 4 + context->gpr[2];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void shll8_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[2] = context->gpr[2] << 8;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void shlr8_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[2] = context->gpr[2] >> 8;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void lds_macl_M_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->macl = context->gpr[2];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void tas_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (536870912 >= context->gpr[2]) {
	context->scratch1 = context->gpr[2] | 536870912;
	} else {
	context->scratch1 = context->gpr[2];
	}
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->cycles += context->opts->gen.clock_divider * 3;
	context->t = !context->scratch1;
	context->scratch1 = 128 | context->scratch1;
	sh2_write8_tmp = context->gpr[2] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[2], context, context->scratch1);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void ldc_rm_gbr_M_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gbr = context->gpr[2];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void mac_w_M_0001_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[2] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[2], context);
	context->gpr[2] = 2 + context->gpr[2];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[1] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[1], context);
	context->gpr[1] = 2 + context->gpr[1];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void shal_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[2]) << 1ULL;
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[2] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void shar_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = (context->gpr[2] >> 1) | ((context->gpr[2] & 2147483648) && 1 ? 0xFFFFFFFFU << (32 - 1) : 0);
	context->t = context->gpr[2] & 1U;
	context->gpr[2] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sts_pr_rn_predec_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[2] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->pr);
	context->did_mem = 1;
	context->gpr[2] = context->gpr[2] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void stc_vbr_rn_predec_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->scratch2 = context->gpr[2] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->vbr);
	context->did_mem = 1;
	context->gpr[2] = context->gpr[2] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void rotcl_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = ((uint64_t)context->gpr[2]) << 1 | ((uint64_t)context->gpr[2]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[2] >> 24 & 128U;
	context->gpr[2] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void rotcr_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = ((uint64_t)context->gpr[2]) >> 1 | ((uint64_t)context->gpr[2]) << (32 + 1 - 1) | (context->t ? 1 : 0) << (32-1);
	context->t = context->gpr[2] & 1U;
	context->gpr[2] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void lds_rm_postinc_pr_M_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[2] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[2], context);
	context->pr = context->scratch1;
	context->gpr[2] = 4 + context->gpr[2];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void ldc_rm_postinc_vbr_M_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[2] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[2], context);
	context->cycles += context->opts->gen.clock_divider * 2;
	context->vbr = context->scratch1;
	context->gpr[2] = 4 + context->gpr[2];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void shll16_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[2] = context->gpr[2] << 16;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void shlr16_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[2] = context->gpr[2] >> 16;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void lds_pr_M_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->pr = context->gpr[2];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void jmp_M_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = context->gpr[2] - 2;
	context->cycles += context->opts->gen.clock_divider * 1;
}
static void ldc_rm_vbr_M_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->vbr = context->gpr[2];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void mac_w_M_0010_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[2] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[2], context);
	context->gpr[2] = 2 + context->gpr[2];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[2] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[2], context);
	context->gpr[2] = 2 + context->gpr[2];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_w_M_0011_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[2] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[2], context);
	context->gpr[2] = 2 + context->gpr[2];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[3] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[3], context);
	context->gpr[3] = 2 + context->gpr[3];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_w_M_0100_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[2] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[2], context);
	context->gpr[2] = 2 + context->gpr[2];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[4] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[4], context);
	context->gpr[4] = 2 + context->gpr[4];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_w_M_0101_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[2] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[2], context);
	context->gpr[2] = 2 + context->gpr[2];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[5] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[5], context);
	context->gpr[5] = 2 + context->gpr[5];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_w_M_0110_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[2] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[2], context);
	context->gpr[2] = 2 + context->gpr[2];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[6] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[6], context);
	context->gpr[6] = 2 + context->gpr[6];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_w_M_0111_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[2] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[2], context);
	context->gpr[2] = 2 + context->gpr[2];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[7] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[7], context);
	context->gpr[7] = 2 + context->gpr[7];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_w_M_1000_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[2] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[2], context);
	context->gpr[2] = 2 + context->gpr[2];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[8] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[8], context);
	context->gpr[8] = 2 + context->gpr[8];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_w_M_1001_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[2] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[2], context);
	context->gpr[2] = 2 + context->gpr[2];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[9] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[9], context);
	context->gpr[9] = 2 + context->gpr[9];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_w_M_1010_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[2] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[2], context);
	context->gpr[2] = 2 + context->gpr[2];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[10] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[10], context);
	context->gpr[10] = 2 + context->gpr[10];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_w_M_1011_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[2] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[2], context);
	context->gpr[2] = 2 + context->gpr[2];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[11] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[11], context);
	context->gpr[11] = 2 + context->gpr[11];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_w_M_1100_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[2] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[2], context);
	context->gpr[2] = 2 + context->gpr[2];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[12] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[12], context);
	context->gpr[12] = 2 + context->gpr[12];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_w_M_1101_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[2] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[2], context);
	context->gpr[2] = 2 + context->gpr[2];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[13] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[13], context);
	context->gpr[13] = 2 + context->gpr[13];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_w_M_1110_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[2] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[2], context);
	context->gpr[2] = 2 + context->gpr[2];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[14] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[14], context);
	context->gpr[14] = 2 + context->gpr[14];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_w_M_1111_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[2] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[2], context);
	context->gpr[2] = 2 + context->gpr[2];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[15] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[15], context);
	context->gpr[15] = 2 + context->gpr[15];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void shll_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[3]) << 1ULL;
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[3] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void shlr_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[3] >> 1;
	context->t = context->gpr[3] & 1U;
	context->gpr[3] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sts_mach_rn_predec_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[3] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->mach);
	context->did_mem = 1;
	context->gpr[3] = context->gpr[3] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void stc_sr_rn_predec_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->sr = 240 & context->sr;
	if (context->t) {
	context->sr = 1 | context->sr;
	}
	if (context->s) {
	context->sr = 2 | context->sr;
	}
	if (context->q) {
	context->sr = 256 | context->sr;
	}
	if (context->m) {
	context->sr = 512 | context->sr;
	}
	context->scratch2 = context->gpr[3] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->sr);
	context->did_mem = 1;
	context->gpr[3] = context->gpr[3] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void rotl_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[3] = context->gpr[3] << 1 | context->gpr[3] >> (32 - 1);
	context->t = context->gpr[3] & 1U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void rotr_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[3] = context->gpr[3] >> 1 | context->gpr[3] << (32 - 1);
	context->t = context->gpr[3] >> 24 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void lds_rm_postinc_mach_M_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[3] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[3], context);
	context->mach = context->scratch1;
	context->gpr[3] = 4 + context->gpr[3];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void ldc_rm_postinc_sr_M_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[3] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[3], context);
	context->cycles += context->opts->gen.clock_divider * 2;
	context->sr = context->scratch1 & 1011;
	context->gpr[3] = 4 + context->gpr[3];
	context->sr = 1011 & context->sr;
	context->t = context->sr & 1;
	context->s = context->sr >> 1;
	context->s = 1 & context->s;
	context->q = context->sr >> 8;
	context->q = 1 & context->q;
	context->m = context->sr >> 9;
	context->m = 1 & context->m;
	sh2_sync_cycle(context, target_cycle);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void shll2_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[3] = context->gpr[3] << 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void shlr2_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[3] = context->gpr[3] >> 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void lds_mach_M_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->mach = context->gpr[3];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void jsr_M_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->pr = context->pc + 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = context->gpr[3] - 2;
	context->cycles += context->opts->gen.clock_divider * 1;
}
static void ldc_rm_sr_M_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->sr = context->gpr[3] & 1011;
	context->sr = 1011 & context->sr;
	context->t = context->sr & 1;
	context->s = context->sr >> 1;
	context->s = 1 & context->s;
	context->q = context->sr >> 8;
	context->q = 1 & context->q;
	context->m = context->sr >> 9;
	context->m = 1 & context->m;
	sh2_sync_cycle(context, target_cycle);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void mac_w_M_0000_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[3] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[3], context);
	context->gpr[3] = 2 + context->gpr[3];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[0] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[0], context);
	context->gpr[0] = 2 + context->gpr[0];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dt_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[3] = context->gpr[3] - 1;
	context->t = context->gpr[3] == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmppz_rn_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[3]) >= ((int32_t)0)) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sts_macl_rn_predec_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[3] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->macl);
	context->did_mem = 1;
	context->gpr[3] = context->gpr[3] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void stc_gbr_rn_predec_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->scratch2 = context->gpr[3] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gbr);
	context->did_mem = 1;
	context->gpr[3] = context->gpr[3] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void cmppl_rn_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[3]) >= ((int32_t)1)) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void lds_rm_postinc_macl_M_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[3] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[3], context);
	context->macl = context->scratch1;
	context->gpr[3] = 4 + context->gpr[3];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void ldc_rm_postinc_gbr_M_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[3] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[3], context);
	context->cycles += context->opts->gen.clock_divider * 2;
	context->gbr = context->scratch1;
	context->gpr[3] = 4 + context->gpr[3];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void shll8_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[3] = context->gpr[3] << 8;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void shlr8_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[3] = context->gpr[3] >> 8;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void lds_macl_M_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->macl = context->gpr[3];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void tas_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (536870912 >= context->gpr[3]) {
	context->scratch1 = context->gpr[3] | 536870912;
	} else {
	context->scratch1 = context->gpr[3];
	}
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->cycles += context->opts->gen.clock_divider * 3;
	context->t = !context->scratch1;
	context->scratch1 = 128 | context->scratch1;
	sh2_write8_tmp = context->gpr[3] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[3], context, context->scratch1);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void ldc_rm_gbr_M_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gbr = context->gpr[3];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void mac_w_M_0001_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[3] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[3], context);
	context->gpr[3] = 2 + context->gpr[3];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[1] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[1], context);
	context->gpr[1] = 2 + context->gpr[1];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void shal_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[3]) << 1ULL;
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[3] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void shar_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = (context->gpr[3] >> 1) | ((context->gpr[3] & 2147483648) && 1 ? 0xFFFFFFFFU << (32 - 1) : 0);
	context->t = context->gpr[3] & 1U;
	context->gpr[3] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sts_pr_rn_predec_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[3] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->pr);
	context->did_mem = 1;
	context->gpr[3] = context->gpr[3] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void stc_vbr_rn_predec_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->scratch2 = context->gpr[3] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->vbr);
	context->did_mem = 1;
	context->gpr[3] = context->gpr[3] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void rotcl_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = ((uint64_t)context->gpr[3]) << 1 | ((uint64_t)context->gpr[3]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[3] >> 24 & 128U;
	context->gpr[3] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void rotcr_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = ((uint64_t)context->gpr[3]) >> 1 | ((uint64_t)context->gpr[3]) << (32 + 1 - 1) | (context->t ? 1 : 0) << (32-1);
	context->t = context->gpr[3] & 1U;
	context->gpr[3] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void lds_rm_postinc_pr_M_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[3] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[3], context);
	context->pr = context->scratch1;
	context->gpr[3] = 4 + context->gpr[3];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void ldc_rm_postinc_vbr_M_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[3] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[3], context);
	context->cycles += context->opts->gen.clock_divider * 2;
	context->vbr = context->scratch1;
	context->gpr[3] = 4 + context->gpr[3];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void shll16_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[3] = context->gpr[3] << 16;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void shlr16_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[3] = context->gpr[3] >> 16;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void lds_pr_M_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->pr = context->gpr[3];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void jmp_M_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = context->gpr[3] - 2;
	context->cycles += context->opts->gen.clock_divider * 1;
}
static void ldc_rm_vbr_M_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->vbr = context->gpr[3];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void mac_w_M_0010_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[3] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[3], context);
	context->gpr[3] = 2 + context->gpr[3];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[2] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[2], context);
	context->gpr[2] = 2 + context->gpr[2];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_w_M_0011_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[3] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[3], context);
	context->gpr[3] = 2 + context->gpr[3];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[3] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[3], context);
	context->gpr[3] = 2 + context->gpr[3];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_w_M_0100_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[3] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[3], context);
	context->gpr[3] = 2 + context->gpr[3];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[4] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[4], context);
	context->gpr[4] = 2 + context->gpr[4];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_w_M_0101_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[3] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[3], context);
	context->gpr[3] = 2 + context->gpr[3];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[5] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[5], context);
	context->gpr[5] = 2 + context->gpr[5];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_w_M_0110_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[3] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[3], context);
	context->gpr[3] = 2 + context->gpr[3];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[6] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[6], context);
	context->gpr[6] = 2 + context->gpr[6];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_w_M_0111_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[3] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[3], context);
	context->gpr[3] = 2 + context->gpr[3];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[7] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[7], context);
	context->gpr[7] = 2 + context->gpr[7];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_w_M_1000_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[3] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[3], context);
	context->gpr[3] = 2 + context->gpr[3];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[8] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[8], context);
	context->gpr[8] = 2 + context->gpr[8];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_w_M_1001_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[3] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[3], context);
	context->gpr[3] = 2 + context->gpr[3];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[9] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[9], context);
	context->gpr[9] = 2 + context->gpr[9];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_w_M_1010_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[3] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[3], context);
	context->gpr[3] = 2 + context->gpr[3];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[10] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[10], context);
	context->gpr[10] = 2 + context->gpr[10];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_w_M_1011_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[3] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[3], context);
	context->gpr[3] = 2 + context->gpr[3];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[11] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[11], context);
	context->gpr[11] = 2 + context->gpr[11];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_w_M_1100_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[3] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[3], context);
	context->gpr[3] = 2 + context->gpr[3];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[12] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[12], context);
	context->gpr[12] = 2 + context->gpr[12];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_w_M_1101_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[3] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[3], context);
	context->gpr[3] = 2 + context->gpr[3];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[13] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[13], context);
	context->gpr[13] = 2 + context->gpr[13];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_w_M_1110_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[3] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[3], context);
	context->gpr[3] = 2 + context->gpr[3];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[14] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[14], context);
	context->gpr[14] = 2 + context->gpr[14];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_w_M_1111_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[3] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[3], context);
	context->gpr[3] = 2 + context->gpr[3];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[15] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[15], context);
	context->gpr[15] = 2 + context->gpr[15];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void shll_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[4]) << 1ULL;
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[4] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void shlr_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[4] >> 1;
	context->t = context->gpr[4] & 1U;
	context->gpr[4] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sts_mach_rn_predec_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[4] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->mach);
	context->did_mem = 1;
	context->gpr[4] = context->gpr[4] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void stc_sr_rn_predec_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->sr = 240 & context->sr;
	if (context->t) {
	context->sr = 1 | context->sr;
	}
	if (context->s) {
	context->sr = 2 | context->sr;
	}
	if (context->q) {
	context->sr = 256 | context->sr;
	}
	if (context->m) {
	context->sr = 512 | context->sr;
	}
	context->scratch2 = context->gpr[4] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->sr);
	context->did_mem = 1;
	context->gpr[4] = context->gpr[4] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void rotl_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[4] = context->gpr[4] << 1 | context->gpr[4] >> (32 - 1);
	context->t = context->gpr[4] & 1U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void rotr_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[4] = context->gpr[4] >> 1 | context->gpr[4] << (32 - 1);
	context->t = context->gpr[4] >> 24 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void lds_rm_postinc_mach_M_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[4] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[4], context);
	context->mach = context->scratch1;
	context->gpr[4] = 4 + context->gpr[4];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void ldc_rm_postinc_sr_M_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[4] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[4], context);
	context->cycles += context->opts->gen.clock_divider * 2;
	context->sr = context->scratch1 & 1011;
	context->gpr[4] = 4 + context->gpr[4];
	context->sr = 1011 & context->sr;
	context->t = context->sr & 1;
	context->s = context->sr >> 1;
	context->s = 1 & context->s;
	context->q = context->sr >> 8;
	context->q = 1 & context->q;
	context->m = context->sr >> 9;
	context->m = 1 & context->m;
	sh2_sync_cycle(context, target_cycle);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void shll2_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[4] = context->gpr[4] << 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void shlr2_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[4] = context->gpr[4] >> 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void lds_mach_M_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->mach = context->gpr[4];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void jsr_M_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->pr = context->pc + 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = context->gpr[4] - 2;
	context->cycles += context->opts->gen.clock_divider * 1;
}
static void ldc_rm_sr_M_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->sr = context->gpr[4] & 1011;
	context->sr = 1011 & context->sr;
	context->t = context->sr & 1;
	context->s = context->sr >> 1;
	context->s = 1 & context->s;
	context->q = context->sr >> 8;
	context->q = 1 & context->q;
	context->m = context->sr >> 9;
	context->m = 1 & context->m;
	sh2_sync_cycle(context, target_cycle);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void mac_w_M_0000_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[4] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[4], context);
	context->gpr[4] = 2 + context->gpr[4];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[0] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[0], context);
	context->gpr[0] = 2 + context->gpr[0];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dt_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[4] = context->gpr[4] - 1;
	context->t = context->gpr[4] == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmppz_rn_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[4]) >= ((int32_t)0)) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sts_macl_rn_predec_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[4] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->macl);
	context->did_mem = 1;
	context->gpr[4] = context->gpr[4] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void stc_gbr_rn_predec_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->scratch2 = context->gpr[4] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gbr);
	context->did_mem = 1;
	context->gpr[4] = context->gpr[4] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void cmppl_rn_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[4]) >= ((int32_t)1)) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void lds_rm_postinc_macl_M_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[4] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[4], context);
	context->macl = context->scratch1;
	context->gpr[4] = 4 + context->gpr[4];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void ldc_rm_postinc_gbr_M_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[4] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[4], context);
	context->cycles += context->opts->gen.clock_divider * 2;
	context->gbr = context->scratch1;
	context->gpr[4] = 4 + context->gpr[4];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void shll8_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[4] = context->gpr[4] << 8;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void shlr8_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[4] = context->gpr[4] >> 8;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void lds_macl_M_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->macl = context->gpr[4];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void tas_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (536870912 >= context->gpr[4]) {
	context->scratch1 = context->gpr[4] | 536870912;
	} else {
	context->scratch1 = context->gpr[4];
	}
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->cycles += context->opts->gen.clock_divider * 3;
	context->t = !context->scratch1;
	context->scratch1 = 128 | context->scratch1;
	sh2_write8_tmp = context->gpr[4] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[4], context, context->scratch1);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void ldc_rm_gbr_M_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gbr = context->gpr[4];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void mac_w_M_0001_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[4] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[4], context);
	context->gpr[4] = 2 + context->gpr[4];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[1] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[1], context);
	context->gpr[1] = 2 + context->gpr[1];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void shal_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[4]) << 1ULL;
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[4] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void shar_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = (context->gpr[4] >> 1) | ((context->gpr[4] & 2147483648) && 1 ? 0xFFFFFFFFU << (32 - 1) : 0);
	context->t = context->gpr[4] & 1U;
	context->gpr[4] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sts_pr_rn_predec_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[4] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->pr);
	context->did_mem = 1;
	context->gpr[4] = context->gpr[4] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void stc_vbr_rn_predec_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->scratch2 = context->gpr[4] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->vbr);
	context->did_mem = 1;
	context->gpr[4] = context->gpr[4] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void rotcl_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = ((uint64_t)context->gpr[4]) << 1 | ((uint64_t)context->gpr[4]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[4] >> 24 & 128U;
	context->gpr[4] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void rotcr_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = ((uint64_t)context->gpr[4]) >> 1 | ((uint64_t)context->gpr[4]) << (32 + 1 - 1) | (context->t ? 1 : 0) << (32-1);
	context->t = context->gpr[4] & 1U;
	context->gpr[4] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void lds_rm_postinc_pr_M_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[4] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[4], context);
	context->pr = context->scratch1;
	context->gpr[4] = 4 + context->gpr[4];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void ldc_rm_postinc_vbr_M_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[4] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[4], context);
	context->cycles += context->opts->gen.clock_divider * 2;
	context->vbr = context->scratch1;
	context->gpr[4] = 4 + context->gpr[4];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void shll16_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[4] = context->gpr[4] << 16;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void shlr16_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[4] = context->gpr[4] >> 16;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void lds_pr_M_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->pr = context->gpr[4];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void jmp_M_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = context->gpr[4] - 2;
	context->cycles += context->opts->gen.clock_divider * 1;
}
static void ldc_rm_vbr_M_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->vbr = context->gpr[4];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void mac_w_M_0010_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[4] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[4], context);
	context->gpr[4] = 2 + context->gpr[4];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[2] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[2], context);
	context->gpr[2] = 2 + context->gpr[2];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_w_M_0011_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[4] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[4], context);
	context->gpr[4] = 2 + context->gpr[4];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[3] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[3], context);
	context->gpr[3] = 2 + context->gpr[3];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_w_M_0100_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[4] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[4], context);
	context->gpr[4] = 2 + context->gpr[4];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[4] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[4], context);
	context->gpr[4] = 2 + context->gpr[4];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_w_M_0101_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[4] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[4], context);
	context->gpr[4] = 2 + context->gpr[4];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[5] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[5], context);
	context->gpr[5] = 2 + context->gpr[5];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_w_M_0110_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[4] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[4], context);
	context->gpr[4] = 2 + context->gpr[4];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[6] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[6], context);
	context->gpr[6] = 2 + context->gpr[6];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_w_M_0111_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[4] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[4], context);
	context->gpr[4] = 2 + context->gpr[4];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[7] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[7], context);
	context->gpr[7] = 2 + context->gpr[7];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_w_M_1000_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[4] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[4], context);
	context->gpr[4] = 2 + context->gpr[4];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[8] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[8], context);
	context->gpr[8] = 2 + context->gpr[8];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_w_M_1001_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[4] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[4], context);
	context->gpr[4] = 2 + context->gpr[4];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[9] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[9], context);
	context->gpr[9] = 2 + context->gpr[9];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_w_M_1010_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[4] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[4], context);
	context->gpr[4] = 2 + context->gpr[4];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[10] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[10], context);
	context->gpr[10] = 2 + context->gpr[10];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_w_M_1011_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[4] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[4], context);
	context->gpr[4] = 2 + context->gpr[4];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[11] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[11], context);
	context->gpr[11] = 2 + context->gpr[11];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_w_M_1100_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[4] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[4], context);
	context->gpr[4] = 2 + context->gpr[4];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[12] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[12], context);
	context->gpr[12] = 2 + context->gpr[12];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_w_M_1101_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[4] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[4], context);
	context->gpr[4] = 2 + context->gpr[4];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[13] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[13], context);
	context->gpr[13] = 2 + context->gpr[13];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_w_M_1110_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[4] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[4], context);
	context->gpr[4] = 2 + context->gpr[4];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[14] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[14], context);
	context->gpr[14] = 2 + context->gpr[14];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_w_M_1111_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[4] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[4], context);
	context->gpr[4] = 2 + context->gpr[4];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[15] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[15], context);
	context->gpr[15] = 2 + context->gpr[15];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void shll_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[5]) << 1ULL;
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[5] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void shlr_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[5] >> 1;
	context->t = context->gpr[5] & 1U;
	context->gpr[5] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sts_mach_rn_predec_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[5] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->mach);
	context->did_mem = 1;
	context->gpr[5] = context->gpr[5] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void stc_sr_rn_predec_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->sr = 240 & context->sr;
	if (context->t) {
	context->sr = 1 | context->sr;
	}
	if (context->s) {
	context->sr = 2 | context->sr;
	}
	if (context->q) {
	context->sr = 256 | context->sr;
	}
	if (context->m) {
	context->sr = 512 | context->sr;
	}
	context->scratch2 = context->gpr[5] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->sr);
	context->did_mem = 1;
	context->gpr[5] = context->gpr[5] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void rotl_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[5] = context->gpr[5] << 1 | context->gpr[5] >> (32 - 1);
	context->t = context->gpr[5] & 1U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void rotr_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[5] = context->gpr[5] >> 1 | context->gpr[5] << (32 - 1);
	context->t = context->gpr[5] >> 24 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void lds_rm_postinc_mach_M_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[5] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[5], context);
	context->mach = context->scratch1;
	context->gpr[5] = 4 + context->gpr[5];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void ldc_rm_postinc_sr_M_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[5] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[5], context);
	context->cycles += context->opts->gen.clock_divider * 2;
	context->sr = context->scratch1 & 1011;
	context->gpr[5] = 4 + context->gpr[5];
	context->sr = 1011 & context->sr;
	context->t = context->sr & 1;
	context->s = context->sr >> 1;
	context->s = 1 & context->s;
	context->q = context->sr >> 8;
	context->q = 1 & context->q;
	context->m = context->sr >> 9;
	context->m = 1 & context->m;
	sh2_sync_cycle(context, target_cycle);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void shll2_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[5] = context->gpr[5] << 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void shlr2_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[5] = context->gpr[5] >> 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void lds_mach_M_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->mach = context->gpr[5];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void jsr_M_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->pr = context->pc + 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = context->gpr[5] - 2;
	context->cycles += context->opts->gen.clock_divider * 1;
}
static void ldc_rm_sr_M_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->sr = context->gpr[5] & 1011;
	context->sr = 1011 & context->sr;
	context->t = context->sr & 1;
	context->s = context->sr >> 1;
	context->s = 1 & context->s;
	context->q = context->sr >> 8;
	context->q = 1 & context->q;
	context->m = context->sr >> 9;
	context->m = 1 & context->m;
	sh2_sync_cycle(context, target_cycle);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void mac_w_M_0000_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[5] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[5], context);
	context->gpr[5] = 2 + context->gpr[5];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[0] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[0], context);
	context->gpr[0] = 2 + context->gpr[0];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dt_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[5] = context->gpr[5] - 1;
	context->t = context->gpr[5] == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmppz_rn_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[5]) >= ((int32_t)0)) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sts_macl_rn_predec_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[5] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->macl);
	context->did_mem = 1;
	context->gpr[5] = context->gpr[5] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void stc_gbr_rn_predec_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->scratch2 = context->gpr[5] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gbr);
	context->did_mem = 1;
	context->gpr[5] = context->gpr[5] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void cmppl_rn_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[5]) >= ((int32_t)1)) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void lds_rm_postinc_macl_M_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[5] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[5], context);
	context->macl = context->scratch1;
	context->gpr[5] = 4 + context->gpr[5];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void ldc_rm_postinc_gbr_M_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[5] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[5], context);
	context->cycles += context->opts->gen.clock_divider * 2;
	context->gbr = context->scratch1;
	context->gpr[5] = 4 + context->gpr[5];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void shll8_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[5] = context->gpr[5] << 8;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void shlr8_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[5] = context->gpr[5] >> 8;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void lds_macl_M_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->macl = context->gpr[5];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void tas_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (536870912 >= context->gpr[5]) {
	context->scratch1 = context->gpr[5] | 536870912;
	} else {
	context->scratch1 = context->gpr[5];
	}
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->cycles += context->opts->gen.clock_divider * 3;
	context->t = !context->scratch1;
	context->scratch1 = 128 | context->scratch1;
	sh2_write8_tmp = context->gpr[5] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[5], context, context->scratch1);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void ldc_rm_gbr_M_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gbr = context->gpr[5];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void mac_w_M_0001_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[5] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[5], context);
	context->gpr[5] = 2 + context->gpr[5];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[1] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[1], context);
	context->gpr[1] = 2 + context->gpr[1];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void shal_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[5]) << 1ULL;
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[5] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void shar_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = (context->gpr[5] >> 1) | ((context->gpr[5] & 2147483648) && 1 ? 0xFFFFFFFFU << (32 - 1) : 0);
	context->t = context->gpr[5] & 1U;
	context->gpr[5] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sts_pr_rn_predec_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[5] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->pr);
	context->did_mem = 1;
	context->gpr[5] = context->gpr[5] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void stc_vbr_rn_predec_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->scratch2 = context->gpr[5] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->vbr);
	context->did_mem = 1;
	context->gpr[5] = context->gpr[5] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void rotcl_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = ((uint64_t)context->gpr[5]) << 1 | ((uint64_t)context->gpr[5]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[5] >> 24 & 128U;
	context->gpr[5] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void rotcr_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = ((uint64_t)context->gpr[5]) >> 1 | ((uint64_t)context->gpr[5]) << (32 + 1 - 1) | (context->t ? 1 : 0) << (32-1);
	context->t = context->gpr[5] & 1U;
	context->gpr[5] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void lds_rm_postinc_pr_M_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[5] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[5], context);
	context->pr = context->scratch1;
	context->gpr[5] = 4 + context->gpr[5];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void ldc_rm_postinc_vbr_M_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[5] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[5], context);
	context->cycles += context->opts->gen.clock_divider * 2;
	context->vbr = context->scratch1;
	context->gpr[5] = 4 + context->gpr[5];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void shll16_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[5] = context->gpr[5] << 16;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void shlr16_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[5] = context->gpr[5] >> 16;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void lds_pr_M_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->pr = context->gpr[5];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void jmp_M_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = context->gpr[5] - 2;
	context->cycles += context->opts->gen.clock_divider * 1;
}
static void ldc_rm_vbr_M_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->vbr = context->gpr[5];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void mac_w_M_0010_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[5] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[5], context);
	context->gpr[5] = 2 + context->gpr[5];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[2] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[2], context);
	context->gpr[2] = 2 + context->gpr[2];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_w_M_0011_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[5] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[5], context);
	context->gpr[5] = 2 + context->gpr[5];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[3] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[3], context);
	context->gpr[3] = 2 + context->gpr[3];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_w_M_0100_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[5] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[5], context);
	context->gpr[5] = 2 + context->gpr[5];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[4] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[4], context);
	context->gpr[4] = 2 + context->gpr[4];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_w_M_0101_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[5] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[5], context);
	context->gpr[5] = 2 + context->gpr[5];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[5] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[5], context);
	context->gpr[5] = 2 + context->gpr[5];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_w_M_0110_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[5] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[5], context);
	context->gpr[5] = 2 + context->gpr[5];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[6] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[6], context);
	context->gpr[6] = 2 + context->gpr[6];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_w_M_0111_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[5] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[5], context);
	context->gpr[5] = 2 + context->gpr[5];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[7] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[7], context);
	context->gpr[7] = 2 + context->gpr[7];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_w_M_1000_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[5] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[5], context);
	context->gpr[5] = 2 + context->gpr[5];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[8] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[8], context);
	context->gpr[8] = 2 + context->gpr[8];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_w_M_1001_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[5] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[5], context);
	context->gpr[5] = 2 + context->gpr[5];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[9] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[9], context);
	context->gpr[9] = 2 + context->gpr[9];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_w_M_1010_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[5] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[5], context);
	context->gpr[5] = 2 + context->gpr[5];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[10] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[10], context);
	context->gpr[10] = 2 + context->gpr[10];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_w_M_1011_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[5] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[5], context);
	context->gpr[5] = 2 + context->gpr[5];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[11] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[11], context);
	context->gpr[11] = 2 + context->gpr[11];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_w_M_1100_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[5] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[5], context);
	context->gpr[5] = 2 + context->gpr[5];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[12] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[12], context);
	context->gpr[12] = 2 + context->gpr[12];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_w_M_1101_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[5] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[5], context);
	context->gpr[5] = 2 + context->gpr[5];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[13] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[13], context);
	context->gpr[13] = 2 + context->gpr[13];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_w_M_1110_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[5] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[5], context);
	context->gpr[5] = 2 + context->gpr[5];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[14] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[14], context);
	context->gpr[14] = 2 + context->gpr[14];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_w_M_1111_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[5] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[5], context);
	context->gpr[5] = 2 + context->gpr[5];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[15] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[15], context);
	context->gpr[15] = 2 + context->gpr[15];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void shll_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[6]) << 1ULL;
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[6] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void shlr_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[6] >> 1;
	context->t = context->gpr[6] & 1U;
	context->gpr[6] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sts_mach_rn_predec_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[6] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->mach);
	context->did_mem = 1;
	context->gpr[6] = context->gpr[6] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void stc_sr_rn_predec_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->sr = 240 & context->sr;
	if (context->t) {
	context->sr = 1 | context->sr;
	}
	if (context->s) {
	context->sr = 2 | context->sr;
	}
	if (context->q) {
	context->sr = 256 | context->sr;
	}
	if (context->m) {
	context->sr = 512 | context->sr;
	}
	context->scratch2 = context->gpr[6] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->sr);
	context->did_mem = 1;
	context->gpr[6] = context->gpr[6] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void rotl_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[6] = context->gpr[6] << 1 | context->gpr[6] >> (32 - 1);
	context->t = context->gpr[6] & 1U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void rotr_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[6] = context->gpr[6] >> 1 | context->gpr[6] << (32 - 1);
	context->t = context->gpr[6] >> 24 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void lds_rm_postinc_mach_M_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[6] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[6], context);
	context->mach = context->scratch1;
	context->gpr[6] = 4 + context->gpr[6];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void ldc_rm_postinc_sr_M_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[6] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[6], context);
	context->cycles += context->opts->gen.clock_divider * 2;
	context->sr = context->scratch1 & 1011;
	context->gpr[6] = 4 + context->gpr[6];
	context->sr = 1011 & context->sr;
	context->t = context->sr & 1;
	context->s = context->sr >> 1;
	context->s = 1 & context->s;
	context->q = context->sr >> 8;
	context->q = 1 & context->q;
	context->m = context->sr >> 9;
	context->m = 1 & context->m;
	sh2_sync_cycle(context, target_cycle);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void shll2_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[6] = context->gpr[6] << 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void shlr2_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[6] = context->gpr[6] >> 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void lds_mach_M_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->mach = context->gpr[6];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void jsr_M_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->pr = context->pc + 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = context->gpr[6] - 2;
	context->cycles += context->opts->gen.clock_divider * 1;
}
static void ldc_rm_sr_M_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->sr = context->gpr[6] & 1011;
	context->sr = 1011 & context->sr;
	context->t = context->sr & 1;
	context->s = context->sr >> 1;
	context->s = 1 & context->s;
	context->q = context->sr >> 8;
	context->q = 1 & context->q;
	context->m = context->sr >> 9;
	context->m = 1 & context->m;
	sh2_sync_cycle(context, target_cycle);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void mac_w_M_0000_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[6] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[6], context);
	context->gpr[6] = 2 + context->gpr[6];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[0] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[0], context);
	context->gpr[0] = 2 + context->gpr[0];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dt_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[6] = context->gpr[6] - 1;
	context->t = context->gpr[6] == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmppz_rn_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[6]) >= ((int32_t)0)) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sts_macl_rn_predec_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[6] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->macl);
	context->did_mem = 1;
	context->gpr[6] = context->gpr[6] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void stc_gbr_rn_predec_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->scratch2 = context->gpr[6] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gbr);
	context->did_mem = 1;
	context->gpr[6] = context->gpr[6] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void cmppl_rn_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[6]) >= ((int32_t)1)) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void lds_rm_postinc_macl_M_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[6] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[6], context);
	context->macl = context->scratch1;
	context->gpr[6] = 4 + context->gpr[6];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void ldc_rm_postinc_gbr_M_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[6] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[6], context);
	context->cycles += context->opts->gen.clock_divider * 2;
	context->gbr = context->scratch1;
	context->gpr[6] = 4 + context->gpr[6];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void shll8_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[6] = context->gpr[6] << 8;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void shlr8_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[6] = context->gpr[6] >> 8;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void lds_macl_M_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->macl = context->gpr[6];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void tas_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (536870912 >= context->gpr[6]) {
	context->scratch1 = context->gpr[6] | 536870912;
	} else {
	context->scratch1 = context->gpr[6];
	}
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->cycles += context->opts->gen.clock_divider * 3;
	context->t = !context->scratch1;
	context->scratch1 = 128 | context->scratch1;
	sh2_write8_tmp = context->gpr[6] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[6], context, context->scratch1);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void ldc_rm_gbr_M_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gbr = context->gpr[6];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void mac_w_M_0001_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[6] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[6], context);
	context->gpr[6] = 2 + context->gpr[6];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[1] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[1], context);
	context->gpr[1] = 2 + context->gpr[1];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void shal_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[6]) << 1ULL;
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[6] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void shar_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = (context->gpr[6] >> 1) | ((context->gpr[6] & 2147483648) && 1 ? 0xFFFFFFFFU << (32 - 1) : 0);
	context->t = context->gpr[6] & 1U;
	context->gpr[6] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sts_pr_rn_predec_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[6] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->pr);
	context->did_mem = 1;
	context->gpr[6] = context->gpr[6] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void stc_vbr_rn_predec_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->scratch2 = context->gpr[6] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->vbr);
	context->did_mem = 1;
	context->gpr[6] = context->gpr[6] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void rotcl_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = ((uint64_t)context->gpr[6]) << 1 | ((uint64_t)context->gpr[6]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[6] >> 24 & 128U;
	context->gpr[6] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void rotcr_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = ((uint64_t)context->gpr[6]) >> 1 | ((uint64_t)context->gpr[6]) << (32 + 1 - 1) | (context->t ? 1 : 0) << (32-1);
	context->t = context->gpr[6] & 1U;
	context->gpr[6] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void lds_rm_postinc_pr_M_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[6] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[6], context);
	context->pr = context->scratch1;
	context->gpr[6] = 4 + context->gpr[6];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void ldc_rm_postinc_vbr_M_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[6] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[6], context);
	context->cycles += context->opts->gen.clock_divider * 2;
	context->vbr = context->scratch1;
	context->gpr[6] = 4 + context->gpr[6];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void shll16_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[6] = context->gpr[6] << 16;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void shlr16_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[6] = context->gpr[6] >> 16;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void lds_pr_M_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->pr = context->gpr[6];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void jmp_M_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = context->gpr[6] - 2;
	context->cycles += context->opts->gen.clock_divider * 1;
}
static void ldc_rm_vbr_M_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->vbr = context->gpr[6];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void mac_w_M_0010_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[6] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[6], context);
	context->gpr[6] = 2 + context->gpr[6];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[2] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[2], context);
	context->gpr[2] = 2 + context->gpr[2];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_w_M_0011_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[6] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[6], context);
	context->gpr[6] = 2 + context->gpr[6];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[3] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[3], context);
	context->gpr[3] = 2 + context->gpr[3];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_w_M_0100_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[6] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[6], context);
	context->gpr[6] = 2 + context->gpr[6];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[4] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[4], context);
	context->gpr[4] = 2 + context->gpr[4];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_w_M_0101_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[6] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[6], context);
	context->gpr[6] = 2 + context->gpr[6];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[5] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[5], context);
	context->gpr[5] = 2 + context->gpr[5];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_w_M_0110_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[6] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[6], context);
	context->gpr[6] = 2 + context->gpr[6];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[6] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[6], context);
	context->gpr[6] = 2 + context->gpr[6];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_w_M_0111_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[6] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[6], context);
	context->gpr[6] = 2 + context->gpr[6];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[7] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[7], context);
	context->gpr[7] = 2 + context->gpr[7];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_w_M_1000_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[6] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[6], context);
	context->gpr[6] = 2 + context->gpr[6];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[8] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[8], context);
	context->gpr[8] = 2 + context->gpr[8];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_w_M_1001_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[6] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[6], context);
	context->gpr[6] = 2 + context->gpr[6];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[9] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[9], context);
	context->gpr[9] = 2 + context->gpr[9];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_w_M_1010_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[6] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[6], context);
	context->gpr[6] = 2 + context->gpr[6];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[10] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[10], context);
	context->gpr[10] = 2 + context->gpr[10];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_w_M_1011_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[6] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[6], context);
	context->gpr[6] = 2 + context->gpr[6];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[11] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[11], context);
	context->gpr[11] = 2 + context->gpr[11];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_w_M_1100_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[6] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[6], context);
	context->gpr[6] = 2 + context->gpr[6];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[12] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[12], context);
	context->gpr[12] = 2 + context->gpr[12];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_w_M_1101_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[6] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[6], context);
	context->gpr[6] = 2 + context->gpr[6];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[13] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[13], context);
	context->gpr[13] = 2 + context->gpr[13];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_w_M_1110_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[6] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[6], context);
	context->gpr[6] = 2 + context->gpr[6];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[14] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[14], context);
	context->gpr[14] = 2 + context->gpr[14];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_w_M_1111_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[6] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[6], context);
	context->gpr[6] = 2 + context->gpr[6];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[15] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[15], context);
	context->gpr[15] = 2 + context->gpr[15];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void shll_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[7]) << 1ULL;
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[7] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void shlr_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[7] >> 1;
	context->t = context->gpr[7] & 1U;
	context->gpr[7] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sts_mach_rn_predec_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[7] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->mach);
	context->did_mem = 1;
	context->gpr[7] = context->gpr[7] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void stc_sr_rn_predec_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->sr = 240 & context->sr;
	if (context->t) {
	context->sr = 1 | context->sr;
	}
	if (context->s) {
	context->sr = 2 | context->sr;
	}
	if (context->q) {
	context->sr = 256 | context->sr;
	}
	if (context->m) {
	context->sr = 512 | context->sr;
	}
	context->scratch2 = context->gpr[7] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->sr);
	context->did_mem = 1;
	context->gpr[7] = context->gpr[7] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void rotl_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[7] = context->gpr[7] << 1 | context->gpr[7] >> (32 - 1);
	context->t = context->gpr[7] & 1U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void rotr_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[7] = context->gpr[7] >> 1 | context->gpr[7] << (32 - 1);
	context->t = context->gpr[7] >> 24 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void lds_rm_postinc_mach_M_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[7] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[7], context);
	context->mach = context->scratch1;
	context->gpr[7] = 4 + context->gpr[7];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void ldc_rm_postinc_sr_M_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[7] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[7], context);
	context->cycles += context->opts->gen.clock_divider * 2;
	context->sr = context->scratch1 & 1011;
	context->gpr[7] = 4 + context->gpr[7];
	context->sr = 1011 & context->sr;
	context->t = context->sr & 1;
	context->s = context->sr >> 1;
	context->s = 1 & context->s;
	context->q = context->sr >> 8;
	context->q = 1 & context->q;
	context->m = context->sr >> 9;
	context->m = 1 & context->m;
	sh2_sync_cycle(context, target_cycle);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void shll2_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[7] = context->gpr[7] << 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void shlr2_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[7] = context->gpr[7] >> 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void lds_mach_M_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->mach = context->gpr[7];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void jsr_M_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->pr = context->pc + 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = context->gpr[7] - 2;
	context->cycles += context->opts->gen.clock_divider * 1;
}
static void ldc_rm_sr_M_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->sr = context->gpr[7] & 1011;
	context->sr = 1011 & context->sr;
	context->t = context->sr & 1;
	context->s = context->sr >> 1;
	context->s = 1 & context->s;
	context->q = context->sr >> 8;
	context->q = 1 & context->q;
	context->m = context->sr >> 9;
	context->m = 1 & context->m;
	sh2_sync_cycle(context, target_cycle);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void mac_w_M_0000_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[7] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[7], context);
	context->gpr[7] = 2 + context->gpr[7];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[0] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[0], context);
	context->gpr[0] = 2 + context->gpr[0];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dt_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[7] = context->gpr[7] - 1;
	context->t = context->gpr[7] == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmppz_rn_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[7]) >= ((int32_t)0)) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sts_macl_rn_predec_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[7] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->macl);
	context->did_mem = 1;
	context->gpr[7] = context->gpr[7] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void stc_gbr_rn_predec_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->scratch2 = context->gpr[7] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gbr);
	context->did_mem = 1;
	context->gpr[7] = context->gpr[7] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void cmppl_rn_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[7]) >= ((int32_t)1)) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void lds_rm_postinc_macl_M_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[7] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[7], context);
	context->macl = context->scratch1;
	context->gpr[7] = 4 + context->gpr[7];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void ldc_rm_postinc_gbr_M_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[7] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[7], context);
	context->cycles += context->opts->gen.clock_divider * 2;
	context->gbr = context->scratch1;
	context->gpr[7] = 4 + context->gpr[7];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void shll8_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[7] = context->gpr[7] << 8;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void shlr8_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[7] = context->gpr[7] >> 8;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void lds_macl_M_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->macl = context->gpr[7];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void tas_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (536870912 >= context->gpr[7]) {
	context->scratch1 = context->gpr[7] | 536870912;
	} else {
	context->scratch1 = context->gpr[7];
	}
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->cycles += context->opts->gen.clock_divider * 3;
	context->t = !context->scratch1;
	context->scratch1 = 128 | context->scratch1;
	sh2_write8_tmp = context->gpr[7] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[7], context, context->scratch1);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void ldc_rm_gbr_M_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gbr = context->gpr[7];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void mac_w_M_0001_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[7] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[7], context);
	context->gpr[7] = 2 + context->gpr[7];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[1] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[1], context);
	context->gpr[1] = 2 + context->gpr[1];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void shal_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[7]) << 1ULL;
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[7] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void shar_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = (context->gpr[7] >> 1) | ((context->gpr[7] & 2147483648) && 1 ? 0xFFFFFFFFU << (32 - 1) : 0);
	context->t = context->gpr[7] & 1U;
	context->gpr[7] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sts_pr_rn_predec_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[7] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->pr);
	context->did_mem = 1;
	context->gpr[7] = context->gpr[7] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void stc_vbr_rn_predec_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->scratch2 = context->gpr[7] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->vbr);
	context->did_mem = 1;
	context->gpr[7] = context->gpr[7] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void rotcl_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = ((uint64_t)context->gpr[7]) << 1 | ((uint64_t)context->gpr[7]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[7] >> 24 & 128U;
	context->gpr[7] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void rotcr_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = ((uint64_t)context->gpr[7]) >> 1 | ((uint64_t)context->gpr[7]) << (32 + 1 - 1) | (context->t ? 1 : 0) << (32-1);
	context->t = context->gpr[7] & 1U;
	context->gpr[7] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void lds_rm_postinc_pr_M_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[7] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[7], context);
	context->pr = context->scratch1;
	context->gpr[7] = 4 + context->gpr[7];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void ldc_rm_postinc_vbr_M_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[7] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[7], context);
	context->cycles += context->opts->gen.clock_divider * 2;
	context->vbr = context->scratch1;
	context->gpr[7] = 4 + context->gpr[7];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void shll16_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[7] = context->gpr[7] << 16;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void shlr16_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[7] = context->gpr[7] >> 16;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void lds_pr_M_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->pr = context->gpr[7];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void jmp_M_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = context->gpr[7] - 2;
	context->cycles += context->opts->gen.clock_divider * 1;
}
static void ldc_rm_vbr_M_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->vbr = context->gpr[7];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void mac_w_M_0010_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[7] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[7], context);
	context->gpr[7] = 2 + context->gpr[7];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[2] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[2], context);
	context->gpr[2] = 2 + context->gpr[2];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_w_M_0011_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[7] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[7], context);
	context->gpr[7] = 2 + context->gpr[7];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[3] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[3], context);
	context->gpr[3] = 2 + context->gpr[3];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_w_M_0100_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[7] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[7], context);
	context->gpr[7] = 2 + context->gpr[7];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[4] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[4], context);
	context->gpr[4] = 2 + context->gpr[4];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_w_M_0101_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[7] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[7], context);
	context->gpr[7] = 2 + context->gpr[7];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[5] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[5], context);
	context->gpr[5] = 2 + context->gpr[5];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_w_M_0110_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[7] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[7], context);
	context->gpr[7] = 2 + context->gpr[7];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[6] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[6], context);
	context->gpr[6] = 2 + context->gpr[6];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_w_M_0111_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[7] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[7], context);
	context->gpr[7] = 2 + context->gpr[7];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[7] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[7], context);
	context->gpr[7] = 2 + context->gpr[7];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_w_M_1000_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[7] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[7], context);
	context->gpr[7] = 2 + context->gpr[7];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[8] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[8], context);
	context->gpr[8] = 2 + context->gpr[8];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_w_M_1001_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[7] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[7], context);
	context->gpr[7] = 2 + context->gpr[7];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[9] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[9], context);
	context->gpr[9] = 2 + context->gpr[9];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_w_M_1010_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[7] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[7], context);
	context->gpr[7] = 2 + context->gpr[7];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[10] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[10], context);
	context->gpr[10] = 2 + context->gpr[10];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_w_M_1011_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[7] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[7], context);
	context->gpr[7] = 2 + context->gpr[7];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[11] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[11], context);
	context->gpr[11] = 2 + context->gpr[11];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_w_M_1100_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[7] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[7], context);
	context->gpr[7] = 2 + context->gpr[7];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[12] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[12], context);
	context->gpr[12] = 2 + context->gpr[12];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_w_M_1101_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[7] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[7], context);
	context->gpr[7] = 2 + context->gpr[7];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[13] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[13], context);
	context->gpr[13] = 2 + context->gpr[13];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_w_M_1110_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[7] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[7], context);
	context->gpr[7] = 2 + context->gpr[7];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[14] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[14], context);
	context->gpr[14] = 2 + context->gpr[14];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_w_M_1111_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[7] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[7], context);
	context->gpr[7] = 2 + context->gpr[7];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[15] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[15], context);
	context->gpr[15] = 2 + context->gpr[15];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void shll_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[8]) << 1ULL;
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[8] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void shlr_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[8] >> 1;
	context->t = context->gpr[8] & 1U;
	context->gpr[8] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sts_mach_rn_predec_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[8] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->mach);
	context->did_mem = 1;
	context->gpr[8] = context->gpr[8] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void stc_sr_rn_predec_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->sr = 240 & context->sr;
	if (context->t) {
	context->sr = 1 | context->sr;
	}
	if (context->s) {
	context->sr = 2 | context->sr;
	}
	if (context->q) {
	context->sr = 256 | context->sr;
	}
	if (context->m) {
	context->sr = 512 | context->sr;
	}
	context->scratch2 = context->gpr[8] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->sr);
	context->did_mem = 1;
	context->gpr[8] = context->gpr[8] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void rotl_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[8] = context->gpr[8] << 1 | context->gpr[8] >> (32 - 1);
	context->t = context->gpr[8] & 1U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void rotr_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[8] = context->gpr[8] >> 1 | context->gpr[8] << (32 - 1);
	context->t = context->gpr[8] >> 24 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void lds_rm_postinc_mach_M_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[8] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[8], context);
	context->mach = context->scratch1;
	context->gpr[8] = 4 + context->gpr[8];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void ldc_rm_postinc_sr_M_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[8] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[8], context);
	context->cycles += context->opts->gen.clock_divider * 2;
	context->sr = context->scratch1 & 1011;
	context->gpr[8] = 4 + context->gpr[8];
	context->sr = 1011 & context->sr;
	context->t = context->sr & 1;
	context->s = context->sr >> 1;
	context->s = 1 & context->s;
	context->q = context->sr >> 8;
	context->q = 1 & context->q;
	context->m = context->sr >> 9;
	context->m = 1 & context->m;
	sh2_sync_cycle(context, target_cycle);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void shll2_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[8] = context->gpr[8] << 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void shlr2_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[8] = context->gpr[8] >> 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void lds_mach_M_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->mach = context->gpr[8];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void jsr_M_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->pr = context->pc + 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = context->gpr[8] - 2;
	context->cycles += context->opts->gen.clock_divider * 1;
}
static void ldc_rm_sr_M_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->sr = context->gpr[8] & 1011;
	context->sr = 1011 & context->sr;
	context->t = context->sr & 1;
	context->s = context->sr >> 1;
	context->s = 1 & context->s;
	context->q = context->sr >> 8;
	context->q = 1 & context->q;
	context->m = context->sr >> 9;
	context->m = 1 & context->m;
	sh2_sync_cycle(context, target_cycle);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void mac_w_M_0000_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[8] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[8], context);
	context->gpr[8] = 2 + context->gpr[8];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[0] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[0], context);
	context->gpr[0] = 2 + context->gpr[0];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dt_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[8] = context->gpr[8] - 1;
	context->t = context->gpr[8] == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmppz_rn_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[8]) >= ((int32_t)0)) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sts_macl_rn_predec_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[8] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->macl);
	context->did_mem = 1;
	context->gpr[8] = context->gpr[8] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void stc_gbr_rn_predec_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->scratch2 = context->gpr[8] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gbr);
	context->did_mem = 1;
	context->gpr[8] = context->gpr[8] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void cmppl_rn_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[8]) >= ((int32_t)1)) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void lds_rm_postinc_macl_M_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[8] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[8], context);
	context->macl = context->scratch1;
	context->gpr[8] = 4 + context->gpr[8];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void ldc_rm_postinc_gbr_M_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[8] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[8], context);
	context->cycles += context->opts->gen.clock_divider * 2;
	context->gbr = context->scratch1;
	context->gpr[8] = 4 + context->gpr[8];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void shll8_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[8] = context->gpr[8] << 8;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void shlr8_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[8] = context->gpr[8] >> 8;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void lds_macl_M_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->macl = context->gpr[8];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void tas_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (536870912 >= context->gpr[8]) {
	context->scratch1 = context->gpr[8] | 536870912;
	} else {
	context->scratch1 = context->gpr[8];
	}
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->cycles += context->opts->gen.clock_divider * 3;
	context->t = !context->scratch1;
	context->scratch1 = 128 | context->scratch1;
	sh2_write8_tmp = context->gpr[8] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[8], context, context->scratch1);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void ldc_rm_gbr_M_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gbr = context->gpr[8];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void mac_w_M_0001_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[8] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[8], context);
	context->gpr[8] = 2 + context->gpr[8];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[1] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[1], context);
	context->gpr[1] = 2 + context->gpr[1];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void shal_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[8]) << 1ULL;
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[8] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void shar_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = (context->gpr[8] >> 1) | ((context->gpr[8] & 2147483648) && 1 ? 0xFFFFFFFFU << (32 - 1) : 0);
	context->t = context->gpr[8] & 1U;
	context->gpr[8] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sts_pr_rn_predec_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[8] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->pr);
	context->did_mem = 1;
	context->gpr[8] = context->gpr[8] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void stc_vbr_rn_predec_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->scratch2 = context->gpr[8] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->vbr);
	context->did_mem = 1;
	context->gpr[8] = context->gpr[8] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void rotcl_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = ((uint64_t)context->gpr[8]) << 1 | ((uint64_t)context->gpr[8]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[8] >> 24 & 128U;
	context->gpr[8] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void rotcr_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = ((uint64_t)context->gpr[8]) >> 1 | ((uint64_t)context->gpr[8]) << (32 + 1 - 1) | (context->t ? 1 : 0) << (32-1);
	context->t = context->gpr[8] & 1U;
	context->gpr[8] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void lds_rm_postinc_pr_M_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[8] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[8], context);
	context->pr = context->scratch1;
	context->gpr[8] = 4 + context->gpr[8];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void ldc_rm_postinc_vbr_M_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[8] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[8], context);
	context->cycles += context->opts->gen.clock_divider * 2;
	context->vbr = context->scratch1;
	context->gpr[8] = 4 + context->gpr[8];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void shll16_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[8] = context->gpr[8] << 16;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void shlr16_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[8] = context->gpr[8] >> 16;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void lds_pr_M_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->pr = context->gpr[8];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void jmp_M_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = context->gpr[8] - 2;
	context->cycles += context->opts->gen.clock_divider * 1;
}
static void ldc_rm_vbr_M_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->vbr = context->gpr[8];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void mac_w_M_0010_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[8] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[8], context);
	context->gpr[8] = 2 + context->gpr[8];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[2] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[2], context);
	context->gpr[2] = 2 + context->gpr[2];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_w_M_0011_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[8] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[8], context);
	context->gpr[8] = 2 + context->gpr[8];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[3] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[3], context);
	context->gpr[3] = 2 + context->gpr[3];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_w_M_0100_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[8] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[8], context);
	context->gpr[8] = 2 + context->gpr[8];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[4] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[4], context);
	context->gpr[4] = 2 + context->gpr[4];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_w_M_0101_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[8] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[8], context);
	context->gpr[8] = 2 + context->gpr[8];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[5] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[5], context);
	context->gpr[5] = 2 + context->gpr[5];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_w_M_0110_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[8] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[8], context);
	context->gpr[8] = 2 + context->gpr[8];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[6] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[6], context);
	context->gpr[6] = 2 + context->gpr[6];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_w_M_0111_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[8] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[8], context);
	context->gpr[8] = 2 + context->gpr[8];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[7] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[7], context);
	context->gpr[7] = 2 + context->gpr[7];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_w_M_1000_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[8] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[8], context);
	context->gpr[8] = 2 + context->gpr[8];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[8] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[8], context);
	context->gpr[8] = 2 + context->gpr[8];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_w_M_1001_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[8] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[8], context);
	context->gpr[8] = 2 + context->gpr[8];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[9] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[9], context);
	context->gpr[9] = 2 + context->gpr[9];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_w_M_1010_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[8] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[8], context);
	context->gpr[8] = 2 + context->gpr[8];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[10] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[10], context);
	context->gpr[10] = 2 + context->gpr[10];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_w_M_1011_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[8] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[8], context);
	context->gpr[8] = 2 + context->gpr[8];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[11] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[11], context);
	context->gpr[11] = 2 + context->gpr[11];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_w_M_1100_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[8] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[8], context);
	context->gpr[8] = 2 + context->gpr[8];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[12] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[12], context);
	context->gpr[12] = 2 + context->gpr[12];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_w_M_1101_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[8] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[8], context);
	context->gpr[8] = 2 + context->gpr[8];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[13] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[13], context);
	context->gpr[13] = 2 + context->gpr[13];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_w_M_1110_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[8] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[8], context);
	context->gpr[8] = 2 + context->gpr[8];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[14] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[14], context);
	context->gpr[14] = 2 + context->gpr[14];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_w_M_1111_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[8] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[8], context);
	context->gpr[8] = 2 + context->gpr[8];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[15] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[15], context);
	context->gpr[15] = 2 + context->gpr[15];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void shll_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[9]) << 1ULL;
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[9] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void shlr_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[9] >> 1;
	context->t = context->gpr[9] & 1U;
	context->gpr[9] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sts_mach_rn_predec_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[9] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->mach);
	context->did_mem = 1;
	context->gpr[9] = context->gpr[9] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void stc_sr_rn_predec_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->sr = 240 & context->sr;
	if (context->t) {
	context->sr = 1 | context->sr;
	}
	if (context->s) {
	context->sr = 2 | context->sr;
	}
	if (context->q) {
	context->sr = 256 | context->sr;
	}
	if (context->m) {
	context->sr = 512 | context->sr;
	}
	context->scratch2 = context->gpr[9] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->sr);
	context->did_mem = 1;
	context->gpr[9] = context->gpr[9] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void rotl_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[9] = context->gpr[9] << 1 | context->gpr[9] >> (32 - 1);
	context->t = context->gpr[9] & 1U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void rotr_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[9] = context->gpr[9] >> 1 | context->gpr[9] << (32 - 1);
	context->t = context->gpr[9] >> 24 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void lds_rm_postinc_mach_M_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[9] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[9], context);
	context->mach = context->scratch1;
	context->gpr[9] = 4 + context->gpr[9];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void ldc_rm_postinc_sr_M_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[9] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[9], context);
	context->cycles += context->opts->gen.clock_divider * 2;
	context->sr = context->scratch1 & 1011;
	context->gpr[9] = 4 + context->gpr[9];
	context->sr = 1011 & context->sr;
	context->t = context->sr & 1;
	context->s = context->sr >> 1;
	context->s = 1 & context->s;
	context->q = context->sr >> 8;
	context->q = 1 & context->q;
	context->m = context->sr >> 9;
	context->m = 1 & context->m;
	sh2_sync_cycle(context, target_cycle);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void shll2_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[9] = context->gpr[9] << 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void shlr2_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[9] = context->gpr[9] >> 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void lds_mach_M_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->mach = context->gpr[9];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void jsr_M_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->pr = context->pc + 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = context->gpr[9] - 2;
	context->cycles += context->opts->gen.clock_divider * 1;
}
static void ldc_rm_sr_M_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->sr = context->gpr[9] & 1011;
	context->sr = 1011 & context->sr;
	context->t = context->sr & 1;
	context->s = context->sr >> 1;
	context->s = 1 & context->s;
	context->q = context->sr >> 8;
	context->q = 1 & context->q;
	context->m = context->sr >> 9;
	context->m = 1 & context->m;
	sh2_sync_cycle(context, target_cycle);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void mac_w_M_0000_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[9] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[9], context);
	context->gpr[9] = 2 + context->gpr[9];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[0] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[0], context);
	context->gpr[0] = 2 + context->gpr[0];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dt_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[9] = context->gpr[9] - 1;
	context->t = context->gpr[9] == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmppz_rn_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[9]) >= ((int32_t)0)) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sts_macl_rn_predec_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[9] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->macl);
	context->did_mem = 1;
	context->gpr[9] = context->gpr[9] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void stc_gbr_rn_predec_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->scratch2 = context->gpr[9] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gbr);
	context->did_mem = 1;
	context->gpr[9] = context->gpr[9] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void cmppl_rn_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[9]) >= ((int32_t)1)) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void lds_rm_postinc_macl_M_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[9] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[9], context);
	context->macl = context->scratch1;
	context->gpr[9] = 4 + context->gpr[9];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void ldc_rm_postinc_gbr_M_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[9] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[9], context);
	context->cycles += context->opts->gen.clock_divider * 2;
	context->gbr = context->scratch1;
	context->gpr[9] = 4 + context->gpr[9];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void shll8_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[9] = context->gpr[9] << 8;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void shlr8_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[9] = context->gpr[9] >> 8;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void lds_macl_M_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->macl = context->gpr[9];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void tas_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (536870912 >= context->gpr[9]) {
	context->scratch1 = context->gpr[9] | 536870912;
	} else {
	context->scratch1 = context->gpr[9];
	}
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->cycles += context->opts->gen.clock_divider * 3;
	context->t = !context->scratch1;
	context->scratch1 = 128 | context->scratch1;
	sh2_write8_tmp = context->gpr[9] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[9], context, context->scratch1);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void ldc_rm_gbr_M_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gbr = context->gpr[9];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void mac_w_M_0001_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[9] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[9], context);
	context->gpr[9] = 2 + context->gpr[9];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[1] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[1], context);
	context->gpr[1] = 2 + context->gpr[1];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void shal_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[9]) << 1ULL;
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[9] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void shar_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = (context->gpr[9] >> 1) | ((context->gpr[9] & 2147483648) && 1 ? 0xFFFFFFFFU << (32 - 1) : 0);
	context->t = context->gpr[9] & 1U;
	context->gpr[9] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sts_pr_rn_predec_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[9] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->pr);
	context->did_mem = 1;
	context->gpr[9] = context->gpr[9] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void stc_vbr_rn_predec_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->scratch2 = context->gpr[9] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->vbr);
	context->did_mem = 1;
	context->gpr[9] = context->gpr[9] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void rotcl_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = ((uint64_t)context->gpr[9]) << 1 | ((uint64_t)context->gpr[9]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[9] >> 24 & 128U;
	context->gpr[9] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void rotcr_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = ((uint64_t)context->gpr[9]) >> 1 | ((uint64_t)context->gpr[9]) << (32 + 1 - 1) | (context->t ? 1 : 0) << (32-1);
	context->t = context->gpr[9] & 1U;
	context->gpr[9] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void lds_rm_postinc_pr_M_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[9] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[9], context);
	context->pr = context->scratch1;
	context->gpr[9] = 4 + context->gpr[9];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void ldc_rm_postinc_vbr_M_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[9] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[9], context);
	context->cycles += context->opts->gen.clock_divider * 2;
	context->vbr = context->scratch1;
	context->gpr[9] = 4 + context->gpr[9];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void shll16_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[9] = context->gpr[9] << 16;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void shlr16_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[9] = context->gpr[9] >> 16;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void lds_pr_M_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->pr = context->gpr[9];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void jmp_M_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = context->gpr[9] - 2;
	context->cycles += context->opts->gen.clock_divider * 1;
}
static void ldc_rm_vbr_M_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->vbr = context->gpr[9];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void mac_w_M_0010_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[9] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[9], context);
	context->gpr[9] = 2 + context->gpr[9];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[2] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[2], context);
	context->gpr[2] = 2 + context->gpr[2];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_w_M_0011_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[9] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[9], context);
	context->gpr[9] = 2 + context->gpr[9];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[3] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[3], context);
	context->gpr[3] = 2 + context->gpr[3];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_w_M_0100_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[9] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[9], context);
	context->gpr[9] = 2 + context->gpr[9];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[4] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[4], context);
	context->gpr[4] = 2 + context->gpr[4];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_w_M_0101_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[9] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[9], context);
	context->gpr[9] = 2 + context->gpr[9];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[5] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[5], context);
	context->gpr[5] = 2 + context->gpr[5];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_w_M_0110_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[9] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[9], context);
	context->gpr[9] = 2 + context->gpr[9];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[6] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[6], context);
	context->gpr[6] = 2 + context->gpr[6];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_w_M_0111_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[9] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[9], context);
	context->gpr[9] = 2 + context->gpr[9];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[7] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[7], context);
	context->gpr[7] = 2 + context->gpr[7];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_w_M_1000_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[9] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[9], context);
	context->gpr[9] = 2 + context->gpr[9];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[8] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[8], context);
	context->gpr[8] = 2 + context->gpr[8];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_w_M_1001_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[9] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[9], context);
	context->gpr[9] = 2 + context->gpr[9];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[9] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[9], context);
	context->gpr[9] = 2 + context->gpr[9];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_w_M_1010_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[9] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[9], context);
	context->gpr[9] = 2 + context->gpr[9];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[10] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[10], context);
	context->gpr[10] = 2 + context->gpr[10];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_w_M_1011_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[9] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[9], context);
	context->gpr[9] = 2 + context->gpr[9];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[11] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[11], context);
	context->gpr[11] = 2 + context->gpr[11];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_w_M_1100_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[9] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[9], context);
	context->gpr[9] = 2 + context->gpr[9];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[12] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[12], context);
	context->gpr[12] = 2 + context->gpr[12];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_w_M_1101_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[9] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[9], context);
	context->gpr[9] = 2 + context->gpr[9];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[13] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[13], context);
	context->gpr[13] = 2 + context->gpr[13];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_w_M_1110_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[9] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[9], context);
	context->gpr[9] = 2 + context->gpr[9];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[14] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[14], context);
	context->gpr[14] = 2 + context->gpr[14];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_w_M_1111_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[9] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[9], context);
	context->gpr[9] = 2 + context->gpr[9];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[15] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[15], context);
	context->gpr[15] = 2 + context->gpr[15];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void shll_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[10]) << 1ULL;
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[10] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void shlr_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[10] >> 1;
	context->t = context->gpr[10] & 1U;
	context->gpr[10] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sts_mach_rn_predec_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[10] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->mach);
	context->did_mem = 1;
	context->gpr[10] = context->gpr[10] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void stc_sr_rn_predec_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->sr = 240 & context->sr;
	if (context->t) {
	context->sr = 1 | context->sr;
	}
	if (context->s) {
	context->sr = 2 | context->sr;
	}
	if (context->q) {
	context->sr = 256 | context->sr;
	}
	if (context->m) {
	context->sr = 512 | context->sr;
	}
	context->scratch2 = context->gpr[10] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->sr);
	context->did_mem = 1;
	context->gpr[10] = context->gpr[10] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void rotl_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[10] = context->gpr[10] << 1 | context->gpr[10] >> (32 - 1);
	context->t = context->gpr[10] & 1U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void rotr_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[10] = context->gpr[10] >> 1 | context->gpr[10] << (32 - 1);
	context->t = context->gpr[10] >> 24 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void lds_rm_postinc_mach_M_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[10] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[10], context);
	context->mach = context->scratch1;
	context->gpr[10] = 4 + context->gpr[10];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void ldc_rm_postinc_sr_M_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[10] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[10], context);
	context->cycles += context->opts->gen.clock_divider * 2;
	context->sr = context->scratch1 & 1011;
	context->gpr[10] = 4 + context->gpr[10];
	context->sr = 1011 & context->sr;
	context->t = context->sr & 1;
	context->s = context->sr >> 1;
	context->s = 1 & context->s;
	context->q = context->sr >> 8;
	context->q = 1 & context->q;
	context->m = context->sr >> 9;
	context->m = 1 & context->m;
	sh2_sync_cycle(context, target_cycle);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void shll2_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[10] = context->gpr[10] << 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void shlr2_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[10] = context->gpr[10] >> 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void lds_mach_M_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->mach = context->gpr[10];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void jsr_M_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->pr = context->pc + 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = context->gpr[10] - 2;
	context->cycles += context->opts->gen.clock_divider * 1;
}
static void ldc_rm_sr_M_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->sr = context->gpr[10] & 1011;
	context->sr = 1011 & context->sr;
	context->t = context->sr & 1;
	context->s = context->sr >> 1;
	context->s = 1 & context->s;
	context->q = context->sr >> 8;
	context->q = 1 & context->q;
	context->m = context->sr >> 9;
	context->m = 1 & context->m;
	sh2_sync_cycle(context, target_cycle);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void mac_w_M_0000_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[10] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[10], context);
	context->gpr[10] = 2 + context->gpr[10];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[0] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[0], context);
	context->gpr[0] = 2 + context->gpr[0];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dt_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[10] = context->gpr[10] - 1;
	context->t = context->gpr[10] == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmppz_rn_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[10]) >= ((int32_t)0)) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sts_macl_rn_predec_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[10] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->macl);
	context->did_mem = 1;
	context->gpr[10] = context->gpr[10] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void stc_gbr_rn_predec_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->scratch2 = context->gpr[10] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gbr);
	context->did_mem = 1;
	context->gpr[10] = context->gpr[10] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void cmppl_rn_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[10]) >= ((int32_t)1)) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void lds_rm_postinc_macl_M_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[10] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[10], context);
	context->macl = context->scratch1;
	context->gpr[10] = 4 + context->gpr[10];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void ldc_rm_postinc_gbr_M_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[10] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[10], context);
	context->cycles += context->opts->gen.clock_divider * 2;
	context->gbr = context->scratch1;
	context->gpr[10] = 4 + context->gpr[10];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void shll8_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[10] = context->gpr[10] << 8;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void shlr8_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[10] = context->gpr[10] >> 8;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void lds_macl_M_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->macl = context->gpr[10];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void tas_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (536870912 >= context->gpr[10]) {
	context->scratch1 = context->gpr[10] | 536870912;
	} else {
	context->scratch1 = context->gpr[10];
	}
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->cycles += context->opts->gen.clock_divider * 3;
	context->t = !context->scratch1;
	context->scratch1 = 128 | context->scratch1;
	sh2_write8_tmp = context->gpr[10] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[10], context, context->scratch1);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void ldc_rm_gbr_M_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gbr = context->gpr[10];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void mac_w_M_0001_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[10] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[10], context);
	context->gpr[10] = 2 + context->gpr[10];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[1] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[1], context);
	context->gpr[1] = 2 + context->gpr[1];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void shal_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[10]) << 1ULL;
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[10] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void shar_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = (context->gpr[10] >> 1) | ((context->gpr[10] & 2147483648) && 1 ? 0xFFFFFFFFU << (32 - 1) : 0);
	context->t = context->gpr[10] & 1U;
	context->gpr[10] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sts_pr_rn_predec_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[10] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->pr);
	context->did_mem = 1;
	context->gpr[10] = context->gpr[10] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void stc_vbr_rn_predec_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->scratch2 = context->gpr[10] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->vbr);
	context->did_mem = 1;
	context->gpr[10] = context->gpr[10] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void rotcl_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = ((uint64_t)context->gpr[10]) << 1 | ((uint64_t)context->gpr[10]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[10] >> 24 & 128U;
	context->gpr[10] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void rotcr_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = ((uint64_t)context->gpr[10]) >> 1 | ((uint64_t)context->gpr[10]) << (32 + 1 - 1) | (context->t ? 1 : 0) << (32-1);
	context->t = context->gpr[10] & 1U;
	context->gpr[10] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void lds_rm_postinc_pr_M_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[10] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[10], context);
	context->pr = context->scratch1;
	context->gpr[10] = 4 + context->gpr[10];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void ldc_rm_postinc_vbr_M_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[10] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[10], context);
	context->cycles += context->opts->gen.clock_divider * 2;
	context->vbr = context->scratch1;
	context->gpr[10] = 4 + context->gpr[10];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void shll16_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[10] = context->gpr[10] << 16;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void shlr16_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[10] = context->gpr[10] >> 16;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void lds_pr_M_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->pr = context->gpr[10];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void jmp_M_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = context->gpr[10] - 2;
	context->cycles += context->opts->gen.clock_divider * 1;
}
static void ldc_rm_vbr_M_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->vbr = context->gpr[10];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void mac_w_M_0010_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[10] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[10], context);
	context->gpr[10] = 2 + context->gpr[10];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[2] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[2], context);
	context->gpr[2] = 2 + context->gpr[2];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_w_M_0011_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[10] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[10], context);
	context->gpr[10] = 2 + context->gpr[10];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[3] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[3], context);
	context->gpr[3] = 2 + context->gpr[3];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_w_M_0100_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[10] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[10], context);
	context->gpr[10] = 2 + context->gpr[10];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[4] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[4], context);
	context->gpr[4] = 2 + context->gpr[4];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_w_M_0101_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[10] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[10], context);
	context->gpr[10] = 2 + context->gpr[10];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[5] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[5], context);
	context->gpr[5] = 2 + context->gpr[5];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_w_M_0110_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[10] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[10], context);
	context->gpr[10] = 2 + context->gpr[10];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[6] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[6], context);
	context->gpr[6] = 2 + context->gpr[6];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_w_M_0111_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[10] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[10], context);
	context->gpr[10] = 2 + context->gpr[10];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[7] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[7], context);
	context->gpr[7] = 2 + context->gpr[7];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_w_M_1000_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[10] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[10], context);
	context->gpr[10] = 2 + context->gpr[10];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[8] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[8], context);
	context->gpr[8] = 2 + context->gpr[8];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_w_M_1001_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[10] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[10], context);
	context->gpr[10] = 2 + context->gpr[10];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[9] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[9], context);
	context->gpr[9] = 2 + context->gpr[9];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_w_M_1010_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[10] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[10], context);
	context->gpr[10] = 2 + context->gpr[10];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[10] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[10], context);
	context->gpr[10] = 2 + context->gpr[10];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_w_M_1011_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[10] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[10], context);
	context->gpr[10] = 2 + context->gpr[10];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[11] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[11], context);
	context->gpr[11] = 2 + context->gpr[11];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_w_M_1100_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[10] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[10], context);
	context->gpr[10] = 2 + context->gpr[10];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[12] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[12], context);
	context->gpr[12] = 2 + context->gpr[12];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_w_M_1101_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[10] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[10], context);
	context->gpr[10] = 2 + context->gpr[10];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[13] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[13], context);
	context->gpr[13] = 2 + context->gpr[13];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_w_M_1110_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[10] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[10], context);
	context->gpr[10] = 2 + context->gpr[10];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[14] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[14], context);
	context->gpr[14] = 2 + context->gpr[14];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_w_M_1111_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[10] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[10], context);
	context->gpr[10] = 2 + context->gpr[10];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[15] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[15], context);
	context->gpr[15] = 2 + context->gpr[15];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void shll_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[11]) << 1ULL;
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[11] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void shlr_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[11] >> 1;
	context->t = context->gpr[11] & 1U;
	context->gpr[11] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sts_mach_rn_predec_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[11] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->mach);
	context->did_mem = 1;
	context->gpr[11] = context->gpr[11] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void stc_sr_rn_predec_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->sr = 240 & context->sr;
	if (context->t) {
	context->sr = 1 | context->sr;
	}
	if (context->s) {
	context->sr = 2 | context->sr;
	}
	if (context->q) {
	context->sr = 256 | context->sr;
	}
	if (context->m) {
	context->sr = 512 | context->sr;
	}
	context->scratch2 = context->gpr[11] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->sr);
	context->did_mem = 1;
	context->gpr[11] = context->gpr[11] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void rotl_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[11] = context->gpr[11] << 1 | context->gpr[11] >> (32 - 1);
	context->t = context->gpr[11] & 1U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void rotr_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[11] = context->gpr[11] >> 1 | context->gpr[11] << (32 - 1);
	context->t = context->gpr[11] >> 24 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void lds_rm_postinc_mach_M_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[11] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[11], context);
	context->mach = context->scratch1;
	context->gpr[11] = 4 + context->gpr[11];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void ldc_rm_postinc_sr_M_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[11] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[11], context);
	context->cycles += context->opts->gen.clock_divider * 2;
	context->sr = context->scratch1 & 1011;
	context->gpr[11] = 4 + context->gpr[11];
	context->sr = 1011 & context->sr;
	context->t = context->sr & 1;
	context->s = context->sr >> 1;
	context->s = 1 & context->s;
	context->q = context->sr >> 8;
	context->q = 1 & context->q;
	context->m = context->sr >> 9;
	context->m = 1 & context->m;
	sh2_sync_cycle(context, target_cycle);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void shll2_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[11] = context->gpr[11] << 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void shlr2_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[11] = context->gpr[11] >> 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void lds_mach_M_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->mach = context->gpr[11];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void jsr_M_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->pr = context->pc + 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = context->gpr[11] - 2;
	context->cycles += context->opts->gen.clock_divider * 1;
}
static void ldc_rm_sr_M_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->sr = context->gpr[11] & 1011;
	context->sr = 1011 & context->sr;
	context->t = context->sr & 1;
	context->s = context->sr >> 1;
	context->s = 1 & context->s;
	context->q = context->sr >> 8;
	context->q = 1 & context->q;
	context->m = context->sr >> 9;
	context->m = 1 & context->m;
	sh2_sync_cycle(context, target_cycle);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void mac_w_M_0000_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[11] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[11], context);
	context->gpr[11] = 2 + context->gpr[11];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[0] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[0], context);
	context->gpr[0] = 2 + context->gpr[0];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dt_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[11] = context->gpr[11] - 1;
	context->t = context->gpr[11] == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmppz_rn_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[11]) >= ((int32_t)0)) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sts_macl_rn_predec_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[11] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->macl);
	context->did_mem = 1;
	context->gpr[11] = context->gpr[11] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void stc_gbr_rn_predec_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->scratch2 = context->gpr[11] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gbr);
	context->did_mem = 1;
	context->gpr[11] = context->gpr[11] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void cmppl_rn_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[11]) >= ((int32_t)1)) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void lds_rm_postinc_macl_M_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[11] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[11], context);
	context->macl = context->scratch1;
	context->gpr[11] = 4 + context->gpr[11];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void ldc_rm_postinc_gbr_M_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[11] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[11], context);
	context->cycles += context->opts->gen.clock_divider * 2;
	context->gbr = context->scratch1;
	context->gpr[11] = 4 + context->gpr[11];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void shll8_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[11] = context->gpr[11] << 8;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void shlr8_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[11] = context->gpr[11] >> 8;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void lds_macl_M_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->macl = context->gpr[11];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void tas_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (536870912 >= context->gpr[11]) {
	context->scratch1 = context->gpr[11] | 536870912;
	} else {
	context->scratch1 = context->gpr[11];
	}
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->cycles += context->opts->gen.clock_divider * 3;
	context->t = !context->scratch1;
	context->scratch1 = 128 | context->scratch1;
	sh2_write8_tmp = context->gpr[11] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[11], context, context->scratch1);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void ldc_rm_gbr_M_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gbr = context->gpr[11];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void mac_w_M_0001_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[11] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[11], context);
	context->gpr[11] = 2 + context->gpr[11];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[1] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[1], context);
	context->gpr[1] = 2 + context->gpr[1];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void shal_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[11]) << 1ULL;
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[11] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void shar_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = (context->gpr[11] >> 1) | ((context->gpr[11] & 2147483648) && 1 ? 0xFFFFFFFFU << (32 - 1) : 0);
	context->t = context->gpr[11] & 1U;
	context->gpr[11] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sts_pr_rn_predec_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[11] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->pr);
	context->did_mem = 1;
	context->gpr[11] = context->gpr[11] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void stc_vbr_rn_predec_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->scratch2 = context->gpr[11] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->vbr);
	context->did_mem = 1;
	context->gpr[11] = context->gpr[11] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void rotcl_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = ((uint64_t)context->gpr[11]) << 1 | ((uint64_t)context->gpr[11]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[11] >> 24 & 128U;
	context->gpr[11] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void rotcr_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = ((uint64_t)context->gpr[11]) >> 1 | ((uint64_t)context->gpr[11]) << (32 + 1 - 1) | (context->t ? 1 : 0) << (32-1);
	context->t = context->gpr[11] & 1U;
	context->gpr[11] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void lds_rm_postinc_pr_M_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[11] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[11], context);
	context->pr = context->scratch1;
	context->gpr[11] = 4 + context->gpr[11];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void ldc_rm_postinc_vbr_M_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[11] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[11], context);
	context->cycles += context->opts->gen.clock_divider * 2;
	context->vbr = context->scratch1;
	context->gpr[11] = 4 + context->gpr[11];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void shll16_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[11] = context->gpr[11] << 16;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void shlr16_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[11] = context->gpr[11] >> 16;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void lds_pr_M_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->pr = context->gpr[11];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void jmp_M_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = context->gpr[11] - 2;
	context->cycles += context->opts->gen.clock_divider * 1;
}
static void ldc_rm_vbr_M_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->vbr = context->gpr[11];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void mac_w_M_0010_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[11] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[11], context);
	context->gpr[11] = 2 + context->gpr[11];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[2] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[2], context);
	context->gpr[2] = 2 + context->gpr[2];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_w_M_0011_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[11] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[11], context);
	context->gpr[11] = 2 + context->gpr[11];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[3] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[3], context);
	context->gpr[3] = 2 + context->gpr[3];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_w_M_0100_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[11] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[11], context);
	context->gpr[11] = 2 + context->gpr[11];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[4] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[4], context);
	context->gpr[4] = 2 + context->gpr[4];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_w_M_0101_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[11] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[11], context);
	context->gpr[11] = 2 + context->gpr[11];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[5] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[5], context);
	context->gpr[5] = 2 + context->gpr[5];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_w_M_0110_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[11] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[11], context);
	context->gpr[11] = 2 + context->gpr[11];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[6] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[6], context);
	context->gpr[6] = 2 + context->gpr[6];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_w_M_0111_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[11] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[11], context);
	context->gpr[11] = 2 + context->gpr[11];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[7] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[7], context);
	context->gpr[7] = 2 + context->gpr[7];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_w_M_1000_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[11] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[11], context);
	context->gpr[11] = 2 + context->gpr[11];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[8] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[8], context);
	context->gpr[8] = 2 + context->gpr[8];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_w_M_1001_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[11] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[11], context);
	context->gpr[11] = 2 + context->gpr[11];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[9] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[9], context);
	context->gpr[9] = 2 + context->gpr[9];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_w_M_1010_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[11] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[11], context);
	context->gpr[11] = 2 + context->gpr[11];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[10] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[10], context);
	context->gpr[10] = 2 + context->gpr[10];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_w_M_1011_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[11] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[11], context);
	context->gpr[11] = 2 + context->gpr[11];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[11] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[11], context);
	context->gpr[11] = 2 + context->gpr[11];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_w_M_1100_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[11] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[11], context);
	context->gpr[11] = 2 + context->gpr[11];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[12] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[12], context);
	context->gpr[12] = 2 + context->gpr[12];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_w_M_1101_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[11] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[11], context);
	context->gpr[11] = 2 + context->gpr[11];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[13] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[13], context);
	context->gpr[13] = 2 + context->gpr[13];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_w_M_1110_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[11] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[11], context);
	context->gpr[11] = 2 + context->gpr[11];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[14] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[14], context);
	context->gpr[14] = 2 + context->gpr[14];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_w_M_1111_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[11] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[11], context);
	context->gpr[11] = 2 + context->gpr[11];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[15] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[15], context);
	context->gpr[15] = 2 + context->gpr[15];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void shll_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[12]) << 1ULL;
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[12] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void shlr_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[12] >> 1;
	context->t = context->gpr[12] & 1U;
	context->gpr[12] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sts_mach_rn_predec_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[12] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->mach);
	context->did_mem = 1;
	context->gpr[12] = context->gpr[12] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void stc_sr_rn_predec_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->sr = 240 & context->sr;
	if (context->t) {
	context->sr = 1 | context->sr;
	}
	if (context->s) {
	context->sr = 2 | context->sr;
	}
	if (context->q) {
	context->sr = 256 | context->sr;
	}
	if (context->m) {
	context->sr = 512 | context->sr;
	}
	context->scratch2 = context->gpr[12] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->sr);
	context->did_mem = 1;
	context->gpr[12] = context->gpr[12] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void rotl_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[12] = context->gpr[12] << 1 | context->gpr[12] >> (32 - 1);
	context->t = context->gpr[12] & 1U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void rotr_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[12] = context->gpr[12] >> 1 | context->gpr[12] << (32 - 1);
	context->t = context->gpr[12] >> 24 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void lds_rm_postinc_mach_M_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[12] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[12], context);
	context->mach = context->scratch1;
	context->gpr[12] = 4 + context->gpr[12];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void ldc_rm_postinc_sr_M_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[12] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[12], context);
	context->cycles += context->opts->gen.clock_divider * 2;
	context->sr = context->scratch1 & 1011;
	context->gpr[12] = 4 + context->gpr[12];
	context->sr = 1011 & context->sr;
	context->t = context->sr & 1;
	context->s = context->sr >> 1;
	context->s = 1 & context->s;
	context->q = context->sr >> 8;
	context->q = 1 & context->q;
	context->m = context->sr >> 9;
	context->m = 1 & context->m;
	sh2_sync_cycle(context, target_cycle);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void shll2_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[12] = context->gpr[12] << 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void shlr2_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[12] = context->gpr[12] >> 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void lds_mach_M_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->mach = context->gpr[12];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void jsr_M_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->pr = context->pc + 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = context->gpr[12] - 2;
	context->cycles += context->opts->gen.clock_divider * 1;
}
static void ldc_rm_sr_M_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->sr = context->gpr[12] & 1011;
	context->sr = 1011 & context->sr;
	context->t = context->sr & 1;
	context->s = context->sr >> 1;
	context->s = 1 & context->s;
	context->q = context->sr >> 8;
	context->q = 1 & context->q;
	context->m = context->sr >> 9;
	context->m = 1 & context->m;
	sh2_sync_cycle(context, target_cycle);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void mac_w_M_0000_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[12] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[12], context);
	context->gpr[12] = 2 + context->gpr[12];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[0] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[0], context);
	context->gpr[0] = 2 + context->gpr[0];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dt_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[12] = context->gpr[12] - 1;
	context->t = context->gpr[12] == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmppz_rn_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[12]) >= ((int32_t)0)) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sts_macl_rn_predec_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[12] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->macl);
	context->did_mem = 1;
	context->gpr[12] = context->gpr[12] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void stc_gbr_rn_predec_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->scratch2 = context->gpr[12] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gbr);
	context->did_mem = 1;
	context->gpr[12] = context->gpr[12] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void cmppl_rn_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[12]) >= ((int32_t)1)) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void lds_rm_postinc_macl_M_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[12] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[12], context);
	context->macl = context->scratch1;
	context->gpr[12] = 4 + context->gpr[12];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void ldc_rm_postinc_gbr_M_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[12] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[12], context);
	context->cycles += context->opts->gen.clock_divider * 2;
	context->gbr = context->scratch1;
	context->gpr[12] = 4 + context->gpr[12];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void shll8_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[12] = context->gpr[12] << 8;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void shlr8_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[12] = context->gpr[12] >> 8;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void lds_macl_M_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->macl = context->gpr[12];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void tas_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (536870912 >= context->gpr[12]) {
	context->scratch1 = context->gpr[12] | 536870912;
	} else {
	context->scratch1 = context->gpr[12];
	}
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->cycles += context->opts->gen.clock_divider * 3;
	context->t = !context->scratch1;
	context->scratch1 = 128 | context->scratch1;
	sh2_write8_tmp = context->gpr[12] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[12], context, context->scratch1);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void ldc_rm_gbr_M_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gbr = context->gpr[12];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void mac_w_M_0001_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[12] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[12], context);
	context->gpr[12] = 2 + context->gpr[12];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[1] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[1], context);
	context->gpr[1] = 2 + context->gpr[1];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void shal_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[12]) << 1ULL;
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[12] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void shar_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = (context->gpr[12] >> 1) | ((context->gpr[12] & 2147483648) && 1 ? 0xFFFFFFFFU << (32 - 1) : 0);
	context->t = context->gpr[12] & 1U;
	context->gpr[12] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sts_pr_rn_predec_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[12] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->pr);
	context->did_mem = 1;
	context->gpr[12] = context->gpr[12] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void stc_vbr_rn_predec_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->scratch2 = context->gpr[12] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->vbr);
	context->did_mem = 1;
	context->gpr[12] = context->gpr[12] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void rotcl_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = ((uint64_t)context->gpr[12]) << 1 | ((uint64_t)context->gpr[12]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[12] >> 24 & 128U;
	context->gpr[12] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void rotcr_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = ((uint64_t)context->gpr[12]) >> 1 | ((uint64_t)context->gpr[12]) << (32 + 1 - 1) | (context->t ? 1 : 0) << (32-1);
	context->t = context->gpr[12] & 1U;
	context->gpr[12] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void lds_rm_postinc_pr_M_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[12] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[12], context);
	context->pr = context->scratch1;
	context->gpr[12] = 4 + context->gpr[12];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void ldc_rm_postinc_vbr_M_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[12] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[12], context);
	context->cycles += context->opts->gen.clock_divider * 2;
	context->vbr = context->scratch1;
	context->gpr[12] = 4 + context->gpr[12];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void shll16_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[12] = context->gpr[12] << 16;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void shlr16_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[12] = context->gpr[12] >> 16;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void lds_pr_M_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->pr = context->gpr[12];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void jmp_M_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = context->gpr[12] - 2;
	context->cycles += context->opts->gen.clock_divider * 1;
}
static void ldc_rm_vbr_M_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->vbr = context->gpr[12];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void mac_w_M_0010_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[12] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[12], context);
	context->gpr[12] = 2 + context->gpr[12];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[2] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[2], context);
	context->gpr[2] = 2 + context->gpr[2];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_w_M_0011_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[12] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[12], context);
	context->gpr[12] = 2 + context->gpr[12];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[3] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[3], context);
	context->gpr[3] = 2 + context->gpr[3];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_w_M_0100_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[12] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[12], context);
	context->gpr[12] = 2 + context->gpr[12];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[4] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[4], context);
	context->gpr[4] = 2 + context->gpr[4];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_w_M_0101_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[12] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[12], context);
	context->gpr[12] = 2 + context->gpr[12];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[5] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[5], context);
	context->gpr[5] = 2 + context->gpr[5];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_w_M_0110_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[12] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[12], context);
	context->gpr[12] = 2 + context->gpr[12];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[6] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[6], context);
	context->gpr[6] = 2 + context->gpr[6];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_w_M_0111_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[12] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[12], context);
	context->gpr[12] = 2 + context->gpr[12];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[7] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[7], context);
	context->gpr[7] = 2 + context->gpr[7];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_w_M_1000_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[12] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[12], context);
	context->gpr[12] = 2 + context->gpr[12];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[8] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[8], context);
	context->gpr[8] = 2 + context->gpr[8];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_w_M_1001_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[12] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[12], context);
	context->gpr[12] = 2 + context->gpr[12];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[9] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[9], context);
	context->gpr[9] = 2 + context->gpr[9];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_w_M_1010_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[12] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[12], context);
	context->gpr[12] = 2 + context->gpr[12];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[10] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[10], context);
	context->gpr[10] = 2 + context->gpr[10];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_w_M_1011_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[12] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[12], context);
	context->gpr[12] = 2 + context->gpr[12];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[11] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[11], context);
	context->gpr[11] = 2 + context->gpr[11];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_w_M_1100_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[12] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[12], context);
	context->gpr[12] = 2 + context->gpr[12];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[12] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[12], context);
	context->gpr[12] = 2 + context->gpr[12];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_w_M_1101_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[12] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[12], context);
	context->gpr[12] = 2 + context->gpr[12];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[13] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[13], context);
	context->gpr[13] = 2 + context->gpr[13];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_w_M_1110_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[12] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[12], context);
	context->gpr[12] = 2 + context->gpr[12];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[14] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[14], context);
	context->gpr[14] = 2 + context->gpr[14];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_w_M_1111_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[12] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[12], context);
	context->gpr[12] = 2 + context->gpr[12];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[15] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[15], context);
	context->gpr[15] = 2 + context->gpr[15];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void shll_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[13]) << 1ULL;
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[13] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void shlr_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[13] >> 1;
	context->t = context->gpr[13] & 1U;
	context->gpr[13] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sts_mach_rn_predec_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[13] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->mach);
	context->did_mem = 1;
	context->gpr[13] = context->gpr[13] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void stc_sr_rn_predec_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->sr = 240 & context->sr;
	if (context->t) {
	context->sr = 1 | context->sr;
	}
	if (context->s) {
	context->sr = 2 | context->sr;
	}
	if (context->q) {
	context->sr = 256 | context->sr;
	}
	if (context->m) {
	context->sr = 512 | context->sr;
	}
	context->scratch2 = context->gpr[13] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->sr);
	context->did_mem = 1;
	context->gpr[13] = context->gpr[13] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void rotl_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[13] = context->gpr[13] << 1 | context->gpr[13] >> (32 - 1);
	context->t = context->gpr[13] & 1U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void rotr_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[13] = context->gpr[13] >> 1 | context->gpr[13] << (32 - 1);
	context->t = context->gpr[13] >> 24 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void lds_rm_postinc_mach_M_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[13] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[13], context);
	context->mach = context->scratch1;
	context->gpr[13] = 4 + context->gpr[13];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void ldc_rm_postinc_sr_M_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[13] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[13], context);
	context->cycles += context->opts->gen.clock_divider * 2;
	context->sr = context->scratch1 & 1011;
	context->gpr[13] = 4 + context->gpr[13];
	context->sr = 1011 & context->sr;
	context->t = context->sr & 1;
	context->s = context->sr >> 1;
	context->s = 1 & context->s;
	context->q = context->sr >> 8;
	context->q = 1 & context->q;
	context->m = context->sr >> 9;
	context->m = 1 & context->m;
	sh2_sync_cycle(context, target_cycle);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void shll2_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[13] = context->gpr[13] << 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void shlr2_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[13] = context->gpr[13] >> 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void lds_mach_M_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->mach = context->gpr[13];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void jsr_M_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->pr = context->pc + 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = context->gpr[13] - 2;
	context->cycles += context->opts->gen.clock_divider * 1;
}
static void ldc_rm_sr_M_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->sr = context->gpr[13] & 1011;
	context->sr = 1011 & context->sr;
	context->t = context->sr & 1;
	context->s = context->sr >> 1;
	context->s = 1 & context->s;
	context->q = context->sr >> 8;
	context->q = 1 & context->q;
	context->m = context->sr >> 9;
	context->m = 1 & context->m;
	sh2_sync_cycle(context, target_cycle);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void mac_w_M_0000_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[13] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[13], context);
	context->gpr[13] = 2 + context->gpr[13];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[0] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[0], context);
	context->gpr[0] = 2 + context->gpr[0];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dt_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[13] = context->gpr[13] - 1;
	context->t = context->gpr[13] == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmppz_rn_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[13]) >= ((int32_t)0)) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sts_macl_rn_predec_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[13] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->macl);
	context->did_mem = 1;
	context->gpr[13] = context->gpr[13] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void stc_gbr_rn_predec_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->scratch2 = context->gpr[13] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gbr);
	context->did_mem = 1;
	context->gpr[13] = context->gpr[13] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void cmppl_rn_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[13]) >= ((int32_t)1)) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void lds_rm_postinc_macl_M_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[13] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[13], context);
	context->macl = context->scratch1;
	context->gpr[13] = 4 + context->gpr[13];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void ldc_rm_postinc_gbr_M_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[13] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[13], context);
	context->cycles += context->opts->gen.clock_divider * 2;
	context->gbr = context->scratch1;
	context->gpr[13] = 4 + context->gpr[13];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void shll8_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[13] = context->gpr[13] << 8;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void shlr8_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[13] = context->gpr[13] >> 8;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void lds_macl_M_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->macl = context->gpr[13];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void tas_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (536870912 >= context->gpr[13]) {
	context->scratch1 = context->gpr[13] | 536870912;
	} else {
	context->scratch1 = context->gpr[13];
	}
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->cycles += context->opts->gen.clock_divider * 3;
	context->t = !context->scratch1;
	context->scratch1 = 128 | context->scratch1;
	sh2_write8_tmp = context->gpr[13] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[13], context, context->scratch1);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void ldc_rm_gbr_M_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gbr = context->gpr[13];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void mac_w_M_0001_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[13] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[13], context);
	context->gpr[13] = 2 + context->gpr[13];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[1] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[1], context);
	context->gpr[1] = 2 + context->gpr[1];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void shal_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[13]) << 1ULL;
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[13] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void shar_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = (context->gpr[13] >> 1) | ((context->gpr[13] & 2147483648) && 1 ? 0xFFFFFFFFU << (32 - 1) : 0);
	context->t = context->gpr[13] & 1U;
	context->gpr[13] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sts_pr_rn_predec_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[13] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->pr);
	context->did_mem = 1;
	context->gpr[13] = context->gpr[13] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void stc_vbr_rn_predec_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->scratch2 = context->gpr[13] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->vbr);
	context->did_mem = 1;
	context->gpr[13] = context->gpr[13] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void rotcl_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = ((uint64_t)context->gpr[13]) << 1 | ((uint64_t)context->gpr[13]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[13] >> 24 & 128U;
	context->gpr[13] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void rotcr_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = ((uint64_t)context->gpr[13]) >> 1 | ((uint64_t)context->gpr[13]) << (32 + 1 - 1) | (context->t ? 1 : 0) << (32-1);
	context->t = context->gpr[13] & 1U;
	context->gpr[13] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void lds_rm_postinc_pr_M_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[13] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[13], context);
	context->pr = context->scratch1;
	context->gpr[13] = 4 + context->gpr[13];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void ldc_rm_postinc_vbr_M_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[13] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[13], context);
	context->cycles += context->opts->gen.clock_divider * 2;
	context->vbr = context->scratch1;
	context->gpr[13] = 4 + context->gpr[13];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void shll16_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[13] = context->gpr[13] << 16;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void shlr16_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[13] = context->gpr[13] >> 16;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void lds_pr_M_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->pr = context->gpr[13];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void jmp_M_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = context->gpr[13] - 2;
	context->cycles += context->opts->gen.clock_divider * 1;
}
static void ldc_rm_vbr_M_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->vbr = context->gpr[13];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void mac_w_M_0010_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[13] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[13], context);
	context->gpr[13] = 2 + context->gpr[13];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[2] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[2], context);
	context->gpr[2] = 2 + context->gpr[2];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_w_M_0011_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[13] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[13], context);
	context->gpr[13] = 2 + context->gpr[13];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[3] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[3], context);
	context->gpr[3] = 2 + context->gpr[3];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_w_M_0100_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[13] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[13], context);
	context->gpr[13] = 2 + context->gpr[13];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[4] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[4], context);
	context->gpr[4] = 2 + context->gpr[4];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_w_M_0101_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[13] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[13], context);
	context->gpr[13] = 2 + context->gpr[13];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[5] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[5], context);
	context->gpr[5] = 2 + context->gpr[5];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_w_M_0110_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[13] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[13], context);
	context->gpr[13] = 2 + context->gpr[13];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[6] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[6], context);
	context->gpr[6] = 2 + context->gpr[6];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_w_M_0111_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[13] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[13], context);
	context->gpr[13] = 2 + context->gpr[13];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[7] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[7], context);
	context->gpr[7] = 2 + context->gpr[7];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_w_M_1000_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[13] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[13], context);
	context->gpr[13] = 2 + context->gpr[13];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[8] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[8], context);
	context->gpr[8] = 2 + context->gpr[8];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_w_M_1001_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[13] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[13], context);
	context->gpr[13] = 2 + context->gpr[13];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[9] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[9], context);
	context->gpr[9] = 2 + context->gpr[9];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_w_M_1010_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[13] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[13], context);
	context->gpr[13] = 2 + context->gpr[13];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[10] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[10], context);
	context->gpr[10] = 2 + context->gpr[10];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_w_M_1011_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[13] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[13], context);
	context->gpr[13] = 2 + context->gpr[13];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[11] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[11], context);
	context->gpr[11] = 2 + context->gpr[11];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_w_M_1100_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[13] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[13], context);
	context->gpr[13] = 2 + context->gpr[13];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[12] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[12], context);
	context->gpr[12] = 2 + context->gpr[12];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_w_M_1101_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[13] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[13], context);
	context->gpr[13] = 2 + context->gpr[13];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[13] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[13], context);
	context->gpr[13] = 2 + context->gpr[13];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_w_M_1110_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[13] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[13], context);
	context->gpr[13] = 2 + context->gpr[13];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[14] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[14], context);
	context->gpr[14] = 2 + context->gpr[14];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_w_M_1111_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[13] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[13], context);
	context->gpr[13] = 2 + context->gpr[13];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[15] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[15], context);
	context->gpr[15] = 2 + context->gpr[15];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void shll_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[14]) << 1ULL;
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[14] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void shlr_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[14] >> 1;
	context->t = context->gpr[14] & 1U;
	context->gpr[14] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sts_mach_rn_predec_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[14] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->mach);
	context->did_mem = 1;
	context->gpr[14] = context->gpr[14] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void stc_sr_rn_predec_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->sr = 240 & context->sr;
	if (context->t) {
	context->sr = 1 | context->sr;
	}
	if (context->s) {
	context->sr = 2 | context->sr;
	}
	if (context->q) {
	context->sr = 256 | context->sr;
	}
	if (context->m) {
	context->sr = 512 | context->sr;
	}
	context->scratch2 = context->gpr[14] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->sr);
	context->did_mem = 1;
	context->gpr[14] = context->gpr[14] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void rotl_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[14] = context->gpr[14] << 1 | context->gpr[14] >> (32 - 1);
	context->t = context->gpr[14] & 1U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void rotr_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[14] = context->gpr[14] >> 1 | context->gpr[14] << (32 - 1);
	context->t = context->gpr[14] >> 24 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void lds_rm_postinc_mach_M_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[14] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[14], context);
	context->mach = context->scratch1;
	context->gpr[14] = 4 + context->gpr[14];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void ldc_rm_postinc_sr_M_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[14] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[14], context);
	context->cycles += context->opts->gen.clock_divider * 2;
	context->sr = context->scratch1 & 1011;
	context->gpr[14] = 4 + context->gpr[14];
	context->sr = 1011 & context->sr;
	context->t = context->sr & 1;
	context->s = context->sr >> 1;
	context->s = 1 & context->s;
	context->q = context->sr >> 8;
	context->q = 1 & context->q;
	context->m = context->sr >> 9;
	context->m = 1 & context->m;
	sh2_sync_cycle(context, target_cycle);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void shll2_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[14] = context->gpr[14] << 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void shlr2_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[14] = context->gpr[14] >> 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void lds_mach_M_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->mach = context->gpr[14];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void jsr_M_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->pr = context->pc + 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = context->gpr[14] - 2;
	context->cycles += context->opts->gen.clock_divider * 1;
}
static void ldc_rm_sr_M_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->sr = context->gpr[14] & 1011;
	context->sr = 1011 & context->sr;
	context->t = context->sr & 1;
	context->s = context->sr >> 1;
	context->s = 1 & context->s;
	context->q = context->sr >> 8;
	context->q = 1 & context->q;
	context->m = context->sr >> 9;
	context->m = 1 & context->m;
	sh2_sync_cycle(context, target_cycle);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void mac_w_M_0000_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[14] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[14], context);
	context->gpr[14] = 2 + context->gpr[14];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[0] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[0], context);
	context->gpr[0] = 2 + context->gpr[0];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dt_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[14] = context->gpr[14] - 1;
	context->t = context->gpr[14] == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmppz_rn_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[14]) >= ((int32_t)0)) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sts_macl_rn_predec_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[14] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->macl);
	context->did_mem = 1;
	context->gpr[14] = context->gpr[14] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void stc_gbr_rn_predec_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->scratch2 = context->gpr[14] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gbr);
	context->did_mem = 1;
	context->gpr[14] = context->gpr[14] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void cmppl_rn_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[14]) >= ((int32_t)1)) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void lds_rm_postinc_macl_M_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[14] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[14], context);
	context->macl = context->scratch1;
	context->gpr[14] = 4 + context->gpr[14];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void ldc_rm_postinc_gbr_M_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[14] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[14], context);
	context->cycles += context->opts->gen.clock_divider * 2;
	context->gbr = context->scratch1;
	context->gpr[14] = 4 + context->gpr[14];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void shll8_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[14] = context->gpr[14] << 8;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void shlr8_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[14] = context->gpr[14] >> 8;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void lds_macl_M_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->macl = context->gpr[14];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void tas_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (536870912 >= context->gpr[14]) {
	context->scratch1 = context->gpr[14] | 536870912;
	} else {
	context->scratch1 = context->gpr[14];
	}
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->cycles += context->opts->gen.clock_divider * 3;
	context->t = !context->scratch1;
	context->scratch1 = 128 | context->scratch1;
	sh2_write8_tmp = context->gpr[14] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[14], context, context->scratch1);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void ldc_rm_gbr_M_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gbr = context->gpr[14];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void mac_w_M_0001_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[14] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[14], context);
	context->gpr[14] = 2 + context->gpr[14];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[1] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[1], context);
	context->gpr[1] = 2 + context->gpr[1];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void shal_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[14]) << 1ULL;
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[14] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void shar_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = (context->gpr[14] >> 1) | ((context->gpr[14] & 2147483648) && 1 ? 0xFFFFFFFFU << (32 - 1) : 0);
	context->t = context->gpr[14] & 1U;
	context->gpr[14] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sts_pr_rn_predec_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[14] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->pr);
	context->did_mem = 1;
	context->gpr[14] = context->gpr[14] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void stc_vbr_rn_predec_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->scratch2 = context->gpr[14] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->vbr);
	context->did_mem = 1;
	context->gpr[14] = context->gpr[14] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void rotcl_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = ((uint64_t)context->gpr[14]) << 1 | ((uint64_t)context->gpr[14]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[14] >> 24 & 128U;
	context->gpr[14] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void rotcr_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = ((uint64_t)context->gpr[14]) >> 1 | ((uint64_t)context->gpr[14]) << (32 + 1 - 1) | (context->t ? 1 : 0) << (32-1);
	context->t = context->gpr[14] & 1U;
	context->gpr[14] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void lds_rm_postinc_pr_M_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[14] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[14], context);
	context->pr = context->scratch1;
	context->gpr[14] = 4 + context->gpr[14];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void ldc_rm_postinc_vbr_M_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[14] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[14], context);
	context->cycles += context->opts->gen.clock_divider * 2;
	context->vbr = context->scratch1;
	context->gpr[14] = 4 + context->gpr[14];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void shll16_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[14] = context->gpr[14] << 16;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void shlr16_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[14] = context->gpr[14] >> 16;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void lds_pr_M_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->pr = context->gpr[14];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void jmp_M_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = context->gpr[14] - 2;
	context->cycles += context->opts->gen.clock_divider * 1;
}
static void ldc_rm_vbr_M_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->vbr = context->gpr[14];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void mac_w_M_0010_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[14] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[14], context);
	context->gpr[14] = 2 + context->gpr[14];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[2] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[2], context);
	context->gpr[2] = 2 + context->gpr[2];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_w_M_0011_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[14] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[14], context);
	context->gpr[14] = 2 + context->gpr[14];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[3] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[3], context);
	context->gpr[3] = 2 + context->gpr[3];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_w_M_0100_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[14] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[14], context);
	context->gpr[14] = 2 + context->gpr[14];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[4] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[4], context);
	context->gpr[4] = 2 + context->gpr[4];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_w_M_0101_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[14] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[14], context);
	context->gpr[14] = 2 + context->gpr[14];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[5] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[5], context);
	context->gpr[5] = 2 + context->gpr[5];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_w_M_0110_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[14] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[14], context);
	context->gpr[14] = 2 + context->gpr[14];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[6] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[6], context);
	context->gpr[6] = 2 + context->gpr[6];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_w_M_0111_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[14] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[14], context);
	context->gpr[14] = 2 + context->gpr[14];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[7] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[7], context);
	context->gpr[7] = 2 + context->gpr[7];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_w_M_1000_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[14] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[14], context);
	context->gpr[14] = 2 + context->gpr[14];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[8] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[8], context);
	context->gpr[8] = 2 + context->gpr[8];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_w_M_1001_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[14] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[14], context);
	context->gpr[14] = 2 + context->gpr[14];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[9] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[9], context);
	context->gpr[9] = 2 + context->gpr[9];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_w_M_1010_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[14] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[14], context);
	context->gpr[14] = 2 + context->gpr[14];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[10] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[10], context);
	context->gpr[10] = 2 + context->gpr[10];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_w_M_1011_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[14] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[14], context);
	context->gpr[14] = 2 + context->gpr[14];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[11] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[11], context);
	context->gpr[11] = 2 + context->gpr[11];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_w_M_1100_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[14] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[14], context);
	context->gpr[14] = 2 + context->gpr[14];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[12] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[12], context);
	context->gpr[12] = 2 + context->gpr[12];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_w_M_1101_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[14] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[14], context);
	context->gpr[14] = 2 + context->gpr[14];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[13] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[13], context);
	context->gpr[13] = 2 + context->gpr[13];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_w_M_1110_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[14] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[14], context);
	context->gpr[14] = 2 + context->gpr[14];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[14] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[14], context);
	context->gpr[14] = 2 + context->gpr[14];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_w_M_1111_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[14] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[14], context);
	context->gpr[14] = 2 + context->gpr[14];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[15] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[15], context);
	context->gpr[15] = 2 + context->gpr[15];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void shll_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[15]) << 1ULL;
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[15] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void shlr_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = context->gpr[15] >> 1;
	context->t = context->gpr[15] & 1U;
	context->gpr[15] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sts_mach_rn_predec_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[15] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->mach);
	context->did_mem = 1;
	context->gpr[15] = context->gpr[15] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void stc_sr_rn_predec_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->sr = 240 & context->sr;
	if (context->t) {
	context->sr = 1 | context->sr;
	}
	if (context->s) {
	context->sr = 2 | context->sr;
	}
	if (context->q) {
	context->sr = 256 | context->sr;
	}
	if (context->m) {
	context->sr = 512 | context->sr;
	}
	context->scratch2 = context->gpr[15] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->sr);
	context->did_mem = 1;
	context->gpr[15] = context->gpr[15] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void rotl_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[15] = context->gpr[15] << 1 | context->gpr[15] >> (32 - 1);
	context->t = context->gpr[15] & 1U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void rotr_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[15] = context->gpr[15] >> 1 | context->gpr[15] << (32 - 1);
	context->t = context->gpr[15] >> 24 & 128U;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void lds_rm_postinc_mach_M_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[15] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[15], context);
	context->mach = context->scratch1;
	context->gpr[15] = 4 + context->gpr[15];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void ldc_rm_postinc_sr_M_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[15] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[15], context);
	context->cycles += context->opts->gen.clock_divider * 2;
	context->sr = context->scratch1 & 1011;
	context->gpr[15] = 4 + context->gpr[15];
	context->sr = 1011 & context->sr;
	context->t = context->sr & 1;
	context->s = context->sr >> 1;
	context->s = 1 & context->s;
	context->q = context->sr >> 8;
	context->q = 1 & context->q;
	context->m = context->sr >> 9;
	context->m = 1 & context->m;
	sh2_sync_cycle(context, target_cycle);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void shll2_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[15] = context->gpr[15] << 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void shlr2_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[15] = context->gpr[15] >> 2;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void lds_mach_M_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->mach = context->gpr[15];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void jsr_M_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->pr = context->pc + 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = context->gpr[15] - 2;
	context->cycles += context->opts->gen.clock_divider * 1;
}
static void ldc_rm_sr_M_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->sr = context->gpr[15] & 1011;
	context->sr = 1011 & context->sr;
	context->t = context->sr & 1;
	context->s = context->sr >> 1;
	context->s = 1 & context->s;
	context->q = context->sr >> 8;
	context->q = 1 & context->q;
	context->m = context->sr >> 9;
	context->m = 1 & context->m;
	sh2_sync_cycle(context, target_cycle);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void mac_w_M_0000_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[15] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[15], context);
	context->gpr[15] = 2 + context->gpr[15];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[0] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[0], context);
	context->gpr[0] = 2 + context->gpr[0];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void dt_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[15] = context->gpr[15] - 1;
	context->t = context->gpr[15] == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmppz_rn_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[15]) >= ((int32_t)0)) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sts_macl_rn_predec_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[15] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->macl);
	context->did_mem = 1;
	context->gpr[15] = context->gpr[15] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void stc_gbr_rn_predec_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->scratch2 = context->gpr[15] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gbr);
	context->did_mem = 1;
	context->gpr[15] = context->gpr[15] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void cmppl_rn_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (((int32_t)context->gpr[15]) >= ((int32_t)1)) {
	context->t = 1;
	} else {
	context->t = 0;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void lds_rm_postinc_macl_M_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[15] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[15], context);
	context->macl = context->scratch1;
	context->gpr[15] = 4 + context->gpr[15];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void ldc_rm_postinc_gbr_M_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[15] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[15], context);
	context->cycles += context->opts->gen.clock_divider * 2;
	context->gbr = context->scratch1;
	context->gpr[15] = 4 + context->gpr[15];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void shll8_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[15] = context->gpr[15] << 8;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void shlr8_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[15] = context->gpr[15] >> 8;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void lds_macl_M_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->macl = context->gpr[15];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void tas_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (536870912 >= context->gpr[15]) {
	context->scratch1 = context->gpr[15] | 536870912;
	} else {
	context->scratch1 = context->gpr[15];
	}
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->cycles += context->opts->gen.clock_divider * 3;
	context->t = !context->scratch1;
	context->scratch1 = 128 | context->scratch1;
	sh2_write8_tmp = context->gpr[15] >> 29;
	context->write8[sh2_write8_tmp](context->gpr[15], context, context->scratch1);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void ldc_rm_gbr_M_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gbr = context->gpr[15];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void mac_w_M_0001_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[15] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[15], context);
	context->gpr[15] = 2 + context->gpr[15];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[1] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[1], context);
	context->gpr[1] = 2 + context->gpr[1];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void shal_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)context->gpr[15]) << 1ULL;
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[15] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void shar_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = (context->gpr[15] >> 1) | ((context->gpr[15] & 2147483648) && 1 ? 0xFFFFFFFFU << (32 - 1) : 0);
	context->t = context->gpr[15] & 1U;
	context->gpr[15] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void sts_pr_rn_predec_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = context->gpr[15] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->pr);
	context->did_mem = 1;
	context->gpr[15] = context->gpr[15] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void stc_vbr_rn_predec_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->scratch2 = context->gpr[15] - 4;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->vbr);
	context->did_mem = 1;
	context->gpr[15] = context->gpr[15] - 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void rotcl_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = ((uint64_t)context->gpr[15]) << 1 | ((uint64_t)context->gpr[15]) >> (32 + 1 - 1) | (context->t ? 1 : 0) << (1 - 1);
	context->t = context->gpr[15] >> 24 & 128U;
	context->gpr[15] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void rotcr_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp32__ = ((uint64_t)context->gpr[15]) >> 1 | ((uint64_t)context->gpr[15]) << (32 + 1 - 1) | (context->t ? 1 : 0) << (32-1);
	context->t = context->gpr[15] & 1U;
	context->gpr[15] = gen_tmp32__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void lds_rm_postinc_pr_M_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[15] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[15], context);
	context->pr = context->scratch1;
	context->gpr[15] = 4 + context->gpr[15];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void ldc_rm_postinc_vbr_M_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[15] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[15], context);
	context->cycles += context->opts->gen.clock_divider * 2;
	context->vbr = context->scratch1;
	context->gpr[15] = 4 + context->gpr[15];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void shll16_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[15] = context->gpr[15] << 16;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void shlr16_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[15] = context->gpr[15] >> 16;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void lds_pr_M_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->pr = context->gpr[15];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void jmp_M_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = context->gpr[15] - 2;
	context->cycles += context->opts->gen.clock_divider * 1;
}
static void ldc_rm_vbr_M_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->vbr = context->gpr[15];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	context->delay_slot = 1;
}
static void mac_w_M_0010_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[15] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[15], context);
	context->gpr[15] = 2 + context->gpr[15];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[2] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[2], context);
	context->gpr[2] = 2 + context->gpr[2];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_w_M_0011_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[15] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[15], context);
	context->gpr[15] = 2 + context->gpr[15];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[3] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[3], context);
	context->gpr[3] = 2 + context->gpr[3];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_w_M_0100_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[15] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[15], context);
	context->gpr[15] = 2 + context->gpr[15];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[4] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[4], context);
	context->gpr[4] = 2 + context->gpr[4];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_w_M_0101_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[15] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[15], context);
	context->gpr[15] = 2 + context->gpr[15];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[5] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[5], context);
	context->gpr[5] = 2 + context->gpr[5];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_w_M_0110_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[15] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[15], context);
	context->gpr[15] = 2 + context->gpr[15];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[6] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[6], context);
	context->gpr[6] = 2 + context->gpr[6];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_w_M_0111_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[15] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[15], context);
	context->gpr[15] = 2 + context->gpr[15];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[7] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[7], context);
	context->gpr[7] = 2 + context->gpr[7];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_w_M_1000_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[15] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[15], context);
	context->gpr[15] = 2 + context->gpr[15];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[8] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[8], context);
	context->gpr[8] = 2 + context->gpr[8];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_w_M_1001_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[15] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[15], context);
	context->gpr[15] = 2 + context->gpr[15];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[9] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[9], context);
	context->gpr[9] = 2 + context->gpr[9];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_w_M_1010_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[15] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[15], context);
	context->gpr[15] = 2 + context->gpr[15];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[10] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[10], context);
	context->gpr[10] = 2 + context->gpr[10];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_w_M_1011_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[15] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[15], context);
	context->gpr[15] = 2 + context->gpr[15];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[11] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[11], context);
	context->gpr[11] = 2 + context->gpr[11];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_w_M_1100_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[15] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[15], context);
	context->gpr[15] = 2 + context->gpr[15];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[12] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[12], context);
	context->gpr[12] = 2 + context->gpr[12];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_w_M_1101_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[15] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[15], context);
	context->gpr[15] = 2 + context->gpr[15];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[13] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[13], context);
	context->gpr[13] = 2 + context->gpr[13];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_w_M_1110_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[15] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[15], context);
	context->gpr[15] = 2 + context->gpr[15];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[14] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[14], context);
	context->gpr[14] = 2 + context->gpr[14];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mac_w_M_1111_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint64_t tmp1;
	uint64_t tmp2;
	uint32_t tmpn;
	uint32_t tmpm;
	uint64_t cmp_tmp64__;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[15] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[15], context);
	context->gpr[15] = 2 + context->gpr[15];
	tmpn = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[15] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[15], context);
	context->gpr[15] = 2 + context->gpr[15];
	tmpm = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	tmp1 = (int64_t)(((int64_t)((int32_t)tmpn)) * ((int64_t)((int32_t)tmpm)));
	if (context->s) {
	tmp2 = context->macl & 2147483648UL ? context->macl | 18446744069414584320ULL : context->macl;
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	if (((int64_t)tmp1) >= ((int64_t)2147483648)) {
	tmp1 = 2147483647ULL;
	context->mach = 1 | context->mach;
	} else {
	if (((int64_t)-2147483649) >= ((int64_t)tmp1)) {
	tmp1 = 2147483648ULL;
	context->mach = 1 | context->mach;
	} else {
	tmp1 = 4294967295ULL & ((uint64_t)tmp1);
	}
	}
	} else {
	tmp2 = ((uint64_t)context->mach) << 32ULL;
	tmp2 = ((uint64_t)context->macl) | ((uint64_t)tmp2);
	tmp1 = ((uint64_t)tmp2) + ((uint64_t)tmp1);
	context->mach = tmp1 >> 32;
	}
	context->macl = tmp1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_0000_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[0] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_0000_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[0] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_0000_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[0] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_0000_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[0] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_0000_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[0] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_0000_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[0] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_0000_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[0] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_0000_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[0] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_0000_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[0] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_0000_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[0] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_0000_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[0] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_0000_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[0] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_0000_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[0] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_0000_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[0] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_0000_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[0] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_0000_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[0] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_0001_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[1] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_0001_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[1] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_0001_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[1] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_0001_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[1] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_0001_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[1] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_0001_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[1] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_0001_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[1] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_0001_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[1] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_0001_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[1] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_0001_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[1] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_0001_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[1] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_0001_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[1] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_0001_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[1] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_0001_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[1] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_0001_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[1] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_0001_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[1] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_0010_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[2] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_0010_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[2] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_0010_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[2] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_0010_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[2] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_0010_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[2] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_0010_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[2] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_0010_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[2] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_0010_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[2] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_0010_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[2] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_0010_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[2] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_0010_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[2] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_0010_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[2] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_0010_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[2] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_0010_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[2] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_0010_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[2] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_0010_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[2] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_0011_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[3] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_0011_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[3] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_0011_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[3] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_0011_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[3] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_0011_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[3] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_0011_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[3] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_0011_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[3] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_0011_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[3] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_0011_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[3] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_0011_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[3] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_0011_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[3] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_0011_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[3] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_0011_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[3] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_0011_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[3] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_0011_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[3] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_0011_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[3] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_0100_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[4] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_0100_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[4] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_0100_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[4] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_0100_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[4] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_0100_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[4] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_0100_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[4] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_0100_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[4] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_0100_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[4] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_0100_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[4] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_0100_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[4] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_0100_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[4] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_0100_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[4] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_0100_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[4] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_0100_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[4] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_0100_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[4] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_0100_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[4] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_0101_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[5] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_0101_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[5] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_0101_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[5] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_0101_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[5] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_0101_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[5] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_0101_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[5] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_0101_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[5] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_0101_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[5] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_0101_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[5] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_0101_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[5] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_0101_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[5] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_0101_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[5] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_0101_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[5] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_0101_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[5] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_0101_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[5] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_0101_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[5] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_0110_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[6] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_0110_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[6] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_0110_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[6] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_0110_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[6] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_0110_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[6] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_0110_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[6] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_0110_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[6] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_0110_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[6] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_0110_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[6] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_0110_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[6] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_0110_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[6] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_0110_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[6] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_0110_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[6] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_0110_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[6] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_0110_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[6] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_0110_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[6] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_0111_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[7] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_0111_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[7] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_0111_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[7] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_0111_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[7] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_0111_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[7] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_0111_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[7] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_0111_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[7] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_0111_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[7] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_0111_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[7] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_0111_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[7] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_0111_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[7] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_0111_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[7] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_0111_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[7] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_0111_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[7] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_0111_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[7] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_0111_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[7] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_1000_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[8] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_1000_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[8] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_1000_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[8] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_1000_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[8] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_1000_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[8] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_1000_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[8] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_1000_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[8] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_1000_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[8] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_1000_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[8] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_1000_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[8] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_1000_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[8] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_1000_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[8] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_1000_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[8] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_1000_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[8] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_1000_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[8] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_1000_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[8] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_1001_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[9] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_1001_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[9] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_1001_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[9] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_1001_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[9] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_1001_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[9] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_1001_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[9] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_1001_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[9] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_1001_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[9] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_1001_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[9] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_1001_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[9] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_1001_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[9] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_1001_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[9] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_1001_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[9] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_1001_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[9] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_1001_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[9] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_1001_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[9] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_1010_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[10] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_1010_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[10] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_1010_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[10] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_1010_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[10] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_1010_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[10] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_1010_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[10] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_1010_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[10] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_1010_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[10] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_1010_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[10] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_1010_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[10] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_1010_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[10] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_1010_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[10] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_1010_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[10] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_1010_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[10] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_1010_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[10] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_1010_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[10] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_1011_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[11] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_1011_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[11] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_1011_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[11] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_1011_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[11] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_1011_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[11] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_1011_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[11] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_1011_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[11] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_1011_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[11] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_1011_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[11] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_1011_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[11] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_1011_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[11] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_1011_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[11] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_1011_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[11] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_1011_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[11] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_1011_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[11] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_1011_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[11] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_1100_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[12] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_1100_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[12] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_1100_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[12] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_1100_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[12] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_1100_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[12] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_1100_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[12] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_1100_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[12] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_1100_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[12] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_1100_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[12] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_1100_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[12] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_1100_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[12] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_1100_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[12] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_1100_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[12] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_1100_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[12] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_1100_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[12] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_1100_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[12] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_1101_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[13] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_1101_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[13] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_1101_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[13] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_1101_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[13] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_1101_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[13] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_1101_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[13] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_1101_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[13] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_1101_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[13] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_1101_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[13] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_1101_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[13] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_1101_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[13] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_1101_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[13] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_1101_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[13] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_1101_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[13] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_1101_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[13] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_1101_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[13] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_1110_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[14] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_1110_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[14] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_1110_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[14] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_1110_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[14] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_1110_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[14] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_1110_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[14] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_1110_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[14] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_1110_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[14] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_1110_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[14] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_1110_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[14] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_1110_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[14] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_1110_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[14] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_1110_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[14] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_1110_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[14] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_1110_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[14] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_1110_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[14] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_1111_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[15] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_1111_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[15] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_1111_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[15] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_1111_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[15] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_1111_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[15] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_1111_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[15] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_1111_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[15] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_1111_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[15] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_1111_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[15] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_1111_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[15] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_1111_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[15] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_1111_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[15] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_1111_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[15] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_1111_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[15] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_1111_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[15] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_1111_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[15] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_0000_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[0] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_0000_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[0] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_0000_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[0] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_0000_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[0] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_0000_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[0] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_0000_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[0] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_0000_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[0] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_0000_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[0] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_0000_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[0] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_0000_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[0] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_0000_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[0] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_0000_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[0] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_0000_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[0] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_0000_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[0] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_0000_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[0] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_0000_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[0] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_0001_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[1] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_0001_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[1] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_0001_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[1] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_0001_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[1] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_0001_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[1] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_0001_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[1] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_0001_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[1] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_0001_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[1] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_0001_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[1] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_0001_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[1] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_0001_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[1] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_0001_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[1] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_0001_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[1] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_0001_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[1] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_0001_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[1] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_0001_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[1] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_0010_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[2] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_0010_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[2] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_0010_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[2] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_0010_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[2] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_0010_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[2] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_0010_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[2] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_0010_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[2] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_0010_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[2] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_0010_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[2] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_0010_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[2] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_0010_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[2] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_0010_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[2] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_0010_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[2] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_0010_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[2] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_0010_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[2] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_0010_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[2] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_0011_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[3] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_0011_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[3] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_0011_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[3] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_0011_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[3] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_0011_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[3] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_0011_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[3] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_0011_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[3] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_0011_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[3] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_0011_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[3] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_0011_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[3] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_0011_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[3] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_0011_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[3] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_0011_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[3] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_0011_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[3] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_0011_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[3] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_0011_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[3] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_0100_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[4] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_0100_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[4] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_0100_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[4] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_0100_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[4] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_0100_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[4] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_0100_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[4] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_0100_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[4] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_0100_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[4] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_0100_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[4] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_0100_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[4] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_0100_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[4] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_0100_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[4] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_0100_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[4] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_0100_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[4] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_0100_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[4] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_0100_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[4] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_0101_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[5] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_0101_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[5] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_0101_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[5] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_0101_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[5] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_0101_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[5] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_0101_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[5] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_0101_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[5] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_0101_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[5] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_0101_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[5] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_0101_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[5] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_0101_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[5] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_0101_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[5] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_0101_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[5] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_0101_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[5] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_0101_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[5] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_0101_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[5] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_0110_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[6] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_0110_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[6] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_0110_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[6] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_0110_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[6] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_0110_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[6] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_0110_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[6] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_0110_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[6] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_0110_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[6] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_0110_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[6] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_0110_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[6] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_0110_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[6] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_0110_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[6] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_0110_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[6] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_0110_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[6] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_0110_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[6] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_0110_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[6] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_0111_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[7] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_0111_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[7] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_0111_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[7] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_0111_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[7] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_0111_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[7] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_0111_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[7] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_0111_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[7] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_0111_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[7] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_0111_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[7] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_0111_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[7] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_0111_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[7] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_0111_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[7] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_0111_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[7] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_0111_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[7] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_0111_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[7] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_0111_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[7] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_1000_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[8] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_1000_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[8] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_1000_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[8] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_1000_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[8] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_1000_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[8] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_1000_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[8] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_1000_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[8] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_1000_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[8] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_1000_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[8] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_1000_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[8] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_1000_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[8] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_1000_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[8] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_1000_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[8] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_1000_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[8] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_1000_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[8] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_1000_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[8] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_1001_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[9] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_1001_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[9] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_1001_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[9] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_1001_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[9] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_1001_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[9] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_1001_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[9] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_1001_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[9] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_1001_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[9] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_1001_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[9] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_1001_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[9] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_1001_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[9] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_1001_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[9] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_1001_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[9] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_1001_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[9] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_1001_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[9] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_1001_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[9] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_1010_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[10] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_1010_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[10] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_1010_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[10] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_1010_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[10] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_1010_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[10] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_1010_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[10] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_1010_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[10] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_1010_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[10] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_1010_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[10] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_1010_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[10] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_1010_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[10] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_1010_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[10] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_1010_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[10] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_1010_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[10] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_1010_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[10] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_1010_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[10] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_1011_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[11] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_1011_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[11] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_1011_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[11] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_1011_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[11] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_1011_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[11] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_1011_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[11] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_1011_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[11] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_1011_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[11] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_1011_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[11] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_1011_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[11] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_1011_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[11] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_1011_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[11] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_1011_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[11] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_1011_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[11] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_1011_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[11] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_1011_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[11] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_1100_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[12] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_1100_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[12] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_1100_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[12] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_1100_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[12] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_1100_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[12] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_1100_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[12] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_1100_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[12] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_1100_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[12] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_1100_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[12] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_1100_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[12] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_1100_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[12] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_1100_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[12] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_1100_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[12] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_1100_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[12] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_1100_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[12] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_1100_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[12] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_1101_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[13] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_1101_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[13] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_1101_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[13] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_1101_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[13] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_1101_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[13] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_1101_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[13] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_1101_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[13] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_1101_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[13] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_1101_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[13] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_1101_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[13] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_1101_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[13] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_1101_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[13] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_1101_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[13] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_1101_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[13] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_1101_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[13] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_1101_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[13] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_1110_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[14] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_1110_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[14] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_1110_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[14] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_1110_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[14] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_1110_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[14] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_1110_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[14] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_1110_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[14] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_1110_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[14] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_1110_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[14] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_1110_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[14] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_1110_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[14] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_1110_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[14] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_1110_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[14] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_1110_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[14] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_1110_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[14] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_1110_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[14] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_1111_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[15] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_1111_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[15] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_1111_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[15] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_1111_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[15] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_1111_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[15] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_1111_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[15] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_1111_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[15] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_1111_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[15] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_1111_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[15] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_1111_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[15] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_1111_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[15] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_1111_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[15] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_1111_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[15] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_1111_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[15] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_1111_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[15] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_1111_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[15] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_0000_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[0] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_0000_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[0] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_0000_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[0] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_0000_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[0] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_0000_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[0] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_0000_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[0] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_0000_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[0] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_0000_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[0] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_0000_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[0] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_0000_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[0] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_0000_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[0] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_0000_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[0] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_0000_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[0] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_0000_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[0] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_0000_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[0] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_0000_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[0] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_0001_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[1] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_0001_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[1] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_0001_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[1] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_0001_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[1] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_0001_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[1] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_0001_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[1] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_0001_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[1] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_0001_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[1] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_0001_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[1] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_0001_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[1] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_0001_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[1] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_0001_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[1] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_0001_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[1] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_0001_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[1] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_0001_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[1] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_0001_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[1] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_0010_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[2] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_0010_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[2] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_0010_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[2] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_0010_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[2] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_0010_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[2] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_0010_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[2] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_0010_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[2] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_0010_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[2] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_0010_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[2] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_0010_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[2] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_0010_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[2] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_0010_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[2] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_0010_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[2] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_0010_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[2] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_0010_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[2] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_0010_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[2] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_0011_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[3] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_0011_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[3] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_0011_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[3] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_0011_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[3] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_0011_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[3] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_0011_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[3] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_0011_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[3] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_0011_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[3] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_0011_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[3] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_0011_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[3] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_0011_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[3] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_0011_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[3] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_0011_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[3] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_0011_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[3] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_0011_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[3] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_0011_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[3] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_0100_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[4] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_0100_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[4] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_0100_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[4] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_0100_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[4] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_0100_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[4] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_0100_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[4] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_0100_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[4] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_0100_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[4] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_0100_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[4] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_0100_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[4] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_0100_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[4] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_0100_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[4] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_0100_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[4] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_0100_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[4] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_0100_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[4] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_0100_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[4] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_0101_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[5] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_0101_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[5] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_0101_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[5] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_0101_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[5] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_0101_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[5] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_0101_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[5] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_0101_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[5] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_0101_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[5] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_0101_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[5] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_0101_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[5] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_0101_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[5] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_0101_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[5] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_0101_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[5] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_0101_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[5] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_0101_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[5] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_0101_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[5] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_0110_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[6] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_0110_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[6] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_0110_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[6] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_0110_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[6] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_0110_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[6] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_0110_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[6] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_0110_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[6] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_0110_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[6] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_0110_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[6] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_0110_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[6] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_0110_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[6] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_0110_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[6] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_0110_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[6] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_0110_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[6] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_0110_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[6] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_0110_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[6] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_0111_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[7] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_0111_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[7] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_0111_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[7] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_0111_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[7] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_0111_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[7] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_0111_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[7] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_0111_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[7] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_0111_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[7] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_0111_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[7] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_0111_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[7] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_0111_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[7] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_0111_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[7] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_0111_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[7] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_0111_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[7] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_0111_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[7] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_0111_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[7] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_1000_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[8] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_1000_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[8] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_1000_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[8] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_1000_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[8] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_1000_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[8] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_1000_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[8] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_1000_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[8] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_1000_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[8] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_1000_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[8] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_1000_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[8] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_1000_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[8] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_1000_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[8] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_1000_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[8] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_1000_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[8] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_1000_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[8] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_1000_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[8] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_1001_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[9] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_1001_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[9] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_1001_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[9] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_1001_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[9] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_1001_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[9] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_1001_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[9] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_1001_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[9] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_1001_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[9] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_1001_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[9] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_1001_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[9] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_1001_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[9] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_1001_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[9] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_1001_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[9] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_1001_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[9] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_1001_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[9] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_1001_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[9] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_1010_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[10] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_1010_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[10] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_1010_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[10] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_1010_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[10] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_1010_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[10] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_1010_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[10] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_1010_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[10] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_1010_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[10] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_1010_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[10] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_1010_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[10] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_1010_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[10] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_1010_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[10] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_1010_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[10] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_1010_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[10] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_1010_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[10] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_1010_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[10] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_1011_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[11] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_1011_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[11] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_1011_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[11] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_1011_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[11] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_1011_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[11] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_1011_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[11] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_1011_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[11] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_1011_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[11] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_1011_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[11] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_1011_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[11] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_1011_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[11] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_1011_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[11] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_1011_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[11] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_1011_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[11] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_1011_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[11] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_1011_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[11] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_1100_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[12] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_1100_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[12] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_1100_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[12] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_1100_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[12] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_1100_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[12] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_1100_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[12] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_1100_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[12] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_1100_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[12] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_1100_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[12] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_1100_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[12] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_1100_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[12] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_1100_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[12] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_1100_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[12] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_1100_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[12] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_1100_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[12] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_1100_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[12] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_1101_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[13] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_1101_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[13] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_1101_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[13] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_1101_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[13] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_1101_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[13] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_1101_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[13] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_1101_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[13] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_1101_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[13] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_1101_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[13] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_1101_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[13] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_1101_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[13] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_1101_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[13] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_1101_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[13] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_1101_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[13] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_1101_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[13] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_1101_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[13] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_1110_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[14] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_1110_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[14] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_1110_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[14] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_1110_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[14] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_1110_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[14] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_1110_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[14] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_1110_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[14] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_1110_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[14] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_1110_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[14] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_1110_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[14] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_1110_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[14] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_1110_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[14] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_1110_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[14] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_1110_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[14] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_1110_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[14] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_1110_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[14] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_1111_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[15] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_1111_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[15] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_1111_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[15] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_1111_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[15] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_1111_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[15] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_1111_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[15] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_1111_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[15] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_1111_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[15] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_1111_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[15] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_1111_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[15] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_1111_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[15] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_1111_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[15] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_1111_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[15] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_1111_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[15] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_1111_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[15] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_1111_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[15] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_0000_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[0] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_0000_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[0] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_0000_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[0] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_0000_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[0] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_0000_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[0] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_0000_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[0] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_0000_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[0] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_0000_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[0] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_0000_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[0] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_0000_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[0] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_0000_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[0] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_0000_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[0] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_0000_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[0] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_0000_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[0] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_0000_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[0] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_0000_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[0] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_0001_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[1] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_0001_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[1] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_0001_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[1] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_0001_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[1] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_0001_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[1] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_0001_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[1] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_0001_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[1] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_0001_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[1] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_0001_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[1] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_0001_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[1] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_0001_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[1] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_0001_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[1] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_0001_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[1] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_0001_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[1] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_0001_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[1] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_0001_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[1] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_0010_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[2] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_0010_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[2] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_0010_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[2] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_0010_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[2] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_0010_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[2] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_0010_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[2] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_0010_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[2] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_0010_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[2] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_0010_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[2] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_0010_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[2] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_0010_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[2] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_0010_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[2] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_0010_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[2] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_0010_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[2] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_0010_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[2] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_0010_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[2] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_0011_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[3] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_0011_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[3] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_0011_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[3] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_0011_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[3] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_0011_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[3] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_0011_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[3] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_0011_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[3] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_0011_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[3] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_0011_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[3] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_0011_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[3] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_0011_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[3] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_0011_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[3] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_0011_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[3] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_0011_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[3] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_0011_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[3] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_0011_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[3] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_0100_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[4] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_0100_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[4] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_0100_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[4] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_0100_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[4] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_0100_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[4] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_0100_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[4] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_0100_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[4] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_0100_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[4] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_0100_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[4] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_0100_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[4] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_0100_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[4] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_0100_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[4] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_0100_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[4] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_0100_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[4] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_0100_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[4] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_0100_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[4] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_0101_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[5] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_0101_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[5] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_0101_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[5] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_0101_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[5] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_0101_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[5] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_0101_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[5] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_0101_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[5] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_0101_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[5] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_0101_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[5] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_0101_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[5] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_0101_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[5] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_0101_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[5] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_0101_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[5] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_0101_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[5] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_0101_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[5] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_0101_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[5] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_0110_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[6] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_0110_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[6] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_0110_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[6] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_0110_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[6] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_0110_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[6] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_0110_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[6] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_0110_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[6] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_0110_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[6] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_0110_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[6] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_0110_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[6] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_0110_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[6] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_0110_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[6] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_0110_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[6] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_0110_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[6] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_0110_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[6] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_0110_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[6] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_0111_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[7] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_0111_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[7] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_0111_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[7] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_0111_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[7] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_0111_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[7] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_0111_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[7] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_0111_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[7] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_0111_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[7] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_0111_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[7] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_0111_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[7] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_0111_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[7] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_0111_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[7] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_0111_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[7] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_0111_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[7] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_0111_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[7] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_0111_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[7] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_1000_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[8] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_1000_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[8] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_1000_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[8] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_1000_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[8] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_1000_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[8] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_1000_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[8] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_1000_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[8] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_1000_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[8] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_1000_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[8] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_1000_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[8] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_1000_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[8] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_1000_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[8] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_1000_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[8] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_1000_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[8] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_1000_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[8] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_1000_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[8] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_1001_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[9] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_1001_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[9] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_1001_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[9] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_1001_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[9] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_1001_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[9] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_1001_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[9] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_1001_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[9] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_1001_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[9] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_1001_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[9] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_1001_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[9] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_1001_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[9] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_1001_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[9] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_1001_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[9] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_1001_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[9] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_1001_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[9] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_1001_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[9] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_1010_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[10] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_1010_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[10] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_1010_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[10] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_1010_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[10] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_1010_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[10] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_1010_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[10] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_1010_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[10] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_1010_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[10] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_1010_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[10] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_1010_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[10] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_1010_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[10] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_1010_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[10] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_1010_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[10] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_1010_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[10] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_1010_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[10] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_1010_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[10] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_1011_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[11] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_1011_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[11] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_1011_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[11] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_1011_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[11] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_1011_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[11] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_1011_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[11] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_1011_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[11] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_1011_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[11] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_1011_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[11] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_1011_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[11] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_1011_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[11] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_1011_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[11] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_1011_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[11] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_1011_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[11] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_1011_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[11] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_1011_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[11] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_1100_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[12] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_1100_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[12] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_1100_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[12] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_1100_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[12] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_1100_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[12] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_1100_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[12] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_1100_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[12] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_1100_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[12] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_1100_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[12] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_1100_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[12] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_1100_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[12] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_1100_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[12] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_1100_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[12] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_1100_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[12] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_1100_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[12] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_1100_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[12] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_1101_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[13] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_1101_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[13] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_1101_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[13] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_1101_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[13] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_1101_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[13] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_1101_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[13] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_1101_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[13] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_1101_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[13] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_1101_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[13] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_1101_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[13] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_1101_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[13] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_1101_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[13] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_1101_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[13] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_1101_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[13] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_1101_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[13] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_1101_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[13] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_1110_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[14] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_1110_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[14] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_1110_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[14] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_1110_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[14] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_1110_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[14] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_1110_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[14] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_1110_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[14] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_1110_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[14] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_1110_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[14] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_1110_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[14] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_1110_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[14] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_1110_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[14] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_1110_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[14] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_1110_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[14] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_1110_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[14] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_1110_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[14] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_1111_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[15] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_1111_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[15] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_1111_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[15] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_1111_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[15] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_1111_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[15] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_1111_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[15] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_1111_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[15] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_1111_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[15] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_1111_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[15] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_1111_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[15] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_1111_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[15] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_1111_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[15] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_1111_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[15] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_1111_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[15] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_1111_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[15] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_1111_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[15] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_0000_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[0] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_0000_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[0] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_0000_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[0] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_0000_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[0] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_0000_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[0] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_0000_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[0] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_0000_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[0] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_0000_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[0] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_0000_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[0] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_0000_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[0] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_0000_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[0] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_0000_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[0] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_0000_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[0] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_0000_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[0] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_0000_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[0] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_0000_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[0] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_0001_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[1] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_0001_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[1] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_0001_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[1] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_0001_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[1] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_0001_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[1] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_0001_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[1] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_0001_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[1] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_0001_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[1] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_0001_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[1] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_0001_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[1] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_0001_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[1] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_0001_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[1] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_0001_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[1] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_0001_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[1] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_0001_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[1] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_0001_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[1] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_0010_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[2] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_0010_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[2] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_0010_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[2] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_0010_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[2] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_0010_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[2] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_0010_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[2] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_0010_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[2] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_0010_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[2] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_0010_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[2] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_0010_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[2] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_0010_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[2] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_0010_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[2] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_0010_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[2] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_0010_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[2] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_0010_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[2] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_0010_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[2] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_0011_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[3] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_0011_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[3] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_0011_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[3] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_0011_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[3] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_0011_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[3] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_0011_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[3] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_0011_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[3] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_0011_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[3] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_0011_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[3] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_0011_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[3] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_0011_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[3] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_0011_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[3] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_0011_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[3] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_0011_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[3] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_0011_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[3] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_0011_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[3] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_0100_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[4] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_0100_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[4] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_0100_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[4] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_0100_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[4] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_0100_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[4] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_0100_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[4] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_0100_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[4] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_0100_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[4] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_0100_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[4] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_0100_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[4] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_0100_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[4] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_0100_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[4] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_0100_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[4] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_0100_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[4] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_0100_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[4] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_0100_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[4] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_0101_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[5] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_0101_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[5] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_0101_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[5] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_0101_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[5] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_0101_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[5] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_0101_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[5] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_0101_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[5] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_0101_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[5] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_0101_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[5] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_0101_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[5] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_0101_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[5] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_0101_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[5] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_0101_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[5] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_0101_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[5] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_0101_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[5] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_0101_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[5] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_0110_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[6] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_0110_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[6] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_0110_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[6] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_0110_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[6] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_0110_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[6] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_0110_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[6] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_0110_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[6] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_0110_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[6] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_0110_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[6] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_0110_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[6] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_0110_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[6] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_0110_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[6] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_0110_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[6] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_0110_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[6] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_0110_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[6] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_0110_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[6] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_0111_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[7] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_0111_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[7] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_0111_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[7] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_0111_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[7] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_0111_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[7] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_0111_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[7] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_0111_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[7] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_0111_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[7] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_0111_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[7] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_0111_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[7] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_0111_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[7] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_0111_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[7] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_0111_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[7] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_0111_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[7] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_0111_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[7] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_0111_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[7] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_1000_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[8] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_1000_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[8] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_1000_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[8] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_1000_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[8] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_1000_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[8] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_1000_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[8] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_1000_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[8] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_1000_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[8] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_1000_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[8] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_1000_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[8] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_1000_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[8] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_1000_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[8] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_1000_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[8] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_1000_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[8] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_1000_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[8] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_1000_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[8] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_1001_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[9] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_1001_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[9] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_1001_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[9] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_1001_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[9] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_1001_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[9] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_1001_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[9] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_1001_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[9] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_1001_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[9] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_1001_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[9] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_1001_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[9] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_1001_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[9] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_1001_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[9] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_1001_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[9] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_1001_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[9] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_1001_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[9] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_1001_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[9] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_1010_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[10] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_1010_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[10] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_1010_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[10] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_1010_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[10] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_1010_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[10] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_1010_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[10] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_1010_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[10] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_1010_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[10] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_1010_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[10] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_1010_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[10] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_1010_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[10] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_1010_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[10] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_1010_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[10] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_1010_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[10] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_1010_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[10] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_1010_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[10] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_1011_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[11] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_1011_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[11] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_1011_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[11] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_1011_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[11] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_1011_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[11] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_1011_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[11] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_1011_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[11] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_1011_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[11] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_1011_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[11] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_1011_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[11] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_1011_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[11] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_1011_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[11] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_1011_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[11] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_1011_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[11] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_1011_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[11] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_1011_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[11] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_1100_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[12] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_1100_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[12] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_1100_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[12] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_1100_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[12] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_1100_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[12] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_1100_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[12] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_1100_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[12] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_1100_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[12] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_1100_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[12] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_1100_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[12] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_1100_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[12] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_1100_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[12] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_1100_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[12] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_1100_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[12] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_1100_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[12] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_1100_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[12] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_1101_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[13] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_1101_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[13] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_1101_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[13] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_1101_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[13] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_1101_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[13] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_1101_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[13] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_1101_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[13] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_1101_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[13] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_1101_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[13] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_1101_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[13] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_1101_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[13] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_1101_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[13] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_1101_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[13] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_1101_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[13] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_1101_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[13] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_1101_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[13] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_1110_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[14] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_1110_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[14] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_1110_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[14] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_1110_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[14] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_1110_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[14] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_1110_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[14] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_1110_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[14] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_1110_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[14] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_1110_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[14] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_1110_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[14] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_1110_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[14] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_1110_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[14] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_1110_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[14] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_1110_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[14] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_1110_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[14] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_1110_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[14] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_1111_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[15] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_1111_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[15] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_1111_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[15] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_1111_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[15] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_1111_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[15] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_1111_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[15] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_1111_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[15] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_1111_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[15] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_1111_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[15] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_1111_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[15] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_1111_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[15] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_1111_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[15] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_1111_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[15] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_1111_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[15] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_1111_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[15] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_1111_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[15] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_0000_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[0] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_0000_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[0] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_0000_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[0] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_0000_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[0] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_0000_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[0] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_0000_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[0] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_0000_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[0] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_0000_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[0] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_0000_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[0] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_0000_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[0] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_0000_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[0] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_0000_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[0] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_0000_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[0] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_0000_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[0] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_0000_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[0] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_0000_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[0] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_0001_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[1] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_0001_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[1] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_0001_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[1] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_0001_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[1] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_0001_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[1] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_0001_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[1] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_0001_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[1] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_0001_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[1] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_0001_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[1] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_0001_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[1] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_0001_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[1] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_0001_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[1] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_0001_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[1] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_0001_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[1] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_0001_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[1] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_0001_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[1] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_0010_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[2] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_0010_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[2] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_0010_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[2] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_0010_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[2] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_0010_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[2] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_0010_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[2] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_0010_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[2] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_0010_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[2] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_0010_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[2] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_0010_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[2] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_0010_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[2] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_0010_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[2] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_0010_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[2] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_0010_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[2] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_0010_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[2] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_0010_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[2] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_0011_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[3] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_0011_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[3] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_0011_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[3] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_0011_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[3] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_0011_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[3] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_0011_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[3] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_0011_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[3] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_0011_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[3] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_0011_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[3] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_0011_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[3] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_0011_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[3] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_0011_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[3] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_0011_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[3] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_0011_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[3] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_0011_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[3] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_0011_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[3] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_0100_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[4] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_0100_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[4] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_0100_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[4] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_0100_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[4] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_0100_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[4] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_0100_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[4] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_0100_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[4] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_0100_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[4] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_0100_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[4] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_0100_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[4] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_0100_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[4] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_0100_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[4] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_0100_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[4] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_0100_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[4] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_0100_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[4] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_0100_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[4] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_0101_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[5] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_0101_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[5] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_0101_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[5] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_0101_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[5] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_0101_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[5] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_0101_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[5] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_0101_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[5] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_0101_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[5] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_0101_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[5] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_0101_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[5] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_0101_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[5] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_0101_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[5] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_0101_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[5] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_0101_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[5] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_0101_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[5] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_0101_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[5] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_0110_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[6] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_0110_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[6] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_0110_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[6] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_0110_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[6] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_0110_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[6] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_0110_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[6] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_0110_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[6] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_0110_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[6] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_0110_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[6] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_0110_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[6] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_0110_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[6] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_0110_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[6] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_0110_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[6] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_0110_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[6] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_0110_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[6] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_0110_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[6] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_0111_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[7] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_0111_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[7] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_0111_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[7] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_0111_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[7] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_0111_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[7] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_0111_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[7] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_0111_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[7] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_0111_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[7] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_0111_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[7] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_0111_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[7] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_0111_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[7] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_0111_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[7] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_0111_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[7] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_0111_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[7] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_0111_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[7] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_0111_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[7] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_1000_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[8] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_1000_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[8] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_1000_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[8] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_1000_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[8] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_1000_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[8] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_1000_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[8] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_1000_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[8] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_1000_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[8] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_1000_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[8] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_1000_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[8] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_1000_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[8] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_1000_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[8] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_1000_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[8] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_1000_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[8] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_1000_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[8] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_1000_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[8] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_1001_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[9] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_1001_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[9] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_1001_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[9] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_1001_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[9] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_1001_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[9] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_1001_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[9] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_1001_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[9] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_1001_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[9] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_1001_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[9] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_1001_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[9] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_1001_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[9] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_1001_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[9] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_1001_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[9] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_1001_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[9] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_1001_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[9] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_1001_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[9] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_1010_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[10] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_1010_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[10] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_1010_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[10] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_1010_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[10] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_1010_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[10] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_1010_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[10] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_1010_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[10] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_1010_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[10] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_1010_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[10] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_1010_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[10] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_1010_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[10] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_1010_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[10] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_1010_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[10] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_1010_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[10] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_1010_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[10] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_1010_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[10] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_1011_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[11] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_1011_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[11] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_1011_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[11] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_1011_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[11] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_1011_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[11] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_1011_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[11] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_1011_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[11] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_1011_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[11] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_1011_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[11] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_1011_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[11] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_1011_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[11] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_1011_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[11] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_1011_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[11] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_1011_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[11] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_1011_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[11] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_1011_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[11] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_1100_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[12] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_1100_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[12] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_1100_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[12] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_1100_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[12] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_1100_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[12] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_1100_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[12] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_1100_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[12] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_1100_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[12] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_1100_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[12] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_1100_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[12] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_1100_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[12] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_1100_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[12] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_1100_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[12] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_1100_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[12] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_1100_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[12] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_1100_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[12] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_1101_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[13] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_1101_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[13] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_1101_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[13] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_1101_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[13] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_1101_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[13] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_1101_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[13] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_1101_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[13] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_1101_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[13] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_1101_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[13] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_1101_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[13] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_1101_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[13] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_1101_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[13] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_1101_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[13] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_1101_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[13] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_1101_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[13] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_1101_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[13] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_1110_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[14] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_1110_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[14] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_1110_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[14] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_1110_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[14] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_1110_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[14] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_1110_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[14] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_1110_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[14] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_1110_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[14] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_1110_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[14] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_1110_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[14] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_1110_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[14] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_1110_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[14] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_1110_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[14] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_1110_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[14] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_1110_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[14] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_1110_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[14] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_1111_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[15] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_1111_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[15] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_1111_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[15] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_1111_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[15] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_1111_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[15] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_1111_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[15] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_1111_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[15] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_1111_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[15] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_1111_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[15] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_1111_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[15] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_1111_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[15] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_1111_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[15] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_1111_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[15] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_1111_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[15] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_1111_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[15] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_1111_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[15] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_0000_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[0] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_0000_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[0] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_0000_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[0] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_0000_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[0] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_0000_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[0] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_0000_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[0] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_0000_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[0] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_0000_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[0] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_0000_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[0] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_0000_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[0] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_0000_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[0] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_0000_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[0] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_0000_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[0] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_0000_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[0] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_0000_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[0] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_0000_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[0] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_0001_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[1] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_0001_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[1] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_0001_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[1] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_0001_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[1] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_0001_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[1] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_0001_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[1] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_0001_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[1] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_0001_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[1] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_0001_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[1] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_0001_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[1] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_0001_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[1] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_0001_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[1] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_0001_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[1] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_0001_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[1] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_0001_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[1] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_0001_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[1] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_0010_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[2] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_0010_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[2] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_0010_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[2] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_0010_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[2] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_0010_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[2] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_0010_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[2] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_0010_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[2] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_0010_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[2] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_0010_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[2] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_0010_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[2] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_0010_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[2] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_0010_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[2] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_0010_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[2] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_0010_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[2] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_0010_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[2] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_0010_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[2] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_0011_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[3] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_0011_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[3] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_0011_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[3] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_0011_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[3] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_0011_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[3] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_0011_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[3] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_0011_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[3] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_0011_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[3] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_0011_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[3] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_0011_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[3] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_0011_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[3] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_0011_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[3] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_0011_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[3] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_0011_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[3] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_0011_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[3] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_0011_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[3] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_0100_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[4] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_0100_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[4] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_0100_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[4] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_0100_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[4] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_0100_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[4] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_0100_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[4] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_0100_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[4] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_0100_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[4] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_0100_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[4] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_0100_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[4] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_0100_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[4] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_0100_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[4] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_0100_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[4] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_0100_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[4] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_0100_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[4] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_0100_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[4] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_0101_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[5] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_0101_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[5] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_0101_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[5] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_0101_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[5] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_0101_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[5] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_0101_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[5] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_0101_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[5] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_0101_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[5] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_0101_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[5] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_0101_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[5] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_0101_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[5] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_0101_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[5] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_0101_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[5] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_0101_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[5] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_0101_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[5] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_0101_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[5] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_0110_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[6] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_0110_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[6] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_0110_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[6] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_0110_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[6] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_0110_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[6] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_0110_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[6] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_0110_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[6] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_0110_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[6] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_0110_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[6] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_0110_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[6] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_0110_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[6] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_0110_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[6] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_0110_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[6] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_0110_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[6] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_0110_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[6] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_0110_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[6] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_0111_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[7] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_0111_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[7] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_0111_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[7] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_0111_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[7] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_0111_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[7] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_0111_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[7] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_0111_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[7] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_0111_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[7] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_0111_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[7] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_0111_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[7] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_0111_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[7] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_0111_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[7] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_0111_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[7] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_0111_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[7] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_0111_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[7] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_0111_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[7] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_1000_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[8] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_1000_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[8] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_1000_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[8] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_1000_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[8] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_1000_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[8] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_1000_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[8] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_1000_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[8] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_1000_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[8] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_1000_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[8] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_1000_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[8] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_1000_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[8] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_1000_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[8] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_1000_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[8] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_1000_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[8] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_1000_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[8] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_1000_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[8] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_1001_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[9] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_1001_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[9] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_1001_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[9] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_1001_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[9] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_1001_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[9] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_1001_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[9] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_1001_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[9] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_1001_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[9] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_1001_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[9] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_1001_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[9] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_1001_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[9] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_1001_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[9] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_1001_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[9] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_1001_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[9] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_1001_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[9] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_1001_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[9] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_1010_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[10] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_1010_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[10] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_1010_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[10] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_1010_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[10] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_1010_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[10] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_1010_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[10] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_1010_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[10] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_1010_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[10] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_1010_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[10] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_1010_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[10] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_1010_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[10] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_1010_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[10] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_1010_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[10] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_1010_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[10] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_1010_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[10] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_1010_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[10] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_1011_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[11] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_1011_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[11] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_1011_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[11] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_1011_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[11] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_1011_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[11] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_1011_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[11] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_1011_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[11] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_1011_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[11] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_1011_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[11] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_1011_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[11] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_1011_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[11] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_1011_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[11] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_1011_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[11] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_1011_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[11] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_1011_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[11] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_1011_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[11] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_1100_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[12] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_1100_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[12] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_1100_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[12] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_1100_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[12] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_1100_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[12] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_1100_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[12] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_1100_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[12] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_1100_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[12] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_1100_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[12] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_1100_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[12] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_1100_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[12] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_1100_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[12] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_1100_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[12] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_1100_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[12] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_1100_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[12] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_1100_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[12] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_1101_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[13] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_1101_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[13] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_1101_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[13] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_1101_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[13] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_1101_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[13] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_1101_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[13] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_1101_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[13] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_1101_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[13] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_1101_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[13] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_1101_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[13] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_1101_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[13] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_1101_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[13] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_1101_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[13] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_1101_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[13] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_1101_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[13] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_1101_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[13] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_1110_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[14] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_1110_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[14] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_1110_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[14] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_1110_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[14] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_1110_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[14] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_1110_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[14] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_1110_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[14] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_1110_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[14] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_1110_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[14] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_1110_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[14] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_1110_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[14] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_1110_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[14] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_1110_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[14] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_1110_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[14] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_1110_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[14] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_1110_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[14] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_1111_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[15] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_1111_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[15] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_1111_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[15] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_1111_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[15] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_1111_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[15] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_1111_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[15] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_1111_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[15] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_1111_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[15] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_1111_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[15] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_1111_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[15] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_1111_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[15] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_1111_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[15] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_1111_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[15] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_1111_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[15] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_1111_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[15] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_1111_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[15] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_0000_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[0] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_0000_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[0] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_0000_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[0] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_0000_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[0] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_0000_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[0] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_0000_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[0] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_0000_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[0] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_0000_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[0] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_0000_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[0] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_0000_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[0] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_0000_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[0] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_0000_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[0] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_0000_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[0] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_0000_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[0] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_0000_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[0] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_0000_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[0] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_0001_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[1] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_0001_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[1] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_0001_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[1] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_0001_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[1] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_0001_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[1] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_0001_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[1] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_0001_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[1] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_0001_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[1] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_0001_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[1] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_0001_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[1] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_0001_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[1] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_0001_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[1] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_0001_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[1] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_0001_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[1] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_0001_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[1] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_0001_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[1] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_0010_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[2] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_0010_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[2] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_0010_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[2] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_0010_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[2] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_0010_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[2] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_0010_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[2] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_0010_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[2] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_0010_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[2] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_0010_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[2] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_0010_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[2] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_0010_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[2] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_0010_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[2] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_0010_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[2] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_0010_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[2] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_0010_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[2] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_0010_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[2] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_0011_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[3] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_0011_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[3] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_0011_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[3] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_0011_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[3] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_0011_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[3] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_0011_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[3] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_0011_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[3] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_0011_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[3] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_0011_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[3] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_0011_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[3] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_0011_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[3] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_0011_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[3] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_0011_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[3] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_0011_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[3] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_0011_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[3] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_0011_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[3] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_0100_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[4] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_0100_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[4] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_0100_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[4] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_0100_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[4] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_0100_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[4] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_0100_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[4] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_0100_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[4] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_0100_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[4] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_0100_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[4] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_0100_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[4] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_0100_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[4] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_0100_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[4] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_0100_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[4] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_0100_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[4] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_0100_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[4] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_0100_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[4] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_0101_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[5] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_0101_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[5] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_0101_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[5] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_0101_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[5] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_0101_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[5] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_0101_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[5] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_0101_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[5] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_0101_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[5] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_0101_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[5] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_0101_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[5] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_0101_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[5] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_0101_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[5] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_0101_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[5] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_0101_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[5] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_0101_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[5] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_0101_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[5] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_0110_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[6] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_0110_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[6] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_0110_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[6] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_0110_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[6] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_0110_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[6] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_0110_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[6] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_0110_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[6] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_0110_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[6] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_0110_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[6] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_0110_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[6] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_0110_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[6] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_0110_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[6] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_0110_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[6] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_0110_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[6] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_0110_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[6] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_0110_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[6] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_0111_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[7] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_0111_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[7] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_0111_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[7] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_0111_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[7] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_0111_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[7] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_0111_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[7] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_0111_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[7] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_0111_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[7] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_0111_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[7] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_0111_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[7] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_0111_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[7] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_0111_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[7] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_0111_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[7] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_0111_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[7] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_0111_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[7] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_0111_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[7] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_1000_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[8] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_1000_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[8] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_1000_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[8] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_1000_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[8] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_1000_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[8] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_1000_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[8] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_1000_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[8] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_1000_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[8] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_1000_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[8] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_1000_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[8] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_1000_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[8] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_1000_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[8] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_1000_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[8] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_1000_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[8] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_1000_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[8] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_1000_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[8] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_1001_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[9] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_1001_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[9] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_1001_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[9] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_1001_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[9] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_1001_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[9] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_1001_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[9] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_1001_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[9] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_1001_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[9] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_1001_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[9] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_1001_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[9] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_1001_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[9] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_1001_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[9] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_1001_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[9] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_1001_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[9] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_1001_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[9] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_1001_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[9] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_1010_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[10] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_1010_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[10] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_1010_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[10] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_1010_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[10] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_1010_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[10] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_1010_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[10] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_1010_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[10] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_1010_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[10] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_1010_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[10] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_1010_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[10] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_1010_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[10] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_1010_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[10] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_1010_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[10] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_1010_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[10] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_1010_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[10] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_1010_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[10] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_1011_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[11] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_1011_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[11] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_1011_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[11] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_1011_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[11] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_1011_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[11] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_1011_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[11] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_1011_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[11] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_1011_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[11] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_1011_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[11] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_1011_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[11] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_1011_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[11] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_1011_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[11] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_1011_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[11] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_1011_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[11] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_1011_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[11] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_1011_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[11] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_1100_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[12] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_1100_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[12] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_1100_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[12] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_1100_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[12] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_1100_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[12] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_1100_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[12] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_1100_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[12] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_1100_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[12] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_1100_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[12] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_1100_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[12] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_1100_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[12] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_1100_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[12] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_1100_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[12] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_1100_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[12] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_1100_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[12] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_1100_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[12] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_1101_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[13] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_1101_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[13] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_1101_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[13] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_1101_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[13] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_1101_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[13] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_1101_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[13] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_1101_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[13] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_1101_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[13] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_1101_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[13] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_1101_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[13] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_1101_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[13] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_1101_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[13] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_1101_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[13] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_1101_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[13] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_1101_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[13] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_1101_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[13] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_1110_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[14] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_1110_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[14] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_1110_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[14] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_1110_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[14] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_1110_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[14] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_1110_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[14] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_1110_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[14] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_1110_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[14] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_1110_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[14] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_1110_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[14] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_1110_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[14] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_1110_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[14] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_1110_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[14] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_1110_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[14] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_1110_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[14] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_1110_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[14] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_1111_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[15] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_1111_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[15] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_1111_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[15] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_1111_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[15] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_1111_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[15] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_1111_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[15] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_1111_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[15] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_1111_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[15] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_1111_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[15] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_1111_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[15] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_1111_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[15] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_1111_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[15] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_1111_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[15] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_1111_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[15] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_1111_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[15] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_1111_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[15] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_0000_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[0] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_0000_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[0] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_0000_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[0] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_0000_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[0] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_0000_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[0] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_0000_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[0] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_0000_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[0] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_0000_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[0] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_0000_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[0] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_0000_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[0] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_0000_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[0] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_0000_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[0] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_0000_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[0] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_0000_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[0] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_0000_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[0] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_0000_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[0] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_0001_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[1] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_0001_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[1] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_0001_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[1] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_0001_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[1] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_0001_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[1] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_0001_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[1] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_0001_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[1] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_0001_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[1] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_0001_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[1] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_0001_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[1] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_0001_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[1] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_0001_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[1] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_0001_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[1] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_0001_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[1] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_0001_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[1] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_0001_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[1] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_0010_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[2] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_0010_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[2] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_0010_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[2] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_0010_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[2] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_0010_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[2] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_0010_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[2] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_0010_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[2] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_0010_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[2] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_0010_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[2] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_0010_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[2] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_0010_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[2] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_0010_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[2] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_0010_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[2] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_0010_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[2] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_0010_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[2] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_0010_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[2] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_0011_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[3] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_0011_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[3] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_0011_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[3] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_0011_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[3] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_0011_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[3] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_0011_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[3] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_0011_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[3] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_0011_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[3] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_0011_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[3] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_0011_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[3] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_0011_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[3] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_0011_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[3] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_0011_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[3] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_0011_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[3] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_0011_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[3] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_0011_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[3] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_0100_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[4] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_0100_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[4] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_0100_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[4] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_0100_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[4] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_0100_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[4] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_0100_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[4] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_0100_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[4] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_0100_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[4] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_0100_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[4] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_0100_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[4] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_0100_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[4] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_0100_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[4] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_0100_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[4] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_0100_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[4] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_0100_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[4] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_0100_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[4] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_0101_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[5] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_0101_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[5] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_0101_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[5] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_0101_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[5] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_0101_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[5] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_0101_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[5] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_0101_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[5] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_0101_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[5] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_0101_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[5] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_0101_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[5] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_0101_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[5] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_0101_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[5] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_0101_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[5] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_0101_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[5] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_0101_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[5] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_0101_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[5] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_0110_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[6] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_0110_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[6] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_0110_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[6] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_0110_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[6] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_0110_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[6] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_0110_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[6] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_0110_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[6] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_0110_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[6] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_0110_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[6] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_0110_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[6] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_0110_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[6] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_0110_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[6] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_0110_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[6] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_0110_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[6] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_0110_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[6] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_0110_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[6] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_0111_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[7] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_0111_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[7] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_0111_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[7] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_0111_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[7] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_0111_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[7] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_0111_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[7] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_0111_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[7] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_0111_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[7] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_0111_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[7] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_0111_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[7] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_0111_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[7] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_0111_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[7] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_0111_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[7] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_0111_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[7] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_0111_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[7] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_0111_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[7] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_1000_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[8] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_1000_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[8] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_1000_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[8] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_1000_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[8] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_1000_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[8] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_1000_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[8] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_1000_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[8] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_1000_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[8] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_1000_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[8] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_1000_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[8] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_1000_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[8] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_1000_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[8] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_1000_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[8] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_1000_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[8] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_1000_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[8] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_1000_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[8] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_1001_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[9] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_1001_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[9] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_1001_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[9] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_1001_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[9] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_1001_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[9] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_1001_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[9] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_1001_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[9] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_1001_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[9] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_1001_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[9] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_1001_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[9] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_1001_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[9] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_1001_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[9] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_1001_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[9] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_1001_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[9] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_1001_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[9] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_1001_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[9] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_1010_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[10] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_1010_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[10] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_1010_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[10] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_1010_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[10] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_1010_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[10] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_1010_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[10] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_1010_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[10] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_1010_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[10] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_1010_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[10] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_1010_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[10] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_1010_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[10] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_1010_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[10] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_1010_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[10] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_1010_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[10] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_1010_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[10] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_1010_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[10] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_1011_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[11] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_1011_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[11] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_1011_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[11] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_1011_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[11] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_1011_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[11] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_1011_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[11] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_1011_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[11] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_1011_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[11] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_1011_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[11] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_1011_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[11] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_1011_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[11] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_1011_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[11] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_1011_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[11] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_1011_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[11] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_1011_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[11] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_1011_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[11] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_1100_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[12] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_1100_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[12] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_1100_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[12] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_1100_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[12] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_1100_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[12] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_1100_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[12] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_1100_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[12] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_1100_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[12] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_1100_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[12] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_1100_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[12] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_1100_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[12] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_1100_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[12] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_1100_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[12] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_1100_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[12] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_1100_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[12] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_1100_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[12] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_1101_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[13] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_1101_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[13] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_1101_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[13] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_1101_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[13] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_1101_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[13] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_1101_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[13] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_1101_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[13] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_1101_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[13] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_1101_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[13] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_1101_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[13] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_1101_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[13] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_1101_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[13] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_1101_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[13] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_1101_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[13] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_1101_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[13] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_1101_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[13] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_1110_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[14] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_1110_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[14] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_1110_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[14] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_1110_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[14] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_1110_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[14] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_1110_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[14] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_1110_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[14] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_1110_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[14] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_1110_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[14] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_1110_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[14] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_1110_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[14] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_1110_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[14] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_1110_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[14] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_1110_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[14] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_1110_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[14] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_1110_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[14] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_1111_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[15] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_1111_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[15] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_1111_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[15] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_1111_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[15] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_1111_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[15] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_1111_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[15] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_1111_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[15] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_1111_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[15] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_1111_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[15] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_1111_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[15] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_1111_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[15] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_1111_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[15] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_1111_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[15] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_1111_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[15] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_1111_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[15] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_1111_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[15] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_0000_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[0] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_0000_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[0] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_0000_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[0] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_0000_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[0] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_0000_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[0] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_0000_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[0] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_0000_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[0] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_0000_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[0] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_0000_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[0] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_0000_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[0] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_0000_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[0] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_0000_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[0] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_0000_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[0] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_0000_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[0] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_0000_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[0] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_0000_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[0] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_0001_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[1] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_0001_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[1] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_0001_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[1] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_0001_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[1] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_0001_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[1] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_0001_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[1] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_0001_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[1] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_0001_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[1] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_0001_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[1] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_0001_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[1] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_0001_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[1] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_0001_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[1] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_0001_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[1] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_0001_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[1] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_0001_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[1] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_0001_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[1] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_0010_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[2] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_0010_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[2] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_0010_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[2] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_0010_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[2] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_0010_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[2] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_0010_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[2] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_0010_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[2] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_0010_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[2] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_0010_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[2] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_0010_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[2] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_0010_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[2] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_0010_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[2] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_0010_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[2] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_0010_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[2] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_0010_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[2] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_0010_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[2] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_0011_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[3] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_0011_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[3] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_0011_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[3] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_0011_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[3] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_0011_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[3] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_0011_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[3] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_0011_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[3] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_0011_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[3] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_0011_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[3] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_0011_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[3] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_0011_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[3] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_0011_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[3] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_0011_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[3] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_0011_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[3] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_0011_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[3] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_0011_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[3] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_0100_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[4] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_0100_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[4] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_0100_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[4] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_0100_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[4] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_0100_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[4] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_0100_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[4] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_0100_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[4] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_0100_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[4] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_0100_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[4] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_0100_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[4] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_0100_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[4] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_0100_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[4] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_0100_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[4] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_0100_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[4] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_0100_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[4] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_0100_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[4] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_0101_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[5] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_0101_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[5] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_0101_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[5] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_0101_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[5] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_0101_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[5] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_0101_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[5] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_0101_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[5] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_0101_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[5] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_0101_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[5] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_0101_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[5] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_0101_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[5] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_0101_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[5] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_0101_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[5] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_0101_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[5] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_0101_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[5] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_0101_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[5] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_0110_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[6] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_0110_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[6] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_0110_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[6] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_0110_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[6] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_0110_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[6] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_0110_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[6] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_0110_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[6] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_0110_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[6] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_0110_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[6] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_0110_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[6] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_0110_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[6] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_0110_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[6] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_0110_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[6] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_0110_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[6] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_0110_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[6] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_0110_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[6] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_0111_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[7] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_0111_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[7] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_0111_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[7] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_0111_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[7] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_0111_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[7] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_0111_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[7] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_0111_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[7] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_0111_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[7] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_0111_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[7] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_0111_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[7] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_0111_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[7] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_0111_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[7] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_0111_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[7] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_0111_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[7] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_0111_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[7] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_0111_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[7] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_1000_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[8] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_1000_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[8] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_1000_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[8] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_1000_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[8] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_1000_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[8] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_1000_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[8] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_1000_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[8] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_1000_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[8] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_1000_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[8] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_1000_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[8] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_1000_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[8] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_1000_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[8] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_1000_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[8] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_1000_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[8] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_1000_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[8] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_1000_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[8] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_1001_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[9] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_1001_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[9] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_1001_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[9] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_1001_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[9] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_1001_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[9] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_1001_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[9] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_1001_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[9] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_1001_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[9] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_1001_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[9] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_1001_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[9] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_1001_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[9] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_1001_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[9] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_1001_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[9] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_1001_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[9] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_1001_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[9] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_1001_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[9] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_1010_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[10] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_1010_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[10] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_1010_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[10] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_1010_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[10] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_1010_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[10] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_1010_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[10] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_1010_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[10] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_1010_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[10] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_1010_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[10] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_1010_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[10] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_1010_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[10] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_1010_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[10] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_1010_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[10] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_1010_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[10] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_1010_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[10] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_1010_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[10] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_1011_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[11] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_1011_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[11] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_1011_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[11] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_1011_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[11] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_1011_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[11] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_1011_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[11] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_1011_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[11] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_1011_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[11] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_1011_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[11] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_1011_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[11] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_1011_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[11] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_1011_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[11] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_1011_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[11] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_1011_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[11] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_1011_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[11] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_1011_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[11] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_1100_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[12] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_1100_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[12] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_1100_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[12] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_1100_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[12] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_1100_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[12] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_1100_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[12] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_1100_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[12] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_1100_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[12] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_1100_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[12] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_1100_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[12] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_1100_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[12] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_1100_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[12] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_1100_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[12] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_1100_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[12] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_1100_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[12] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_1100_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[12] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_1101_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[13] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_1101_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[13] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_1101_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[13] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_1101_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[13] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_1101_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[13] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_1101_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[13] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_1101_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[13] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_1101_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[13] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_1101_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[13] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_1101_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[13] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_1101_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[13] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_1101_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[13] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_1101_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[13] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_1101_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[13] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_1101_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[13] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_1101_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[13] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_1110_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[14] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_1110_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[14] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_1110_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[14] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_1110_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[14] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_1110_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[14] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_1110_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[14] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_1110_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[14] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_1110_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[14] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_1110_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[14] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_1110_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[14] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_1110_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[14] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_1110_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[14] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_1110_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[14] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_1110_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[14] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_1110_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[14] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_1110_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[14] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_1111_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[15] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_1111_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[15] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_1111_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[15] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_1111_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[15] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_1111_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[15] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_1111_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[15] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_1111_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[15] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_1111_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[15] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_1111_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[15] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_1111_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[15] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_1111_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[15] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_1111_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[15] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_1111_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[15] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_1111_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[15] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_1111_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[15] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_1111_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[15] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_0000_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[0] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_0000_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[0] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_0000_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[0] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_0000_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[0] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_0000_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[0] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_0000_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[0] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_0000_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[0] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_0000_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[0] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_0000_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[0] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_0000_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[0] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_0000_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[0] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_0000_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[0] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_0000_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[0] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_0000_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[0] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_0000_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[0] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_0000_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[0] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_0001_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[1] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_0001_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[1] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_0001_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[1] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_0001_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[1] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_0001_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[1] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_0001_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[1] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_0001_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[1] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_0001_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[1] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_0001_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[1] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_0001_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[1] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_0001_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[1] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_0001_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[1] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_0001_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[1] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_0001_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[1] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_0001_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[1] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_0001_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[1] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_0010_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[2] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_0010_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[2] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_0010_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[2] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_0010_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[2] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_0010_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[2] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_0010_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[2] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_0010_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[2] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_0010_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[2] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_0010_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[2] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_0010_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[2] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_0010_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[2] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_0010_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[2] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_0010_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[2] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_0010_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[2] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_0010_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[2] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_0010_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[2] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_0011_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[3] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_0011_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[3] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_0011_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[3] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_0011_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[3] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_0011_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[3] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_0011_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[3] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_0011_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[3] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_0011_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[3] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_0011_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[3] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_0011_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[3] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_0011_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[3] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_0011_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[3] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_0011_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[3] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_0011_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[3] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_0011_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[3] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_0011_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[3] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_0100_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[4] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_0100_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[4] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_0100_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[4] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_0100_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[4] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_0100_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[4] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_0100_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[4] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_0100_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[4] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_0100_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[4] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_0100_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[4] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_0100_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[4] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_0100_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[4] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_0100_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[4] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_0100_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[4] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_0100_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[4] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_0100_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[4] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_0100_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[4] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_0101_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[5] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_0101_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[5] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_0101_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[5] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_0101_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[5] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_0101_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[5] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_0101_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[5] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_0101_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[5] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_0101_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[5] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_0101_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[5] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_0101_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[5] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_0101_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[5] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_0101_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[5] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_0101_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[5] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_0101_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[5] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_0101_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[5] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_0101_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[5] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_0110_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[6] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_0110_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[6] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_0110_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[6] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_0110_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[6] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_0110_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[6] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_0110_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[6] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_0110_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[6] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_0110_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[6] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_0110_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[6] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_0110_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[6] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_0110_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[6] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_0110_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[6] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_0110_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[6] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_0110_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[6] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_0110_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[6] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_0110_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[6] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_0111_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[7] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_0111_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[7] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_0111_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[7] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_0111_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[7] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_0111_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[7] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_0111_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[7] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_0111_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[7] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_0111_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[7] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_0111_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[7] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_0111_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[7] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_0111_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[7] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_0111_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[7] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_0111_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[7] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_0111_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[7] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_0111_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[7] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_0111_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[7] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_1000_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[8] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_1000_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[8] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_1000_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[8] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_1000_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[8] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_1000_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[8] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_1000_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[8] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_1000_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[8] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_1000_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[8] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_1000_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[8] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_1000_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[8] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_1000_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[8] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_1000_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[8] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_1000_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[8] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_1000_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[8] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_1000_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[8] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_1000_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[8] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_1001_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[9] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_1001_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[9] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_1001_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[9] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_1001_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[9] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_1001_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[9] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_1001_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[9] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_1001_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[9] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_1001_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[9] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_1001_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[9] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_1001_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[9] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_1001_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[9] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_1001_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[9] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_1001_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[9] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_1001_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[9] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_1001_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[9] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_1001_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[9] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_1010_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[10] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_1010_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[10] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_1010_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[10] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_1010_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[10] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_1010_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[10] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_1010_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[10] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_1010_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[10] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_1010_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[10] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_1010_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[10] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_1010_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[10] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_1010_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[10] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_1010_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[10] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_1010_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[10] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_1010_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[10] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_1010_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[10] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_1010_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[10] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_1011_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[11] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_1011_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[11] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_1011_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[11] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_1011_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[11] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_1011_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[11] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_1011_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[11] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_1011_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[11] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_1011_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[11] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_1011_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[11] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_1011_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[11] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_1011_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[11] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_1011_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[11] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_1011_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[11] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_1011_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[11] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_1011_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[11] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_1011_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[11] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_1100_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[12] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_1100_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[12] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_1100_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[12] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_1100_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[12] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_1100_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[12] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_1100_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[12] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_1100_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[12] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_1100_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[12] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_1100_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[12] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_1100_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[12] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_1100_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[12] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_1100_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[12] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_1100_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[12] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_1100_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[12] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_1100_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[12] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_1100_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[12] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_1101_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[13] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_1101_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[13] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_1101_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[13] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_1101_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[13] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_1101_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[13] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_1101_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[13] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_1101_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[13] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_1101_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[13] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_1101_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[13] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_1101_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[13] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_1101_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[13] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_1101_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[13] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_1101_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[13] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_1101_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[13] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_1101_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[13] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_1101_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[13] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_1110_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[14] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_1110_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[14] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_1110_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[14] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_1110_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[14] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_1110_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[14] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_1110_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[14] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_1110_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[14] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_1110_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[14] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_1110_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[14] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_1110_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[14] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_1110_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[14] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_1110_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[14] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_1110_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[14] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_1110_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[14] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_1110_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[14] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_1110_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[14] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_1111_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[15] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_1111_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[15] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_1111_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[15] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_1111_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[15] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_1111_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[15] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_1111_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[15] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_1111_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[15] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_1111_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[15] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_1111_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[15] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_1111_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[15] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_1111_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[15] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_1111_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[15] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_1111_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[15] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_1111_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[15] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_1111_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[15] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_1111_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[15] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_0000_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[0] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_0000_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[0] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_0000_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[0] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_0000_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[0] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_0000_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[0] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_0000_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[0] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_0000_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[0] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_0000_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[0] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_0000_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[0] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_0000_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[0] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_0000_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[0] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_0000_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[0] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_0000_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[0] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_0000_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[0] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_0000_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[0] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_0000_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[0] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_0001_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[1] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_0001_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[1] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_0001_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[1] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_0001_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[1] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_0001_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[1] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_0001_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[1] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_0001_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[1] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_0001_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[1] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_0001_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[1] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_0001_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[1] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_0001_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[1] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_0001_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[1] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_0001_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[1] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_0001_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[1] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_0001_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[1] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_0001_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[1] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_0010_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[2] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_0010_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[2] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_0010_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[2] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_0010_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[2] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_0010_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[2] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_0010_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[2] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_0010_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[2] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_0010_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[2] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_0010_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[2] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_0010_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[2] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_0010_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[2] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_0010_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[2] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_0010_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[2] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_0010_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[2] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_0010_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[2] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_0010_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[2] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_0011_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[3] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_0011_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[3] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_0011_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[3] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_0011_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[3] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_0011_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[3] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_0011_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[3] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_0011_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[3] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_0011_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[3] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_0011_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[3] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_0011_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[3] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_0011_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[3] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_0011_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[3] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_0011_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[3] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_0011_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[3] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_0011_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[3] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_0011_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[3] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_0100_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[4] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_0100_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[4] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_0100_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[4] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_0100_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[4] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_0100_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[4] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_0100_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[4] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_0100_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[4] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_0100_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[4] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_0100_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[4] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_0100_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[4] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_0100_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[4] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_0100_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[4] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_0100_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[4] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_0100_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[4] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_0100_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[4] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_0100_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[4] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_0101_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[5] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_0101_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[5] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_0101_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[5] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_0101_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[5] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_0101_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[5] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_0101_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[5] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_0101_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[5] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_0101_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[5] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_0101_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[5] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_0101_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[5] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_0101_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[5] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_0101_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[5] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_0101_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[5] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_0101_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[5] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_0101_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[5] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_0101_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[5] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_0110_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[6] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_0110_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[6] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_0110_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[6] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_0110_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[6] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_0110_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[6] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_0110_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[6] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_0110_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[6] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_0110_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[6] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_0110_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[6] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_0110_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[6] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_0110_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[6] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_0110_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[6] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_0110_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[6] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_0110_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[6] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_0110_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[6] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_0110_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[6] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_0111_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[7] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_0111_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[7] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_0111_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[7] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_0111_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[7] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_0111_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[7] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_0111_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[7] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_0111_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[7] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_0111_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[7] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_0111_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[7] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_0111_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[7] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_0111_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[7] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_0111_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[7] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_0111_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[7] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_0111_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[7] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_0111_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[7] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_0111_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[7] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_1000_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[8] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_1000_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[8] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_1000_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[8] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_1000_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[8] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_1000_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[8] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_1000_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[8] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_1000_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[8] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_1000_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[8] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_1000_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[8] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_1000_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[8] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_1000_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[8] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_1000_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[8] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_1000_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[8] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_1000_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[8] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_1000_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[8] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_1000_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[8] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_1001_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[9] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_1001_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[9] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_1001_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[9] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_1001_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[9] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_1001_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[9] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_1001_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[9] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_1001_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[9] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_1001_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[9] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_1001_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[9] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_1001_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[9] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_1001_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[9] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_1001_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[9] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_1001_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[9] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_1001_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[9] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_1001_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[9] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_1001_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[9] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_1010_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[10] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_1010_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[10] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_1010_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[10] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_1010_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[10] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_1010_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[10] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_1010_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[10] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_1010_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[10] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_1010_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[10] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_1010_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[10] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_1010_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[10] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_1010_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[10] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_1010_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[10] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_1010_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[10] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_1010_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[10] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_1010_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[10] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_1010_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[10] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_1011_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[11] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_1011_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[11] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_1011_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[11] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_1011_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[11] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_1011_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[11] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_1011_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[11] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_1011_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[11] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_1011_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[11] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_1011_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[11] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_1011_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[11] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_1011_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[11] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_1011_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[11] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_1011_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[11] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_1011_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[11] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_1011_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[11] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_1011_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[11] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_1100_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[12] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_1100_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[12] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_1100_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[12] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_1100_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[12] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_1100_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[12] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_1100_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[12] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_1100_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[12] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_1100_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[12] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_1100_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[12] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_1100_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[12] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_1100_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[12] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_1100_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[12] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_1100_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[12] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_1100_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[12] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_1100_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[12] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_1100_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[12] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_1101_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[13] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_1101_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[13] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_1101_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[13] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_1101_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[13] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_1101_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[13] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_1101_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[13] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_1101_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[13] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_1101_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[13] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_1101_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[13] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_1101_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[13] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_1101_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[13] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_1101_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[13] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_1101_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[13] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_1101_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[13] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_1101_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[13] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_1101_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[13] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_1110_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[14] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_1110_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[14] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_1110_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[14] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_1110_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[14] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_1110_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[14] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_1110_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[14] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_1110_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[14] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_1110_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[14] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_1110_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[14] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_1110_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[14] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_1110_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[14] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_1110_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[14] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_1110_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[14] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_1110_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[14] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_1110_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[14] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_1110_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[14] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_1111_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[15] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_1111_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[15] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_1111_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[15] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_1111_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[15] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_1111_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[15] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_1111_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[15] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_1111_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[15] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_1111_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[15] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_1111_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[15] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_1111_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[15] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_1111_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[15] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_1111_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[15] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_1111_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[15] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_1111_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[15] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_1111_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[15] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_1111_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[15] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_0000_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[0] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_0000_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[0] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_0000_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[0] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_0000_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[0] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_0000_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[0] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_0000_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[0] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_0000_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[0] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_0000_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[0] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_0000_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[0] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_0000_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[0] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_0000_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[0] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_0000_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[0] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_0000_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[0] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_0000_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[0] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_0000_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[0] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_0000_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[0] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_0001_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[1] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_0001_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[1] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_0001_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[1] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_0001_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[1] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_0001_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[1] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_0001_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[1] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_0001_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[1] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_0001_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[1] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_0001_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[1] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_0001_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[1] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_0001_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[1] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_0001_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[1] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_0001_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[1] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_0001_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[1] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_0001_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[1] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_0001_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[1] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_0010_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[2] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_0010_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[2] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_0010_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[2] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_0010_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[2] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_0010_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[2] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_0010_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[2] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_0010_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[2] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_0010_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[2] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_0010_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[2] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_0010_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[2] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_0010_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[2] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_0010_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[2] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_0010_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[2] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_0010_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[2] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_0010_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[2] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_0010_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[2] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_0011_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[3] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_0011_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[3] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_0011_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[3] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_0011_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[3] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_0011_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[3] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_0011_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[3] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_0011_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[3] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_0011_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[3] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_0011_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[3] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_0011_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[3] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_0011_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[3] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_0011_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[3] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_0011_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[3] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_0011_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[3] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_0011_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[3] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_0011_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[3] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_0100_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[4] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_0100_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[4] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_0100_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[4] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_0100_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[4] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_0100_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[4] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_0100_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[4] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_0100_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[4] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_0100_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[4] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_0100_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[4] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_0100_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[4] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_0100_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[4] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_0100_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[4] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_0100_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[4] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_0100_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[4] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_0100_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[4] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_0100_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[4] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_0101_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[5] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_0101_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[5] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_0101_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[5] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_0101_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[5] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_0101_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[5] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_0101_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[5] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_0101_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[5] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_0101_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[5] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_0101_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[5] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_0101_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[5] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_0101_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[5] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_0101_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[5] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_0101_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[5] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_0101_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[5] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_0101_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[5] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_0101_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[5] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_0110_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[6] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_0110_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[6] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_0110_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[6] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_0110_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[6] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_0110_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[6] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_0110_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[6] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_0110_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[6] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_0110_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[6] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_0110_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[6] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_0110_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[6] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_0110_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[6] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_0110_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[6] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_0110_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[6] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_0110_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[6] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_0110_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[6] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_0110_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[6] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_0111_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[7] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_0111_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[7] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_0111_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[7] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_0111_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[7] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_0111_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[7] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_0111_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[7] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_0111_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[7] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_0111_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[7] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_0111_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[7] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_0111_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[7] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_0111_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[7] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_0111_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[7] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_0111_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[7] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_0111_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[7] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_0111_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[7] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_0111_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[7] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_1000_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[8] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_1000_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[8] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_1000_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[8] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_1000_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[8] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_1000_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[8] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_1000_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[8] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_1000_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[8] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_1000_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[8] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_1000_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[8] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_1000_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[8] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_1000_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[8] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_1000_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[8] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_1000_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[8] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_1000_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[8] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_1000_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[8] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_1000_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[8] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_1001_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[9] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_1001_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[9] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_1001_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[9] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_1001_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[9] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_1001_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[9] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_1001_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[9] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_1001_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[9] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_1001_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[9] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_1001_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[9] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_1001_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[9] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_1001_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[9] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_1001_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[9] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_1001_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[9] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_1001_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[9] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_1001_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[9] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_1001_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[9] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_1010_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[10] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_1010_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[10] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_1010_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[10] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_1010_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[10] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_1010_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[10] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_1010_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[10] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_1010_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[10] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_1010_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[10] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_1010_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[10] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_1010_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[10] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_1010_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[10] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_1010_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[10] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_1010_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[10] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_1010_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[10] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_1010_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[10] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_1010_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[10] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_1011_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[11] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_1011_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[11] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_1011_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[11] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_1011_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[11] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_1011_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[11] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_1011_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[11] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_1011_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[11] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_1011_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[11] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_1011_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[11] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_1011_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[11] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_1011_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[11] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_1011_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[11] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_1011_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[11] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_1011_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[11] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_1011_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[11] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_1011_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[11] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_1100_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[12] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_1100_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[12] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_1100_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[12] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_1100_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[12] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_1100_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[12] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_1100_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[12] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_1100_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[12] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_1100_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[12] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_1100_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[12] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_1100_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[12] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_1100_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[12] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_1100_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[12] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_1100_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[12] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_1100_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[12] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_1100_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[12] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_1100_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[12] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_1101_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[13] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_1101_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[13] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_1101_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[13] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_1101_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[13] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_1101_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[13] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_1101_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[13] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_1101_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[13] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_1101_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[13] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_1101_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[13] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_1101_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[13] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_1101_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[13] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_1101_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[13] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_1101_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[13] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_1101_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[13] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_1101_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[13] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_1101_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[13] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_1110_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[14] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_1110_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[14] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_1110_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[14] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_1110_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[14] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_1110_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[14] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_1110_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[14] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_1110_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[14] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_1110_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[14] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_1110_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[14] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_1110_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[14] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_1110_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[14] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_1110_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[14] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_1110_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[14] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_1110_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[14] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_1110_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[14] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_1110_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[14] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_1111_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[15] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_1111_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[15] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_1111_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[15] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_1111_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[15] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_1111_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[15] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_1111_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[15] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_1111_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[15] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_1111_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[15] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_1111_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[15] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_1111_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[15] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_1111_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[15] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_1111_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[15] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_1111_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[15] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_1111_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[15] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_1111_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[15] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_1111_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[15] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_0000_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[0] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_0000_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[0] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_0000_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[0] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_0000_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[0] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_0000_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[0] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_0000_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[0] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_0000_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[0] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_0000_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[0] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_0000_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[0] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_0000_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[0] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_0000_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[0] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_0000_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[0] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_0000_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[0] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_0000_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[0] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_0000_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[0] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_0000_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[0] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_0001_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[1] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_0001_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[1] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_0001_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[1] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_0001_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[1] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_0001_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[1] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_0001_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[1] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_0001_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[1] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_0001_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[1] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_0001_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[1] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_0001_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[1] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_0001_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[1] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_0001_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[1] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_0001_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[1] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_0001_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[1] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_0001_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[1] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_0001_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[1] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_0010_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[2] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_0010_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[2] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_0010_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[2] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_0010_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[2] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_0010_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[2] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_0010_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[2] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_0010_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[2] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_0010_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[2] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_0010_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[2] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_0010_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[2] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_0010_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[2] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_0010_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[2] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_0010_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[2] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_0010_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[2] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_0010_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[2] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_0010_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[2] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_0011_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[3] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_0011_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[3] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_0011_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[3] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_0011_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[3] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_0011_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[3] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_0011_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[3] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_0011_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[3] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_0011_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[3] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_0011_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[3] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_0011_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[3] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_0011_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[3] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_0011_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[3] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_0011_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[3] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_0011_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[3] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_0011_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[3] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_0011_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[3] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_0100_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[4] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_0100_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[4] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_0100_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[4] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_0100_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[4] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_0100_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[4] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_0100_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[4] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_0100_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[4] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_0100_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[4] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_0100_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[4] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_0100_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[4] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_0100_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[4] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_0100_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[4] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_0100_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[4] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_0100_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[4] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_0100_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[4] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_0100_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[4] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_0101_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[5] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_0101_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[5] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_0101_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[5] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_0101_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[5] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_0101_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[5] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_0101_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[5] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_0101_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[5] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_0101_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[5] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_0101_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[5] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_0101_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[5] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_0101_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[5] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_0101_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[5] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_0101_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[5] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_0101_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[5] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_0101_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[5] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_0101_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[5] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_0110_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[6] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_0110_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[6] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_0110_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[6] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_0110_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[6] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_0110_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[6] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_0110_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[6] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_0110_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[6] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_0110_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[6] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_0110_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[6] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_0110_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[6] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_0110_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[6] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_0110_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[6] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_0110_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[6] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_0110_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[6] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_0110_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[6] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_0110_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[6] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_0111_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[7] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_0111_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[7] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_0111_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[7] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_0111_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[7] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_0111_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[7] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_0111_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[7] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_0111_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[7] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_0111_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[7] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_0111_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[7] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_0111_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[7] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_0111_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[7] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_0111_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[7] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_0111_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[7] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_0111_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[7] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_0111_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[7] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_0111_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[7] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_1000_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[8] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_1000_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[8] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_1000_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[8] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_1000_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[8] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_1000_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[8] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_1000_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[8] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_1000_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[8] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_1000_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[8] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_1000_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[8] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_1000_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[8] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_1000_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[8] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_1000_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[8] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_1000_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[8] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_1000_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[8] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_1000_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[8] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_1000_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[8] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_1001_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[9] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_1001_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[9] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_1001_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[9] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_1001_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[9] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_1001_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[9] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_1001_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[9] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_1001_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[9] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_1001_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[9] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_1001_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[9] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_1001_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[9] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_1001_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[9] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_1001_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[9] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_1001_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[9] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_1001_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[9] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_1001_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[9] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_1001_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[9] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_1010_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[10] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_1010_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[10] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_1010_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[10] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_1010_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[10] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_1010_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[10] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_1010_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[10] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_1010_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[10] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_1010_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[10] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_1010_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[10] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_1010_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[10] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_1010_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[10] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_1010_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[10] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_1010_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[10] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_1010_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[10] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_1010_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[10] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_1010_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[10] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_1011_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[11] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_1011_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[11] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_1011_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[11] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_1011_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[11] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_1011_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[11] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_1011_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[11] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_1011_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[11] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_1011_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[11] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_1011_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[11] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_1011_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[11] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_1011_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[11] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_1011_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[11] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_1011_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[11] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_1011_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[11] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_1011_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[11] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_1011_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[11] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_1100_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[12] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_1100_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[12] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_1100_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[12] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_1100_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[12] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_1100_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[12] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_1100_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[12] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_1100_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[12] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_1100_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[12] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_1100_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[12] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_1100_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[12] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_1100_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[12] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_1100_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[12] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_1100_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[12] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_1100_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[12] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_1100_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[12] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_1100_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[12] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_1101_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[13] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_1101_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[13] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_1101_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[13] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_1101_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[13] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_1101_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[13] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_1101_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[13] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_1101_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[13] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_1101_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[13] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_1101_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[13] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_1101_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[13] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_1101_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[13] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_1101_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[13] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_1101_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[13] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_1101_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[13] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_1101_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[13] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_1101_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[13] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_1110_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[14] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_1110_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[14] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_1110_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[14] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_1110_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[14] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_1110_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[14] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_1110_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[14] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_1110_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[14] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_1110_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[14] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_1110_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[14] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_1110_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[14] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_1110_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[14] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_1110_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[14] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_1110_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[14] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_1110_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[14] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_1110_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[14] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_1110_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[14] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_1111_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[15] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_1111_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[15] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_1111_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[15] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_1111_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[15] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_1111_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[15] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_1111_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[15] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_1111_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[15] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_1111_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[15] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_1111_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[15] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_1111_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[15] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_1111_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[15] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_1111_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[15] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_1111_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[15] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_1111_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[15] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_1111_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[15] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_1111_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[15] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_0000_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[0] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_0000_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[0] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_0000_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[0] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_0000_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[0] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_0000_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[0] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_0000_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[0] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_0000_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[0] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_0000_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[0] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_0000_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[0] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_0000_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[0] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_0000_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[0] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_0000_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[0] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_0000_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[0] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_0000_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[0] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_0000_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[0] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_0000_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[0] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_0001_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[1] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_0001_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[1] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_0001_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[1] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_0001_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[1] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_0001_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[1] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_0001_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[1] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_0001_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[1] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_0001_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[1] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_0001_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[1] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_0001_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[1] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_0001_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[1] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_0001_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[1] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_0001_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[1] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_0001_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[1] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_0001_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[1] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_0001_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[1] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_0010_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[2] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_0010_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[2] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_0010_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[2] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_0010_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[2] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_0010_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[2] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_0010_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[2] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_0010_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[2] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_0010_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[2] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_0010_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[2] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_0010_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[2] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_0010_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[2] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_0010_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[2] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_0010_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[2] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_0010_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[2] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_0010_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[2] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_0010_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[2] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_0011_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[3] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_0011_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[3] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_0011_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[3] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_0011_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[3] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_0011_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[3] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_0011_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[3] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_0011_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[3] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_0011_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[3] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_0011_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[3] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_0011_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[3] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_0011_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[3] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_0011_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[3] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_0011_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[3] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_0011_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[3] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_0011_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[3] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_0011_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[3] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_0100_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[4] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_0100_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[4] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_0100_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[4] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_0100_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[4] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_0100_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[4] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_0100_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[4] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_0100_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[4] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_0100_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[4] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_0100_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[4] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_0100_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[4] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_0100_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[4] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_0100_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[4] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_0100_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[4] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_0100_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[4] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_0100_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[4] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_0100_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[4] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_0101_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[5] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_0101_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[5] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_0101_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[5] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_0101_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[5] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_0101_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[5] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_0101_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[5] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_0101_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[5] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_0101_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[5] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_0101_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[5] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_0101_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[5] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_0101_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[5] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_0101_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[5] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_0101_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[5] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_0101_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[5] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_0101_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[5] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_0101_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[5] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_0110_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[6] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_0110_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[6] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_0110_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[6] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_0110_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[6] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_0110_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[6] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_0110_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[6] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_0110_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[6] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_0110_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[6] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_0110_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[6] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_0110_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[6] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_0110_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[6] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_0110_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[6] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_0110_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[6] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_0110_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[6] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_0110_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[6] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_0110_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[6] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_0111_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[7] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_0111_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[7] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_0111_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[7] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_0111_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[7] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_0111_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[7] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_0111_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[7] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_0111_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[7] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_0111_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[7] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_0111_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[7] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_0111_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[7] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_0111_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[7] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_0111_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[7] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_0111_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[7] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_0111_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[7] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_0111_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[7] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_0111_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[7] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_1000_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[8] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_1000_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[8] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_1000_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[8] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_1000_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[8] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_1000_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[8] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_1000_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[8] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_1000_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[8] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_1000_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[8] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_1000_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[8] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_1000_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[8] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_1000_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[8] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_1000_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[8] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_1000_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[8] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_1000_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[8] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_1000_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[8] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_1000_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[8] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_1001_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[9] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_1001_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[9] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_1001_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[9] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_1001_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[9] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_1001_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[9] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_1001_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[9] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_1001_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[9] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_1001_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[9] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_1001_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[9] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_1001_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[9] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_1001_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[9] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_1001_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[9] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_1001_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[9] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_1001_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[9] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_1001_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[9] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_1001_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[9] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_1010_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[10] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_1010_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[10] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_1010_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[10] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_1010_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[10] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_1010_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[10] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_1010_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[10] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_1010_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[10] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_1010_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[10] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_1010_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[10] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_1010_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[10] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_1010_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[10] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_1010_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[10] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_1010_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[10] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_1010_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[10] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_1010_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[10] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_1010_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[10] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_1011_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[11] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_1011_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[11] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_1011_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[11] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_1011_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[11] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_1011_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[11] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_1011_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[11] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_1011_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[11] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_1011_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[11] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_1011_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[11] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_1011_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[11] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_1011_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[11] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_1011_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[11] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_1011_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[11] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_1011_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[11] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_1011_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[11] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_1011_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[11] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_1100_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[12] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_1100_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[12] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_1100_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[12] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_1100_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[12] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_1100_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[12] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_1100_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[12] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_1100_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[12] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_1100_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[12] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_1100_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[12] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_1100_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[12] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_1100_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[12] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_1100_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[12] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_1100_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[12] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_1100_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[12] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_1100_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[12] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_1100_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[12] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_1101_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[13] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_1101_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[13] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_1101_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[13] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_1101_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[13] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_1101_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[13] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_1101_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[13] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_1101_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[13] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_1101_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[13] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_1101_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[13] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_1101_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[13] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_1101_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[13] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_1101_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[13] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_1101_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[13] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_1101_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[13] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_1101_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[13] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_1101_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[13] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_1110_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[14] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_1110_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[14] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_1110_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[14] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_1110_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[14] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_1110_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[14] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_1110_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[14] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_1110_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[14] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_1110_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[14] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_1110_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[14] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_1110_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[14] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_1110_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[14] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_1110_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[14] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_1110_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[14] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_1110_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[14] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_1110_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[14] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_1110_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[14] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_1111_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[15] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_1111_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[15] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_1111_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[15] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_1111_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[15] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_1111_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[15] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_1111_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[15] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_1111_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[15] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_1111_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[15] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_1111_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[15] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_1111_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[15] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_1111_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[15] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_1111_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[15] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_1111_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[15] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_1111_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[15] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_1111_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[15] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_1111_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[15] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_0000_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[0] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_0000_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[0] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_0000_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[0] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_0000_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[0] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_0000_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[0] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_0000_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[0] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_0000_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[0] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_0000_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[0] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_0000_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[0] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_0000_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[0] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_0000_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[0] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_0000_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[0] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_0000_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[0] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_0000_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[0] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_0000_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[0] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_0000_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[0] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_0001_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[1] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_0001_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[1] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_0001_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[1] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_0001_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[1] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_0001_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[1] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_0001_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[1] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_0001_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[1] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_0001_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[1] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_0001_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[1] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_0001_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[1] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_0001_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[1] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_0001_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[1] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_0001_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[1] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_0001_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[1] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_0001_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[1] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_0001_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[1] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_0010_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[2] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_0010_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[2] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_0010_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[2] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_0010_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[2] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_0010_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[2] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_0010_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[2] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_0010_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[2] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_0010_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[2] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_0010_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[2] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_0010_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[2] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_0010_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[2] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_0010_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[2] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_0010_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[2] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_0010_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[2] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_0010_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[2] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_0010_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[2] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_0011_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[3] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_0011_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[3] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_0011_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[3] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_0011_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[3] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_0011_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[3] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_0011_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[3] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_0011_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[3] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_0011_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[3] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_0011_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[3] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_0011_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[3] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_0011_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[3] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_0011_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[3] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_0011_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[3] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_0011_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[3] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_0011_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[3] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_0011_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[3] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_0100_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[4] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_0100_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[4] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_0100_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[4] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_0100_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[4] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_0100_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[4] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_0100_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[4] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_0100_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[4] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_0100_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[4] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_0100_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[4] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_0100_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[4] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_0100_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[4] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_0100_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[4] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_0100_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[4] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_0100_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[4] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_0100_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[4] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_0100_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[4] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_0101_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[5] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_0101_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[5] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_0101_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[5] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_0101_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[5] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_0101_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[5] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_0101_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[5] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_0101_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[5] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_0101_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[5] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_0101_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[5] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_0101_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[5] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_0101_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[5] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_0101_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[5] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_0101_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[5] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_0101_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[5] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_0101_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[5] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_0101_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[5] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_0110_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[6] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_0110_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[6] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_0110_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[6] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_0110_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[6] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_0110_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[6] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_0110_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[6] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_0110_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[6] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_0110_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[6] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_0110_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[6] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_0110_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[6] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_0110_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[6] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_0110_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[6] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_0110_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[6] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_0110_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[6] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_0110_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[6] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_0110_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[6] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_0111_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[7] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_0111_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[7] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_0111_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[7] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_0111_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[7] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_0111_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[7] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_0111_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[7] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_0111_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[7] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_0111_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[7] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_0111_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[7] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_0111_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[7] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_0111_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[7] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_0111_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[7] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_0111_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[7] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_0111_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[7] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_0111_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[7] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_0111_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[7] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_1000_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[8] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_1000_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[8] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_1000_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[8] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_1000_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[8] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_1000_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[8] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_1000_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[8] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_1000_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[8] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_1000_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[8] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_1000_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[8] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_1000_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[8] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_1000_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[8] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_1000_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[8] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_1000_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[8] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_1000_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[8] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_1000_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[8] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_1000_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[8] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_1001_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[9] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_1001_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[9] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_1001_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[9] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_1001_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[9] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_1001_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[9] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_1001_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[9] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_1001_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[9] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_1001_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[9] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_1001_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[9] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_1001_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[9] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_1001_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[9] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_1001_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[9] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_1001_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[9] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_1001_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[9] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_1001_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[9] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_1001_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[9] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_1010_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[10] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_1010_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[10] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_1010_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[10] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_1010_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[10] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_1010_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[10] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_1010_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[10] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_1010_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[10] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_1010_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[10] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_1010_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[10] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_1010_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[10] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_1010_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[10] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_1010_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[10] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_1010_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[10] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_1010_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[10] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_1010_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[10] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_1010_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[10] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_1011_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[11] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_1011_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[11] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_1011_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[11] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_1011_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[11] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_1011_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[11] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_1011_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[11] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_1011_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[11] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_1011_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[11] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_1011_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[11] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_1011_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[11] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_1011_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[11] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_1011_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[11] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_1011_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[11] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_1011_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[11] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_1011_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[11] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_1011_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[11] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_1100_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[12] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_1100_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[12] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_1100_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[12] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_1100_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[12] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_1100_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[12] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_1100_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[12] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_1100_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[12] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_1100_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[12] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_1100_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[12] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_1100_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[12] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_1100_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[12] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_1100_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[12] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_1100_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[12] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_1100_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[12] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_1100_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[12] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_1100_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[12] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_1101_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[13] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_1101_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[13] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_1101_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[13] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_1101_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[13] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_1101_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[13] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_1101_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[13] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_1101_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[13] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_1101_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[13] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_1101_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[13] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_1101_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[13] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_1101_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[13] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_1101_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[13] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_1101_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[13] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_1101_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[13] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_1101_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[13] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_1101_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[13] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_1110_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[14] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_1110_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[14] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_1110_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[14] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_1110_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[14] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_1110_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[14] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_1110_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[14] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_1110_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[14] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_1110_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[14] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_1110_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[14] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_1110_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[14] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_1110_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[14] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_1110_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[14] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_1110_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[14] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_1110_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[14] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_1110_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[14] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_1110_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[14] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0000_M_1111_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[15] + 0;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0001_M_1111_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[15] + 4;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0010_M_1111_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[15] + 8;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0011_M_1111_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[15] + 12;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0100_M_1111_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[15] + 16;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0101_M_1111_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[15] + 20;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0110_M_1111_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[15] + 24;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_0111_M_1111_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[15] + 28;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1000_M_1111_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 32;
	context->scratch1 = context->gpr[15] + 32;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1001_M_1111_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 36;
	context->scratch1 = context->gpr[15] + 36;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1010_M_1111_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 40;
	context->scratch1 = context->gpr[15] + 40;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1011_M_1111_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 44;
	context->scratch1 = context->gpr[15] + 44;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1100_M_1111_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 48;
	context->scratch1 = context->gpr[15] + 48;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1101_M_1111_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 52;
	context->scratch1 = context->gpr[15] + 52;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1110_M_1111_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 56;
	context->scratch1 = context->gpr[15] + 56;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_rn_l_D_1111_M_1111_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 60;
	context->scratch1 = context->gpr[15] + 60;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_0000_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[0] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[0], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_0000_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[0] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[0], context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_0000_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[0] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[0], context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_0000_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[0] = context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_0000_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t cmp_tmp32__;
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[0] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[0], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_0000_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t cmp_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[0] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[0], context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_0000_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t cmp_tmp32__;
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[0] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[0], context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_0000_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[0] = ~context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_0000_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[0] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[0] << 8;
	temp2 = 65280 & temp2;
	context->gpr[0] = context->gpr[0] & 4294901760;
	context->gpr[0] = temp1 | context->gpr[0];
	context->gpr[0] = temp2 | context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_0000_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[0] >> 16;
	context->gpr[0] = context->gpr[0] << 16;
	context->gpr[0] = temp | context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_0000_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[0]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[0] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_0000_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[0] = -context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_0000_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[0] = context->gpr[0] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_0000_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[0] = context->gpr[0] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_0000_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[0] = (context->gpr[0] & ~65535) | ((context->gpr[0] & 255) & 128 ? (context->gpr[0] & 255) | 65280 : (context->gpr[0] & 255));
	context->gpr[0] = (context->gpr[0] & 65535) & 32768 ? (context->gpr[0] & 65535) | 4294901760 : (context->gpr[0] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_0000_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[0] = (context->gpr[0] & 65535) & 32768 ? (context->gpr[0] & 65535) | 4294901760 : (context->gpr[0] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_0001_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[1] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[1], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_0001_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[1] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[1], context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_0001_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[1] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[1], context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_0001_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[0] = context->gpr[1];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_0001_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[1] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[1], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[1] = 1 + context->gpr[1];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_0001_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[1] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[1], context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[1] = 2 + context->gpr[1];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_0001_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[1] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[1], context);
	context->gpr[0] = context->scratch1;
	context->gpr[1] = 4 + context->gpr[1];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_0001_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[0] = ~context->gpr[1];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_0001_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[1] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[1] << 8;
	temp2 = 65280 & temp2;
	context->gpr[0] = context->gpr[1] & 4294901760;
	context->gpr[0] = temp1 | context->gpr[0];
	context->gpr[0] = temp2 | context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_0001_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[1] >> 16;
	context->gpr[0] = context->gpr[1] << 16;
	context->gpr[0] = temp | context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_0001_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[1]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[0] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_0001_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[0] = -context->gpr[1];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_0001_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[0] = context->gpr[1] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_0001_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[0] = context->gpr[1] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_0001_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[0] = (context->gpr[0] & ~65535) | ((context->gpr[1] & 255) & 128 ? (context->gpr[1] & 255) | 65280 : (context->gpr[1] & 255));
	context->gpr[0] = (context->gpr[0] & 65535) & 32768 ? (context->gpr[0] & 65535) | 4294901760 : (context->gpr[0] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_0001_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[0] = (context->gpr[1] & 65535) & 32768 ? (context->gpr[1] & 65535) | 4294901760 : (context->gpr[1] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_0010_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[2] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[2], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_0010_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[2] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[2], context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_0010_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[2] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[2], context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_0010_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[0] = context->gpr[2];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_0010_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[2] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[2], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[2] = 1 + context->gpr[2];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_0010_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[2] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[2], context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[2] = 2 + context->gpr[2];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_0010_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[2] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[2], context);
	context->gpr[0] = context->scratch1;
	context->gpr[2] = 4 + context->gpr[2];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_0010_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[0] = ~context->gpr[2];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_0010_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[2] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[2] << 8;
	temp2 = 65280 & temp2;
	context->gpr[0] = context->gpr[2] & 4294901760;
	context->gpr[0] = temp1 | context->gpr[0];
	context->gpr[0] = temp2 | context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_0010_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[2] >> 16;
	context->gpr[0] = context->gpr[2] << 16;
	context->gpr[0] = temp | context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_0010_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[2]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[0] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_0010_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[0] = -context->gpr[2];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_0010_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[0] = context->gpr[2] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_0010_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[0] = context->gpr[2] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_0010_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[0] = (context->gpr[0] & ~65535) | ((context->gpr[2] & 255) & 128 ? (context->gpr[2] & 255) | 65280 : (context->gpr[2] & 255));
	context->gpr[0] = (context->gpr[0] & 65535) & 32768 ? (context->gpr[0] & 65535) | 4294901760 : (context->gpr[0] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_0010_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[0] = (context->gpr[2] & 65535) & 32768 ? (context->gpr[2] & 65535) | 4294901760 : (context->gpr[2] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_0011_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[3] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[3], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_0011_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[3] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[3], context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_0011_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[3] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[3], context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_0011_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[0] = context->gpr[3];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_0011_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[3] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[3], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[3] = 1 + context->gpr[3];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_0011_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[3] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[3], context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[3] = 2 + context->gpr[3];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_0011_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[3] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[3], context);
	context->gpr[0] = context->scratch1;
	context->gpr[3] = 4 + context->gpr[3];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_0011_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[0] = ~context->gpr[3];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_0011_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[3] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[3] << 8;
	temp2 = 65280 & temp2;
	context->gpr[0] = context->gpr[3] & 4294901760;
	context->gpr[0] = temp1 | context->gpr[0];
	context->gpr[0] = temp2 | context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_0011_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[3] >> 16;
	context->gpr[0] = context->gpr[3] << 16;
	context->gpr[0] = temp | context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_0011_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[3]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[0] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_0011_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[0] = -context->gpr[3];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_0011_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[0] = context->gpr[3] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_0011_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[0] = context->gpr[3] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_0011_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[0] = (context->gpr[0] & ~65535) | ((context->gpr[3] & 255) & 128 ? (context->gpr[3] & 255) | 65280 : (context->gpr[3] & 255));
	context->gpr[0] = (context->gpr[0] & 65535) & 32768 ? (context->gpr[0] & 65535) | 4294901760 : (context->gpr[0] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_0011_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[0] = (context->gpr[3] & 65535) & 32768 ? (context->gpr[3] & 65535) | 4294901760 : (context->gpr[3] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_0100_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[4] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[4], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_0100_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[4] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[4], context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_0100_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[4] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[4], context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_0100_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[0] = context->gpr[4];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_0100_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[4] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[4], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[4] = 1 + context->gpr[4];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_0100_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[4] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[4], context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[4] = 2 + context->gpr[4];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_0100_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[4] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[4], context);
	context->gpr[0] = context->scratch1;
	context->gpr[4] = 4 + context->gpr[4];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_0100_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[0] = ~context->gpr[4];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_0100_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[4] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[4] << 8;
	temp2 = 65280 & temp2;
	context->gpr[0] = context->gpr[4] & 4294901760;
	context->gpr[0] = temp1 | context->gpr[0];
	context->gpr[0] = temp2 | context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_0100_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[4] >> 16;
	context->gpr[0] = context->gpr[4] << 16;
	context->gpr[0] = temp | context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_0100_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[4]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[0] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_0100_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[0] = -context->gpr[4];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_0100_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[0] = context->gpr[4] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_0100_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[0] = context->gpr[4] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_0100_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[0] = (context->gpr[0] & ~65535) | ((context->gpr[4] & 255) & 128 ? (context->gpr[4] & 255) | 65280 : (context->gpr[4] & 255));
	context->gpr[0] = (context->gpr[0] & 65535) & 32768 ? (context->gpr[0] & 65535) | 4294901760 : (context->gpr[0] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_0100_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[0] = (context->gpr[4] & 65535) & 32768 ? (context->gpr[4] & 65535) | 4294901760 : (context->gpr[4] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_0101_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[5] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[5], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_0101_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[5] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[5], context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_0101_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[5] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[5], context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_0101_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[0] = context->gpr[5];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_0101_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[5] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[5], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[5] = 1 + context->gpr[5];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_0101_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[5] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[5], context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[5] = 2 + context->gpr[5];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_0101_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[5] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[5], context);
	context->gpr[0] = context->scratch1;
	context->gpr[5] = 4 + context->gpr[5];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_0101_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[0] = ~context->gpr[5];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_0101_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[5] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[5] << 8;
	temp2 = 65280 & temp2;
	context->gpr[0] = context->gpr[5] & 4294901760;
	context->gpr[0] = temp1 | context->gpr[0];
	context->gpr[0] = temp2 | context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_0101_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[5] >> 16;
	context->gpr[0] = context->gpr[5] << 16;
	context->gpr[0] = temp | context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_0101_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[5]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[0] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_0101_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[0] = -context->gpr[5];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_0101_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[0] = context->gpr[5] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_0101_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[0] = context->gpr[5] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_0101_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[0] = (context->gpr[0] & ~65535) | ((context->gpr[5] & 255) & 128 ? (context->gpr[5] & 255) | 65280 : (context->gpr[5] & 255));
	context->gpr[0] = (context->gpr[0] & 65535) & 32768 ? (context->gpr[0] & 65535) | 4294901760 : (context->gpr[0] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_0101_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[0] = (context->gpr[5] & 65535) & 32768 ? (context->gpr[5] & 65535) | 4294901760 : (context->gpr[5] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_0110_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[6] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[6], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_0110_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[6] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[6], context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_0110_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[6] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[6], context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_0110_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[0] = context->gpr[6];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_0110_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[6] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[6], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[6] = 1 + context->gpr[6];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_0110_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[6] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[6], context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[6] = 2 + context->gpr[6];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_0110_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[6] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[6], context);
	context->gpr[0] = context->scratch1;
	context->gpr[6] = 4 + context->gpr[6];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_0110_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[0] = ~context->gpr[6];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_0110_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[6] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[6] << 8;
	temp2 = 65280 & temp2;
	context->gpr[0] = context->gpr[6] & 4294901760;
	context->gpr[0] = temp1 | context->gpr[0];
	context->gpr[0] = temp2 | context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_0110_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[6] >> 16;
	context->gpr[0] = context->gpr[6] << 16;
	context->gpr[0] = temp | context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_0110_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[6]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[0] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_0110_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[0] = -context->gpr[6];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_0110_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[0] = context->gpr[6] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_0110_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[0] = context->gpr[6] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_0110_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[0] = (context->gpr[0] & ~65535) | ((context->gpr[6] & 255) & 128 ? (context->gpr[6] & 255) | 65280 : (context->gpr[6] & 255));
	context->gpr[0] = (context->gpr[0] & 65535) & 32768 ? (context->gpr[0] & 65535) | 4294901760 : (context->gpr[0] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_0110_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[0] = (context->gpr[6] & 65535) & 32768 ? (context->gpr[6] & 65535) | 4294901760 : (context->gpr[6] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_0111_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[7] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[7], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_0111_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[7] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[7], context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_0111_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[7] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[7], context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_0111_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[0] = context->gpr[7];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_0111_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[7] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[7], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[7] = 1 + context->gpr[7];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_0111_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[7] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[7], context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[7] = 2 + context->gpr[7];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_0111_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[7] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[7], context);
	context->gpr[0] = context->scratch1;
	context->gpr[7] = 4 + context->gpr[7];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_0111_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[0] = ~context->gpr[7];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_0111_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[7] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[7] << 8;
	temp2 = 65280 & temp2;
	context->gpr[0] = context->gpr[7] & 4294901760;
	context->gpr[0] = temp1 | context->gpr[0];
	context->gpr[0] = temp2 | context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_0111_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[7] >> 16;
	context->gpr[0] = context->gpr[7] << 16;
	context->gpr[0] = temp | context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_0111_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[7]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[0] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_0111_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[0] = -context->gpr[7];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_0111_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[0] = context->gpr[7] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_0111_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[0] = context->gpr[7] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_0111_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[0] = (context->gpr[0] & ~65535) | ((context->gpr[7] & 255) & 128 ? (context->gpr[7] & 255) | 65280 : (context->gpr[7] & 255));
	context->gpr[0] = (context->gpr[0] & 65535) & 32768 ? (context->gpr[0] & 65535) | 4294901760 : (context->gpr[0] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_0111_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[0] = (context->gpr[7] & 65535) & 32768 ? (context->gpr[7] & 65535) | 4294901760 : (context->gpr[7] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_1000_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[8] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[8], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_1000_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[8] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[8], context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_1000_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[8] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[8], context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_1000_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[0] = context->gpr[8];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_1000_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[8] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[8], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[8] = 1 + context->gpr[8];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_1000_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[8] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[8], context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[8] = 2 + context->gpr[8];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_1000_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[8] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[8], context);
	context->gpr[0] = context->scratch1;
	context->gpr[8] = 4 + context->gpr[8];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_1000_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[0] = ~context->gpr[8];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_1000_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[8] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[8] << 8;
	temp2 = 65280 & temp2;
	context->gpr[0] = context->gpr[8] & 4294901760;
	context->gpr[0] = temp1 | context->gpr[0];
	context->gpr[0] = temp2 | context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_1000_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[8] >> 16;
	context->gpr[0] = context->gpr[8] << 16;
	context->gpr[0] = temp | context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_1000_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[8]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[0] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_1000_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[0] = -context->gpr[8];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_1000_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[0] = context->gpr[8] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_1000_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[0] = context->gpr[8] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_1000_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[0] = (context->gpr[0] & ~65535) | ((context->gpr[8] & 255) & 128 ? (context->gpr[8] & 255) | 65280 : (context->gpr[8] & 255));
	context->gpr[0] = (context->gpr[0] & 65535) & 32768 ? (context->gpr[0] & 65535) | 4294901760 : (context->gpr[0] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_1000_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[0] = (context->gpr[8] & 65535) & 32768 ? (context->gpr[8] & 65535) | 4294901760 : (context->gpr[8] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_1001_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[9] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[9], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_1001_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[9] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[9], context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_1001_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[9] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[9], context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_1001_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[0] = context->gpr[9];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_1001_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[9] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[9], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[9] = 1 + context->gpr[9];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_1001_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[9] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[9], context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[9] = 2 + context->gpr[9];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_1001_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[9] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[9], context);
	context->gpr[0] = context->scratch1;
	context->gpr[9] = 4 + context->gpr[9];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_1001_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[0] = ~context->gpr[9];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_1001_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[9] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[9] << 8;
	temp2 = 65280 & temp2;
	context->gpr[0] = context->gpr[9] & 4294901760;
	context->gpr[0] = temp1 | context->gpr[0];
	context->gpr[0] = temp2 | context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_1001_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[9] >> 16;
	context->gpr[0] = context->gpr[9] << 16;
	context->gpr[0] = temp | context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_1001_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[9]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[0] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_1001_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[0] = -context->gpr[9];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_1001_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[0] = context->gpr[9] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_1001_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[0] = context->gpr[9] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_1001_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[0] = (context->gpr[0] & ~65535) | ((context->gpr[9] & 255) & 128 ? (context->gpr[9] & 255) | 65280 : (context->gpr[9] & 255));
	context->gpr[0] = (context->gpr[0] & 65535) & 32768 ? (context->gpr[0] & 65535) | 4294901760 : (context->gpr[0] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_1001_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[0] = (context->gpr[9] & 65535) & 32768 ? (context->gpr[9] & 65535) | 4294901760 : (context->gpr[9] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_1010_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[10] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[10], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_1010_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[10] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[10], context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_1010_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[10] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[10], context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_1010_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[0] = context->gpr[10];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_1010_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[10] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[10], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[10] = 1 + context->gpr[10];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_1010_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[10] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[10], context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[10] = 2 + context->gpr[10];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_1010_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[10] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[10], context);
	context->gpr[0] = context->scratch1;
	context->gpr[10] = 4 + context->gpr[10];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_1010_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[0] = ~context->gpr[10];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_1010_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[10] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[10] << 8;
	temp2 = 65280 & temp2;
	context->gpr[0] = context->gpr[10] & 4294901760;
	context->gpr[0] = temp1 | context->gpr[0];
	context->gpr[0] = temp2 | context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_1010_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[10] >> 16;
	context->gpr[0] = context->gpr[10] << 16;
	context->gpr[0] = temp | context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_1010_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[10]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[0] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_1010_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[0] = -context->gpr[10];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_1010_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[0] = context->gpr[10] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_1010_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[0] = context->gpr[10] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_1010_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[0] = (context->gpr[0] & ~65535) | ((context->gpr[10] & 255) & 128 ? (context->gpr[10] & 255) | 65280 : (context->gpr[10] & 255));
	context->gpr[0] = (context->gpr[0] & 65535) & 32768 ? (context->gpr[0] & 65535) | 4294901760 : (context->gpr[0] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_1010_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[0] = (context->gpr[10] & 65535) & 32768 ? (context->gpr[10] & 65535) | 4294901760 : (context->gpr[10] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_1011_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[11] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[11], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_1011_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[11] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[11], context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_1011_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[11] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[11], context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_1011_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[0] = context->gpr[11];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_1011_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[11] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[11], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[11] = 1 + context->gpr[11];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_1011_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[11] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[11], context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[11] = 2 + context->gpr[11];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_1011_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[11] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[11], context);
	context->gpr[0] = context->scratch1;
	context->gpr[11] = 4 + context->gpr[11];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_1011_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[0] = ~context->gpr[11];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_1011_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[11] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[11] << 8;
	temp2 = 65280 & temp2;
	context->gpr[0] = context->gpr[11] & 4294901760;
	context->gpr[0] = temp1 | context->gpr[0];
	context->gpr[0] = temp2 | context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_1011_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[11] >> 16;
	context->gpr[0] = context->gpr[11] << 16;
	context->gpr[0] = temp | context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_1011_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[11]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[0] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_1011_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[0] = -context->gpr[11];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_1011_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[0] = context->gpr[11] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_1011_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[0] = context->gpr[11] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_1011_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[0] = (context->gpr[0] & ~65535) | ((context->gpr[11] & 255) & 128 ? (context->gpr[11] & 255) | 65280 : (context->gpr[11] & 255));
	context->gpr[0] = (context->gpr[0] & 65535) & 32768 ? (context->gpr[0] & 65535) | 4294901760 : (context->gpr[0] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_1011_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[0] = (context->gpr[11] & 65535) & 32768 ? (context->gpr[11] & 65535) | 4294901760 : (context->gpr[11] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_1100_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[12] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[12], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_1100_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[12] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[12], context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_1100_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[12] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[12], context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_1100_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[0] = context->gpr[12];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_1100_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[12] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[12], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[12] = 1 + context->gpr[12];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_1100_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[12] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[12], context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[12] = 2 + context->gpr[12];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_1100_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[12] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[12], context);
	context->gpr[0] = context->scratch1;
	context->gpr[12] = 4 + context->gpr[12];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_1100_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[0] = ~context->gpr[12];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_1100_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[12] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[12] << 8;
	temp2 = 65280 & temp2;
	context->gpr[0] = context->gpr[12] & 4294901760;
	context->gpr[0] = temp1 | context->gpr[0];
	context->gpr[0] = temp2 | context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_1100_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[12] >> 16;
	context->gpr[0] = context->gpr[12] << 16;
	context->gpr[0] = temp | context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_1100_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[12]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[0] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_1100_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[0] = -context->gpr[12];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_1100_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[0] = context->gpr[12] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_1100_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[0] = context->gpr[12] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_1100_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[0] = (context->gpr[0] & ~65535) | ((context->gpr[12] & 255) & 128 ? (context->gpr[12] & 255) | 65280 : (context->gpr[12] & 255));
	context->gpr[0] = (context->gpr[0] & 65535) & 32768 ? (context->gpr[0] & 65535) | 4294901760 : (context->gpr[0] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_1100_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[0] = (context->gpr[12] & 65535) & 32768 ? (context->gpr[12] & 65535) | 4294901760 : (context->gpr[12] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_1101_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[13] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[13], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_1101_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[13] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[13], context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_1101_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[13] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[13], context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_1101_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[0] = context->gpr[13];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_1101_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[13] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[13], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[13] = 1 + context->gpr[13];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_1101_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[13] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[13], context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[13] = 2 + context->gpr[13];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_1101_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[13] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[13], context);
	context->gpr[0] = context->scratch1;
	context->gpr[13] = 4 + context->gpr[13];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_1101_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[0] = ~context->gpr[13];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_1101_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[13] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[13] << 8;
	temp2 = 65280 & temp2;
	context->gpr[0] = context->gpr[13] & 4294901760;
	context->gpr[0] = temp1 | context->gpr[0];
	context->gpr[0] = temp2 | context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_1101_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[13] >> 16;
	context->gpr[0] = context->gpr[13] << 16;
	context->gpr[0] = temp | context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_1101_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[13]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[0] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_1101_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[0] = -context->gpr[13];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_1101_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[0] = context->gpr[13] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_1101_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[0] = context->gpr[13] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_1101_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[0] = (context->gpr[0] & ~65535) | ((context->gpr[13] & 255) & 128 ? (context->gpr[13] & 255) | 65280 : (context->gpr[13] & 255));
	context->gpr[0] = (context->gpr[0] & 65535) & 32768 ? (context->gpr[0] & 65535) | 4294901760 : (context->gpr[0] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_1101_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[0] = (context->gpr[13] & 65535) & 32768 ? (context->gpr[13] & 65535) | 4294901760 : (context->gpr[13] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_1110_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[14] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[14], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_1110_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[14] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[14], context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_1110_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[14] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[14], context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_1110_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[0] = context->gpr[14];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_1110_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[14] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[14], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[14] = 1 + context->gpr[14];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_1110_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[14] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[14], context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[14] = 2 + context->gpr[14];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_1110_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[14] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[14], context);
	context->gpr[0] = context->scratch1;
	context->gpr[14] = 4 + context->gpr[14];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_1110_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[0] = ~context->gpr[14];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_1110_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[14] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[14] << 8;
	temp2 = 65280 & temp2;
	context->gpr[0] = context->gpr[14] & 4294901760;
	context->gpr[0] = temp1 | context->gpr[0];
	context->gpr[0] = temp2 | context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_1110_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[14] >> 16;
	context->gpr[0] = context->gpr[14] << 16;
	context->gpr[0] = temp | context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_1110_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[14]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[0] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_1110_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[0] = -context->gpr[14];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_1110_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[0] = context->gpr[14] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_1110_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[0] = context->gpr[14] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_1110_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[0] = (context->gpr[0] & ~65535) | ((context->gpr[14] & 255) & 128 ? (context->gpr[14] & 255) | 65280 : (context->gpr[14] & 255));
	context->gpr[0] = (context->gpr[0] & 65535) & 32768 ? (context->gpr[0] & 65535) | 4294901760 : (context->gpr[0] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_1110_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[0] = (context->gpr[14] & 65535) & 32768 ? (context->gpr[14] & 65535) | 4294901760 : (context->gpr[14] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_1111_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[15] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[15], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_1111_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[15] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[15], context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_1111_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[15] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[15], context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_1111_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[0] = context->gpr[15];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_1111_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[15] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[15], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[15] = 1 + context->gpr[15];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_1111_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[15] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[15], context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[15] = 2 + context->gpr[15];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_1111_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[15] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[15], context);
	context->gpr[0] = context->scratch1;
	context->gpr[15] = 4 + context->gpr[15];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_1111_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[0] = ~context->gpr[15];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_1111_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[15] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[15] << 8;
	temp2 = 65280 & temp2;
	context->gpr[0] = context->gpr[15] & 4294901760;
	context->gpr[0] = temp1 | context->gpr[0];
	context->gpr[0] = temp2 | context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_1111_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[15] >> 16;
	context->gpr[0] = context->gpr[15] << 16;
	context->gpr[0] = temp | context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_1111_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[15]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[0] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_1111_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[0] = -context->gpr[15];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_1111_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[0] = context->gpr[15] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_1111_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[0] = context->gpr[15] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_1111_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[0] = (context->gpr[0] & ~65535) | ((context->gpr[15] & 255) & 128 ? (context->gpr[15] & 255) | 65280 : (context->gpr[15] & 255));
	context->gpr[0] = (context->gpr[0] & 65535) & 32768 ? (context->gpr[0] & 65535) | 4294901760 : (context->gpr[0] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_1111_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[0] = (context->gpr[15] & 65535) & 32768 ? (context->gpr[15] & 65535) | 4294901760 : (context->gpr[15] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_0000_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[0] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[0], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[1] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_0000_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[0] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[0], context);
	context->gpr[1] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_0000_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[0] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[0], context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_0000_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[1] = context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_0000_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[0] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[0], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[1] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[0] = 1 + context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_0000_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[0] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[0], context);
	context->gpr[1] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[0] = 2 + context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_0000_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[0] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[0], context);
	context->gpr[1] = context->scratch1;
	context->gpr[0] = 4 + context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_0000_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[1] = ~context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_0000_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[0] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[0] << 8;
	temp2 = 65280 & temp2;
	context->gpr[1] = context->gpr[0] & 4294901760;
	context->gpr[1] = temp1 | context->gpr[1];
	context->gpr[1] = temp2 | context->gpr[1];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_0000_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[0] >> 16;
	context->gpr[1] = context->gpr[0] << 16;
	context->gpr[1] = temp | context->gpr[1];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_0000_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[0]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[1] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_0000_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[1] = -context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_0000_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[1] = context->gpr[0] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_0000_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[1] = context->gpr[0] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_0000_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[1] = (context->gpr[1] & ~65535) | ((context->gpr[0] & 255) & 128 ? (context->gpr[0] & 255) | 65280 : (context->gpr[0] & 255));
	context->gpr[1] = (context->gpr[1] & 65535) & 32768 ? (context->gpr[1] & 65535) | 4294901760 : (context->gpr[1] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_0000_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[1] = (context->gpr[0] & 65535) & 32768 ? (context->gpr[0] & 65535) | 4294901760 : (context->gpr[0] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_0001_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[1] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[1], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[1] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_0001_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[1] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[1], context);
	context->gpr[1] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_0001_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[1] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[1], context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_0001_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[1] = context->gpr[1];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_0001_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[1] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[1], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[1] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_0001_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[1] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[1], context);
	context->gpr[1] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_0001_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[1] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[1], context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_0001_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[1] = ~context->gpr[1];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_0001_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[1] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[1] << 8;
	temp2 = 65280 & temp2;
	context->gpr[1] = context->gpr[1] & 4294901760;
	context->gpr[1] = temp1 | context->gpr[1];
	context->gpr[1] = temp2 | context->gpr[1];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_0001_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[1] >> 16;
	context->gpr[1] = context->gpr[1] << 16;
	context->gpr[1] = temp | context->gpr[1];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_0001_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[1]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[1] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_0001_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[1] = -context->gpr[1];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_0001_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[1] = context->gpr[1] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_0001_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[1] = context->gpr[1] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_0001_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[1] = (context->gpr[1] & ~65535) | ((context->gpr[1] & 255) & 128 ? (context->gpr[1] & 255) | 65280 : (context->gpr[1] & 255));
	context->gpr[1] = (context->gpr[1] & 65535) & 32768 ? (context->gpr[1] & 65535) | 4294901760 : (context->gpr[1] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_0001_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[1] = (context->gpr[1] & 65535) & 32768 ? (context->gpr[1] & 65535) | 4294901760 : (context->gpr[1] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_0010_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[2] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[2], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[1] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_0010_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[2] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[2], context);
	context->gpr[1] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_0010_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[2] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[2], context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_0010_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[1] = context->gpr[2];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_0010_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[2] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[2], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[1] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[2] = 1 + context->gpr[2];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_0010_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[2] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[2], context);
	context->gpr[1] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[2] = 2 + context->gpr[2];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_0010_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[2] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[2], context);
	context->gpr[1] = context->scratch1;
	context->gpr[2] = 4 + context->gpr[2];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_0010_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[1] = ~context->gpr[2];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_0010_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[2] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[2] << 8;
	temp2 = 65280 & temp2;
	context->gpr[1] = context->gpr[2] & 4294901760;
	context->gpr[1] = temp1 | context->gpr[1];
	context->gpr[1] = temp2 | context->gpr[1];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_0010_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[2] >> 16;
	context->gpr[1] = context->gpr[2] << 16;
	context->gpr[1] = temp | context->gpr[1];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_0010_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[2]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[1] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_0010_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[1] = -context->gpr[2];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_0010_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[1] = context->gpr[2] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_0010_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[1] = context->gpr[2] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_0010_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[1] = (context->gpr[1] & ~65535) | ((context->gpr[2] & 255) & 128 ? (context->gpr[2] & 255) | 65280 : (context->gpr[2] & 255));
	context->gpr[1] = (context->gpr[1] & 65535) & 32768 ? (context->gpr[1] & 65535) | 4294901760 : (context->gpr[1] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_0010_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[1] = (context->gpr[2] & 65535) & 32768 ? (context->gpr[2] & 65535) | 4294901760 : (context->gpr[2] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_0011_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[3] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[3], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[1] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_0011_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[3] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[3], context);
	context->gpr[1] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_0011_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[3] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[3], context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_0011_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[1] = context->gpr[3];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_0011_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[3] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[3], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[1] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[3] = 1 + context->gpr[3];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_0011_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[3] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[3], context);
	context->gpr[1] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[3] = 2 + context->gpr[3];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_0011_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[3] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[3], context);
	context->gpr[1] = context->scratch1;
	context->gpr[3] = 4 + context->gpr[3];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_0011_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[1] = ~context->gpr[3];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_0011_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[3] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[3] << 8;
	temp2 = 65280 & temp2;
	context->gpr[1] = context->gpr[3] & 4294901760;
	context->gpr[1] = temp1 | context->gpr[1];
	context->gpr[1] = temp2 | context->gpr[1];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_0011_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[3] >> 16;
	context->gpr[1] = context->gpr[3] << 16;
	context->gpr[1] = temp | context->gpr[1];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_0011_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[3]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[1] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_0011_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[1] = -context->gpr[3];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_0011_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[1] = context->gpr[3] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_0011_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[1] = context->gpr[3] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_0011_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[1] = (context->gpr[1] & ~65535) | ((context->gpr[3] & 255) & 128 ? (context->gpr[3] & 255) | 65280 : (context->gpr[3] & 255));
	context->gpr[1] = (context->gpr[1] & 65535) & 32768 ? (context->gpr[1] & 65535) | 4294901760 : (context->gpr[1] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_0011_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[1] = (context->gpr[3] & 65535) & 32768 ? (context->gpr[3] & 65535) | 4294901760 : (context->gpr[3] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_0100_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[4] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[4], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[1] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_0100_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[4] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[4], context);
	context->gpr[1] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_0100_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[4] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[4], context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_0100_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[1] = context->gpr[4];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_0100_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[4] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[4], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[1] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[4] = 1 + context->gpr[4];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_0100_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[4] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[4], context);
	context->gpr[1] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[4] = 2 + context->gpr[4];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_0100_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[4] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[4], context);
	context->gpr[1] = context->scratch1;
	context->gpr[4] = 4 + context->gpr[4];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_0100_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[1] = ~context->gpr[4];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_0100_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[4] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[4] << 8;
	temp2 = 65280 & temp2;
	context->gpr[1] = context->gpr[4] & 4294901760;
	context->gpr[1] = temp1 | context->gpr[1];
	context->gpr[1] = temp2 | context->gpr[1];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_0100_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[4] >> 16;
	context->gpr[1] = context->gpr[4] << 16;
	context->gpr[1] = temp | context->gpr[1];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_0100_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[4]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[1] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_0100_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[1] = -context->gpr[4];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_0100_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[1] = context->gpr[4] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_0100_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[1] = context->gpr[4] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_0100_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[1] = (context->gpr[1] & ~65535) | ((context->gpr[4] & 255) & 128 ? (context->gpr[4] & 255) | 65280 : (context->gpr[4] & 255));
	context->gpr[1] = (context->gpr[1] & 65535) & 32768 ? (context->gpr[1] & 65535) | 4294901760 : (context->gpr[1] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_0100_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[1] = (context->gpr[4] & 65535) & 32768 ? (context->gpr[4] & 65535) | 4294901760 : (context->gpr[4] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_0101_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[5] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[5], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[1] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_0101_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[5] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[5], context);
	context->gpr[1] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_0101_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[5] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[5], context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_0101_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[1] = context->gpr[5];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_0101_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[5] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[5], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[1] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[5] = 1 + context->gpr[5];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_0101_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[5] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[5], context);
	context->gpr[1] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[5] = 2 + context->gpr[5];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_0101_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[5] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[5], context);
	context->gpr[1] = context->scratch1;
	context->gpr[5] = 4 + context->gpr[5];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_0101_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[1] = ~context->gpr[5];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_0101_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[5] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[5] << 8;
	temp2 = 65280 & temp2;
	context->gpr[1] = context->gpr[5] & 4294901760;
	context->gpr[1] = temp1 | context->gpr[1];
	context->gpr[1] = temp2 | context->gpr[1];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_0101_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[5] >> 16;
	context->gpr[1] = context->gpr[5] << 16;
	context->gpr[1] = temp | context->gpr[1];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_0101_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[5]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[1] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_0101_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[1] = -context->gpr[5];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_0101_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[1] = context->gpr[5] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_0101_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[1] = context->gpr[5] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_0101_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[1] = (context->gpr[1] & ~65535) | ((context->gpr[5] & 255) & 128 ? (context->gpr[5] & 255) | 65280 : (context->gpr[5] & 255));
	context->gpr[1] = (context->gpr[1] & 65535) & 32768 ? (context->gpr[1] & 65535) | 4294901760 : (context->gpr[1] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_0101_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[1] = (context->gpr[5] & 65535) & 32768 ? (context->gpr[5] & 65535) | 4294901760 : (context->gpr[5] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_0110_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[6] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[6], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[1] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_0110_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[6] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[6], context);
	context->gpr[1] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_0110_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[6] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[6], context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_0110_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[1] = context->gpr[6];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_0110_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[6] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[6], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[1] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[6] = 1 + context->gpr[6];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_0110_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[6] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[6], context);
	context->gpr[1] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[6] = 2 + context->gpr[6];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_0110_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[6] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[6], context);
	context->gpr[1] = context->scratch1;
	context->gpr[6] = 4 + context->gpr[6];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_0110_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[1] = ~context->gpr[6];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_0110_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[6] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[6] << 8;
	temp2 = 65280 & temp2;
	context->gpr[1] = context->gpr[6] & 4294901760;
	context->gpr[1] = temp1 | context->gpr[1];
	context->gpr[1] = temp2 | context->gpr[1];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_0110_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[6] >> 16;
	context->gpr[1] = context->gpr[6] << 16;
	context->gpr[1] = temp | context->gpr[1];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_0110_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[6]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[1] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_0110_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[1] = -context->gpr[6];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_0110_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[1] = context->gpr[6] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_0110_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[1] = context->gpr[6] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_0110_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[1] = (context->gpr[1] & ~65535) | ((context->gpr[6] & 255) & 128 ? (context->gpr[6] & 255) | 65280 : (context->gpr[6] & 255));
	context->gpr[1] = (context->gpr[1] & 65535) & 32768 ? (context->gpr[1] & 65535) | 4294901760 : (context->gpr[1] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_0110_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[1] = (context->gpr[6] & 65535) & 32768 ? (context->gpr[6] & 65535) | 4294901760 : (context->gpr[6] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_0111_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[7] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[7], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[1] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_0111_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[7] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[7], context);
	context->gpr[1] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_0111_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[7] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[7], context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_0111_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[1] = context->gpr[7];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_0111_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[7] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[7], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[1] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[7] = 1 + context->gpr[7];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_0111_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[7] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[7], context);
	context->gpr[1] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[7] = 2 + context->gpr[7];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_0111_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[7] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[7], context);
	context->gpr[1] = context->scratch1;
	context->gpr[7] = 4 + context->gpr[7];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_0111_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[1] = ~context->gpr[7];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_0111_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[7] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[7] << 8;
	temp2 = 65280 & temp2;
	context->gpr[1] = context->gpr[7] & 4294901760;
	context->gpr[1] = temp1 | context->gpr[1];
	context->gpr[1] = temp2 | context->gpr[1];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_0111_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[7] >> 16;
	context->gpr[1] = context->gpr[7] << 16;
	context->gpr[1] = temp | context->gpr[1];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_0111_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[7]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[1] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_0111_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[1] = -context->gpr[7];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_0111_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[1] = context->gpr[7] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_0111_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[1] = context->gpr[7] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_0111_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[1] = (context->gpr[1] & ~65535) | ((context->gpr[7] & 255) & 128 ? (context->gpr[7] & 255) | 65280 : (context->gpr[7] & 255));
	context->gpr[1] = (context->gpr[1] & 65535) & 32768 ? (context->gpr[1] & 65535) | 4294901760 : (context->gpr[1] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_0111_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[1] = (context->gpr[7] & 65535) & 32768 ? (context->gpr[7] & 65535) | 4294901760 : (context->gpr[7] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_1000_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[8] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[8], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[1] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_1000_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[8] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[8], context);
	context->gpr[1] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_1000_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[8] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[8], context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_1000_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[1] = context->gpr[8];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_1000_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[8] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[8], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[1] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[8] = 1 + context->gpr[8];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_1000_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[8] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[8], context);
	context->gpr[1] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[8] = 2 + context->gpr[8];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_1000_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[8] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[8], context);
	context->gpr[1] = context->scratch1;
	context->gpr[8] = 4 + context->gpr[8];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_1000_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[1] = ~context->gpr[8];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_1000_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[8] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[8] << 8;
	temp2 = 65280 & temp2;
	context->gpr[1] = context->gpr[8] & 4294901760;
	context->gpr[1] = temp1 | context->gpr[1];
	context->gpr[1] = temp2 | context->gpr[1];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_1000_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[8] >> 16;
	context->gpr[1] = context->gpr[8] << 16;
	context->gpr[1] = temp | context->gpr[1];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_1000_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[8]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[1] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_1000_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[1] = -context->gpr[8];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_1000_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[1] = context->gpr[8] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_1000_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[1] = context->gpr[8] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_1000_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[1] = (context->gpr[1] & ~65535) | ((context->gpr[8] & 255) & 128 ? (context->gpr[8] & 255) | 65280 : (context->gpr[8] & 255));
	context->gpr[1] = (context->gpr[1] & 65535) & 32768 ? (context->gpr[1] & 65535) | 4294901760 : (context->gpr[1] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_1000_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[1] = (context->gpr[8] & 65535) & 32768 ? (context->gpr[8] & 65535) | 4294901760 : (context->gpr[8] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_1001_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[9] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[9], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[1] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_1001_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[9] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[9], context);
	context->gpr[1] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_1001_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[9] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[9], context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_1001_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[1] = context->gpr[9];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_1001_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[9] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[9], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[1] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[9] = 1 + context->gpr[9];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_1001_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[9] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[9], context);
	context->gpr[1] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[9] = 2 + context->gpr[9];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_1001_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[9] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[9], context);
	context->gpr[1] = context->scratch1;
	context->gpr[9] = 4 + context->gpr[9];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_1001_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[1] = ~context->gpr[9];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_1001_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[9] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[9] << 8;
	temp2 = 65280 & temp2;
	context->gpr[1] = context->gpr[9] & 4294901760;
	context->gpr[1] = temp1 | context->gpr[1];
	context->gpr[1] = temp2 | context->gpr[1];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_1001_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[9] >> 16;
	context->gpr[1] = context->gpr[9] << 16;
	context->gpr[1] = temp | context->gpr[1];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_1001_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[9]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[1] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_1001_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[1] = -context->gpr[9];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_1001_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[1] = context->gpr[9] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_1001_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[1] = context->gpr[9] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_1001_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[1] = (context->gpr[1] & ~65535) | ((context->gpr[9] & 255) & 128 ? (context->gpr[9] & 255) | 65280 : (context->gpr[9] & 255));
	context->gpr[1] = (context->gpr[1] & 65535) & 32768 ? (context->gpr[1] & 65535) | 4294901760 : (context->gpr[1] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_1001_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[1] = (context->gpr[9] & 65535) & 32768 ? (context->gpr[9] & 65535) | 4294901760 : (context->gpr[9] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_1010_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[10] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[10], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[1] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_1010_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[10] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[10], context);
	context->gpr[1] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_1010_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[10] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[10], context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_1010_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[1] = context->gpr[10];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_1010_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[10] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[10], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[1] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[10] = 1 + context->gpr[10];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_1010_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[10] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[10], context);
	context->gpr[1] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[10] = 2 + context->gpr[10];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_1010_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[10] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[10], context);
	context->gpr[1] = context->scratch1;
	context->gpr[10] = 4 + context->gpr[10];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_1010_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[1] = ~context->gpr[10];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_1010_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[10] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[10] << 8;
	temp2 = 65280 & temp2;
	context->gpr[1] = context->gpr[10] & 4294901760;
	context->gpr[1] = temp1 | context->gpr[1];
	context->gpr[1] = temp2 | context->gpr[1];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_1010_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[10] >> 16;
	context->gpr[1] = context->gpr[10] << 16;
	context->gpr[1] = temp | context->gpr[1];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_1010_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[10]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[1] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_1010_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[1] = -context->gpr[10];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_1010_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[1] = context->gpr[10] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_1010_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[1] = context->gpr[10] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_1010_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[1] = (context->gpr[1] & ~65535) | ((context->gpr[10] & 255) & 128 ? (context->gpr[10] & 255) | 65280 : (context->gpr[10] & 255));
	context->gpr[1] = (context->gpr[1] & 65535) & 32768 ? (context->gpr[1] & 65535) | 4294901760 : (context->gpr[1] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_1010_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[1] = (context->gpr[10] & 65535) & 32768 ? (context->gpr[10] & 65535) | 4294901760 : (context->gpr[10] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_1011_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[11] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[11], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[1] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_1011_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[11] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[11], context);
	context->gpr[1] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_1011_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[11] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[11], context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_1011_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[1] = context->gpr[11];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_1011_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[11] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[11], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[1] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[11] = 1 + context->gpr[11];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_1011_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[11] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[11], context);
	context->gpr[1] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[11] = 2 + context->gpr[11];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_1011_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[11] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[11], context);
	context->gpr[1] = context->scratch1;
	context->gpr[11] = 4 + context->gpr[11];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_1011_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[1] = ~context->gpr[11];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_1011_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[11] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[11] << 8;
	temp2 = 65280 & temp2;
	context->gpr[1] = context->gpr[11] & 4294901760;
	context->gpr[1] = temp1 | context->gpr[1];
	context->gpr[1] = temp2 | context->gpr[1];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_1011_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[11] >> 16;
	context->gpr[1] = context->gpr[11] << 16;
	context->gpr[1] = temp | context->gpr[1];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_1011_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[11]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[1] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_1011_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[1] = -context->gpr[11];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_1011_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[1] = context->gpr[11] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_1011_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[1] = context->gpr[11] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_1011_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[1] = (context->gpr[1] & ~65535) | ((context->gpr[11] & 255) & 128 ? (context->gpr[11] & 255) | 65280 : (context->gpr[11] & 255));
	context->gpr[1] = (context->gpr[1] & 65535) & 32768 ? (context->gpr[1] & 65535) | 4294901760 : (context->gpr[1] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_1011_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[1] = (context->gpr[11] & 65535) & 32768 ? (context->gpr[11] & 65535) | 4294901760 : (context->gpr[11] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_1100_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[12] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[12], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[1] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_1100_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[12] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[12], context);
	context->gpr[1] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_1100_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[12] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[12], context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_1100_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[1] = context->gpr[12];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_1100_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[12] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[12], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[1] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[12] = 1 + context->gpr[12];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_1100_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[12] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[12], context);
	context->gpr[1] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[12] = 2 + context->gpr[12];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_1100_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[12] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[12], context);
	context->gpr[1] = context->scratch1;
	context->gpr[12] = 4 + context->gpr[12];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_1100_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[1] = ~context->gpr[12];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_1100_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[12] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[12] << 8;
	temp2 = 65280 & temp2;
	context->gpr[1] = context->gpr[12] & 4294901760;
	context->gpr[1] = temp1 | context->gpr[1];
	context->gpr[1] = temp2 | context->gpr[1];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_1100_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[12] >> 16;
	context->gpr[1] = context->gpr[12] << 16;
	context->gpr[1] = temp | context->gpr[1];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_1100_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[12]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[1] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_1100_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[1] = -context->gpr[12];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_1100_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[1] = context->gpr[12] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_1100_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[1] = context->gpr[12] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_1100_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[1] = (context->gpr[1] & ~65535) | ((context->gpr[12] & 255) & 128 ? (context->gpr[12] & 255) | 65280 : (context->gpr[12] & 255));
	context->gpr[1] = (context->gpr[1] & 65535) & 32768 ? (context->gpr[1] & 65535) | 4294901760 : (context->gpr[1] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_1100_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[1] = (context->gpr[12] & 65535) & 32768 ? (context->gpr[12] & 65535) | 4294901760 : (context->gpr[12] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_1101_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[13] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[13], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[1] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_1101_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[13] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[13], context);
	context->gpr[1] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_1101_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[13] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[13], context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_1101_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[1] = context->gpr[13];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_1101_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[13] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[13], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[1] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[13] = 1 + context->gpr[13];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_1101_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[13] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[13], context);
	context->gpr[1] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[13] = 2 + context->gpr[13];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_1101_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[13] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[13], context);
	context->gpr[1] = context->scratch1;
	context->gpr[13] = 4 + context->gpr[13];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_1101_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[1] = ~context->gpr[13];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_1101_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[13] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[13] << 8;
	temp2 = 65280 & temp2;
	context->gpr[1] = context->gpr[13] & 4294901760;
	context->gpr[1] = temp1 | context->gpr[1];
	context->gpr[1] = temp2 | context->gpr[1];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_1101_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[13] >> 16;
	context->gpr[1] = context->gpr[13] << 16;
	context->gpr[1] = temp | context->gpr[1];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_1101_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[13]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[1] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_1101_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[1] = -context->gpr[13];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_1101_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[1] = context->gpr[13] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_1101_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[1] = context->gpr[13] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_1101_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[1] = (context->gpr[1] & ~65535) | ((context->gpr[13] & 255) & 128 ? (context->gpr[13] & 255) | 65280 : (context->gpr[13] & 255));
	context->gpr[1] = (context->gpr[1] & 65535) & 32768 ? (context->gpr[1] & 65535) | 4294901760 : (context->gpr[1] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_1101_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[1] = (context->gpr[13] & 65535) & 32768 ? (context->gpr[13] & 65535) | 4294901760 : (context->gpr[13] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_1110_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[14] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[14], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[1] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_1110_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[14] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[14], context);
	context->gpr[1] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_1110_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[14] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[14], context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_1110_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[1] = context->gpr[14];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_1110_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[14] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[14], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[1] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[14] = 1 + context->gpr[14];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_1110_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[14] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[14], context);
	context->gpr[1] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[14] = 2 + context->gpr[14];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_1110_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[14] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[14], context);
	context->gpr[1] = context->scratch1;
	context->gpr[14] = 4 + context->gpr[14];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_1110_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[1] = ~context->gpr[14];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_1110_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[14] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[14] << 8;
	temp2 = 65280 & temp2;
	context->gpr[1] = context->gpr[14] & 4294901760;
	context->gpr[1] = temp1 | context->gpr[1];
	context->gpr[1] = temp2 | context->gpr[1];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_1110_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[14] >> 16;
	context->gpr[1] = context->gpr[14] << 16;
	context->gpr[1] = temp | context->gpr[1];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_1110_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[14]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[1] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_1110_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[1] = -context->gpr[14];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_1110_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[1] = context->gpr[14] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_1110_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[1] = context->gpr[14] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_1110_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[1] = (context->gpr[1] & ~65535) | ((context->gpr[14] & 255) & 128 ? (context->gpr[14] & 255) | 65280 : (context->gpr[14] & 255));
	context->gpr[1] = (context->gpr[1] & 65535) & 32768 ? (context->gpr[1] & 65535) | 4294901760 : (context->gpr[1] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_1110_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[1] = (context->gpr[14] & 65535) & 32768 ? (context->gpr[14] & 65535) | 4294901760 : (context->gpr[14] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_1111_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[15] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[15], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[1] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_1111_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[15] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[15], context);
	context->gpr[1] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_1111_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[15] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[15], context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_1111_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[1] = context->gpr[15];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_1111_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[15] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[15], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[1] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[15] = 1 + context->gpr[15];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_1111_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[15] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[15], context);
	context->gpr[1] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[15] = 2 + context->gpr[15];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_1111_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[15] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[15], context);
	context->gpr[1] = context->scratch1;
	context->gpr[15] = 4 + context->gpr[15];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_1111_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[1] = ~context->gpr[15];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_1111_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[15] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[15] << 8;
	temp2 = 65280 & temp2;
	context->gpr[1] = context->gpr[15] & 4294901760;
	context->gpr[1] = temp1 | context->gpr[1];
	context->gpr[1] = temp2 | context->gpr[1];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_1111_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[15] >> 16;
	context->gpr[1] = context->gpr[15] << 16;
	context->gpr[1] = temp | context->gpr[1];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_1111_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[15]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[1] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_1111_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[1] = -context->gpr[15];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_1111_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[1] = context->gpr[15] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_1111_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[1] = context->gpr[15] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_1111_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[1] = (context->gpr[1] & ~65535) | ((context->gpr[15] & 255) & 128 ? (context->gpr[15] & 255) | 65280 : (context->gpr[15] & 255));
	context->gpr[1] = (context->gpr[1] & 65535) & 32768 ? (context->gpr[1] & 65535) | 4294901760 : (context->gpr[1] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_1111_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[1] = (context->gpr[15] & 65535) & 32768 ? (context->gpr[15] & 65535) | 4294901760 : (context->gpr[15] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_0000_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[0] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[0], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[2] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_0000_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[0] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[0], context);
	context->gpr[2] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_0000_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[0] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[0], context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_0000_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[2] = context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_0000_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[0] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[0], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[2] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[0] = 1 + context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_0000_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[0] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[0], context);
	context->gpr[2] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[0] = 2 + context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_0000_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[0] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[0], context);
	context->gpr[2] = context->scratch1;
	context->gpr[0] = 4 + context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_0000_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[2] = ~context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_0000_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[0] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[0] << 8;
	temp2 = 65280 & temp2;
	context->gpr[2] = context->gpr[0] & 4294901760;
	context->gpr[2] = temp1 | context->gpr[2];
	context->gpr[2] = temp2 | context->gpr[2];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_0000_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[0] >> 16;
	context->gpr[2] = context->gpr[0] << 16;
	context->gpr[2] = temp | context->gpr[2];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_0000_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[0]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[2] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_0000_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[2] = -context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_0000_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[2] = context->gpr[0] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_0000_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[2] = context->gpr[0] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_0000_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[2] = (context->gpr[2] & ~65535) | ((context->gpr[0] & 255) & 128 ? (context->gpr[0] & 255) | 65280 : (context->gpr[0] & 255));
	context->gpr[2] = (context->gpr[2] & 65535) & 32768 ? (context->gpr[2] & 65535) | 4294901760 : (context->gpr[2] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_0000_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[2] = (context->gpr[0] & 65535) & 32768 ? (context->gpr[0] & 65535) | 4294901760 : (context->gpr[0] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_0001_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[1] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[1], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[2] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_0001_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[1] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[1], context);
	context->gpr[2] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_0001_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[1] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[1], context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_0001_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[2] = context->gpr[1];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_0001_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[1] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[1], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[2] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[1] = 1 + context->gpr[1];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_0001_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[1] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[1], context);
	context->gpr[2] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[1] = 2 + context->gpr[1];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_0001_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[1] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[1], context);
	context->gpr[2] = context->scratch1;
	context->gpr[1] = 4 + context->gpr[1];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_0001_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[2] = ~context->gpr[1];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_0001_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[1] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[1] << 8;
	temp2 = 65280 & temp2;
	context->gpr[2] = context->gpr[1] & 4294901760;
	context->gpr[2] = temp1 | context->gpr[2];
	context->gpr[2] = temp2 | context->gpr[2];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_0001_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[1] >> 16;
	context->gpr[2] = context->gpr[1] << 16;
	context->gpr[2] = temp | context->gpr[2];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_0001_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[1]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[2] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_0001_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[2] = -context->gpr[1];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_0001_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[2] = context->gpr[1] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_0001_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[2] = context->gpr[1] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_0001_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[2] = (context->gpr[2] & ~65535) | ((context->gpr[1] & 255) & 128 ? (context->gpr[1] & 255) | 65280 : (context->gpr[1] & 255));
	context->gpr[2] = (context->gpr[2] & 65535) & 32768 ? (context->gpr[2] & 65535) | 4294901760 : (context->gpr[2] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_0001_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[2] = (context->gpr[1] & 65535) & 32768 ? (context->gpr[1] & 65535) | 4294901760 : (context->gpr[1] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_0010_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[2] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[2], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[2] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_0010_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[2] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[2], context);
	context->gpr[2] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_0010_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[2] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[2], context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_0010_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[2] = context->gpr[2];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_0010_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[2] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[2], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[2] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_0010_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[2] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[2], context);
	context->gpr[2] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_0010_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[2] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[2], context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_0010_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[2] = ~context->gpr[2];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_0010_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[2] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[2] << 8;
	temp2 = 65280 & temp2;
	context->gpr[2] = context->gpr[2] & 4294901760;
	context->gpr[2] = temp1 | context->gpr[2];
	context->gpr[2] = temp2 | context->gpr[2];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_0010_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[2] >> 16;
	context->gpr[2] = context->gpr[2] << 16;
	context->gpr[2] = temp | context->gpr[2];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_0010_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[2]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[2] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_0010_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[2] = -context->gpr[2];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_0010_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[2] = context->gpr[2] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_0010_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[2] = context->gpr[2] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_0010_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[2] = (context->gpr[2] & ~65535) | ((context->gpr[2] & 255) & 128 ? (context->gpr[2] & 255) | 65280 : (context->gpr[2] & 255));
	context->gpr[2] = (context->gpr[2] & 65535) & 32768 ? (context->gpr[2] & 65535) | 4294901760 : (context->gpr[2] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_0010_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[2] = (context->gpr[2] & 65535) & 32768 ? (context->gpr[2] & 65535) | 4294901760 : (context->gpr[2] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_0011_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[3] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[3], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[2] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_0011_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[3] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[3], context);
	context->gpr[2] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_0011_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[3] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[3], context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_0011_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[2] = context->gpr[3];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_0011_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[3] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[3], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[2] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[3] = 1 + context->gpr[3];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_0011_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[3] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[3], context);
	context->gpr[2] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[3] = 2 + context->gpr[3];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_0011_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[3] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[3], context);
	context->gpr[2] = context->scratch1;
	context->gpr[3] = 4 + context->gpr[3];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_0011_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[2] = ~context->gpr[3];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_0011_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[3] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[3] << 8;
	temp2 = 65280 & temp2;
	context->gpr[2] = context->gpr[3] & 4294901760;
	context->gpr[2] = temp1 | context->gpr[2];
	context->gpr[2] = temp2 | context->gpr[2];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_0011_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[3] >> 16;
	context->gpr[2] = context->gpr[3] << 16;
	context->gpr[2] = temp | context->gpr[2];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_0011_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[3]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[2] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_0011_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[2] = -context->gpr[3];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_0011_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[2] = context->gpr[3] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_0011_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[2] = context->gpr[3] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_0011_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[2] = (context->gpr[2] & ~65535) | ((context->gpr[3] & 255) & 128 ? (context->gpr[3] & 255) | 65280 : (context->gpr[3] & 255));
	context->gpr[2] = (context->gpr[2] & 65535) & 32768 ? (context->gpr[2] & 65535) | 4294901760 : (context->gpr[2] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_0011_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[2] = (context->gpr[3] & 65535) & 32768 ? (context->gpr[3] & 65535) | 4294901760 : (context->gpr[3] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_0100_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[4] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[4], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[2] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_0100_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[4] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[4], context);
	context->gpr[2] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_0100_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[4] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[4], context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_0100_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[2] = context->gpr[4];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_0100_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[4] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[4], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[2] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[4] = 1 + context->gpr[4];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_0100_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[4] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[4], context);
	context->gpr[2] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[4] = 2 + context->gpr[4];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_0100_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[4] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[4], context);
	context->gpr[2] = context->scratch1;
	context->gpr[4] = 4 + context->gpr[4];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_0100_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[2] = ~context->gpr[4];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_0100_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[4] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[4] << 8;
	temp2 = 65280 & temp2;
	context->gpr[2] = context->gpr[4] & 4294901760;
	context->gpr[2] = temp1 | context->gpr[2];
	context->gpr[2] = temp2 | context->gpr[2];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_0100_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[4] >> 16;
	context->gpr[2] = context->gpr[4] << 16;
	context->gpr[2] = temp | context->gpr[2];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_0100_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[4]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[2] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_0100_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[2] = -context->gpr[4];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_0100_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[2] = context->gpr[4] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_0100_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[2] = context->gpr[4] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_0100_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[2] = (context->gpr[2] & ~65535) | ((context->gpr[4] & 255) & 128 ? (context->gpr[4] & 255) | 65280 : (context->gpr[4] & 255));
	context->gpr[2] = (context->gpr[2] & 65535) & 32768 ? (context->gpr[2] & 65535) | 4294901760 : (context->gpr[2] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_0100_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[2] = (context->gpr[4] & 65535) & 32768 ? (context->gpr[4] & 65535) | 4294901760 : (context->gpr[4] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_0101_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[5] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[5], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[2] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_0101_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[5] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[5], context);
	context->gpr[2] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_0101_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[5] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[5], context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_0101_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[2] = context->gpr[5];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_0101_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[5] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[5], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[2] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[5] = 1 + context->gpr[5];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_0101_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[5] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[5], context);
	context->gpr[2] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[5] = 2 + context->gpr[5];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_0101_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[5] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[5], context);
	context->gpr[2] = context->scratch1;
	context->gpr[5] = 4 + context->gpr[5];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_0101_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[2] = ~context->gpr[5];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_0101_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[5] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[5] << 8;
	temp2 = 65280 & temp2;
	context->gpr[2] = context->gpr[5] & 4294901760;
	context->gpr[2] = temp1 | context->gpr[2];
	context->gpr[2] = temp2 | context->gpr[2];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_0101_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[5] >> 16;
	context->gpr[2] = context->gpr[5] << 16;
	context->gpr[2] = temp | context->gpr[2];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_0101_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[5]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[2] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_0101_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[2] = -context->gpr[5];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_0101_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[2] = context->gpr[5] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_0101_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[2] = context->gpr[5] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_0101_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[2] = (context->gpr[2] & ~65535) | ((context->gpr[5] & 255) & 128 ? (context->gpr[5] & 255) | 65280 : (context->gpr[5] & 255));
	context->gpr[2] = (context->gpr[2] & 65535) & 32768 ? (context->gpr[2] & 65535) | 4294901760 : (context->gpr[2] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_0101_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[2] = (context->gpr[5] & 65535) & 32768 ? (context->gpr[5] & 65535) | 4294901760 : (context->gpr[5] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_0110_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[6] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[6], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[2] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_0110_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[6] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[6], context);
	context->gpr[2] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_0110_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[6] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[6], context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_0110_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[2] = context->gpr[6];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_0110_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[6] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[6], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[2] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[6] = 1 + context->gpr[6];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_0110_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[6] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[6], context);
	context->gpr[2] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[6] = 2 + context->gpr[6];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_0110_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[6] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[6], context);
	context->gpr[2] = context->scratch1;
	context->gpr[6] = 4 + context->gpr[6];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_0110_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[2] = ~context->gpr[6];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_0110_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[6] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[6] << 8;
	temp2 = 65280 & temp2;
	context->gpr[2] = context->gpr[6] & 4294901760;
	context->gpr[2] = temp1 | context->gpr[2];
	context->gpr[2] = temp2 | context->gpr[2];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_0110_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[6] >> 16;
	context->gpr[2] = context->gpr[6] << 16;
	context->gpr[2] = temp | context->gpr[2];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_0110_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[6]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[2] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_0110_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[2] = -context->gpr[6];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_0110_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[2] = context->gpr[6] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_0110_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[2] = context->gpr[6] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_0110_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[2] = (context->gpr[2] & ~65535) | ((context->gpr[6] & 255) & 128 ? (context->gpr[6] & 255) | 65280 : (context->gpr[6] & 255));
	context->gpr[2] = (context->gpr[2] & 65535) & 32768 ? (context->gpr[2] & 65535) | 4294901760 : (context->gpr[2] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_0110_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[2] = (context->gpr[6] & 65535) & 32768 ? (context->gpr[6] & 65535) | 4294901760 : (context->gpr[6] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_0111_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[7] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[7], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[2] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_0111_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[7] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[7], context);
	context->gpr[2] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_0111_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[7] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[7], context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_0111_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[2] = context->gpr[7];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_0111_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[7] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[7], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[2] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[7] = 1 + context->gpr[7];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_0111_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[7] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[7], context);
	context->gpr[2] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[7] = 2 + context->gpr[7];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_0111_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[7] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[7], context);
	context->gpr[2] = context->scratch1;
	context->gpr[7] = 4 + context->gpr[7];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_0111_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[2] = ~context->gpr[7];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_0111_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[7] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[7] << 8;
	temp2 = 65280 & temp2;
	context->gpr[2] = context->gpr[7] & 4294901760;
	context->gpr[2] = temp1 | context->gpr[2];
	context->gpr[2] = temp2 | context->gpr[2];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_0111_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[7] >> 16;
	context->gpr[2] = context->gpr[7] << 16;
	context->gpr[2] = temp | context->gpr[2];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_0111_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[7]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[2] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_0111_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[2] = -context->gpr[7];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_0111_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[2] = context->gpr[7] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_0111_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[2] = context->gpr[7] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_0111_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[2] = (context->gpr[2] & ~65535) | ((context->gpr[7] & 255) & 128 ? (context->gpr[7] & 255) | 65280 : (context->gpr[7] & 255));
	context->gpr[2] = (context->gpr[2] & 65535) & 32768 ? (context->gpr[2] & 65535) | 4294901760 : (context->gpr[2] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_0111_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[2] = (context->gpr[7] & 65535) & 32768 ? (context->gpr[7] & 65535) | 4294901760 : (context->gpr[7] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_1000_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[8] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[8], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[2] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_1000_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[8] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[8], context);
	context->gpr[2] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_1000_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[8] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[8], context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_1000_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[2] = context->gpr[8];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_1000_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[8] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[8], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[2] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[8] = 1 + context->gpr[8];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_1000_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[8] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[8], context);
	context->gpr[2] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[8] = 2 + context->gpr[8];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_1000_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[8] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[8], context);
	context->gpr[2] = context->scratch1;
	context->gpr[8] = 4 + context->gpr[8];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_1000_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[2] = ~context->gpr[8];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_1000_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[8] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[8] << 8;
	temp2 = 65280 & temp2;
	context->gpr[2] = context->gpr[8] & 4294901760;
	context->gpr[2] = temp1 | context->gpr[2];
	context->gpr[2] = temp2 | context->gpr[2];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_1000_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[8] >> 16;
	context->gpr[2] = context->gpr[8] << 16;
	context->gpr[2] = temp | context->gpr[2];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_1000_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[8]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[2] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_1000_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[2] = -context->gpr[8];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_1000_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[2] = context->gpr[8] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_1000_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[2] = context->gpr[8] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_1000_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[2] = (context->gpr[2] & ~65535) | ((context->gpr[8] & 255) & 128 ? (context->gpr[8] & 255) | 65280 : (context->gpr[8] & 255));
	context->gpr[2] = (context->gpr[2] & 65535) & 32768 ? (context->gpr[2] & 65535) | 4294901760 : (context->gpr[2] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_1000_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[2] = (context->gpr[8] & 65535) & 32768 ? (context->gpr[8] & 65535) | 4294901760 : (context->gpr[8] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_1001_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[9] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[9], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[2] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_1001_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[9] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[9], context);
	context->gpr[2] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_1001_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[9] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[9], context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_1001_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[2] = context->gpr[9];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_1001_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[9] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[9], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[2] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[9] = 1 + context->gpr[9];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_1001_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[9] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[9], context);
	context->gpr[2] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[9] = 2 + context->gpr[9];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_1001_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[9] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[9], context);
	context->gpr[2] = context->scratch1;
	context->gpr[9] = 4 + context->gpr[9];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_1001_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[2] = ~context->gpr[9];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_1001_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[9] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[9] << 8;
	temp2 = 65280 & temp2;
	context->gpr[2] = context->gpr[9] & 4294901760;
	context->gpr[2] = temp1 | context->gpr[2];
	context->gpr[2] = temp2 | context->gpr[2];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_1001_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[9] >> 16;
	context->gpr[2] = context->gpr[9] << 16;
	context->gpr[2] = temp | context->gpr[2];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_1001_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[9]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[2] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_1001_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[2] = -context->gpr[9];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_1001_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[2] = context->gpr[9] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_1001_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[2] = context->gpr[9] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_1001_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[2] = (context->gpr[2] & ~65535) | ((context->gpr[9] & 255) & 128 ? (context->gpr[9] & 255) | 65280 : (context->gpr[9] & 255));
	context->gpr[2] = (context->gpr[2] & 65535) & 32768 ? (context->gpr[2] & 65535) | 4294901760 : (context->gpr[2] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_1001_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[2] = (context->gpr[9] & 65535) & 32768 ? (context->gpr[9] & 65535) | 4294901760 : (context->gpr[9] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_1010_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[10] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[10], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[2] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_1010_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[10] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[10], context);
	context->gpr[2] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_1010_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[10] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[10], context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_1010_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[2] = context->gpr[10];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_1010_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[10] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[10], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[2] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[10] = 1 + context->gpr[10];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_1010_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[10] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[10], context);
	context->gpr[2] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[10] = 2 + context->gpr[10];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_1010_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[10] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[10], context);
	context->gpr[2] = context->scratch1;
	context->gpr[10] = 4 + context->gpr[10];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_1010_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[2] = ~context->gpr[10];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_1010_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[10] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[10] << 8;
	temp2 = 65280 & temp2;
	context->gpr[2] = context->gpr[10] & 4294901760;
	context->gpr[2] = temp1 | context->gpr[2];
	context->gpr[2] = temp2 | context->gpr[2];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_1010_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[10] >> 16;
	context->gpr[2] = context->gpr[10] << 16;
	context->gpr[2] = temp | context->gpr[2];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_1010_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[10]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[2] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_1010_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[2] = -context->gpr[10];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_1010_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[2] = context->gpr[10] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_1010_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[2] = context->gpr[10] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_1010_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[2] = (context->gpr[2] & ~65535) | ((context->gpr[10] & 255) & 128 ? (context->gpr[10] & 255) | 65280 : (context->gpr[10] & 255));
	context->gpr[2] = (context->gpr[2] & 65535) & 32768 ? (context->gpr[2] & 65535) | 4294901760 : (context->gpr[2] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_1010_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[2] = (context->gpr[10] & 65535) & 32768 ? (context->gpr[10] & 65535) | 4294901760 : (context->gpr[10] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_1011_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[11] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[11], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[2] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_1011_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[11] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[11], context);
	context->gpr[2] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_1011_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[11] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[11], context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_1011_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[2] = context->gpr[11];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_1011_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[11] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[11], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[2] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[11] = 1 + context->gpr[11];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_1011_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[11] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[11], context);
	context->gpr[2] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[11] = 2 + context->gpr[11];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_1011_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[11] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[11], context);
	context->gpr[2] = context->scratch1;
	context->gpr[11] = 4 + context->gpr[11];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_1011_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[2] = ~context->gpr[11];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_1011_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[11] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[11] << 8;
	temp2 = 65280 & temp2;
	context->gpr[2] = context->gpr[11] & 4294901760;
	context->gpr[2] = temp1 | context->gpr[2];
	context->gpr[2] = temp2 | context->gpr[2];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_1011_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[11] >> 16;
	context->gpr[2] = context->gpr[11] << 16;
	context->gpr[2] = temp | context->gpr[2];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_1011_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[11]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[2] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_1011_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[2] = -context->gpr[11];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_1011_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[2] = context->gpr[11] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_1011_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[2] = context->gpr[11] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_1011_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[2] = (context->gpr[2] & ~65535) | ((context->gpr[11] & 255) & 128 ? (context->gpr[11] & 255) | 65280 : (context->gpr[11] & 255));
	context->gpr[2] = (context->gpr[2] & 65535) & 32768 ? (context->gpr[2] & 65535) | 4294901760 : (context->gpr[2] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_1011_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[2] = (context->gpr[11] & 65535) & 32768 ? (context->gpr[11] & 65535) | 4294901760 : (context->gpr[11] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_1100_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[12] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[12], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[2] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_1100_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[12] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[12], context);
	context->gpr[2] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_1100_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[12] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[12], context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_1100_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[2] = context->gpr[12];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_1100_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[12] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[12], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[2] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[12] = 1 + context->gpr[12];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_1100_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[12] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[12], context);
	context->gpr[2] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[12] = 2 + context->gpr[12];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_1100_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[12] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[12], context);
	context->gpr[2] = context->scratch1;
	context->gpr[12] = 4 + context->gpr[12];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_1100_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[2] = ~context->gpr[12];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_1100_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[12] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[12] << 8;
	temp2 = 65280 & temp2;
	context->gpr[2] = context->gpr[12] & 4294901760;
	context->gpr[2] = temp1 | context->gpr[2];
	context->gpr[2] = temp2 | context->gpr[2];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_1100_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[12] >> 16;
	context->gpr[2] = context->gpr[12] << 16;
	context->gpr[2] = temp | context->gpr[2];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_1100_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[12]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[2] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_1100_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[2] = -context->gpr[12];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_1100_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[2] = context->gpr[12] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_1100_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[2] = context->gpr[12] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_1100_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[2] = (context->gpr[2] & ~65535) | ((context->gpr[12] & 255) & 128 ? (context->gpr[12] & 255) | 65280 : (context->gpr[12] & 255));
	context->gpr[2] = (context->gpr[2] & 65535) & 32768 ? (context->gpr[2] & 65535) | 4294901760 : (context->gpr[2] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_1100_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[2] = (context->gpr[12] & 65535) & 32768 ? (context->gpr[12] & 65535) | 4294901760 : (context->gpr[12] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_1101_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[13] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[13], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[2] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_1101_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[13] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[13], context);
	context->gpr[2] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_1101_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[13] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[13], context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_1101_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[2] = context->gpr[13];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_1101_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[13] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[13], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[2] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[13] = 1 + context->gpr[13];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_1101_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[13] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[13], context);
	context->gpr[2] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[13] = 2 + context->gpr[13];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_1101_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[13] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[13], context);
	context->gpr[2] = context->scratch1;
	context->gpr[13] = 4 + context->gpr[13];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_1101_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[2] = ~context->gpr[13];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_1101_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[13] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[13] << 8;
	temp2 = 65280 & temp2;
	context->gpr[2] = context->gpr[13] & 4294901760;
	context->gpr[2] = temp1 | context->gpr[2];
	context->gpr[2] = temp2 | context->gpr[2];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_1101_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[13] >> 16;
	context->gpr[2] = context->gpr[13] << 16;
	context->gpr[2] = temp | context->gpr[2];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_1101_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[13]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[2] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_1101_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[2] = -context->gpr[13];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_1101_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[2] = context->gpr[13] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_1101_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[2] = context->gpr[13] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_1101_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[2] = (context->gpr[2] & ~65535) | ((context->gpr[13] & 255) & 128 ? (context->gpr[13] & 255) | 65280 : (context->gpr[13] & 255));
	context->gpr[2] = (context->gpr[2] & 65535) & 32768 ? (context->gpr[2] & 65535) | 4294901760 : (context->gpr[2] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_1101_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[2] = (context->gpr[13] & 65535) & 32768 ? (context->gpr[13] & 65535) | 4294901760 : (context->gpr[13] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_1110_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[14] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[14], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[2] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_1110_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[14] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[14], context);
	context->gpr[2] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_1110_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[14] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[14], context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_1110_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[2] = context->gpr[14];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_1110_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[14] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[14], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[2] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[14] = 1 + context->gpr[14];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_1110_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[14] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[14], context);
	context->gpr[2] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[14] = 2 + context->gpr[14];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_1110_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[14] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[14], context);
	context->gpr[2] = context->scratch1;
	context->gpr[14] = 4 + context->gpr[14];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_1110_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[2] = ~context->gpr[14];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_1110_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[14] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[14] << 8;
	temp2 = 65280 & temp2;
	context->gpr[2] = context->gpr[14] & 4294901760;
	context->gpr[2] = temp1 | context->gpr[2];
	context->gpr[2] = temp2 | context->gpr[2];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_1110_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[14] >> 16;
	context->gpr[2] = context->gpr[14] << 16;
	context->gpr[2] = temp | context->gpr[2];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_1110_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[14]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[2] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_1110_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[2] = -context->gpr[14];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_1110_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[2] = context->gpr[14] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_1110_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[2] = context->gpr[14] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_1110_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[2] = (context->gpr[2] & ~65535) | ((context->gpr[14] & 255) & 128 ? (context->gpr[14] & 255) | 65280 : (context->gpr[14] & 255));
	context->gpr[2] = (context->gpr[2] & 65535) & 32768 ? (context->gpr[2] & 65535) | 4294901760 : (context->gpr[2] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_1110_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[2] = (context->gpr[14] & 65535) & 32768 ? (context->gpr[14] & 65535) | 4294901760 : (context->gpr[14] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_1111_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[15] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[15], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[2] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_1111_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[15] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[15], context);
	context->gpr[2] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_1111_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[15] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[15], context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_1111_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[2] = context->gpr[15];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_1111_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[15] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[15], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[2] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[15] = 1 + context->gpr[15];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_1111_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[15] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[15], context);
	context->gpr[2] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[15] = 2 + context->gpr[15];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_1111_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[15] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[15], context);
	context->gpr[2] = context->scratch1;
	context->gpr[15] = 4 + context->gpr[15];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_1111_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[2] = ~context->gpr[15];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_1111_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[15] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[15] << 8;
	temp2 = 65280 & temp2;
	context->gpr[2] = context->gpr[15] & 4294901760;
	context->gpr[2] = temp1 | context->gpr[2];
	context->gpr[2] = temp2 | context->gpr[2];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_1111_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[15] >> 16;
	context->gpr[2] = context->gpr[15] << 16;
	context->gpr[2] = temp | context->gpr[2];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_1111_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[15]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[2] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_1111_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[2] = -context->gpr[15];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_1111_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[2] = context->gpr[15] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_1111_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[2] = context->gpr[15] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_1111_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[2] = (context->gpr[2] & ~65535) | ((context->gpr[15] & 255) & 128 ? (context->gpr[15] & 255) | 65280 : (context->gpr[15] & 255));
	context->gpr[2] = (context->gpr[2] & 65535) & 32768 ? (context->gpr[2] & 65535) | 4294901760 : (context->gpr[2] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_1111_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[2] = (context->gpr[15] & 65535) & 32768 ? (context->gpr[15] & 65535) | 4294901760 : (context->gpr[15] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_0000_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[0] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[0], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[3] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_0000_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[0] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[0], context);
	context->gpr[3] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_0000_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[0] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[0], context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_0000_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[3] = context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_0000_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[0] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[0], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[3] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[0] = 1 + context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_0000_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[0] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[0], context);
	context->gpr[3] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[0] = 2 + context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_0000_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[0] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[0], context);
	context->gpr[3] = context->scratch1;
	context->gpr[0] = 4 + context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_0000_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[3] = ~context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_0000_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[0] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[0] << 8;
	temp2 = 65280 & temp2;
	context->gpr[3] = context->gpr[0] & 4294901760;
	context->gpr[3] = temp1 | context->gpr[3];
	context->gpr[3] = temp2 | context->gpr[3];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_0000_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[0] >> 16;
	context->gpr[3] = context->gpr[0] << 16;
	context->gpr[3] = temp | context->gpr[3];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_0000_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[0]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[3] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_0000_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[3] = -context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_0000_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[3] = context->gpr[0] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_0000_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[3] = context->gpr[0] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_0000_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[3] = (context->gpr[3] & ~65535) | ((context->gpr[0] & 255) & 128 ? (context->gpr[0] & 255) | 65280 : (context->gpr[0] & 255));
	context->gpr[3] = (context->gpr[3] & 65535) & 32768 ? (context->gpr[3] & 65535) | 4294901760 : (context->gpr[3] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_0000_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[3] = (context->gpr[0] & 65535) & 32768 ? (context->gpr[0] & 65535) | 4294901760 : (context->gpr[0] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_0001_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[1] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[1], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[3] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_0001_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[1] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[1], context);
	context->gpr[3] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_0001_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[1] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[1], context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_0001_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[3] = context->gpr[1];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_0001_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[1] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[1], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[3] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[1] = 1 + context->gpr[1];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_0001_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[1] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[1], context);
	context->gpr[3] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[1] = 2 + context->gpr[1];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_0001_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[1] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[1], context);
	context->gpr[3] = context->scratch1;
	context->gpr[1] = 4 + context->gpr[1];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_0001_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[3] = ~context->gpr[1];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_0001_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[1] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[1] << 8;
	temp2 = 65280 & temp2;
	context->gpr[3] = context->gpr[1] & 4294901760;
	context->gpr[3] = temp1 | context->gpr[3];
	context->gpr[3] = temp2 | context->gpr[3];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_0001_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[1] >> 16;
	context->gpr[3] = context->gpr[1] << 16;
	context->gpr[3] = temp | context->gpr[3];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_0001_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[1]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[3] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_0001_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[3] = -context->gpr[1];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_0001_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[3] = context->gpr[1] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_0001_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[3] = context->gpr[1] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_0001_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[3] = (context->gpr[3] & ~65535) | ((context->gpr[1] & 255) & 128 ? (context->gpr[1] & 255) | 65280 : (context->gpr[1] & 255));
	context->gpr[3] = (context->gpr[3] & 65535) & 32768 ? (context->gpr[3] & 65535) | 4294901760 : (context->gpr[3] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_0001_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[3] = (context->gpr[1] & 65535) & 32768 ? (context->gpr[1] & 65535) | 4294901760 : (context->gpr[1] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_0010_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[2] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[2], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[3] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_0010_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[2] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[2], context);
	context->gpr[3] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_0010_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[2] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[2], context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_0010_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[3] = context->gpr[2];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_0010_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[2] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[2], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[3] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[2] = 1 + context->gpr[2];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_0010_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[2] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[2], context);
	context->gpr[3] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[2] = 2 + context->gpr[2];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_0010_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[2] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[2], context);
	context->gpr[3] = context->scratch1;
	context->gpr[2] = 4 + context->gpr[2];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_0010_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[3] = ~context->gpr[2];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_0010_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[2] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[2] << 8;
	temp2 = 65280 & temp2;
	context->gpr[3] = context->gpr[2] & 4294901760;
	context->gpr[3] = temp1 | context->gpr[3];
	context->gpr[3] = temp2 | context->gpr[3];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_0010_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[2] >> 16;
	context->gpr[3] = context->gpr[2] << 16;
	context->gpr[3] = temp | context->gpr[3];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_0010_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[2]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[3] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_0010_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[3] = -context->gpr[2];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_0010_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[3] = context->gpr[2] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_0010_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[3] = context->gpr[2] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_0010_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[3] = (context->gpr[3] & ~65535) | ((context->gpr[2] & 255) & 128 ? (context->gpr[2] & 255) | 65280 : (context->gpr[2] & 255));
	context->gpr[3] = (context->gpr[3] & 65535) & 32768 ? (context->gpr[3] & 65535) | 4294901760 : (context->gpr[3] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_0010_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[3] = (context->gpr[2] & 65535) & 32768 ? (context->gpr[2] & 65535) | 4294901760 : (context->gpr[2] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_0011_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[3] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[3], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[3] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_0011_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[3] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[3], context);
	context->gpr[3] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_0011_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[3] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[3], context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_0011_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[3] = context->gpr[3];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_0011_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[3] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[3], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[3] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_0011_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[3] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[3], context);
	context->gpr[3] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_0011_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[3] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[3], context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_0011_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[3] = ~context->gpr[3];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_0011_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[3] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[3] << 8;
	temp2 = 65280 & temp2;
	context->gpr[3] = context->gpr[3] & 4294901760;
	context->gpr[3] = temp1 | context->gpr[3];
	context->gpr[3] = temp2 | context->gpr[3];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_0011_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[3] >> 16;
	context->gpr[3] = context->gpr[3] << 16;
	context->gpr[3] = temp | context->gpr[3];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_0011_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[3]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[3] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_0011_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[3] = -context->gpr[3];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_0011_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[3] = context->gpr[3] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_0011_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[3] = context->gpr[3] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_0011_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[3] = (context->gpr[3] & ~65535) | ((context->gpr[3] & 255) & 128 ? (context->gpr[3] & 255) | 65280 : (context->gpr[3] & 255));
	context->gpr[3] = (context->gpr[3] & 65535) & 32768 ? (context->gpr[3] & 65535) | 4294901760 : (context->gpr[3] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_0011_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[3] = (context->gpr[3] & 65535) & 32768 ? (context->gpr[3] & 65535) | 4294901760 : (context->gpr[3] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_0100_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[4] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[4], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[3] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_0100_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[4] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[4], context);
	context->gpr[3] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_0100_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[4] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[4], context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_0100_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[3] = context->gpr[4];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_0100_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[4] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[4], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[3] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[4] = 1 + context->gpr[4];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_0100_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[4] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[4], context);
	context->gpr[3] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[4] = 2 + context->gpr[4];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_0100_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[4] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[4], context);
	context->gpr[3] = context->scratch1;
	context->gpr[4] = 4 + context->gpr[4];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_0100_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[3] = ~context->gpr[4];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_0100_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[4] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[4] << 8;
	temp2 = 65280 & temp2;
	context->gpr[3] = context->gpr[4] & 4294901760;
	context->gpr[3] = temp1 | context->gpr[3];
	context->gpr[3] = temp2 | context->gpr[3];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_0100_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[4] >> 16;
	context->gpr[3] = context->gpr[4] << 16;
	context->gpr[3] = temp | context->gpr[3];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_0100_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[4]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[3] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_0100_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[3] = -context->gpr[4];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_0100_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[3] = context->gpr[4] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_0100_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[3] = context->gpr[4] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_0100_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[3] = (context->gpr[3] & ~65535) | ((context->gpr[4] & 255) & 128 ? (context->gpr[4] & 255) | 65280 : (context->gpr[4] & 255));
	context->gpr[3] = (context->gpr[3] & 65535) & 32768 ? (context->gpr[3] & 65535) | 4294901760 : (context->gpr[3] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_0100_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[3] = (context->gpr[4] & 65535) & 32768 ? (context->gpr[4] & 65535) | 4294901760 : (context->gpr[4] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_0101_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[5] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[5], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[3] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_0101_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[5] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[5], context);
	context->gpr[3] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_0101_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[5] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[5], context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_0101_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[3] = context->gpr[5];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_0101_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[5] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[5], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[3] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[5] = 1 + context->gpr[5];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_0101_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[5] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[5], context);
	context->gpr[3] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[5] = 2 + context->gpr[5];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_0101_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[5] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[5], context);
	context->gpr[3] = context->scratch1;
	context->gpr[5] = 4 + context->gpr[5];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_0101_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[3] = ~context->gpr[5];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_0101_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[5] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[5] << 8;
	temp2 = 65280 & temp2;
	context->gpr[3] = context->gpr[5] & 4294901760;
	context->gpr[3] = temp1 | context->gpr[3];
	context->gpr[3] = temp2 | context->gpr[3];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_0101_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[5] >> 16;
	context->gpr[3] = context->gpr[5] << 16;
	context->gpr[3] = temp | context->gpr[3];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_0101_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[5]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[3] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_0101_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[3] = -context->gpr[5];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_0101_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[3] = context->gpr[5] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_0101_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[3] = context->gpr[5] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_0101_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[3] = (context->gpr[3] & ~65535) | ((context->gpr[5] & 255) & 128 ? (context->gpr[5] & 255) | 65280 : (context->gpr[5] & 255));
	context->gpr[3] = (context->gpr[3] & 65535) & 32768 ? (context->gpr[3] & 65535) | 4294901760 : (context->gpr[3] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_0101_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[3] = (context->gpr[5] & 65535) & 32768 ? (context->gpr[5] & 65535) | 4294901760 : (context->gpr[5] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_0110_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[6] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[6], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[3] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_0110_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[6] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[6], context);
	context->gpr[3] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_0110_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[6] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[6], context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_0110_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[3] = context->gpr[6];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_0110_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[6] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[6], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[3] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[6] = 1 + context->gpr[6];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_0110_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[6] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[6], context);
	context->gpr[3] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[6] = 2 + context->gpr[6];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_0110_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[6] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[6], context);
	context->gpr[3] = context->scratch1;
	context->gpr[6] = 4 + context->gpr[6];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_0110_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[3] = ~context->gpr[6];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_0110_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[6] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[6] << 8;
	temp2 = 65280 & temp2;
	context->gpr[3] = context->gpr[6] & 4294901760;
	context->gpr[3] = temp1 | context->gpr[3];
	context->gpr[3] = temp2 | context->gpr[3];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_0110_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[6] >> 16;
	context->gpr[3] = context->gpr[6] << 16;
	context->gpr[3] = temp | context->gpr[3];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_0110_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[6]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[3] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_0110_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[3] = -context->gpr[6];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_0110_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[3] = context->gpr[6] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_0110_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[3] = context->gpr[6] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_0110_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[3] = (context->gpr[3] & ~65535) | ((context->gpr[6] & 255) & 128 ? (context->gpr[6] & 255) | 65280 : (context->gpr[6] & 255));
	context->gpr[3] = (context->gpr[3] & 65535) & 32768 ? (context->gpr[3] & 65535) | 4294901760 : (context->gpr[3] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_0110_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[3] = (context->gpr[6] & 65535) & 32768 ? (context->gpr[6] & 65535) | 4294901760 : (context->gpr[6] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_0111_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[7] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[7], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[3] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_0111_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[7] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[7], context);
	context->gpr[3] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_0111_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[7] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[7], context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_0111_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[3] = context->gpr[7];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_0111_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[7] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[7], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[3] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[7] = 1 + context->gpr[7];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_0111_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[7] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[7], context);
	context->gpr[3] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[7] = 2 + context->gpr[7];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_0111_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[7] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[7], context);
	context->gpr[3] = context->scratch1;
	context->gpr[7] = 4 + context->gpr[7];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_0111_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[3] = ~context->gpr[7];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_0111_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[7] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[7] << 8;
	temp2 = 65280 & temp2;
	context->gpr[3] = context->gpr[7] & 4294901760;
	context->gpr[3] = temp1 | context->gpr[3];
	context->gpr[3] = temp2 | context->gpr[3];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_0111_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[7] >> 16;
	context->gpr[3] = context->gpr[7] << 16;
	context->gpr[3] = temp | context->gpr[3];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_0111_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[7]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[3] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_0111_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[3] = -context->gpr[7];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_0111_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[3] = context->gpr[7] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_0111_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[3] = context->gpr[7] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_0111_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[3] = (context->gpr[3] & ~65535) | ((context->gpr[7] & 255) & 128 ? (context->gpr[7] & 255) | 65280 : (context->gpr[7] & 255));
	context->gpr[3] = (context->gpr[3] & 65535) & 32768 ? (context->gpr[3] & 65535) | 4294901760 : (context->gpr[3] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_0111_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[3] = (context->gpr[7] & 65535) & 32768 ? (context->gpr[7] & 65535) | 4294901760 : (context->gpr[7] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_1000_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[8] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[8], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[3] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_1000_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[8] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[8], context);
	context->gpr[3] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_1000_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[8] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[8], context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_1000_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[3] = context->gpr[8];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_1000_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[8] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[8], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[3] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[8] = 1 + context->gpr[8];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_1000_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[8] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[8], context);
	context->gpr[3] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[8] = 2 + context->gpr[8];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_1000_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[8] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[8], context);
	context->gpr[3] = context->scratch1;
	context->gpr[8] = 4 + context->gpr[8];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_1000_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[3] = ~context->gpr[8];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_1000_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[8] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[8] << 8;
	temp2 = 65280 & temp2;
	context->gpr[3] = context->gpr[8] & 4294901760;
	context->gpr[3] = temp1 | context->gpr[3];
	context->gpr[3] = temp2 | context->gpr[3];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_1000_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[8] >> 16;
	context->gpr[3] = context->gpr[8] << 16;
	context->gpr[3] = temp | context->gpr[3];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_1000_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[8]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[3] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_1000_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[3] = -context->gpr[8];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_1000_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[3] = context->gpr[8] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_1000_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[3] = context->gpr[8] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_1000_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[3] = (context->gpr[3] & ~65535) | ((context->gpr[8] & 255) & 128 ? (context->gpr[8] & 255) | 65280 : (context->gpr[8] & 255));
	context->gpr[3] = (context->gpr[3] & 65535) & 32768 ? (context->gpr[3] & 65535) | 4294901760 : (context->gpr[3] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_1000_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[3] = (context->gpr[8] & 65535) & 32768 ? (context->gpr[8] & 65535) | 4294901760 : (context->gpr[8] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_1001_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[9] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[9], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[3] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_1001_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[9] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[9], context);
	context->gpr[3] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_1001_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[9] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[9], context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_1001_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[3] = context->gpr[9];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_1001_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[9] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[9], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[3] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[9] = 1 + context->gpr[9];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_1001_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[9] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[9], context);
	context->gpr[3] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[9] = 2 + context->gpr[9];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_1001_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[9] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[9], context);
	context->gpr[3] = context->scratch1;
	context->gpr[9] = 4 + context->gpr[9];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_1001_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[3] = ~context->gpr[9];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_1001_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[9] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[9] << 8;
	temp2 = 65280 & temp2;
	context->gpr[3] = context->gpr[9] & 4294901760;
	context->gpr[3] = temp1 | context->gpr[3];
	context->gpr[3] = temp2 | context->gpr[3];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_1001_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[9] >> 16;
	context->gpr[3] = context->gpr[9] << 16;
	context->gpr[3] = temp | context->gpr[3];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_1001_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[9]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[3] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_1001_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[3] = -context->gpr[9];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_1001_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[3] = context->gpr[9] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_1001_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[3] = context->gpr[9] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_1001_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[3] = (context->gpr[3] & ~65535) | ((context->gpr[9] & 255) & 128 ? (context->gpr[9] & 255) | 65280 : (context->gpr[9] & 255));
	context->gpr[3] = (context->gpr[3] & 65535) & 32768 ? (context->gpr[3] & 65535) | 4294901760 : (context->gpr[3] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_1001_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[3] = (context->gpr[9] & 65535) & 32768 ? (context->gpr[9] & 65535) | 4294901760 : (context->gpr[9] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_1010_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[10] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[10], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[3] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_1010_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[10] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[10], context);
	context->gpr[3] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_1010_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[10] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[10], context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_1010_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[3] = context->gpr[10];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_1010_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[10] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[10], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[3] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[10] = 1 + context->gpr[10];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_1010_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[10] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[10], context);
	context->gpr[3] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[10] = 2 + context->gpr[10];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_1010_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[10] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[10], context);
	context->gpr[3] = context->scratch1;
	context->gpr[10] = 4 + context->gpr[10];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_1010_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[3] = ~context->gpr[10];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_1010_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[10] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[10] << 8;
	temp2 = 65280 & temp2;
	context->gpr[3] = context->gpr[10] & 4294901760;
	context->gpr[3] = temp1 | context->gpr[3];
	context->gpr[3] = temp2 | context->gpr[3];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_1010_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[10] >> 16;
	context->gpr[3] = context->gpr[10] << 16;
	context->gpr[3] = temp | context->gpr[3];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_1010_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[10]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[3] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_1010_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[3] = -context->gpr[10];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_1010_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[3] = context->gpr[10] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_1010_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[3] = context->gpr[10] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_1010_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[3] = (context->gpr[3] & ~65535) | ((context->gpr[10] & 255) & 128 ? (context->gpr[10] & 255) | 65280 : (context->gpr[10] & 255));
	context->gpr[3] = (context->gpr[3] & 65535) & 32768 ? (context->gpr[3] & 65535) | 4294901760 : (context->gpr[3] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_1010_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[3] = (context->gpr[10] & 65535) & 32768 ? (context->gpr[10] & 65535) | 4294901760 : (context->gpr[10] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_1011_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[11] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[11], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[3] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_1011_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[11] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[11], context);
	context->gpr[3] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_1011_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[11] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[11], context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_1011_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[3] = context->gpr[11];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_1011_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[11] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[11], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[3] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[11] = 1 + context->gpr[11];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_1011_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[11] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[11], context);
	context->gpr[3] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[11] = 2 + context->gpr[11];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_1011_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[11] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[11], context);
	context->gpr[3] = context->scratch1;
	context->gpr[11] = 4 + context->gpr[11];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_1011_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[3] = ~context->gpr[11];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_1011_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[11] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[11] << 8;
	temp2 = 65280 & temp2;
	context->gpr[3] = context->gpr[11] & 4294901760;
	context->gpr[3] = temp1 | context->gpr[3];
	context->gpr[3] = temp2 | context->gpr[3];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_1011_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[11] >> 16;
	context->gpr[3] = context->gpr[11] << 16;
	context->gpr[3] = temp | context->gpr[3];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_1011_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[11]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[3] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_1011_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[3] = -context->gpr[11];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_1011_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[3] = context->gpr[11] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_1011_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[3] = context->gpr[11] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_1011_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[3] = (context->gpr[3] & ~65535) | ((context->gpr[11] & 255) & 128 ? (context->gpr[11] & 255) | 65280 : (context->gpr[11] & 255));
	context->gpr[3] = (context->gpr[3] & 65535) & 32768 ? (context->gpr[3] & 65535) | 4294901760 : (context->gpr[3] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_1011_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[3] = (context->gpr[11] & 65535) & 32768 ? (context->gpr[11] & 65535) | 4294901760 : (context->gpr[11] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_1100_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[12] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[12], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[3] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_1100_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[12] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[12], context);
	context->gpr[3] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_1100_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[12] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[12], context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_1100_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[3] = context->gpr[12];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_1100_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[12] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[12], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[3] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[12] = 1 + context->gpr[12];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_1100_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[12] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[12], context);
	context->gpr[3] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[12] = 2 + context->gpr[12];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_1100_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[12] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[12], context);
	context->gpr[3] = context->scratch1;
	context->gpr[12] = 4 + context->gpr[12];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_1100_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[3] = ~context->gpr[12];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_1100_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[12] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[12] << 8;
	temp2 = 65280 & temp2;
	context->gpr[3] = context->gpr[12] & 4294901760;
	context->gpr[3] = temp1 | context->gpr[3];
	context->gpr[3] = temp2 | context->gpr[3];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_1100_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[12] >> 16;
	context->gpr[3] = context->gpr[12] << 16;
	context->gpr[3] = temp | context->gpr[3];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_1100_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[12]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[3] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_1100_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[3] = -context->gpr[12];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_1100_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[3] = context->gpr[12] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_1100_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[3] = context->gpr[12] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_1100_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[3] = (context->gpr[3] & ~65535) | ((context->gpr[12] & 255) & 128 ? (context->gpr[12] & 255) | 65280 : (context->gpr[12] & 255));
	context->gpr[3] = (context->gpr[3] & 65535) & 32768 ? (context->gpr[3] & 65535) | 4294901760 : (context->gpr[3] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_1100_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[3] = (context->gpr[12] & 65535) & 32768 ? (context->gpr[12] & 65535) | 4294901760 : (context->gpr[12] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_1101_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[13] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[13], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[3] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_1101_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[13] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[13], context);
	context->gpr[3] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_1101_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[13] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[13], context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_1101_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[3] = context->gpr[13];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_1101_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[13] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[13], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[3] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[13] = 1 + context->gpr[13];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_1101_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[13] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[13], context);
	context->gpr[3] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[13] = 2 + context->gpr[13];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_1101_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[13] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[13], context);
	context->gpr[3] = context->scratch1;
	context->gpr[13] = 4 + context->gpr[13];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_1101_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[3] = ~context->gpr[13];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_1101_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[13] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[13] << 8;
	temp2 = 65280 & temp2;
	context->gpr[3] = context->gpr[13] & 4294901760;
	context->gpr[3] = temp1 | context->gpr[3];
	context->gpr[3] = temp2 | context->gpr[3];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_1101_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[13] >> 16;
	context->gpr[3] = context->gpr[13] << 16;
	context->gpr[3] = temp | context->gpr[3];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_1101_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[13]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[3] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_1101_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[3] = -context->gpr[13];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_1101_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[3] = context->gpr[13] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_1101_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[3] = context->gpr[13] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_1101_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[3] = (context->gpr[3] & ~65535) | ((context->gpr[13] & 255) & 128 ? (context->gpr[13] & 255) | 65280 : (context->gpr[13] & 255));
	context->gpr[3] = (context->gpr[3] & 65535) & 32768 ? (context->gpr[3] & 65535) | 4294901760 : (context->gpr[3] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_1101_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[3] = (context->gpr[13] & 65535) & 32768 ? (context->gpr[13] & 65535) | 4294901760 : (context->gpr[13] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_1110_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[14] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[14], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[3] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_1110_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[14] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[14], context);
	context->gpr[3] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_1110_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[14] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[14], context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_1110_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[3] = context->gpr[14];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_1110_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[14] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[14], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[3] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[14] = 1 + context->gpr[14];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_1110_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[14] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[14], context);
	context->gpr[3] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[14] = 2 + context->gpr[14];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_1110_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[14] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[14], context);
	context->gpr[3] = context->scratch1;
	context->gpr[14] = 4 + context->gpr[14];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_1110_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[3] = ~context->gpr[14];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_1110_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[14] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[14] << 8;
	temp2 = 65280 & temp2;
	context->gpr[3] = context->gpr[14] & 4294901760;
	context->gpr[3] = temp1 | context->gpr[3];
	context->gpr[3] = temp2 | context->gpr[3];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_1110_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[14] >> 16;
	context->gpr[3] = context->gpr[14] << 16;
	context->gpr[3] = temp | context->gpr[3];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_1110_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[14]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[3] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_1110_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[3] = -context->gpr[14];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_1110_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[3] = context->gpr[14] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_1110_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[3] = context->gpr[14] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_1110_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[3] = (context->gpr[3] & ~65535) | ((context->gpr[14] & 255) & 128 ? (context->gpr[14] & 255) | 65280 : (context->gpr[14] & 255));
	context->gpr[3] = (context->gpr[3] & 65535) & 32768 ? (context->gpr[3] & 65535) | 4294901760 : (context->gpr[3] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_1110_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[3] = (context->gpr[14] & 65535) & 32768 ? (context->gpr[14] & 65535) | 4294901760 : (context->gpr[14] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_1111_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[15] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[15], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[3] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_1111_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[15] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[15], context);
	context->gpr[3] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_1111_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[15] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[15], context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_1111_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[3] = context->gpr[15];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_1111_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[15] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[15], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[3] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[15] = 1 + context->gpr[15];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_1111_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[15] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[15], context);
	context->gpr[3] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[15] = 2 + context->gpr[15];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_1111_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[15] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[15], context);
	context->gpr[3] = context->scratch1;
	context->gpr[15] = 4 + context->gpr[15];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_1111_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[3] = ~context->gpr[15];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_1111_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[15] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[15] << 8;
	temp2 = 65280 & temp2;
	context->gpr[3] = context->gpr[15] & 4294901760;
	context->gpr[3] = temp1 | context->gpr[3];
	context->gpr[3] = temp2 | context->gpr[3];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_1111_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[15] >> 16;
	context->gpr[3] = context->gpr[15] << 16;
	context->gpr[3] = temp | context->gpr[3];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_1111_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[15]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[3] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_1111_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[3] = -context->gpr[15];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_1111_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[3] = context->gpr[15] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_1111_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[3] = context->gpr[15] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_1111_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[3] = (context->gpr[3] & ~65535) | ((context->gpr[15] & 255) & 128 ? (context->gpr[15] & 255) | 65280 : (context->gpr[15] & 255));
	context->gpr[3] = (context->gpr[3] & 65535) & 32768 ? (context->gpr[3] & 65535) | 4294901760 : (context->gpr[3] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_1111_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[3] = (context->gpr[15] & 65535) & 32768 ? (context->gpr[15] & 65535) | 4294901760 : (context->gpr[15] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_0000_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[0] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[0], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[4] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_0000_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[0] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[0], context);
	context->gpr[4] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_0000_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[0] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[0], context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_0000_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[4] = context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_0000_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[0] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[0], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[4] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[0] = 1 + context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_0000_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[0] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[0], context);
	context->gpr[4] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[0] = 2 + context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_0000_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[0] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[0], context);
	context->gpr[4] = context->scratch1;
	context->gpr[0] = 4 + context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_0000_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[4] = ~context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_0000_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[0] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[0] << 8;
	temp2 = 65280 & temp2;
	context->gpr[4] = context->gpr[0] & 4294901760;
	context->gpr[4] = temp1 | context->gpr[4];
	context->gpr[4] = temp2 | context->gpr[4];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_0000_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[0] >> 16;
	context->gpr[4] = context->gpr[0] << 16;
	context->gpr[4] = temp | context->gpr[4];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_0000_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[0]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[4] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_0000_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[4] = -context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_0000_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[4] = context->gpr[0] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_0000_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[4] = context->gpr[0] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_0000_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[4] = (context->gpr[4] & ~65535) | ((context->gpr[0] & 255) & 128 ? (context->gpr[0] & 255) | 65280 : (context->gpr[0] & 255));
	context->gpr[4] = (context->gpr[4] & 65535) & 32768 ? (context->gpr[4] & 65535) | 4294901760 : (context->gpr[4] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_0000_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[4] = (context->gpr[0] & 65535) & 32768 ? (context->gpr[0] & 65535) | 4294901760 : (context->gpr[0] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_0001_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[1] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[1], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[4] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_0001_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[1] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[1], context);
	context->gpr[4] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_0001_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[1] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[1], context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_0001_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[4] = context->gpr[1];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_0001_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[1] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[1], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[4] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[1] = 1 + context->gpr[1];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_0001_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[1] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[1], context);
	context->gpr[4] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[1] = 2 + context->gpr[1];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_0001_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[1] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[1], context);
	context->gpr[4] = context->scratch1;
	context->gpr[1] = 4 + context->gpr[1];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_0001_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[4] = ~context->gpr[1];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_0001_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[1] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[1] << 8;
	temp2 = 65280 & temp2;
	context->gpr[4] = context->gpr[1] & 4294901760;
	context->gpr[4] = temp1 | context->gpr[4];
	context->gpr[4] = temp2 | context->gpr[4];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_0001_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[1] >> 16;
	context->gpr[4] = context->gpr[1] << 16;
	context->gpr[4] = temp | context->gpr[4];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_0001_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[1]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[4] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_0001_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[4] = -context->gpr[1];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_0001_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[4] = context->gpr[1] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_0001_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[4] = context->gpr[1] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_0001_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[4] = (context->gpr[4] & ~65535) | ((context->gpr[1] & 255) & 128 ? (context->gpr[1] & 255) | 65280 : (context->gpr[1] & 255));
	context->gpr[4] = (context->gpr[4] & 65535) & 32768 ? (context->gpr[4] & 65535) | 4294901760 : (context->gpr[4] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_0001_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[4] = (context->gpr[1] & 65535) & 32768 ? (context->gpr[1] & 65535) | 4294901760 : (context->gpr[1] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_0010_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[2] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[2], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[4] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_0010_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[2] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[2], context);
	context->gpr[4] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_0010_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[2] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[2], context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_0010_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[4] = context->gpr[2];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_0010_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[2] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[2], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[4] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[2] = 1 + context->gpr[2];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_0010_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[2] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[2], context);
	context->gpr[4] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[2] = 2 + context->gpr[2];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_0010_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[2] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[2], context);
	context->gpr[4] = context->scratch1;
	context->gpr[2] = 4 + context->gpr[2];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_0010_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[4] = ~context->gpr[2];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_0010_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[2] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[2] << 8;
	temp2 = 65280 & temp2;
	context->gpr[4] = context->gpr[2] & 4294901760;
	context->gpr[4] = temp1 | context->gpr[4];
	context->gpr[4] = temp2 | context->gpr[4];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_0010_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[2] >> 16;
	context->gpr[4] = context->gpr[2] << 16;
	context->gpr[4] = temp | context->gpr[4];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_0010_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[2]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[4] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_0010_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[4] = -context->gpr[2];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_0010_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[4] = context->gpr[2] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_0010_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[4] = context->gpr[2] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_0010_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[4] = (context->gpr[4] & ~65535) | ((context->gpr[2] & 255) & 128 ? (context->gpr[2] & 255) | 65280 : (context->gpr[2] & 255));
	context->gpr[4] = (context->gpr[4] & 65535) & 32768 ? (context->gpr[4] & 65535) | 4294901760 : (context->gpr[4] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_0010_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[4] = (context->gpr[2] & 65535) & 32768 ? (context->gpr[2] & 65535) | 4294901760 : (context->gpr[2] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_0011_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[3] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[3], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[4] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_0011_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[3] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[3], context);
	context->gpr[4] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_0011_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[3] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[3], context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_0011_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[4] = context->gpr[3];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_0011_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[3] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[3], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[4] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[3] = 1 + context->gpr[3];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_0011_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[3] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[3], context);
	context->gpr[4] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[3] = 2 + context->gpr[3];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_0011_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[3] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[3], context);
	context->gpr[4] = context->scratch1;
	context->gpr[3] = 4 + context->gpr[3];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_0011_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[4] = ~context->gpr[3];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_0011_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[3] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[3] << 8;
	temp2 = 65280 & temp2;
	context->gpr[4] = context->gpr[3] & 4294901760;
	context->gpr[4] = temp1 | context->gpr[4];
	context->gpr[4] = temp2 | context->gpr[4];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_0011_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[3] >> 16;
	context->gpr[4] = context->gpr[3] << 16;
	context->gpr[4] = temp | context->gpr[4];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_0011_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[3]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[4] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_0011_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[4] = -context->gpr[3];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_0011_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[4] = context->gpr[3] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_0011_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[4] = context->gpr[3] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_0011_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[4] = (context->gpr[4] & ~65535) | ((context->gpr[3] & 255) & 128 ? (context->gpr[3] & 255) | 65280 : (context->gpr[3] & 255));
	context->gpr[4] = (context->gpr[4] & 65535) & 32768 ? (context->gpr[4] & 65535) | 4294901760 : (context->gpr[4] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_0011_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[4] = (context->gpr[3] & 65535) & 32768 ? (context->gpr[3] & 65535) | 4294901760 : (context->gpr[3] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_0100_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[4] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[4], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[4] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_0100_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[4] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[4], context);
	context->gpr[4] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_0100_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[4] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[4], context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_0100_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[4] = context->gpr[4];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_0100_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[4] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[4], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[4] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_0100_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[4] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[4], context);
	context->gpr[4] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_0100_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[4] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[4], context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_0100_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[4] = ~context->gpr[4];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_0100_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[4] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[4] << 8;
	temp2 = 65280 & temp2;
	context->gpr[4] = context->gpr[4] & 4294901760;
	context->gpr[4] = temp1 | context->gpr[4];
	context->gpr[4] = temp2 | context->gpr[4];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_0100_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[4] >> 16;
	context->gpr[4] = context->gpr[4] << 16;
	context->gpr[4] = temp | context->gpr[4];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_0100_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[4]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[4] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_0100_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[4] = -context->gpr[4];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_0100_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[4] = context->gpr[4] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_0100_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[4] = context->gpr[4] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_0100_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[4] = (context->gpr[4] & ~65535) | ((context->gpr[4] & 255) & 128 ? (context->gpr[4] & 255) | 65280 : (context->gpr[4] & 255));
	context->gpr[4] = (context->gpr[4] & 65535) & 32768 ? (context->gpr[4] & 65535) | 4294901760 : (context->gpr[4] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_0100_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[4] = (context->gpr[4] & 65535) & 32768 ? (context->gpr[4] & 65535) | 4294901760 : (context->gpr[4] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_0101_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[5] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[5], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[4] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_0101_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[5] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[5], context);
	context->gpr[4] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_0101_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[5] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[5], context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_0101_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[4] = context->gpr[5];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_0101_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[5] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[5], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[4] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[5] = 1 + context->gpr[5];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_0101_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[5] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[5], context);
	context->gpr[4] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[5] = 2 + context->gpr[5];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_0101_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[5] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[5], context);
	context->gpr[4] = context->scratch1;
	context->gpr[5] = 4 + context->gpr[5];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_0101_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[4] = ~context->gpr[5];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_0101_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[5] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[5] << 8;
	temp2 = 65280 & temp2;
	context->gpr[4] = context->gpr[5] & 4294901760;
	context->gpr[4] = temp1 | context->gpr[4];
	context->gpr[4] = temp2 | context->gpr[4];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_0101_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[5] >> 16;
	context->gpr[4] = context->gpr[5] << 16;
	context->gpr[4] = temp | context->gpr[4];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_0101_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[5]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[4] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_0101_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[4] = -context->gpr[5];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_0101_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[4] = context->gpr[5] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_0101_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[4] = context->gpr[5] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_0101_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[4] = (context->gpr[4] & ~65535) | ((context->gpr[5] & 255) & 128 ? (context->gpr[5] & 255) | 65280 : (context->gpr[5] & 255));
	context->gpr[4] = (context->gpr[4] & 65535) & 32768 ? (context->gpr[4] & 65535) | 4294901760 : (context->gpr[4] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_0101_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[4] = (context->gpr[5] & 65535) & 32768 ? (context->gpr[5] & 65535) | 4294901760 : (context->gpr[5] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_0110_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[6] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[6], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[4] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_0110_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[6] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[6], context);
	context->gpr[4] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_0110_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[6] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[6], context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_0110_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[4] = context->gpr[6];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_0110_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[6] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[6], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[4] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[6] = 1 + context->gpr[6];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_0110_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[6] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[6], context);
	context->gpr[4] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[6] = 2 + context->gpr[6];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_0110_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[6] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[6], context);
	context->gpr[4] = context->scratch1;
	context->gpr[6] = 4 + context->gpr[6];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_0110_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[4] = ~context->gpr[6];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_0110_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[6] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[6] << 8;
	temp2 = 65280 & temp2;
	context->gpr[4] = context->gpr[6] & 4294901760;
	context->gpr[4] = temp1 | context->gpr[4];
	context->gpr[4] = temp2 | context->gpr[4];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_0110_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[6] >> 16;
	context->gpr[4] = context->gpr[6] << 16;
	context->gpr[4] = temp | context->gpr[4];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_0110_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[6]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[4] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_0110_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[4] = -context->gpr[6];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_0110_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[4] = context->gpr[6] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_0110_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[4] = context->gpr[6] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_0110_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[4] = (context->gpr[4] & ~65535) | ((context->gpr[6] & 255) & 128 ? (context->gpr[6] & 255) | 65280 : (context->gpr[6] & 255));
	context->gpr[4] = (context->gpr[4] & 65535) & 32768 ? (context->gpr[4] & 65535) | 4294901760 : (context->gpr[4] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_0110_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[4] = (context->gpr[6] & 65535) & 32768 ? (context->gpr[6] & 65535) | 4294901760 : (context->gpr[6] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_0111_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[7] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[7], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[4] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_0111_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[7] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[7], context);
	context->gpr[4] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_0111_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[7] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[7], context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_0111_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[4] = context->gpr[7];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_0111_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[7] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[7], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[4] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[7] = 1 + context->gpr[7];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_0111_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[7] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[7], context);
	context->gpr[4] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[7] = 2 + context->gpr[7];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_0111_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[7] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[7], context);
	context->gpr[4] = context->scratch1;
	context->gpr[7] = 4 + context->gpr[7];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_0111_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[4] = ~context->gpr[7];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_0111_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[7] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[7] << 8;
	temp2 = 65280 & temp2;
	context->gpr[4] = context->gpr[7] & 4294901760;
	context->gpr[4] = temp1 | context->gpr[4];
	context->gpr[4] = temp2 | context->gpr[4];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_0111_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[7] >> 16;
	context->gpr[4] = context->gpr[7] << 16;
	context->gpr[4] = temp | context->gpr[4];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_0111_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[7]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[4] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_0111_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[4] = -context->gpr[7];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_0111_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[4] = context->gpr[7] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_0111_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[4] = context->gpr[7] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_0111_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[4] = (context->gpr[4] & ~65535) | ((context->gpr[7] & 255) & 128 ? (context->gpr[7] & 255) | 65280 : (context->gpr[7] & 255));
	context->gpr[4] = (context->gpr[4] & 65535) & 32768 ? (context->gpr[4] & 65535) | 4294901760 : (context->gpr[4] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_0111_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[4] = (context->gpr[7] & 65535) & 32768 ? (context->gpr[7] & 65535) | 4294901760 : (context->gpr[7] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_1000_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[8] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[8], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[4] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_1000_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[8] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[8], context);
	context->gpr[4] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_1000_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[8] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[8], context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_1000_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[4] = context->gpr[8];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_1000_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[8] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[8], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[4] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[8] = 1 + context->gpr[8];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_1000_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[8] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[8], context);
	context->gpr[4] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[8] = 2 + context->gpr[8];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_1000_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[8] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[8], context);
	context->gpr[4] = context->scratch1;
	context->gpr[8] = 4 + context->gpr[8];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_1000_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[4] = ~context->gpr[8];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_1000_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[8] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[8] << 8;
	temp2 = 65280 & temp2;
	context->gpr[4] = context->gpr[8] & 4294901760;
	context->gpr[4] = temp1 | context->gpr[4];
	context->gpr[4] = temp2 | context->gpr[4];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_1000_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[8] >> 16;
	context->gpr[4] = context->gpr[8] << 16;
	context->gpr[4] = temp | context->gpr[4];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_1000_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[8]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[4] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_1000_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[4] = -context->gpr[8];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_1000_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[4] = context->gpr[8] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_1000_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[4] = context->gpr[8] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_1000_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[4] = (context->gpr[4] & ~65535) | ((context->gpr[8] & 255) & 128 ? (context->gpr[8] & 255) | 65280 : (context->gpr[8] & 255));
	context->gpr[4] = (context->gpr[4] & 65535) & 32768 ? (context->gpr[4] & 65535) | 4294901760 : (context->gpr[4] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_1000_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[4] = (context->gpr[8] & 65535) & 32768 ? (context->gpr[8] & 65535) | 4294901760 : (context->gpr[8] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_1001_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[9] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[9], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[4] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_1001_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[9] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[9], context);
	context->gpr[4] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_1001_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[9] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[9], context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_1001_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[4] = context->gpr[9];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_1001_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[9] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[9], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[4] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[9] = 1 + context->gpr[9];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_1001_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[9] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[9], context);
	context->gpr[4] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[9] = 2 + context->gpr[9];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_1001_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[9] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[9], context);
	context->gpr[4] = context->scratch1;
	context->gpr[9] = 4 + context->gpr[9];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_1001_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[4] = ~context->gpr[9];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_1001_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[9] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[9] << 8;
	temp2 = 65280 & temp2;
	context->gpr[4] = context->gpr[9] & 4294901760;
	context->gpr[4] = temp1 | context->gpr[4];
	context->gpr[4] = temp2 | context->gpr[4];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_1001_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[9] >> 16;
	context->gpr[4] = context->gpr[9] << 16;
	context->gpr[4] = temp | context->gpr[4];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_1001_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[9]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[4] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_1001_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[4] = -context->gpr[9];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_1001_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[4] = context->gpr[9] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_1001_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[4] = context->gpr[9] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_1001_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[4] = (context->gpr[4] & ~65535) | ((context->gpr[9] & 255) & 128 ? (context->gpr[9] & 255) | 65280 : (context->gpr[9] & 255));
	context->gpr[4] = (context->gpr[4] & 65535) & 32768 ? (context->gpr[4] & 65535) | 4294901760 : (context->gpr[4] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_1001_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[4] = (context->gpr[9] & 65535) & 32768 ? (context->gpr[9] & 65535) | 4294901760 : (context->gpr[9] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_1010_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[10] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[10], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[4] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_1010_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[10] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[10], context);
	context->gpr[4] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_1010_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[10] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[10], context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_1010_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[4] = context->gpr[10];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_1010_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[10] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[10], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[4] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[10] = 1 + context->gpr[10];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_1010_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[10] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[10], context);
	context->gpr[4] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[10] = 2 + context->gpr[10];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_1010_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[10] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[10], context);
	context->gpr[4] = context->scratch1;
	context->gpr[10] = 4 + context->gpr[10];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_1010_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[4] = ~context->gpr[10];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_1010_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[10] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[10] << 8;
	temp2 = 65280 & temp2;
	context->gpr[4] = context->gpr[10] & 4294901760;
	context->gpr[4] = temp1 | context->gpr[4];
	context->gpr[4] = temp2 | context->gpr[4];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_1010_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[10] >> 16;
	context->gpr[4] = context->gpr[10] << 16;
	context->gpr[4] = temp | context->gpr[4];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_1010_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[10]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[4] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_1010_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[4] = -context->gpr[10];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_1010_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[4] = context->gpr[10] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_1010_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[4] = context->gpr[10] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_1010_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[4] = (context->gpr[4] & ~65535) | ((context->gpr[10] & 255) & 128 ? (context->gpr[10] & 255) | 65280 : (context->gpr[10] & 255));
	context->gpr[4] = (context->gpr[4] & 65535) & 32768 ? (context->gpr[4] & 65535) | 4294901760 : (context->gpr[4] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_1010_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[4] = (context->gpr[10] & 65535) & 32768 ? (context->gpr[10] & 65535) | 4294901760 : (context->gpr[10] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_1011_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[11] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[11], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[4] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_1011_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[11] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[11], context);
	context->gpr[4] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_1011_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[11] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[11], context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_1011_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[4] = context->gpr[11];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_1011_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[11] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[11], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[4] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[11] = 1 + context->gpr[11];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_1011_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[11] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[11], context);
	context->gpr[4] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[11] = 2 + context->gpr[11];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_1011_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[11] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[11], context);
	context->gpr[4] = context->scratch1;
	context->gpr[11] = 4 + context->gpr[11];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_1011_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[4] = ~context->gpr[11];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_1011_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[11] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[11] << 8;
	temp2 = 65280 & temp2;
	context->gpr[4] = context->gpr[11] & 4294901760;
	context->gpr[4] = temp1 | context->gpr[4];
	context->gpr[4] = temp2 | context->gpr[4];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_1011_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[11] >> 16;
	context->gpr[4] = context->gpr[11] << 16;
	context->gpr[4] = temp | context->gpr[4];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_1011_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[11]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[4] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_1011_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[4] = -context->gpr[11];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_1011_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[4] = context->gpr[11] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_1011_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[4] = context->gpr[11] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_1011_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[4] = (context->gpr[4] & ~65535) | ((context->gpr[11] & 255) & 128 ? (context->gpr[11] & 255) | 65280 : (context->gpr[11] & 255));
	context->gpr[4] = (context->gpr[4] & 65535) & 32768 ? (context->gpr[4] & 65535) | 4294901760 : (context->gpr[4] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_1011_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[4] = (context->gpr[11] & 65535) & 32768 ? (context->gpr[11] & 65535) | 4294901760 : (context->gpr[11] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_1100_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[12] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[12], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[4] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_1100_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[12] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[12], context);
	context->gpr[4] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_1100_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[12] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[12], context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_1100_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[4] = context->gpr[12];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_1100_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[12] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[12], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[4] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[12] = 1 + context->gpr[12];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_1100_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[12] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[12], context);
	context->gpr[4] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[12] = 2 + context->gpr[12];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_1100_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[12] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[12], context);
	context->gpr[4] = context->scratch1;
	context->gpr[12] = 4 + context->gpr[12];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_1100_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[4] = ~context->gpr[12];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_1100_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[12] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[12] << 8;
	temp2 = 65280 & temp2;
	context->gpr[4] = context->gpr[12] & 4294901760;
	context->gpr[4] = temp1 | context->gpr[4];
	context->gpr[4] = temp2 | context->gpr[4];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_1100_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[12] >> 16;
	context->gpr[4] = context->gpr[12] << 16;
	context->gpr[4] = temp | context->gpr[4];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_1100_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[12]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[4] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_1100_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[4] = -context->gpr[12];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_1100_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[4] = context->gpr[12] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_1100_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[4] = context->gpr[12] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_1100_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[4] = (context->gpr[4] & ~65535) | ((context->gpr[12] & 255) & 128 ? (context->gpr[12] & 255) | 65280 : (context->gpr[12] & 255));
	context->gpr[4] = (context->gpr[4] & 65535) & 32768 ? (context->gpr[4] & 65535) | 4294901760 : (context->gpr[4] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_1100_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[4] = (context->gpr[12] & 65535) & 32768 ? (context->gpr[12] & 65535) | 4294901760 : (context->gpr[12] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_1101_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[13] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[13], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[4] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_1101_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[13] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[13], context);
	context->gpr[4] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_1101_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[13] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[13], context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_1101_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[4] = context->gpr[13];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_1101_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[13] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[13], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[4] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[13] = 1 + context->gpr[13];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_1101_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[13] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[13], context);
	context->gpr[4] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[13] = 2 + context->gpr[13];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_1101_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[13] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[13], context);
	context->gpr[4] = context->scratch1;
	context->gpr[13] = 4 + context->gpr[13];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_1101_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[4] = ~context->gpr[13];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_1101_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[13] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[13] << 8;
	temp2 = 65280 & temp2;
	context->gpr[4] = context->gpr[13] & 4294901760;
	context->gpr[4] = temp1 | context->gpr[4];
	context->gpr[4] = temp2 | context->gpr[4];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_1101_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[13] >> 16;
	context->gpr[4] = context->gpr[13] << 16;
	context->gpr[4] = temp | context->gpr[4];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_1101_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[13]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[4] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_1101_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[4] = -context->gpr[13];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_1101_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[4] = context->gpr[13] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_1101_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[4] = context->gpr[13] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_1101_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[4] = (context->gpr[4] & ~65535) | ((context->gpr[13] & 255) & 128 ? (context->gpr[13] & 255) | 65280 : (context->gpr[13] & 255));
	context->gpr[4] = (context->gpr[4] & 65535) & 32768 ? (context->gpr[4] & 65535) | 4294901760 : (context->gpr[4] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_1101_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[4] = (context->gpr[13] & 65535) & 32768 ? (context->gpr[13] & 65535) | 4294901760 : (context->gpr[13] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_1110_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[14] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[14], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[4] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_1110_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[14] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[14], context);
	context->gpr[4] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_1110_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[14] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[14], context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_1110_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[4] = context->gpr[14];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_1110_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[14] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[14], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[4] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[14] = 1 + context->gpr[14];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_1110_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[14] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[14], context);
	context->gpr[4] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[14] = 2 + context->gpr[14];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_1110_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[14] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[14], context);
	context->gpr[4] = context->scratch1;
	context->gpr[14] = 4 + context->gpr[14];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_1110_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[4] = ~context->gpr[14];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_1110_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[14] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[14] << 8;
	temp2 = 65280 & temp2;
	context->gpr[4] = context->gpr[14] & 4294901760;
	context->gpr[4] = temp1 | context->gpr[4];
	context->gpr[4] = temp2 | context->gpr[4];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_1110_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[14] >> 16;
	context->gpr[4] = context->gpr[14] << 16;
	context->gpr[4] = temp | context->gpr[4];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_1110_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[14]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[4] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_1110_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[4] = -context->gpr[14];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_1110_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[4] = context->gpr[14] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_1110_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[4] = context->gpr[14] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_1110_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[4] = (context->gpr[4] & ~65535) | ((context->gpr[14] & 255) & 128 ? (context->gpr[14] & 255) | 65280 : (context->gpr[14] & 255));
	context->gpr[4] = (context->gpr[4] & 65535) & 32768 ? (context->gpr[4] & 65535) | 4294901760 : (context->gpr[4] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_1110_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[4] = (context->gpr[14] & 65535) & 32768 ? (context->gpr[14] & 65535) | 4294901760 : (context->gpr[14] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_1111_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[15] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[15], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[4] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_1111_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[15] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[15], context);
	context->gpr[4] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_1111_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[15] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[15], context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_1111_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[4] = context->gpr[15];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_1111_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[15] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[15], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[4] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[15] = 1 + context->gpr[15];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_1111_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[15] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[15], context);
	context->gpr[4] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[15] = 2 + context->gpr[15];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_1111_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[15] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[15], context);
	context->gpr[4] = context->scratch1;
	context->gpr[15] = 4 + context->gpr[15];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_1111_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[4] = ~context->gpr[15];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_1111_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[15] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[15] << 8;
	temp2 = 65280 & temp2;
	context->gpr[4] = context->gpr[15] & 4294901760;
	context->gpr[4] = temp1 | context->gpr[4];
	context->gpr[4] = temp2 | context->gpr[4];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_1111_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[15] >> 16;
	context->gpr[4] = context->gpr[15] << 16;
	context->gpr[4] = temp | context->gpr[4];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_1111_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[15]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[4] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_1111_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[4] = -context->gpr[15];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_1111_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[4] = context->gpr[15] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_1111_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[4] = context->gpr[15] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_1111_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[4] = (context->gpr[4] & ~65535) | ((context->gpr[15] & 255) & 128 ? (context->gpr[15] & 255) | 65280 : (context->gpr[15] & 255));
	context->gpr[4] = (context->gpr[4] & 65535) & 32768 ? (context->gpr[4] & 65535) | 4294901760 : (context->gpr[4] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_1111_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[4] = (context->gpr[15] & 65535) & 32768 ? (context->gpr[15] & 65535) | 4294901760 : (context->gpr[15] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_0000_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[0] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[0], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[5] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_0000_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[0] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[0], context);
	context->gpr[5] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_0000_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[0] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[0], context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_0000_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[5] = context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_0000_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[0] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[0], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[5] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[0] = 1 + context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_0000_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[0] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[0], context);
	context->gpr[5] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[0] = 2 + context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_0000_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[0] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[0], context);
	context->gpr[5] = context->scratch1;
	context->gpr[0] = 4 + context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_0000_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[5] = ~context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_0000_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[0] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[0] << 8;
	temp2 = 65280 & temp2;
	context->gpr[5] = context->gpr[0] & 4294901760;
	context->gpr[5] = temp1 | context->gpr[5];
	context->gpr[5] = temp2 | context->gpr[5];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_0000_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[0] >> 16;
	context->gpr[5] = context->gpr[0] << 16;
	context->gpr[5] = temp | context->gpr[5];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_0000_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[0]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[5] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_0000_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[5] = -context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_0000_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[5] = context->gpr[0] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_0000_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[5] = context->gpr[0] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_0000_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[5] = (context->gpr[5] & ~65535) | ((context->gpr[0] & 255) & 128 ? (context->gpr[0] & 255) | 65280 : (context->gpr[0] & 255));
	context->gpr[5] = (context->gpr[5] & 65535) & 32768 ? (context->gpr[5] & 65535) | 4294901760 : (context->gpr[5] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_0000_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[5] = (context->gpr[0] & 65535) & 32768 ? (context->gpr[0] & 65535) | 4294901760 : (context->gpr[0] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_0001_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[1] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[1], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[5] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_0001_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[1] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[1], context);
	context->gpr[5] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_0001_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[1] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[1], context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_0001_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[5] = context->gpr[1];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_0001_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[1] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[1], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[5] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[1] = 1 + context->gpr[1];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_0001_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[1] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[1], context);
	context->gpr[5] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[1] = 2 + context->gpr[1];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_0001_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[1] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[1], context);
	context->gpr[5] = context->scratch1;
	context->gpr[1] = 4 + context->gpr[1];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_0001_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[5] = ~context->gpr[1];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_0001_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[1] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[1] << 8;
	temp2 = 65280 & temp2;
	context->gpr[5] = context->gpr[1] & 4294901760;
	context->gpr[5] = temp1 | context->gpr[5];
	context->gpr[5] = temp2 | context->gpr[5];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_0001_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[1] >> 16;
	context->gpr[5] = context->gpr[1] << 16;
	context->gpr[5] = temp | context->gpr[5];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_0001_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[1]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[5] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_0001_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[5] = -context->gpr[1];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_0001_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[5] = context->gpr[1] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_0001_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[5] = context->gpr[1] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_0001_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[5] = (context->gpr[5] & ~65535) | ((context->gpr[1] & 255) & 128 ? (context->gpr[1] & 255) | 65280 : (context->gpr[1] & 255));
	context->gpr[5] = (context->gpr[5] & 65535) & 32768 ? (context->gpr[5] & 65535) | 4294901760 : (context->gpr[5] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_0001_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[5] = (context->gpr[1] & 65535) & 32768 ? (context->gpr[1] & 65535) | 4294901760 : (context->gpr[1] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_0010_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[2] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[2], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[5] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_0010_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[2] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[2], context);
	context->gpr[5] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_0010_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[2] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[2], context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_0010_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[5] = context->gpr[2];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_0010_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[2] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[2], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[5] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[2] = 1 + context->gpr[2];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_0010_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[2] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[2], context);
	context->gpr[5] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[2] = 2 + context->gpr[2];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_0010_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[2] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[2], context);
	context->gpr[5] = context->scratch1;
	context->gpr[2] = 4 + context->gpr[2];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_0010_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[5] = ~context->gpr[2];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_0010_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[2] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[2] << 8;
	temp2 = 65280 & temp2;
	context->gpr[5] = context->gpr[2] & 4294901760;
	context->gpr[5] = temp1 | context->gpr[5];
	context->gpr[5] = temp2 | context->gpr[5];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_0010_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[2] >> 16;
	context->gpr[5] = context->gpr[2] << 16;
	context->gpr[5] = temp | context->gpr[5];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_0010_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[2]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[5] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_0010_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[5] = -context->gpr[2];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_0010_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[5] = context->gpr[2] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_0010_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[5] = context->gpr[2] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_0010_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[5] = (context->gpr[5] & ~65535) | ((context->gpr[2] & 255) & 128 ? (context->gpr[2] & 255) | 65280 : (context->gpr[2] & 255));
	context->gpr[5] = (context->gpr[5] & 65535) & 32768 ? (context->gpr[5] & 65535) | 4294901760 : (context->gpr[5] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_0010_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[5] = (context->gpr[2] & 65535) & 32768 ? (context->gpr[2] & 65535) | 4294901760 : (context->gpr[2] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_0011_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[3] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[3], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[5] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_0011_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[3] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[3], context);
	context->gpr[5] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_0011_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[3] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[3], context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_0011_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[5] = context->gpr[3];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_0011_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[3] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[3], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[5] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[3] = 1 + context->gpr[3];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_0011_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[3] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[3], context);
	context->gpr[5] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[3] = 2 + context->gpr[3];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_0011_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[3] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[3], context);
	context->gpr[5] = context->scratch1;
	context->gpr[3] = 4 + context->gpr[3];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_0011_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[5] = ~context->gpr[3];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_0011_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[3] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[3] << 8;
	temp2 = 65280 & temp2;
	context->gpr[5] = context->gpr[3] & 4294901760;
	context->gpr[5] = temp1 | context->gpr[5];
	context->gpr[5] = temp2 | context->gpr[5];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_0011_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[3] >> 16;
	context->gpr[5] = context->gpr[3] << 16;
	context->gpr[5] = temp | context->gpr[5];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_0011_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[3]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[5] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_0011_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[5] = -context->gpr[3];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_0011_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[5] = context->gpr[3] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_0011_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[5] = context->gpr[3] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_0011_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[5] = (context->gpr[5] & ~65535) | ((context->gpr[3] & 255) & 128 ? (context->gpr[3] & 255) | 65280 : (context->gpr[3] & 255));
	context->gpr[5] = (context->gpr[5] & 65535) & 32768 ? (context->gpr[5] & 65535) | 4294901760 : (context->gpr[5] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_0011_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[5] = (context->gpr[3] & 65535) & 32768 ? (context->gpr[3] & 65535) | 4294901760 : (context->gpr[3] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_0100_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[4] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[4], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[5] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_0100_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[4] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[4], context);
	context->gpr[5] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_0100_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[4] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[4], context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_0100_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[5] = context->gpr[4];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_0100_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[4] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[4], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[5] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[4] = 1 + context->gpr[4];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_0100_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[4] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[4], context);
	context->gpr[5] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[4] = 2 + context->gpr[4];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_0100_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[4] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[4], context);
	context->gpr[5] = context->scratch1;
	context->gpr[4] = 4 + context->gpr[4];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_0100_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[5] = ~context->gpr[4];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_0100_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[4] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[4] << 8;
	temp2 = 65280 & temp2;
	context->gpr[5] = context->gpr[4] & 4294901760;
	context->gpr[5] = temp1 | context->gpr[5];
	context->gpr[5] = temp2 | context->gpr[5];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_0100_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[4] >> 16;
	context->gpr[5] = context->gpr[4] << 16;
	context->gpr[5] = temp | context->gpr[5];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_0100_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[4]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[5] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_0100_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[5] = -context->gpr[4];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_0100_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[5] = context->gpr[4] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_0100_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[5] = context->gpr[4] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_0100_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[5] = (context->gpr[5] & ~65535) | ((context->gpr[4] & 255) & 128 ? (context->gpr[4] & 255) | 65280 : (context->gpr[4] & 255));
	context->gpr[5] = (context->gpr[5] & 65535) & 32768 ? (context->gpr[5] & 65535) | 4294901760 : (context->gpr[5] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_0100_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[5] = (context->gpr[4] & 65535) & 32768 ? (context->gpr[4] & 65535) | 4294901760 : (context->gpr[4] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_0101_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[5] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[5], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[5] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_0101_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[5] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[5], context);
	context->gpr[5] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_0101_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[5] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[5], context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_0101_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[5] = context->gpr[5];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_0101_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[5] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[5], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[5] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_0101_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[5] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[5], context);
	context->gpr[5] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_0101_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[5] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[5], context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_0101_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[5] = ~context->gpr[5];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_0101_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[5] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[5] << 8;
	temp2 = 65280 & temp2;
	context->gpr[5] = context->gpr[5] & 4294901760;
	context->gpr[5] = temp1 | context->gpr[5];
	context->gpr[5] = temp2 | context->gpr[5];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_0101_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[5] >> 16;
	context->gpr[5] = context->gpr[5] << 16;
	context->gpr[5] = temp | context->gpr[5];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_0101_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[5]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[5] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_0101_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[5] = -context->gpr[5];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_0101_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[5] = context->gpr[5] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_0101_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[5] = context->gpr[5] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_0101_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[5] = (context->gpr[5] & ~65535) | ((context->gpr[5] & 255) & 128 ? (context->gpr[5] & 255) | 65280 : (context->gpr[5] & 255));
	context->gpr[5] = (context->gpr[5] & 65535) & 32768 ? (context->gpr[5] & 65535) | 4294901760 : (context->gpr[5] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_0101_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[5] = (context->gpr[5] & 65535) & 32768 ? (context->gpr[5] & 65535) | 4294901760 : (context->gpr[5] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_0110_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[6] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[6], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[5] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_0110_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[6] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[6], context);
	context->gpr[5] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_0110_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[6] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[6], context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_0110_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[5] = context->gpr[6];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_0110_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[6] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[6], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[5] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[6] = 1 + context->gpr[6];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_0110_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[6] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[6], context);
	context->gpr[5] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[6] = 2 + context->gpr[6];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_0110_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[6] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[6], context);
	context->gpr[5] = context->scratch1;
	context->gpr[6] = 4 + context->gpr[6];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_0110_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[5] = ~context->gpr[6];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_0110_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[6] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[6] << 8;
	temp2 = 65280 & temp2;
	context->gpr[5] = context->gpr[6] & 4294901760;
	context->gpr[5] = temp1 | context->gpr[5];
	context->gpr[5] = temp2 | context->gpr[5];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_0110_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[6] >> 16;
	context->gpr[5] = context->gpr[6] << 16;
	context->gpr[5] = temp | context->gpr[5];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_0110_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[6]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[5] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_0110_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[5] = -context->gpr[6];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_0110_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[5] = context->gpr[6] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_0110_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[5] = context->gpr[6] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_0110_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[5] = (context->gpr[5] & ~65535) | ((context->gpr[6] & 255) & 128 ? (context->gpr[6] & 255) | 65280 : (context->gpr[6] & 255));
	context->gpr[5] = (context->gpr[5] & 65535) & 32768 ? (context->gpr[5] & 65535) | 4294901760 : (context->gpr[5] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_0110_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[5] = (context->gpr[6] & 65535) & 32768 ? (context->gpr[6] & 65535) | 4294901760 : (context->gpr[6] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_0111_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[7] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[7], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[5] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_0111_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[7] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[7], context);
	context->gpr[5] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_0111_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[7] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[7], context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_0111_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[5] = context->gpr[7];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_0111_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[7] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[7], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[5] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[7] = 1 + context->gpr[7];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_0111_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[7] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[7], context);
	context->gpr[5] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[7] = 2 + context->gpr[7];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_0111_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[7] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[7], context);
	context->gpr[5] = context->scratch1;
	context->gpr[7] = 4 + context->gpr[7];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_0111_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[5] = ~context->gpr[7];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_0111_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[7] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[7] << 8;
	temp2 = 65280 & temp2;
	context->gpr[5] = context->gpr[7] & 4294901760;
	context->gpr[5] = temp1 | context->gpr[5];
	context->gpr[5] = temp2 | context->gpr[5];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_0111_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[7] >> 16;
	context->gpr[5] = context->gpr[7] << 16;
	context->gpr[5] = temp | context->gpr[5];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_0111_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[7]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[5] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_0111_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[5] = -context->gpr[7];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_0111_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[5] = context->gpr[7] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_0111_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[5] = context->gpr[7] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_0111_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[5] = (context->gpr[5] & ~65535) | ((context->gpr[7] & 255) & 128 ? (context->gpr[7] & 255) | 65280 : (context->gpr[7] & 255));
	context->gpr[5] = (context->gpr[5] & 65535) & 32768 ? (context->gpr[5] & 65535) | 4294901760 : (context->gpr[5] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_0111_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[5] = (context->gpr[7] & 65535) & 32768 ? (context->gpr[7] & 65535) | 4294901760 : (context->gpr[7] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_1000_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[8] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[8], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[5] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_1000_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[8] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[8], context);
	context->gpr[5] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_1000_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[8] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[8], context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_1000_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[5] = context->gpr[8];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_1000_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[8] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[8], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[5] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[8] = 1 + context->gpr[8];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_1000_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[8] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[8], context);
	context->gpr[5] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[8] = 2 + context->gpr[8];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_1000_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[8] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[8], context);
	context->gpr[5] = context->scratch1;
	context->gpr[8] = 4 + context->gpr[8];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_1000_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[5] = ~context->gpr[8];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_1000_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[8] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[8] << 8;
	temp2 = 65280 & temp2;
	context->gpr[5] = context->gpr[8] & 4294901760;
	context->gpr[5] = temp1 | context->gpr[5];
	context->gpr[5] = temp2 | context->gpr[5];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_1000_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[8] >> 16;
	context->gpr[5] = context->gpr[8] << 16;
	context->gpr[5] = temp | context->gpr[5];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_1000_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[8]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[5] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_1000_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[5] = -context->gpr[8];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_1000_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[5] = context->gpr[8] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_1000_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[5] = context->gpr[8] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_1000_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[5] = (context->gpr[5] & ~65535) | ((context->gpr[8] & 255) & 128 ? (context->gpr[8] & 255) | 65280 : (context->gpr[8] & 255));
	context->gpr[5] = (context->gpr[5] & 65535) & 32768 ? (context->gpr[5] & 65535) | 4294901760 : (context->gpr[5] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_1000_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[5] = (context->gpr[8] & 65535) & 32768 ? (context->gpr[8] & 65535) | 4294901760 : (context->gpr[8] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_1001_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[9] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[9], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[5] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_1001_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[9] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[9], context);
	context->gpr[5] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_1001_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[9] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[9], context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_1001_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[5] = context->gpr[9];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_1001_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[9] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[9], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[5] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[9] = 1 + context->gpr[9];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_1001_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[9] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[9], context);
	context->gpr[5] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[9] = 2 + context->gpr[9];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_1001_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[9] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[9], context);
	context->gpr[5] = context->scratch1;
	context->gpr[9] = 4 + context->gpr[9];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_1001_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[5] = ~context->gpr[9];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_1001_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[9] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[9] << 8;
	temp2 = 65280 & temp2;
	context->gpr[5] = context->gpr[9] & 4294901760;
	context->gpr[5] = temp1 | context->gpr[5];
	context->gpr[5] = temp2 | context->gpr[5];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_1001_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[9] >> 16;
	context->gpr[5] = context->gpr[9] << 16;
	context->gpr[5] = temp | context->gpr[5];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_1001_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[9]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[5] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_1001_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[5] = -context->gpr[9];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_1001_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[5] = context->gpr[9] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_1001_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[5] = context->gpr[9] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_1001_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[5] = (context->gpr[5] & ~65535) | ((context->gpr[9] & 255) & 128 ? (context->gpr[9] & 255) | 65280 : (context->gpr[9] & 255));
	context->gpr[5] = (context->gpr[5] & 65535) & 32768 ? (context->gpr[5] & 65535) | 4294901760 : (context->gpr[5] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_1001_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[5] = (context->gpr[9] & 65535) & 32768 ? (context->gpr[9] & 65535) | 4294901760 : (context->gpr[9] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_1010_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[10] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[10], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[5] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_1010_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[10] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[10], context);
	context->gpr[5] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_1010_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[10] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[10], context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_1010_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[5] = context->gpr[10];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_1010_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[10] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[10], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[5] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[10] = 1 + context->gpr[10];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_1010_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[10] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[10], context);
	context->gpr[5] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[10] = 2 + context->gpr[10];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_1010_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[10] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[10], context);
	context->gpr[5] = context->scratch1;
	context->gpr[10] = 4 + context->gpr[10];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_1010_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[5] = ~context->gpr[10];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_1010_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[10] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[10] << 8;
	temp2 = 65280 & temp2;
	context->gpr[5] = context->gpr[10] & 4294901760;
	context->gpr[5] = temp1 | context->gpr[5];
	context->gpr[5] = temp2 | context->gpr[5];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_1010_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[10] >> 16;
	context->gpr[5] = context->gpr[10] << 16;
	context->gpr[5] = temp | context->gpr[5];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_1010_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[10]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[5] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_1010_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[5] = -context->gpr[10];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_1010_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[5] = context->gpr[10] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_1010_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[5] = context->gpr[10] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_1010_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[5] = (context->gpr[5] & ~65535) | ((context->gpr[10] & 255) & 128 ? (context->gpr[10] & 255) | 65280 : (context->gpr[10] & 255));
	context->gpr[5] = (context->gpr[5] & 65535) & 32768 ? (context->gpr[5] & 65535) | 4294901760 : (context->gpr[5] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_1010_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[5] = (context->gpr[10] & 65535) & 32768 ? (context->gpr[10] & 65535) | 4294901760 : (context->gpr[10] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_1011_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[11] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[11], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[5] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_1011_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[11] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[11], context);
	context->gpr[5] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_1011_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[11] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[11], context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_1011_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[5] = context->gpr[11];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_1011_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[11] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[11], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[5] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[11] = 1 + context->gpr[11];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_1011_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[11] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[11], context);
	context->gpr[5] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[11] = 2 + context->gpr[11];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_1011_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[11] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[11], context);
	context->gpr[5] = context->scratch1;
	context->gpr[11] = 4 + context->gpr[11];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_1011_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[5] = ~context->gpr[11];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_1011_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[11] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[11] << 8;
	temp2 = 65280 & temp2;
	context->gpr[5] = context->gpr[11] & 4294901760;
	context->gpr[5] = temp1 | context->gpr[5];
	context->gpr[5] = temp2 | context->gpr[5];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_1011_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[11] >> 16;
	context->gpr[5] = context->gpr[11] << 16;
	context->gpr[5] = temp | context->gpr[5];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_1011_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[11]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[5] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_1011_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[5] = -context->gpr[11];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_1011_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[5] = context->gpr[11] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_1011_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[5] = context->gpr[11] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_1011_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[5] = (context->gpr[5] & ~65535) | ((context->gpr[11] & 255) & 128 ? (context->gpr[11] & 255) | 65280 : (context->gpr[11] & 255));
	context->gpr[5] = (context->gpr[5] & 65535) & 32768 ? (context->gpr[5] & 65535) | 4294901760 : (context->gpr[5] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_1011_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[5] = (context->gpr[11] & 65535) & 32768 ? (context->gpr[11] & 65535) | 4294901760 : (context->gpr[11] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_1100_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[12] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[12], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[5] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_1100_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[12] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[12], context);
	context->gpr[5] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_1100_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[12] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[12], context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_1100_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[5] = context->gpr[12];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_1100_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[12] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[12], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[5] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[12] = 1 + context->gpr[12];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_1100_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[12] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[12], context);
	context->gpr[5] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[12] = 2 + context->gpr[12];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_1100_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[12] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[12], context);
	context->gpr[5] = context->scratch1;
	context->gpr[12] = 4 + context->gpr[12];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_1100_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[5] = ~context->gpr[12];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_1100_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[12] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[12] << 8;
	temp2 = 65280 & temp2;
	context->gpr[5] = context->gpr[12] & 4294901760;
	context->gpr[5] = temp1 | context->gpr[5];
	context->gpr[5] = temp2 | context->gpr[5];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_1100_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[12] >> 16;
	context->gpr[5] = context->gpr[12] << 16;
	context->gpr[5] = temp | context->gpr[5];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_1100_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[12]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[5] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_1100_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[5] = -context->gpr[12];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_1100_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[5] = context->gpr[12] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_1100_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[5] = context->gpr[12] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_1100_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[5] = (context->gpr[5] & ~65535) | ((context->gpr[12] & 255) & 128 ? (context->gpr[12] & 255) | 65280 : (context->gpr[12] & 255));
	context->gpr[5] = (context->gpr[5] & 65535) & 32768 ? (context->gpr[5] & 65535) | 4294901760 : (context->gpr[5] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_1100_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[5] = (context->gpr[12] & 65535) & 32768 ? (context->gpr[12] & 65535) | 4294901760 : (context->gpr[12] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_1101_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[13] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[13], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[5] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_1101_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[13] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[13], context);
	context->gpr[5] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_1101_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[13] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[13], context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_1101_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[5] = context->gpr[13];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_1101_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[13] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[13], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[5] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[13] = 1 + context->gpr[13];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_1101_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[13] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[13], context);
	context->gpr[5] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[13] = 2 + context->gpr[13];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_1101_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[13] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[13], context);
	context->gpr[5] = context->scratch1;
	context->gpr[13] = 4 + context->gpr[13];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_1101_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[5] = ~context->gpr[13];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_1101_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[13] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[13] << 8;
	temp2 = 65280 & temp2;
	context->gpr[5] = context->gpr[13] & 4294901760;
	context->gpr[5] = temp1 | context->gpr[5];
	context->gpr[5] = temp2 | context->gpr[5];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_1101_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[13] >> 16;
	context->gpr[5] = context->gpr[13] << 16;
	context->gpr[5] = temp | context->gpr[5];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_1101_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[13]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[5] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_1101_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[5] = -context->gpr[13];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_1101_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[5] = context->gpr[13] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_1101_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[5] = context->gpr[13] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_1101_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[5] = (context->gpr[5] & ~65535) | ((context->gpr[13] & 255) & 128 ? (context->gpr[13] & 255) | 65280 : (context->gpr[13] & 255));
	context->gpr[5] = (context->gpr[5] & 65535) & 32768 ? (context->gpr[5] & 65535) | 4294901760 : (context->gpr[5] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_1101_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[5] = (context->gpr[13] & 65535) & 32768 ? (context->gpr[13] & 65535) | 4294901760 : (context->gpr[13] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_1110_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[14] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[14], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[5] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_1110_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[14] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[14], context);
	context->gpr[5] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_1110_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[14] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[14], context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_1110_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[5] = context->gpr[14];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_1110_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[14] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[14], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[5] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[14] = 1 + context->gpr[14];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_1110_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[14] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[14], context);
	context->gpr[5] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[14] = 2 + context->gpr[14];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_1110_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[14] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[14], context);
	context->gpr[5] = context->scratch1;
	context->gpr[14] = 4 + context->gpr[14];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_1110_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[5] = ~context->gpr[14];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_1110_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[14] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[14] << 8;
	temp2 = 65280 & temp2;
	context->gpr[5] = context->gpr[14] & 4294901760;
	context->gpr[5] = temp1 | context->gpr[5];
	context->gpr[5] = temp2 | context->gpr[5];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_1110_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[14] >> 16;
	context->gpr[5] = context->gpr[14] << 16;
	context->gpr[5] = temp | context->gpr[5];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_1110_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[14]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[5] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_1110_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[5] = -context->gpr[14];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_1110_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[5] = context->gpr[14] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_1110_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[5] = context->gpr[14] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_1110_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[5] = (context->gpr[5] & ~65535) | ((context->gpr[14] & 255) & 128 ? (context->gpr[14] & 255) | 65280 : (context->gpr[14] & 255));
	context->gpr[5] = (context->gpr[5] & 65535) & 32768 ? (context->gpr[5] & 65535) | 4294901760 : (context->gpr[5] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_1110_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[5] = (context->gpr[14] & 65535) & 32768 ? (context->gpr[14] & 65535) | 4294901760 : (context->gpr[14] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_1111_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[15] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[15], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[5] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_1111_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[15] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[15], context);
	context->gpr[5] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_1111_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[15] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[15], context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_1111_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[5] = context->gpr[15];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_1111_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[15] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[15], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[5] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[15] = 1 + context->gpr[15];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_1111_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[15] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[15], context);
	context->gpr[5] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[15] = 2 + context->gpr[15];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_1111_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[15] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[15], context);
	context->gpr[5] = context->scratch1;
	context->gpr[15] = 4 + context->gpr[15];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_1111_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[5] = ~context->gpr[15];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_1111_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[15] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[15] << 8;
	temp2 = 65280 & temp2;
	context->gpr[5] = context->gpr[15] & 4294901760;
	context->gpr[5] = temp1 | context->gpr[5];
	context->gpr[5] = temp2 | context->gpr[5];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_1111_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[15] >> 16;
	context->gpr[5] = context->gpr[15] << 16;
	context->gpr[5] = temp | context->gpr[5];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_1111_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[15]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[5] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_1111_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[5] = -context->gpr[15];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_1111_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[5] = context->gpr[15] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_1111_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[5] = context->gpr[15] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_1111_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[5] = (context->gpr[5] & ~65535) | ((context->gpr[15] & 255) & 128 ? (context->gpr[15] & 255) | 65280 : (context->gpr[15] & 255));
	context->gpr[5] = (context->gpr[5] & 65535) & 32768 ? (context->gpr[5] & 65535) | 4294901760 : (context->gpr[5] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_1111_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[5] = (context->gpr[15] & 65535) & 32768 ? (context->gpr[15] & 65535) | 4294901760 : (context->gpr[15] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_0000_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[0] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[0], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[6] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_0000_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[0] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[0], context);
	context->gpr[6] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_0000_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[0] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[0], context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_0000_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[6] = context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_0000_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[0] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[0], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[6] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[0] = 1 + context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_0000_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[0] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[0], context);
	context->gpr[6] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[0] = 2 + context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_0000_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[0] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[0], context);
	context->gpr[6] = context->scratch1;
	context->gpr[0] = 4 + context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_0000_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[6] = ~context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_0000_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[0] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[0] << 8;
	temp2 = 65280 & temp2;
	context->gpr[6] = context->gpr[0] & 4294901760;
	context->gpr[6] = temp1 | context->gpr[6];
	context->gpr[6] = temp2 | context->gpr[6];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_0000_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[0] >> 16;
	context->gpr[6] = context->gpr[0] << 16;
	context->gpr[6] = temp | context->gpr[6];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_0000_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[0]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[6] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_0000_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[6] = -context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_0000_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[6] = context->gpr[0] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_0000_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[6] = context->gpr[0] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_0000_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[6] = (context->gpr[6] & ~65535) | ((context->gpr[0] & 255) & 128 ? (context->gpr[0] & 255) | 65280 : (context->gpr[0] & 255));
	context->gpr[6] = (context->gpr[6] & 65535) & 32768 ? (context->gpr[6] & 65535) | 4294901760 : (context->gpr[6] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_0000_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[6] = (context->gpr[0] & 65535) & 32768 ? (context->gpr[0] & 65535) | 4294901760 : (context->gpr[0] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_0001_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[1] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[1], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[6] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_0001_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[1] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[1], context);
	context->gpr[6] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_0001_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[1] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[1], context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_0001_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[6] = context->gpr[1];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_0001_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[1] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[1], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[6] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[1] = 1 + context->gpr[1];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_0001_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[1] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[1], context);
	context->gpr[6] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[1] = 2 + context->gpr[1];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_0001_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[1] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[1], context);
	context->gpr[6] = context->scratch1;
	context->gpr[1] = 4 + context->gpr[1];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_0001_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[6] = ~context->gpr[1];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_0001_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[1] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[1] << 8;
	temp2 = 65280 & temp2;
	context->gpr[6] = context->gpr[1] & 4294901760;
	context->gpr[6] = temp1 | context->gpr[6];
	context->gpr[6] = temp2 | context->gpr[6];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_0001_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[1] >> 16;
	context->gpr[6] = context->gpr[1] << 16;
	context->gpr[6] = temp | context->gpr[6];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_0001_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[1]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[6] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_0001_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[6] = -context->gpr[1];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_0001_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[6] = context->gpr[1] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_0001_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[6] = context->gpr[1] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_0001_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[6] = (context->gpr[6] & ~65535) | ((context->gpr[1] & 255) & 128 ? (context->gpr[1] & 255) | 65280 : (context->gpr[1] & 255));
	context->gpr[6] = (context->gpr[6] & 65535) & 32768 ? (context->gpr[6] & 65535) | 4294901760 : (context->gpr[6] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_0001_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[6] = (context->gpr[1] & 65535) & 32768 ? (context->gpr[1] & 65535) | 4294901760 : (context->gpr[1] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_0010_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[2] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[2], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[6] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_0010_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[2] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[2], context);
	context->gpr[6] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_0010_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[2] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[2], context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_0010_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[6] = context->gpr[2];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_0010_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[2] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[2], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[6] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[2] = 1 + context->gpr[2];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_0010_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[2] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[2], context);
	context->gpr[6] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[2] = 2 + context->gpr[2];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_0010_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[2] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[2], context);
	context->gpr[6] = context->scratch1;
	context->gpr[2] = 4 + context->gpr[2];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_0010_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[6] = ~context->gpr[2];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_0010_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[2] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[2] << 8;
	temp2 = 65280 & temp2;
	context->gpr[6] = context->gpr[2] & 4294901760;
	context->gpr[6] = temp1 | context->gpr[6];
	context->gpr[6] = temp2 | context->gpr[6];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_0010_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[2] >> 16;
	context->gpr[6] = context->gpr[2] << 16;
	context->gpr[6] = temp | context->gpr[6];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_0010_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[2]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[6] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_0010_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[6] = -context->gpr[2];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_0010_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[6] = context->gpr[2] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_0010_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[6] = context->gpr[2] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_0010_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[6] = (context->gpr[6] & ~65535) | ((context->gpr[2] & 255) & 128 ? (context->gpr[2] & 255) | 65280 : (context->gpr[2] & 255));
	context->gpr[6] = (context->gpr[6] & 65535) & 32768 ? (context->gpr[6] & 65535) | 4294901760 : (context->gpr[6] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_0010_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[6] = (context->gpr[2] & 65535) & 32768 ? (context->gpr[2] & 65535) | 4294901760 : (context->gpr[2] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_0011_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[3] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[3], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[6] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_0011_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[3] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[3], context);
	context->gpr[6] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_0011_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[3] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[3], context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_0011_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[6] = context->gpr[3];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_0011_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[3] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[3], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[6] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[3] = 1 + context->gpr[3];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_0011_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[3] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[3], context);
	context->gpr[6] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[3] = 2 + context->gpr[3];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_0011_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[3] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[3], context);
	context->gpr[6] = context->scratch1;
	context->gpr[3] = 4 + context->gpr[3];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_0011_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[6] = ~context->gpr[3];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_0011_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[3] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[3] << 8;
	temp2 = 65280 & temp2;
	context->gpr[6] = context->gpr[3] & 4294901760;
	context->gpr[6] = temp1 | context->gpr[6];
	context->gpr[6] = temp2 | context->gpr[6];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_0011_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[3] >> 16;
	context->gpr[6] = context->gpr[3] << 16;
	context->gpr[6] = temp | context->gpr[6];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_0011_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[3]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[6] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_0011_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[6] = -context->gpr[3];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_0011_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[6] = context->gpr[3] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_0011_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[6] = context->gpr[3] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_0011_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[6] = (context->gpr[6] & ~65535) | ((context->gpr[3] & 255) & 128 ? (context->gpr[3] & 255) | 65280 : (context->gpr[3] & 255));
	context->gpr[6] = (context->gpr[6] & 65535) & 32768 ? (context->gpr[6] & 65535) | 4294901760 : (context->gpr[6] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_0011_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[6] = (context->gpr[3] & 65535) & 32768 ? (context->gpr[3] & 65535) | 4294901760 : (context->gpr[3] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_0100_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[4] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[4], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[6] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_0100_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[4] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[4], context);
	context->gpr[6] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_0100_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[4] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[4], context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_0100_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[6] = context->gpr[4];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_0100_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[4] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[4], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[6] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[4] = 1 + context->gpr[4];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_0100_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[4] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[4], context);
	context->gpr[6] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[4] = 2 + context->gpr[4];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_0100_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[4] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[4], context);
	context->gpr[6] = context->scratch1;
	context->gpr[4] = 4 + context->gpr[4];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_0100_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[6] = ~context->gpr[4];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_0100_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[4] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[4] << 8;
	temp2 = 65280 & temp2;
	context->gpr[6] = context->gpr[4] & 4294901760;
	context->gpr[6] = temp1 | context->gpr[6];
	context->gpr[6] = temp2 | context->gpr[6];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_0100_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[4] >> 16;
	context->gpr[6] = context->gpr[4] << 16;
	context->gpr[6] = temp | context->gpr[6];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_0100_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[4]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[6] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_0100_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[6] = -context->gpr[4];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_0100_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[6] = context->gpr[4] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_0100_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[6] = context->gpr[4] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_0100_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[6] = (context->gpr[6] & ~65535) | ((context->gpr[4] & 255) & 128 ? (context->gpr[4] & 255) | 65280 : (context->gpr[4] & 255));
	context->gpr[6] = (context->gpr[6] & 65535) & 32768 ? (context->gpr[6] & 65535) | 4294901760 : (context->gpr[6] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_0100_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[6] = (context->gpr[4] & 65535) & 32768 ? (context->gpr[4] & 65535) | 4294901760 : (context->gpr[4] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_0101_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[5] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[5], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[6] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_0101_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[5] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[5], context);
	context->gpr[6] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_0101_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[5] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[5], context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_0101_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[6] = context->gpr[5];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_0101_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[5] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[5], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[6] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[5] = 1 + context->gpr[5];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_0101_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[5] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[5], context);
	context->gpr[6] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[5] = 2 + context->gpr[5];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_0101_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[5] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[5], context);
	context->gpr[6] = context->scratch1;
	context->gpr[5] = 4 + context->gpr[5];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_0101_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[6] = ~context->gpr[5];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_0101_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[5] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[5] << 8;
	temp2 = 65280 & temp2;
	context->gpr[6] = context->gpr[5] & 4294901760;
	context->gpr[6] = temp1 | context->gpr[6];
	context->gpr[6] = temp2 | context->gpr[6];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_0101_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[5] >> 16;
	context->gpr[6] = context->gpr[5] << 16;
	context->gpr[6] = temp | context->gpr[6];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_0101_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[5]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[6] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_0101_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[6] = -context->gpr[5];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_0101_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[6] = context->gpr[5] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_0101_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[6] = context->gpr[5] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_0101_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[6] = (context->gpr[6] & ~65535) | ((context->gpr[5] & 255) & 128 ? (context->gpr[5] & 255) | 65280 : (context->gpr[5] & 255));
	context->gpr[6] = (context->gpr[6] & 65535) & 32768 ? (context->gpr[6] & 65535) | 4294901760 : (context->gpr[6] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_0101_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[6] = (context->gpr[5] & 65535) & 32768 ? (context->gpr[5] & 65535) | 4294901760 : (context->gpr[5] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_0110_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[6] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[6], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[6] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_0110_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[6] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[6], context);
	context->gpr[6] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_0110_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[6] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[6], context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_0110_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[6] = context->gpr[6];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_0110_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[6] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[6], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[6] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_0110_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[6] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[6], context);
	context->gpr[6] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_0110_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[6] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[6], context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_0110_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[6] = ~context->gpr[6];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_0110_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[6] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[6] << 8;
	temp2 = 65280 & temp2;
	context->gpr[6] = context->gpr[6] & 4294901760;
	context->gpr[6] = temp1 | context->gpr[6];
	context->gpr[6] = temp2 | context->gpr[6];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_0110_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[6] >> 16;
	context->gpr[6] = context->gpr[6] << 16;
	context->gpr[6] = temp | context->gpr[6];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_0110_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[6]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[6] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_0110_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[6] = -context->gpr[6];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_0110_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[6] = context->gpr[6] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_0110_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[6] = context->gpr[6] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_0110_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[6] = (context->gpr[6] & ~65535) | ((context->gpr[6] & 255) & 128 ? (context->gpr[6] & 255) | 65280 : (context->gpr[6] & 255));
	context->gpr[6] = (context->gpr[6] & 65535) & 32768 ? (context->gpr[6] & 65535) | 4294901760 : (context->gpr[6] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_0110_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[6] = (context->gpr[6] & 65535) & 32768 ? (context->gpr[6] & 65535) | 4294901760 : (context->gpr[6] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_0111_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[7] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[7], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[6] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_0111_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[7] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[7], context);
	context->gpr[6] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_0111_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[7] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[7], context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_0111_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[6] = context->gpr[7];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_0111_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[7] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[7], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[6] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[7] = 1 + context->gpr[7];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_0111_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[7] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[7], context);
	context->gpr[6] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[7] = 2 + context->gpr[7];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_0111_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[7] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[7], context);
	context->gpr[6] = context->scratch1;
	context->gpr[7] = 4 + context->gpr[7];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_0111_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[6] = ~context->gpr[7];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_0111_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[7] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[7] << 8;
	temp2 = 65280 & temp2;
	context->gpr[6] = context->gpr[7] & 4294901760;
	context->gpr[6] = temp1 | context->gpr[6];
	context->gpr[6] = temp2 | context->gpr[6];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_0111_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[7] >> 16;
	context->gpr[6] = context->gpr[7] << 16;
	context->gpr[6] = temp | context->gpr[6];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_0111_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[7]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[6] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_0111_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[6] = -context->gpr[7];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_0111_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[6] = context->gpr[7] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_0111_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[6] = context->gpr[7] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_0111_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[6] = (context->gpr[6] & ~65535) | ((context->gpr[7] & 255) & 128 ? (context->gpr[7] & 255) | 65280 : (context->gpr[7] & 255));
	context->gpr[6] = (context->gpr[6] & 65535) & 32768 ? (context->gpr[6] & 65535) | 4294901760 : (context->gpr[6] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_0111_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[6] = (context->gpr[7] & 65535) & 32768 ? (context->gpr[7] & 65535) | 4294901760 : (context->gpr[7] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_1000_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[8] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[8], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[6] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_1000_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[8] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[8], context);
	context->gpr[6] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_1000_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[8] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[8], context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_1000_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[6] = context->gpr[8];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_1000_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[8] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[8], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[6] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[8] = 1 + context->gpr[8];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_1000_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[8] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[8], context);
	context->gpr[6] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[8] = 2 + context->gpr[8];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_1000_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[8] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[8], context);
	context->gpr[6] = context->scratch1;
	context->gpr[8] = 4 + context->gpr[8];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_1000_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[6] = ~context->gpr[8];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_1000_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[8] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[8] << 8;
	temp2 = 65280 & temp2;
	context->gpr[6] = context->gpr[8] & 4294901760;
	context->gpr[6] = temp1 | context->gpr[6];
	context->gpr[6] = temp2 | context->gpr[6];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_1000_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[8] >> 16;
	context->gpr[6] = context->gpr[8] << 16;
	context->gpr[6] = temp | context->gpr[6];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_1000_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[8]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[6] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_1000_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[6] = -context->gpr[8];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_1000_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[6] = context->gpr[8] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_1000_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[6] = context->gpr[8] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_1000_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[6] = (context->gpr[6] & ~65535) | ((context->gpr[8] & 255) & 128 ? (context->gpr[8] & 255) | 65280 : (context->gpr[8] & 255));
	context->gpr[6] = (context->gpr[6] & 65535) & 32768 ? (context->gpr[6] & 65535) | 4294901760 : (context->gpr[6] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_1000_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[6] = (context->gpr[8] & 65535) & 32768 ? (context->gpr[8] & 65535) | 4294901760 : (context->gpr[8] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_1001_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[9] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[9], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[6] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_1001_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[9] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[9], context);
	context->gpr[6] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_1001_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[9] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[9], context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_1001_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[6] = context->gpr[9];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_1001_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[9] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[9], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[6] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[9] = 1 + context->gpr[9];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_1001_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[9] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[9], context);
	context->gpr[6] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[9] = 2 + context->gpr[9];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_1001_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[9] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[9], context);
	context->gpr[6] = context->scratch1;
	context->gpr[9] = 4 + context->gpr[9];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_1001_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[6] = ~context->gpr[9];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_1001_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[9] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[9] << 8;
	temp2 = 65280 & temp2;
	context->gpr[6] = context->gpr[9] & 4294901760;
	context->gpr[6] = temp1 | context->gpr[6];
	context->gpr[6] = temp2 | context->gpr[6];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_1001_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[9] >> 16;
	context->gpr[6] = context->gpr[9] << 16;
	context->gpr[6] = temp | context->gpr[6];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_1001_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[9]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[6] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_1001_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[6] = -context->gpr[9];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_1001_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[6] = context->gpr[9] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_1001_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[6] = context->gpr[9] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_1001_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[6] = (context->gpr[6] & ~65535) | ((context->gpr[9] & 255) & 128 ? (context->gpr[9] & 255) | 65280 : (context->gpr[9] & 255));
	context->gpr[6] = (context->gpr[6] & 65535) & 32768 ? (context->gpr[6] & 65535) | 4294901760 : (context->gpr[6] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_1001_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[6] = (context->gpr[9] & 65535) & 32768 ? (context->gpr[9] & 65535) | 4294901760 : (context->gpr[9] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_1010_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[10] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[10], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[6] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_1010_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[10] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[10], context);
	context->gpr[6] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_1010_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[10] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[10], context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_1010_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[6] = context->gpr[10];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_1010_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[10] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[10], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[6] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[10] = 1 + context->gpr[10];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_1010_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[10] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[10], context);
	context->gpr[6] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[10] = 2 + context->gpr[10];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_1010_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[10] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[10], context);
	context->gpr[6] = context->scratch1;
	context->gpr[10] = 4 + context->gpr[10];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_1010_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[6] = ~context->gpr[10];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_1010_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[10] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[10] << 8;
	temp2 = 65280 & temp2;
	context->gpr[6] = context->gpr[10] & 4294901760;
	context->gpr[6] = temp1 | context->gpr[6];
	context->gpr[6] = temp2 | context->gpr[6];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_1010_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[10] >> 16;
	context->gpr[6] = context->gpr[10] << 16;
	context->gpr[6] = temp | context->gpr[6];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_1010_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[10]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[6] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_1010_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[6] = -context->gpr[10];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_1010_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[6] = context->gpr[10] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_1010_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[6] = context->gpr[10] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_1010_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[6] = (context->gpr[6] & ~65535) | ((context->gpr[10] & 255) & 128 ? (context->gpr[10] & 255) | 65280 : (context->gpr[10] & 255));
	context->gpr[6] = (context->gpr[6] & 65535) & 32768 ? (context->gpr[6] & 65535) | 4294901760 : (context->gpr[6] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_1010_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[6] = (context->gpr[10] & 65535) & 32768 ? (context->gpr[10] & 65535) | 4294901760 : (context->gpr[10] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_1011_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[11] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[11], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[6] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_1011_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[11] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[11], context);
	context->gpr[6] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_1011_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[11] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[11], context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_1011_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[6] = context->gpr[11];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_1011_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[11] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[11], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[6] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[11] = 1 + context->gpr[11];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_1011_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[11] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[11], context);
	context->gpr[6] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[11] = 2 + context->gpr[11];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_1011_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[11] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[11], context);
	context->gpr[6] = context->scratch1;
	context->gpr[11] = 4 + context->gpr[11];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_1011_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[6] = ~context->gpr[11];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_1011_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[11] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[11] << 8;
	temp2 = 65280 & temp2;
	context->gpr[6] = context->gpr[11] & 4294901760;
	context->gpr[6] = temp1 | context->gpr[6];
	context->gpr[6] = temp2 | context->gpr[6];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_1011_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[11] >> 16;
	context->gpr[6] = context->gpr[11] << 16;
	context->gpr[6] = temp | context->gpr[6];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_1011_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[11]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[6] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_1011_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[6] = -context->gpr[11];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_1011_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[6] = context->gpr[11] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_1011_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[6] = context->gpr[11] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_1011_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[6] = (context->gpr[6] & ~65535) | ((context->gpr[11] & 255) & 128 ? (context->gpr[11] & 255) | 65280 : (context->gpr[11] & 255));
	context->gpr[6] = (context->gpr[6] & 65535) & 32768 ? (context->gpr[6] & 65535) | 4294901760 : (context->gpr[6] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_1011_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[6] = (context->gpr[11] & 65535) & 32768 ? (context->gpr[11] & 65535) | 4294901760 : (context->gpr[11] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_1100_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[12] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[12], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[6] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_1100_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[12] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[12], context);
	context->gpr[6] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_1100_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[12] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[12], context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_1100_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[6] = context->gpr[12];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_1100_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[12] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[12], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[6] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[12] = 1 + context->gpr[12];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_1100_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[12] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[12], context);
	context->gpr[6] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[12] = 2 + context->gpr[12];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_1100_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[12] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[12], context);
	context->gpr[6] = context->scratch1;
	context->gpr[12] = 4 + context->gpr[12];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_1100_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[6] = ~context->gpr[12];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_1100_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[12] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[12] << 8;
	temp2 = 65280 & temp2;
	context->gpr[6] = context->gpr[12] & 4294901760;
	context->gpr[6] = temp1 | context->gpr[6];
	context->gpr[6] = temp2 | context->gpr[6];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_1100_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[12] >> 16;
	context->gpr[6] = context->gpr[12] << 16;
	context->gpr[6] = temp | context->gpr[6];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_1100_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[12]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[6] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_1100_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[6] = -context->gpr[12];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_1100_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[6] = context->gpr[12] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_1100_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[6] = context->gpr[12] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_1100_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[6] = (context->gpr[6] & ~65535) | ((context->gpr[12] & 255) & 128 ? (context->gpr[12] & 255) | 65280 : (context->gpr[12] & 255));
	context->gpr[6] = (context->gpr[6] & 65535) & 32768 ? (context->gpr[6] & 65535) | 4294901760 : (context->gpr[6] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_1100_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[6] = (context->gpr[12] & 65535) & 32768 ? (context->gpr[12] & 65535) | 4294901760 : (context->gpr[12] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_1101_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[13] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[13], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[6] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_1101_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[13] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[13], context);
	context->gpr[6] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_1101_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[13] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[13], context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_1101_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[6] = context->gpr[13];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_1101_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[13] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[13], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[6] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[13] = 1 + context->gpr[13];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_1101_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[13] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[13], context);
	context->gpr[6] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[13] = 2 + context->gpr[13];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_1101_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[13] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[13], context);
	context->gpr[6] = context->scratch1;
	context->gpr[13] = 4 + context->gpr[13];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_1101_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[6] = ~context->gpr[13];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_1101_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[13] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[13] << 8;
	temp2 = 65280 & temp2;
	context->gpr[6] = context->gpr[13] & 4294901760;
	context->gpr[6] = temp1 | context->gpr[6];
	context->gpr[6] = temp2 | context->gpr[6];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_1101_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[13] >> 16;
	context->gpr[6] = context->gpr[13] << 16;
	context->gpr[6] = temp | context->gpr[6];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_1101_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[13]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[6] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_1101_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[6] = -context->gpr[13];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_1101_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[6] = context->gpr[13] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_1101_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[6] = context->gpr[13] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_1101_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[6] = (context->gpr[6] & ~65535) | ((context->gpr[13] & 255) & 128 ? (context->gpr[13] & 255) | 65280 : (context->gpr[13] & 255));
	context->gpr[6] = (context->gpr[6] & 65535) & 32768 ? (context->gpr[6] & 65535) | 4294901760 : (context->gpr[6] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_1101_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[6] = (context->gpr[13] & 65535) & 32768 ? (context->gpr[13] & 65535) | 4294901760 : (context->gpr[13] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_1110_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[14] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[14], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[6] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_1110_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[14] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[14], context);
	context->gpr[6] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_1110_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[14] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[14], context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_1110_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[6] = context->gpr[14];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_1110_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[14] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[14], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[6] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[14] = 1 + context->gpr[14];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_1110_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[14] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[14], context);
	context->gpr[6] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[14] = 2 + context->gpr[14];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_1110_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[14] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[14], context);
	context->gpr[6] = context->scratch1;
	context->gpr[14] = 4 + context->gpr[14];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_1110_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[6] = ~context->gpr[14];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_1110_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[14] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[14] << 8;
	temp2 = 65280 & temp2;
	context->gpr[6] = context->gpr[14] & 4294901760;
	context->gpr[6] = temp1 | context->gpr[6];
	context->gpr[6] = temp2 | context->gpr[6];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_1110_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[14] >> 16;
	context->gpr[6] = context->gpr[14] << 16;
	context->gpr[6] = temp | context->gpr[6];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_1110_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[14]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[6] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_1110_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[6] = -context->gpr[14];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_1110_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[6] = context->gpr[14] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_1110_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[6] = context->gpr[14] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_1110_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[6] = (context->gpr[6] & ~65535) | ((context->gpr[14] & 255) & 128 ? (context->gpr[14] & 255) | 65280 : (context->gpr[14] & 255));
	context->gpr[6] = (context->gpr[6] & 65535) & 32768 ? (context->gpr[6] & 65535) | 4294901760 : (context->gpr[6] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_1110_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[6] = (context->gpr[14] & 65535) & 32768 ? (context->gpr[14] & 65535) | 4294901760 : (context->gpr[14] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_1111_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[15] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[15], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[6] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_1111_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[15] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[15], context);
	context->gpr[6] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_1111_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[15] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[15], context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_1111_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[6] = context->gpr[15];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_1111_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[15] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[15], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[6] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[15] = 1 + context->gpr[15];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_1111_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[15] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[15], context);
	context->gpr[6] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[15] = 2 + context->gpr[15];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_1111_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[15] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[15], context);
	context->gpr[6] = context->scratch1;
	context->gpr[15] = 4 + context->gpr[15];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_1111_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[6] = ~context->gpr[15];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_1111_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[15] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[15] << 8;
	temp2 = 65280 & temp2;
	context->gpr[6] = context->gpr[15] & 4294901760;
	context->gpr[6] = temp1 | context->gpr[6];
	context->gpr[6] = temp2 | context->gpr[6];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_1111_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[15] >> 16;
	context->gpr[6] = context->gpr[15] << 16;
	context->gpr[6] = temp | context->gpr[6];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_1111_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[15]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[6] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_1111_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[6] = -context->gpr[15];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_1111_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[6] = context->gpr[15] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_1111_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[6] = context->gpr[15] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_1111_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[6] = (context->gpr[6] & ~65535) | ((context->gpr[15] & 255) & 128 ? (context->gpr[15] & 255) | 65280 : (context->gpr[15] & 255));
	context->gpr[6] = (context->gpr[6] & 65535) & 32768 ? (context->gpr[6] & 65535) | 4294901760 : (context->gpr[6] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_1111_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[6] = (context->gpr[15] & 65535) & 32768 ? (context->gpr[15] & 65535) | 4294901760 : (context->gpr[15] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_0000_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[0] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[0], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[7] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_0000_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[0] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[0], context);
	context->gpr[7] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_0000_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[0] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[0], context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_0000_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[7] = context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_0000_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[0] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[0], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[7] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[0] = 1 + context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_0000_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[0] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[0], context);
	context->gpr[7] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[0] = 2 + context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_0000_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[0] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[0], context);
	context->gpr[7] = context->scratch1;
	context->gpr[0] = 4 + context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_0000_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[7] = ~context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_0000_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[0] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[0] << 8;
	temp2 = 65280 & temp2;
	context->gpr[7] = context->gpr[0] & 4294901760;
	context->gpr[7] = temp1 | context->gpr[7];
	context->gpr[7] = temp2 | context->gpr[7];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_0000_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[0] >> 16;
	context->gpr[7] = context->gpr[0] << 16;
	context->gpr[7] = temp | context->gpr[7];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_0000_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[0]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[7] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_0000_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[7] = -context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_0000_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[7] = context->gpr[0] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_0000_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[7] = context->gpr[0] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_0000_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[7] = (context->gpr[7] & ~65535) | ((context->gpr[0] & 255) & 128 ? (context->gpr[0] & 255) | 65280 : (context->gpr[0] & 255));
	context->gpr[7] = (context->gpr[7] & 65535) & 32768 ? (context->gpr[7] & 65535) | 4294901760 : (context->gpr[7] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_0000_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[7] = (context->gpr[0] & 65535) & 32768 ? (context->gpr[0] & 65535) | 4294901760 : (context->gpr[0] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_0001_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[1] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[1], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[7] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_0001_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[1] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[1], context);
	context->gpr[7] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_0001_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[1] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[1], context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_0001_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[7] = context->gpr[1];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_0001_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[1] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[1], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[7] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[1] = 1 + context->gpr[1];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_0001_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[1] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[1], context);
	context->gpr[7] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[1] = 2 + context->gpr[1];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_0001_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[1] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[1], context);
	context->gpr[7] = context->scratch1;
	context->gpr[1] = 4 + context->gpr[1];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_0001_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[7] = ~context->gpr[1];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_0001_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[1] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[1] << 8;
	temp2 = 65280 & temp2;
	context->gpr[7] = context->gpr[1] & 4294901760;
	context->gpr[7] = temp1 | context->gpr[7];
	context->gpr[7] = temp2 | context->gpr[7];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_0001_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[1] >> 16;
	context->gpr[7] = context->gpr[1] << 16;
	context->gpr[7] = temp | context->gpr[7];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_0001_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[1]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[7] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_0001_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[7] = -context->gpr[1];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_0001_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[7] = context->gpr[1] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_0001_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[7] = context->gpr[1] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_0001_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[7] = (context->gpr[7] & ~65535) | ((context->gpr[1] & 255) & 128 ? (context->gpr[1] & 255) | 65280 : (context->gpr[1] & 255));
	context->gpr[7] = (context->gpr[7] & 65535) & 32768 ? (context->gpr[7] & 65535) | 4294901760 : (context->gpr[7] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_0001_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[7] = (context->gpr[1] & 65535) & 32768 ? (context->gpr[1] & 65535) | 4294901760 : (context->gpr[1] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_0010_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[2] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[2], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[7] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_0010_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[2] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[2], context);
	context->gpr[7] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_0010_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[2] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[2], context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_0010_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[7] = context->gpr[2];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_0010_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[2] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[2], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[7] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[2] = 1 + context->gpr[2];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_0010_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[2] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[2], context);
	context->gpr[7] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[2] = 2 + context->gpr[2];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_0010_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[2] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[2], context);
	context->gpr[7] = context->scratch1;
	context->gpr[2] = 4 + context->gpr[2];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_0010_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[7] = ~context->gpr[2];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_0010_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[2] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[2] << 8;
	temp2 = 65280 & temp2;
	context->gpr[7] = context->gpr[2] & 4294901760;
	context->gpr[7] = temp1 | context->gpr[7];
	context->gpr[7] = temp2 | context->gpr[7];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_0010_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[2] >> 16;
	context->gpr[7] = context->gpr[2] << 16;
	context->gpr[7] = temp | context->gpr[7];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_0010_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[2]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[7] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_0010_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[7] = -context->gpr[2];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_0010_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[7] = context->gpr[2] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_0010_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[7] = context->gpr[2] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_0010_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[7] = (context->gpr[7] & ~65535) | ((context->gpr[2] & 255) & 128 ? (context->gpr[2] & 255) | 65280 : (context->gpr[2] & 255));
	context->gpr[7] = (context->gpr[7] & 65535) & 32768 ? (context->gpr[7] & 65535) | 4294901760 : (context->gpr[7] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_0010_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[7] = (context->gpr[2] & 65535) & 32768 ? (context->gpr[2] & 65535) | 4294901760 : (context->gpr[2] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_0011_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[3] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[3], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[7] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_0011_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[3] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[3], context);
	context->gpr[7] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_0011_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[3] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[3], context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_0011_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[7] = context->gpr[3];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_0011_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[3] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[3], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[7] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[3] = 1 + context->gpr[3];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_0011_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[3] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[3], context);
	context->gpr[7] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[3] = 2 + context->gpr[3];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_0011_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[3] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[3], context);
	context->gpr[7] = context->scratch1;
	context->gpr[3] = 4 + context->gpr[3];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_0011_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[7] = ~context->gpr[3];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_0011_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[3] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[3] << 8;
	temp2 = 65280 & temp2;
	context->gpr[7] = context->gpr[3] & 4294901760;
	context->gpr[7] = temp1 | context->gpr[7];
	context->gpr[7] = temp2 | context->gpr[7];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_0011_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[3] >> 16;
	context->gpr[7] = context->gpr[3] << 16;
	context->gpr[7] = temp | context->gpr[7];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_0011_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[3]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[7] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_0011_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[7] = -context->gpr[3];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_0011_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[7] = context->gpr[3] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_0011_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[7] = context->gpr[3] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_0011_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[7] = (context->gpr[7] & ~65535) | ((context->gpr[3] & 255) & 128 ? (context->gpr[3] & 255) | 65280 : (context->gpr[3] & 255));
	context->gpr[7] = (context->gpr[7] & 65535) & 32768 ? (context->gpr[7] & 65535) | 4294901760 : (context->gpr[7] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_0011_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[7] = (context->gpr[3] & 65535) & 32768 ? (context->gpr[3] & 65535) | 4294901760 : (context->gpr[3] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_0100_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[4] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[4], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[7] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_0100_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[4] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[4], context);
	context->gpr[7] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_0100_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[4] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[4], context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_0100_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[7] = context->gpr[4];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_0100_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[4] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[4], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[7] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[4] = 1 + context->gpr[4];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_0100_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[4] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[4], context);
	context->gpr[7] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[4] = 2 + context->gpr[4];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_0100_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[4] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[4], context);
	context->gpr[7] = context->scratch1;
	context->gpr[4] = 4 + context->gpr[4];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_0100_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[7] = ~context->gpr[4];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_0100_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[4] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[4] << 8;
	temp2 = 65280 & temp2;
	context->gpr[7] = context->gpr[4] & 4294901760;
	context->gpr[7] = temp1 | context->gpr[7];
	context->gpr[7] = temp2 | context->gpr[7];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_0100_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[4] >> 16;
	context->gpr[7] = context->gpr[4] << 16;
	context->gpr[7] = temp | context->gpr[7];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_0100_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[4]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[7] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_0100_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[7] = -context->gpr[4];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_0100_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[7] = context->gpr[4] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_0100_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[7] = context->gpr[4] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_0100_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[7] = (context->gpr[7] & ~65535) | ((context->gpr[4] & 255) & 128 ? (context->gpr[4] & 255) | 65280 : (context->gpr[4] & 255));
	context->gpr[7] = (context->gpr[7] & 65535) & 32768 ? (context->gpr[7] & 65535) | 4294901760 : (context->gpr[7] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_0100_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[7] = (context->gpr[4] & 65535) & 32768 ? (context->gpr[4] & 65535) | 4294901760 : (context->gpr[4] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_0101_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[5] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[5], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[7] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_0101_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[5] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[5], context);
	context->gpr[7] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_0101_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[5] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[5], context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_0101_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[7] = context->gpr[5];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_0101_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[5] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[5], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[7] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[5] = 1 + context->gpr[5];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_0101_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[5] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[5], context);
	context->gpr[7] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[5] = 2 + context->gpr[5];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_0101_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[5] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[5], context);
	context->gpr[7] = context->scratch1;
	context->gpr[5] = 4 + context->gpr[5];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_0101_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[7] = ~context->gpr[5];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_0101_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[5] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[5] << 8;
	temp2 = 65280 & temp2;
	context->gpr[7] = context->gpr[5] & 4294901760;
	context->gpr[7] = temp1 | context->gpr[7];
	context->gpr[7] = temp2 | context->gpr[7];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_0101_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[5] >> 16;
	context->gpr[7] = context->gpr[5] << 16;
	context->gpr[7] = temp | context->gpr[7];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_0101_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[5]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[7] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_0101_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[7] = -context->gpr[5];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_0101_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[7] = context->gpr[5] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_0101_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[7] = context->gpr[5] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_0101_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[7] = (context->gpr[7] & ~65535) | ((context->gpr[5] & 255) & 128 ? (context->gpr[5] & 255) | 65280 : (context->gpr[5] & 255));
	context->gpr[7] = (context->gpr[7] & 65535) & 32768 ? (context->gpr[7] & 65535) | 4294901760 : (context->gpr[7] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_0101_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[7] = (context->gpr[5] & 65535) & 32768 ? (context->gpr[5] & 65535) | 4294901760 : (context->gpr[5] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_0110_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[6] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[6], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[7] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_0110_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[6] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[6], context);
	context->gpr[7] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_0110_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[6] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[6], context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_0110_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[7] = context->gpr[6];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_0110_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[6] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[6], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[7] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[6] = 1 + context->gpr[6];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_0110_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[6] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[6], context);
	context->gpr[7] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[6] = 2 + context->gpr[6];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_0110_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[6] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[6], context);
	context->gpr[7] = context->scratch1;
	context->gpr[6] = 4 + context->gpr[6];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_0110_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[7] = ~context->gpr[6];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_0110_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[6] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[6] << 8;
	temp2 = 65280 & temp2;
	context->gpr[7] = context->gpr[6] & 4294901760;
	context->gpr[7] = temp1 | context->gpr[7];
	context->gpr[7] = temp2 | context->gpr[7];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_0110_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[6] >> 16;
	context->gpr[7] = context->gpr[6] << 16;
	context->gpr[7] = temp | context->gpr[7];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_0110_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[6]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[7] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_0110_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[7] = -context->gpr[6];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_0110_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[7] = context->gpr[6] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_0110_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[7] = context->gpr[6] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_0110_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[7] = (context->gpr[7] & ~65535) | ((context->gpr[6] & 255) & 128 ? (context->gpr[6] & 255) | 65280 : (context->gpr[6] & 255));
	context->gpr[7] = (context->gpr[7] & 65535) & 32768 ? (context->gpr[7] & 65535) | 4294901760 : (context->gpr[7] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_0110_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[7] = (context->gpr[6] & 65535) & 32768 ? (context->gpr[6] & 65535) | 4294901760 : (context->gpr[6] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_0111_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[7] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[7], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[7] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_0111_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[7] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[7], context);
	context->gpr[7] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_0111_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[7] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[7], context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_0111_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[7] = context->gpr[7];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_0111_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[7] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[7], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[7] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_0111_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[7] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[7], context);
	context->gpr[7] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_0111_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[7] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[7], context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_0111_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[7] = ~context->gpr[7];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_0111_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[7] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[7] << 8;
	temp2 = 65280 & temp2;
	context->gpr[7] = context->gpr[7] & 4294901760;
	context->gpr[7] = temp1 | context->gpr[7];
	context->gpr[7] = temp2 | context->gpr[7];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_0111_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[7] >> 16;
	context->gpr[7] = context->gpr[7] << 16;
	context->gpr[7] = temp | context->gpr[7];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_0111_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[7]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[7] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_0111_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[7] = -context->gpr[7];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_0111_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[7] = context->gpr[7] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_0111_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[7] = context->gpr[7] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_0111_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[7] = (context->gpr[7] & ~65535) | ((context->gpr[7] & 255) & 128 ? (context->gpr[7] & 255) | 65280 : (context->gpr[7] & 255));
	context->gpr[7] = (context->gpr[7] & 65535) & 32768 ? (context->gpr[7] & 65535) | 4294901760 : (context->gpr[7] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_0111_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[7] = (context->gpr[7] & 65535) & 32768 ? (context->gpr[7] & 65535) | 4294901760 : (context->gpr[7] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_1000_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[8] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[8], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[7] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_1000_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[8] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[8], context);
	context->gpr[7] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_1000_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[8] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[8], context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_1000_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[7] = context->gpr[8];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_1000_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[8] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[8], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[7] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[8] = 1 + context->gpr[8];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_1000_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[8] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[8], context);
	context->gpr[7] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[8] = 2 + context->gpr[8];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_1000_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[8] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[8], context);
	context->gpr[7] = context->scratch1;
	context->gpr[8] = 4 + context->gpr[8];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_1000_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[7] = ~context->gpr[8];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_1000_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[8] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[8] << 8;
	temp2 = 65280 & temp2;
	context->gpr[7] = context->gpr[8] & 4294901760;
	context->gpr[7] = temp1 | context->gpr[7];
	context->gpr[7] = temp2 | context->gpr[7];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_1000_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[8] >> 16;
	context->gpr[7] = context->gpr[8] << 16;
	context->gpr[7] = temp | context->gpr[7];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_1000_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[8]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[7] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_1000_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[7] = -context->gpr[8];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_1000_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[7] = context->gpr[8] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_1000_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[7] = context->gpr[8] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_1000_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[7] = (context->gpr[7] & ~65535) | ((context->gpr[8] & 255) & 128 ? (context->gpr[8] & 255) | 65280 : (context->gpr[8] & 255));
	context->gpr[7] = (context->gpr[7] & 65535) & 32768 ? (context->gpr[7] & 65535) | 4294901760 : (context->gpr[7] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_1000_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[7] = (context->gpr[8] & 65535) & 32768 ? (context->gpr[8] & 65535) | 4294901760 : (context->gpr[8] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_1001_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[9] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[9], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[7] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_1001_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[9] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[9], context);
	context->gpr[7] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_1001_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[9] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[9], context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_1001_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[7] = context->gpr[9];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_1001_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[9] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[9], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[7] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[9] = 1 + context->gpr[9];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_1001_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[9] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[9], context);
	context->gpr[7] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[9] = 2 + context->gpr[9];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_1001_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[9] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[9], context);
	context->gpr[7] = context->scratch1;
	context->gpr[9] = 4 + context->gpr[9];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_1001_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[7] = ~context->gpr[9];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_1001_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[9] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[9] << 8;
	temp2 = 65280 & temp2;
	context->gpr[7] = context->gpr[9] & 4294901760;
	context->gpr[7] = temp1 | context->gpr[7];
	context->gpr[7] = temp2 | context->gpr[7];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_1001_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[9] >> 16;
	context->gpr[7] = context->gpr[9] << 16;
	context->gpr[7] = temp | context->gpr[7];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_1001_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[9]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[7] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_1001_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[7] = -context->gpr[9];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_1001_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[7] = context->gpr[9] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_1001_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[7] = context->gpr[9] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_1001_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[7] = (context->gpr[7] & ~65535) | ((context->gpr[9] & 255) & 128 ? (context->gpr[9] & 255) | 65280 : (context->gpr[9] & 255));
	context->gpr[7] = (context->gpr[7] & 65535) & 32768 ? (context->gpr[7] & 65535) | 4294901760 : (context->gpr[7] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_1001_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[7] = (context->gpr[9] & 65535) & 32768 ? (context->gpr[9] & 65535) | 4294901760 : (context->gpr[9] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_1010_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[10] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[10], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[7] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_1010_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[10] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[10], context);
	context->gpr[7] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_1010_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[10] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[10], context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_1010_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[7] = context->gpr[10];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_1010_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[10] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[10], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[7] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[10] = 1 + context->gpr[10];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_1010_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[10] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[10], context);
	context->gpr[7] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[10] = 2 + context->gpr[10];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_1010_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[10] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[10], context);
	context->gpr[7] = context->scratch1;
	context->gpr[10] = 4 + context->gpr[10];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_1010_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[7] = ~context->gpr[10];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_1010_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[10] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[10] << 8;
	temp2 = 65280 & temp2;
	context->gpr[7] = context->gpr[10] & 4294901760;
	context->gpr[7] = temp1 | context->gpr[7];
	context->gpr[7] = temp2 | context->gpr[7];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_1010_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[10] >> 16;
	context->gpr[7] = context->gpr[10] << 16;
	context->gpr[7] = temp | context->gpr[7];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_1010_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[10]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[7] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_1010_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[7] = -context->gpr[10];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_1010_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[7] = context->gpr[10] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_1010_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[7] = context->gpr[10] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_1010_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[7] = (context->gpr[7] & ~65535) | ((context->gpr[10] & 255) & 128 ? (context->gpr[10] & 255) | 65280 : (context->gpr[10] & 255));
	context->gpr[7] = (context->gpr[7] & 65535) & 32768 ? (context->gpr[7] & 65535) | 4294901760 : (context->gpr[7] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_1010_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[7] = (context->gpr[10] & 65535) & 32768 ? (context->gpr[10] & 65535) | 4294901760 : (context->gpr[10] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_1011_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[11] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[11], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[7] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_1011_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[11] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[11], context);
	context->gpr[7] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_1011_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[11] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[11], context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_1011_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[7] = context->gpr[11];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_1011_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[11] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[11], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[7] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[11] = 1 + context->gpr[11];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_1011_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[11] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[11], context);
	context->gpr[7] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[11] = 2 + context->gpr[11];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_1011_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[11] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[11], context);
	context->gpr[7] = context->scratch1;
	context->gpr[11] = 4 + context->gpr[11];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_1011_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[7] = ~context->gpr[11];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_1011_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[11] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[11] << 8;
	temp2 = 65280 & temp2;
	context->gpr[7] = context->gpr[11] & 4294901760;
	context->gpr[7] = temp1 | context->gpr[7];
	context->gpr[7] = temp2 | context->gpr[7];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_1011_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[11] >> 16;
	context->gpr[7] = context->gpr[11] << 16;
	context->gpr[7] = temp | context->gpr[7];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_1011_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[11]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[7] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_1011_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[7] = -context->gpr[11];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_1011_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[7] = context->gpr[11] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_1011_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[7] = context->gpr[11] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_1011_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[7] = (context->gpr[7] & ~65535) | ((context->gpr[11] & 255) & 128 ? (context->gpr[11] & 255) | 65280 : (context->gpr[11] & 255));
	context->gpr[7] = (context->gpr[7] & 65535) & 32768 ? (context->gpr[7] & 65535) | 4294901760 : (context->gpr[7] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_1011_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[7] = (context->gpr[11] & 65535) & 32768 ? (context->gpr[11] & 65535) | 4294901760 : (context->gpr[11] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_1100_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[12] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[12], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[7] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_1100_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[12] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[12], context);
	context->gpr[7] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_1100_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[12] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[12], context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_1100_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[7] = context->gpr[12];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_1100_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[12] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[12], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[7] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[12] = 1 + context->gpr[12];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_1100_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[12] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[12], context);
	context->gpr[7] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[12] = 2 + context->gpr[12];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_1100_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[12] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[12], context);
	context->gpr[7] = context->scratch1;
	context->gpr[12] = 4 + context->gpr[12];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_1100_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[7] = ~context->gpr[12];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_1100_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[12] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[12] << 8;
	temp2 = 65280 & temp2;
	context->gpr[7] = context->gpr[12] & 4294901760;
	context->gpr[7] = temp1 | context->gpr[7];
	context->gpr[7] = temp2 | context->gpr[7];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_1100_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[12] >> 16;
	context->gpr[7] = context->gpr[12] << 16;
	context->gpr[7] = temp | context->gpr[7];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_1100_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[12]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[7] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_1100_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[7] = -context->gpr[12];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_1100_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[7] = context->gpr[12] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_1100_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[7] = context->gpr[12] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_1100_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[7] = (context->gpr[7] & ~65535) | ((context->gpr[12] & 255) & 128 ? (context->gpr[12] & 255) | 65280 : (context->gpr[12] & 255));
	context->gpr[7] = (context->gpr[7] & 65535) & 32768 ? (context->gpr[7] & 65535) | 4294901760 : (context->gpr[7] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_1100_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[7] = (context->gpr[12] & 65535) & 32768 ? (context->gpr[12] & 65535) | 4294901760 : (context->gpr[12] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_1101_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[13] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[13], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[7] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_1101_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[13] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[13], context);
	context->gpr[7] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_1101_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[13] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[13], context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_1101_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[7] = context->gpr[13];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_1101_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[13] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[13], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[7] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[13] = 1 + context->gpr[13];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_1101_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[13] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[13], context);
	context->gpr[7] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[13] = 2 + context->gpr[13];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_1101_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[13] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[13], context);
	context->gpr[7] = context->scratch1;
	context->gpr[13] = 4 + context->gpr[13];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_1101_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[7] = ~context->gpr[13];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_1101_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[13] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[13] << 8;
	temp2 = 65280 & temp2;
	context->gpr[7] = context->gpr[13] & 4294901760;
	context->gpr[7] = temp1 | context->gpr[7];
	context->gpr[7] = temp2 | context->gpr[7];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_1101_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[13] >> 16;
	context->gpr[7] = context->gpr[13] << 16;
	context->gpr[7] = temp | context->gpr[7];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_1101_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[13]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[7] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_1101_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[7] = -context->gpr[13];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_1101_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[7] = context->gpr[13] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_1101_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[7] = context->gpr[13] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_1101_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[7] = (context->gpr[7] & ~65535) | ((context->gpr[13] & 255) & 128 ? (context->gpr[13] & 255) | 65280 : (context->gpr[13] & 255));
	context->gpr[7] = (context->gpr[7] & 65535) & 32768 ? (context->gpr[7] & 65535) | 4294901760 : (context->gpr[7] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_1101_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[7] = (context->gpr[13] & 65535) & 32768 ? (context->gpr[13] & 65535) | 4294901760 : (context->gpr[13] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_1110_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[14] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[14], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[7] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_1110_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[14] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[14], context);
	context->gpr[7] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_1110_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[14] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[14], context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_1110_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[7] = context->gpr[14];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_1110_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[14] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[14], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[7] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[14] = 1 + context->gpr[14];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_1110_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[14] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[14], context);
	context->gpr[7] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[14] = 2 + context->gpr[14];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_1110_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[14] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[14], context);
	context->gpr[7] = context->scratch1;
	context->gpr[14] = 4 + context->gpr[14];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_1110_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[7] = ~context->gpr[14];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_1110_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[14] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[14] << 8;
	temp2 = 65280 & temp2;
	context->gpr[7] = context->gpr[14] & 4294901760;
	context->gpr[7] = temp1 | context->gpr[7];
	context->gpr[7] = temp2 | context->gpr[7];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_1110_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[14] >> 16;
	context->gpr[7] = context->gpr[14] << 16;
	context->gpr[7] = temp | context->gpr[7];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_1110_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[14]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[7] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_1110_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[7] = -context->gpr[14];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_1110_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[7] = context->gpr[14] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_1110_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[7] = context->gpr[14] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_1110_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[7] = (context->gpr[7] & ~65535) | ((context->gpr[14] & 255) & 128 ? (context->gpr[14] & 255) | 65280 : (context->gpr[14] & 255));
	context->gpr[7] = (context->gpr[7] & 65535) & 32768 ? (context->gpr[7] & 65535) | 4294901760 : (context->gpr[7] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_1110_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[7] = (context->gpr[14] & 65535) & 32768 ? (context->gpr[14] & 65535) | 4294901760 : (context->gpr[14] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_1111_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[15] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[15], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[7] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_1111_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[15] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[15], context);
	context->gpr[7] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_1111_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[15] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[15], context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_1111_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[7] = context->gpr[15];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_1111_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[15] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[15], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[7] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[15] = 1 + context->gpr[15];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_1111_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[15] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[15], context);
	context->gpr[7] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[15] = 2 + context->gpr[15];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_1111_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[15] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[15], context);
	context->gpr[7] = context->scratch1;
	context->gpr[15] = 4 + context->gpr[15];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_1111_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[7] = ~context->gpr[15];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_1111_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[15] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[15] << 8;
	temp2 = 65280 & temp2;
	context->gpr[7] = context->gpr[15] & 4294901760;
	context->gpr[7] = temp1 | context->gpr[7];
	context->gpr[7] = temp2 | context->gpr[7];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_1111_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[15] >> 16;
	context->gpr[7] = context->gpr[15] << 16;
	context->gpr[7] = temp | context->gpr[7];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_1111_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[15]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[7] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_1111_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[7] = -context->gpr[15];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_1111_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[7] = context->gpr[15] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_1111_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[7] = context->gpr[15] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_1111_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[7] = (context->gpr[7] & ~65535) | ((context->gpr[15] & 255) & 128 ? (context->gpr[15] & 255) | 65280 : (context->gpr[15] & 255));
	context->gpr[7] = (context->gpr[7] & 65535) & 32768 ? (context->gpr[7] & 65535) | 4294901760 : (context->gpr[7] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_1111_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[7] = (context->gpr[15] & 65535) & 32768 ? (context->gpr[15] & 65535) | 4294901760 : (context->gpr[15] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_0000_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[0] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[0], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[8] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_0000_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[0] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[0], context);
	context->gpr[8] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_0000_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[0] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[0], context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_0000_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[8] = context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_0000_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[0] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[0], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[8] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[0] = 1 + context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_0000_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[0] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[0], context);
	context->gpr[8] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[0] = 2 + context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_0000_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[0] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[0], context);
	context->gpr[8] = context->scratch1;
	context->gpr[0] = 4 + context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_0000_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[8] = ~context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_0000_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[0] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[0] << 8;
	temp2 = 65280 & temp2;
	context->gpr[8] = context->gpr[0] & 4294901760;
	context->gpr[8] = temp1 | context->gpr[8];
	context->gpr[8] = temp2 | context->gpr[8];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_0000_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[0] >> 16;
	context->gpr[8] = context->gpr[0] << 16;
	context->gpr[8] = temp | context->gpr[8];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_0000_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[0]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[8] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_0000_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[8] = -context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_0000_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[8] = context->gpr[0] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_0000_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[8] = context->gpr[0] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_0000_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[8] = (context->gpr[8] & ~65535) | ((context->gpr[0] & 255) & 128 ? (context->gpr[0] & 255) | 65280 : (context->gpr[0] & 255));
	context->gpr[8] = (context->gpr[8] & 65535) & 32768 ? (context->gpr[8] & 65535) | 4294901760 : (context->gpr[8] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_0000_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[8] = (context->gpr[0] & 65535) & 32768 ? (context->gpr[0] & 65535) | 4294901760 : (context->gpr[0] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_0001_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[1] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[1], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[8] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_0001_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[1] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[1], context);
	context->gpr[8] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_0001_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[1] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[1], context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_0001_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[8] = context->gpr[1];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_0001_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[1] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[1], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[8] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[1] = 1 + context->gpr[1];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_0001_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[1] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[1], context);
	context->gpr[8] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[1] = 2 + context->gpr[1];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_0001_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[1] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[1], context);
	context->gpr[8] = context->scratch1;
	context->gpr[1] = 4 + context->gpr[1];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_0001_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[8] = ~context->gpr[1];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_0001_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[1] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[1] << 8;
	temp2 = 65280 & temp2;
	context->gpr[8] = context->gpr[1] & 4294901760;
	context->gpr[8] = temp1 | context->gpr[8];
	context->gpr[8] = temp2 | context->gpr[8];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_0001_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[1] >> 16;
	context->gpr[8] = context->gpr[1] << 16;
	context->gpr[8] = temp | context->gpr[8];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_0001_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[1]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[8] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_0001_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[8] = -context->gpr[1];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_0001_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[8] = context->gpr[1] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_0001_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[8] = context->gpr[1] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_0001_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[8] = (context->gpr[8] & ~65535) | ((context->gpr[1] & 255) & 128 ? (context->gpr[1] & 255) | 65280 : (context->gpr[1] & 255));
	context->gpr[8] = (context->gpr[8] & 65535) & 32768 ? (context->gpr[8] & 65535) | 4294901760 : (context->gpr[8] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_0001_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[8] = (context->gpr[1] & 65535) & 32768 ? (context->gpr[1] & 65535) | 4294901760 : (context->gpr[1] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_0010_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[2] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[2], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[8] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_0010_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[2] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[2], context);
	context->gpr[8] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_0010_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[2] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[2], context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_0010_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[8] = context->gpr[2];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_0010_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[2] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[2], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[8] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[2] = 1 + context->gpr[2];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_0010_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[2] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[2], context);
	context->gpr[8] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[2] = 2 + context->gpr[2];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_0010_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[2] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[2], context);
	context->gpr[8] = context->scratch1;
	context->gpr[2] = 4 + context->gpr[2];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_0010_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[8] = ~context->gpr[2];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_0010_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[2] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[2] << 8;
	temp2 = 65280 & temp2;
	context->gpr[8] = context->gpr[2] & 4294901760;
	context->gpr[8] = temp1 | context->gpr[8];
	context->gpr[8] = temp2 | context->gpr[8];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_0010_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[2] >> 16;
	context->gpr[8] = context->gpr[2] << 16;
	context->gpr[8] = temp | context->gpr[8];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_0010_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[2]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[8] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_0010_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[8] = -context->gpr[2];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_0010_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[8] = context->gpr[2] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_0010_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[8] = context->gpr[2] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_0010_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[8] = (context->gpr[8] & ~65535) | ((context->gpr[2] & 255) & 128 ? (context->gpr[2] & 255) | 65280 : (context->gpr[2] & 255));
	context->gpr[8] = (context->gpr[8] & 65535) & 32768 ? (context->gpr[8] & 65535) | 4294901760 : (context->gpr[8] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_0010_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[8] = (context->gpr[2] & 65535) & 32768 ? (context->gpr[2] & 65535) | 4294901760 : (context->gpr[2] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_0011_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[3] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[3], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[8] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_0011_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[3] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[3], context);
	context->gpr[8] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_0011_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[3] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[3], context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_0011_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[8] = context->gpr[3];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_0011_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[3] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[3], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[8] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[3] = 1 + context->gpr[3];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_0011_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[3] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[3], context);
	context->gpr[8] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[3] = 2 + context->gpr[3];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_0011_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[3] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[3], context);
	context->gpr[8] = context->scratch1;
	context->gpr[3] = 4 + context->gpr[3];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_0011_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[8] = ~context->gpr[3];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_0011_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[3] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[3] << 8;
	temp2 = 65280 & temp2;
	context->gpr[8] = context->gpr[3] & 4294901760;
	context->gpr[8] = temp1 | context->gpr[8];
	context->gpr[8] = temp2 | context->gpr[8];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_0011_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[3] >> 16;
	context->gpr[8] = context->gpr[3] << 16;
	context->gpr[8] = temp | context->gpr[8];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_0011_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[3]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[8] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_0011_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[8] = -context->gpr[3];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_0011_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[8] = context->gpr[3] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_0011_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[8] = context->gpr[3] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_0011_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[8] = (context->gpr[8] & ~65535) | ((context->gpr[3] & 255) & 128 ? (context->gpr[3] & 255) | 65280 : (context->gpr[3] & 255));
	context->gpr[8] = (context->gpr[8] & 65535) & 32768 ? (context->gpr[8] & 65535) | 4294901760 : (context->gpr[8] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_0011_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[8] = (context->gpr[3] & 65535) & 32768 ? (context->gpr[3] & 65535) | 4294901760 : (context->gpr[3] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_0100_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[4] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[4], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[8] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_0100_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[4] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[4], context);
	context->gpr[8] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_0100_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[4] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[4], context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_0100_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[8] = context->gpr[4];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_0100_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[4] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[4], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[8] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[4] = 1 + context->gpr[4];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_0100_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[4] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[4], context);
	context->gpr[8] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[4] = 2 + context->gpr[4];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_0100_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[4] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[4], context);
	context->gpr[8] = context->scratch1;
	context->gpr[4] = 4 + context->gpr[4];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_0100_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[8] = ~context->gpr[4];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_0100_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[4] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[4] << 8;
	temp2 = 65280 & temp2;
	context->gpr[8] = context->gpr[4] & 4294901760;
	context->gpr[8] = temp1 | context->gpr[8];
	context->gpr[8] = temp2 | context->gpr[8];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_0100_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[4] >> 16;
	context->gpr[8] = context->gpr[4] << 16;
	context->gpr[8] = temp | context->gpr[8];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_0100_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[4]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[8] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_0100_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[8] = -context->gpr[4];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_0100_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[8] = context->gpr[4] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_0100_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[8] = context->gpr[4] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_0100_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[8] = (context->gpr[8] & ~65535) | ((context->gpr[4] & 255) & 128 ? (context->gpr[4] & 255) | 65280 : (context->gpr[4] & 255));
	context->gpr[8] = (context->gpr[8] & 65535) & 32768 ? (context->gpr[8] & 65535) | 4294901760 : (context->gpr[8] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_0100_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[8] = (context->gpr[4] & 65535) & 32768 ? (context->gpr[4] & 65535) | 4294901760 : (context->gpr[4] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_0101_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[5] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[5], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[8] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_0101_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[5] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[5], context);
	context->gpr[8] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_0101_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[5] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[5], context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_0101_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[8] = context->gpr[5];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_0101_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[5] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[5], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[8] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[5] = 1 + context->gpr[5];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_0101_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[5] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[5], context);
	context->gpr[8] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[5] = 2 + context->gpr[5];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_0101_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[5] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[5], context);
	context->gpr[8] = context->scratch1;
	context->gpr[5] = 4 + context->gpr[5];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_0101_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[8] = ~context->gpr[5];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_0101_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[5] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[5] << 8;
	temp2 = 65280 & temp2;
	context->gpr[8] = context->gpr[5] & 4294901760;
	context->gpr[8] = temp1 | context->gpr[8];
	context->gpr[8] = temp2 | context->gpr[8];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_0101_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[5] >> 16;
	context->gpr[8] = context->gpr[5] << 16;
	context->gpr[8] = temp | context->gpr[8];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_0101_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[5]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[8] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_0101_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[8] = -context->gpr[5];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_0101_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[8] = context->gpr[5] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_0101_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[8] = context->gpr[5] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_0101_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[8] = (context->gpr[8] & ~65535) | ((context->gpr[5] & 255) & 128 ? (context->gpr[5] & 255) | 65280 : (context->gpr[5] & 255));
	context->gpr[8] = (context->gpr[8] & 65535) & 32768 ? (context->gpr[8] & 65535) | 4294901760 : (context->gpr[8] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_0101_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[8] = (context->gpr[5] & 65535) & 32768 ? (context->gpr[5] & 65535) | 4294901760 : (context->gpr[5] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_0110_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[6] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[6], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[8] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_0110_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[6] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[6], context);
	context->gpr[8] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_0110_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[6] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[6], context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_0110_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[8] = context->gpr[6];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_0110_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[6] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[6], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[8] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[6] = 1 + context->gpr[6];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_0110_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[6] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[6], context);
	context->gpr[8] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[6] = 2 + context->gpr[6];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_0110_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[6] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[6], context);
	context->gpr[8] = context->scratch1;
	context->gpr[6] = 4 + context->gpr[6];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_0110_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[8] = ~context->gpr[6];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_0110_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[6] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[6] << 8;
	temp2 = 65280 & temp2;
	context->gpr[8] = context->gpr[6] & 4294901760;
	context->gpr[8] = temp1 | context->gpr[8];
	context->gpr[8] = temp2 | context->gpr[8];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_0110_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[6] >> 16;
	context->gpr[8] = context->gpr[6] << 16;
	context->gpr[8] = temp | context->gpr[8];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_0110_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[6]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[8] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_0110_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[8] = -context->gpr[6];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_0110_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[8] = context->gpr[6] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_0110_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[8] = context->gpr[6] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_0110_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[8] = (context->gpr[8] & ~65535) | ((context->gpr[6] & 255) & 128 ? (context->gpr[6] & 255) | 65280 : (context->gpr[6] & 255));
	context->gpr[8] = (context->gpr[8] & 65535) & 32768 ? (context->gpr[8] & 65535) | 4294901760 : (context->gpr[8] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_0110_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[8] = (context->gpr[6] & 65535) & 32768 ? (context->gpr[6] & 65535) | 4294901760 : (context->gpr[6] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_0111_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[7] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[7], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[8] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_0111_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[7] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[7], context);
	context->gpr[8] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_0111_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[7] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[7], context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_0111_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[8] = context->gpr[7];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_0111_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[7] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[7], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[8] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[7] = 1 + context->gpr[7];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_0111_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[7] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[7], context);
	context->gpr[8] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[7] = 2 + context->gpr[7];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_0111_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[7] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[7], context);
	context->gpr[8] = context->scratch1;
	context->gpr[7] = 4 + context->gpr[7];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_0111_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[8] = ~context->gpr[7];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_0111_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[7] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[7] << 8;
	temp2 = 65280 & temp2;
	context->gpr[8] = context->gpr[7] & 4294901760;
	context->gpr[8] = temp1 | context->gpr[8];
	context->gpr[8] = temp2 | context->gpr[8];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_0111_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[7] >> 16;
	context->gpr[8] = context->gpr[7] << 16;
	context->gpr[8] = temp | context->gpr[8];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_0111_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[7]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[8] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_0111_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[8] = -context->gpr[7];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_0111_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[8] = context->gpr[7] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_0111_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[8] = context->gpr[7] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_0111_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[8] = (context->gpr[8] & ~65535) | ((context->gpr[7] & 255) & 128 ? (context->gpr[7] & 255) | 65280 : (context->gpr[7] & 255));
	context->gpr[8] = (context->gpr[8] & 65535) & 32768 ? (context->gpr[8] & 65535) | 4294901760 : (context->gpr[8] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_0111_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[8] = (context->gpr[7] & 65535) & 32768 ? (context->gpr[7] & 65535) | 4294901760 : (context->gpr[7] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_1000_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[8] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[8], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[8] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_1000_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[8] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[8], context);
	context->gpr[8] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_1000_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[8] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[8], context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_1000_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[8] = context->gpr[8];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_1000_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[8] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[8], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[8] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_1000_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[8] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[8], context);
	context->gpr[8] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_1000_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[8] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[8], context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_1000_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[8] = ~context->gpr[8];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_1000_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[8] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[8] << 8;
	temp2 = 65280 & temp2;
	context->gpr[8] = context->gpr[8] & 4294901760;
	context->gpr[8] = temp1 | context->gpr[8];
	context->gpr[8] = temp2 | context->gpr[8];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_1000_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[8] >> 16;
	context->gpr[8] = context->gpr[8] << 16;
	context->gpr[8] = temp | context->gpr[8];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_1000_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[8]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[8] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_1000_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[8] = -context->gpr[8];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_1000_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[8] = context->gpr[8] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_1000_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[8] = context->gpr[8] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_1000_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[8] = (context->gpr[8] & ~65535) | ((context->gpr[8] & 255) & 128 ? (context->gpr[8] & 255) | 65280 : (context->gpr[8] & 255));
	context->gpr[8] = (context->gpr[8] & 65535) & 32768 ? (context->gpr[8] & 65535) | 4294901760 : (context->gpr[8] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_1000_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[8] = (context->gpr[8] & 65535) & 32768 ? (context->gpr[8] & 65535) | 4294901760 : (context->gpr[8] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_1001_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[9] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[9], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[8] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_1001_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[9] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[9], context);
	context->gpr[8] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_1001_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[9] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[9], context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_1001_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[8] = context->gpr[9];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_1001_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[9] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[9], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[8] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[9] = 1 + context->gpr[9];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_1001_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[9] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[9], context);
	context->gpr[8] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[9] = 2 + context->gpr[9];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_1001_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[9] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[9], context);
	context->gpr[8] = context->scratch1;
	context->gpr[9] = 4 + context->gpr[9];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_1001_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[8] = ~context->gpr[9];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_1001_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[9] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[9] << 8;
	temp2 = 65280 & temp2;
	context->gpr[8] = context->gpr[9] & 4294901760;
	context->gpr[8] = temp1 | context->gpr[8];
	context->gpr[8] = temp2 | context->gpr[8];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_1001_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[9] >> 16;
	context->gpr[8] = context->gpr[9] << 16;
	context->gpr[8] = temp | context->gpr[8];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_1001_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[9]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[8] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_1001_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[8] = -context->gpr[9];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_1001_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[8] = context->gpr[9] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_1001_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[8] = context->gpr[9] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_1001_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[8] = (context->gpr[8] & ~65535) | ((context->gpr[9] & 255) & 128 ? (context->gpr[9] & 255) | 65280 : (context->gpr[9] & 255));
	context->gpr[8] = (context->gpr[8] & 65535) & 32768 ? (context->gpr[8] & 65535) | 4294901760 : (context->gpr[8] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_1001_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[8] = (context->gpr[9] & 65535) & 32768 ? (context->gpr[9] & 65535) | 4294901760 : (context->gpr[9] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_1010_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[10] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[10], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[8] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_1010_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[10] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[10], context);
	context->gpr[8] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_1010_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[10] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[10], context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_1010_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[8] = context->gpr[10];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_1010_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[10] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[10], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[8] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[10] = 1 + context->gpr[10];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_1010_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[10] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[10], context);
	context->gpr[8] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[10] = 2 + context->gpr[10];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_1010_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[10] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[10], context);
	context->gpr[8] = context->scratch1;
	context->gpr[10] = 4 + context->gpr[10];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_1010_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[8] = ~context->gpr[10];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_1010_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[10] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[10] << 8;
	temp2 = 65280 & temp2;
	context->gpr[8] = context->gpr[10] & 4294901760;
	context->gpr[8] = temp1 | context->gpr[8];
	context->gpr[8] = temp2 | context->gpr[8];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_1010_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[10] >> 16;
	context->gpr[8] = context->gpr[10] << 16;
	context->gpr[8] = temp | context->gpr[8];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_1010_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[10]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[8] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_1010_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[8] = -context->gpr[10];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_1010_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[8] = context->gpr[10] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_1010_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[8] = context->gpr[10] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_1010_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[8] = (context->gpr[8] & ~65535) | ((context->gpr[10] & 255) & 128 ? (context->gpr[10] & 255) | 65280 : (context->gpr[10] & 255));
	context->gpr[8] = (context->gpr[8] & 65535) & 32768 ? (context->gpr[8] & 65535) | 4294901760 : (context->gpr[8] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_1010_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[8] = (context->gpr[10] & 65535) & 32768 ? (context->gpr[10] & 65535) | 4294901760 : (context->gpr[10] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_1011_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[11] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[11], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[8] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_1011_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[11] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[11], context);
	context->gpr[8] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_1011_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[11] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[11], context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_1011_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[8] = context->gpr[11];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_1011_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[11] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[11], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[8] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[11] = 1 + context->gpr[11];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_1011_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[11] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[11], context);
	context->gpr[8] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[11] = 2 + context->gpr[11];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_1011_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[11] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[11], context);
	context->gpr[8] = context->scratch1;
	context->gpr[11] = 4 + context->gpr[11];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_1011_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[8] = ~context->gpr[11];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_1011_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[11] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[11] << 8;
	temp2 = 65280 & temp2;
	context->gpr[8] = context->gpr[11] & 4294901760;
	context->gpr[8] = temp1 | context->gpr[8];
	context->gpr[8] = temp2 | context->gpr[8];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_1011_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[11] >> 16;
	context->gpr[8] = context->gpr[11] << 16;
	context->gpr[8] = temp | context->gpr[8];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_1011_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[11]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[8] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_1011_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[8] = -context->gpr[11];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_1011_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[8] = context->gpr[11] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_1011_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[8] = context->gpr[11] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_1011_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[8] = (context->gpr[8] & ~65535) | ((context->gpr[11] & 255) & 128 ? (context->gpr[11] & 255) | 65280 : (context->gpr[11] & 255));
	context->gpr[8] = (context->gpr[8] & 65535) & 32768 ? (context->gpr[8] & 65535) | 4294901760 : (context->gpr[8] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_1011_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[8] = (context->gpr[11] & 65535) & 32768 ? (context->gpr[11] & 65535) | 4294901760 : (context->gpr[11] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_1100_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[12] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[12], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[8] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_1100_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[12] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[12], context);
	context->gpr[8] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_1100_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[12] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[12], context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_1100_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[8] = context->gpr[12];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_1100_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[12] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[12], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[8] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[12] = 1 + context->gpr[12];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_1100_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[12] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[12], context);
	context->gpr[8] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[12] = 2 + context->gpr[12];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_1100_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[12] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[12], context);
	context->gpr[8] = context->scratch1;
	context->gpr[12] = 4 + context->gpr[12];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_1100_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[8] = ~context->gpr[12];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_1100_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[12] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[12] << 8;
	temp2 = 65280 & temp2;
	context->gpr[8] = context->gpr[12] & 4294901760;
	context->gpr[8] = temp1 | context->gpr[8];
	context->gpr[8] = temp2 | context->gpr[8];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_1100_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[12] >> 16;
	context->gpr[8] = context->gpr[12] << 16;
	context->gpr[8] = temp | context->gpr[8];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_1100_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[12]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[8] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_1100_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[8] = -context->gpr[12];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_1100_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[8] = context->gpr[12] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_1100_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[8] = context->gpr[12] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_1100_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[8] = (context->gpr[8] & ~65535) | ((context->gpr[12] & 255) & 128 ? (context->gpr[12] & 255) | 65280 : (context->gpr[12] & 255));
	context->gpr[8] = (context->gpr[8] & 65535) & 32768 ? (context->gpr[8] & 65535) | 4294901760 : (context->gpr[8] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_1100_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[8] = (context->gpr[12] & 65535) & 32768 ? (context->gpr[12] & 65535) | 4294901760 : (context->gpr[12] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_1101_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[13] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[13], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[8] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_1101_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[13] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[13], context);
	context->gpr[8] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_1101_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[13] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[13], context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_1101_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[8] = context->gpr[13];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_1101_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[13] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[13], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[8] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[13] = 1 + context->gpr[13];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_1101_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[13] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[13], context);
	context->gpr[8] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[13] = 2 + context->gpr[13];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_1101_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[13] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[13], context);
	context->gpr[8] = context->scratch1;
	context->gpr[13] = 4 + context->gpr[13];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_1101_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[8] = ~context->gpr[13];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_1101_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[13] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[13] << 8;
	temp2 = 65280 & temp2;
	context->gpr[8] = context->gpr[13] & 4294901760;
	context->gpr[8] = temp1 | context->gpr[8];
	context->gpr[8] = temp2 | context->gpr[8];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_1101_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[13] >> 16;
	context->gpr[8] = context->gpr[13] << 16;
	context->gpr[8] = temp | context->gpr[8];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_1101_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[13]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[8] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_1101_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[8] = -context->gpr[13];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_1101_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[8] = context->gpr[13] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_1101_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[8] = context->gpr[13] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_1101_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[8] = (context->gpr[8] & ~65535) | ((context->gpr[13] & 255) & 128 ? (context->gpr[13] & 255) | 65280 : (context->gpr[13] & 255));
	context->gpr[8] = (context->gpr[8] & 65535) & 32768 ? (context->gpr[8] & 65535) | 4294901760 : (context->gpr[8] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_1101_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[8] = (context->gpr[13] & 65535) & 32768 ? (context->gpr[13] & 65535) | 4294901760 : (context->gpr[13] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_1110_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[14] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[14], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[8] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_1110_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[14] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[14], context);
	context->gpr[8] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_1110_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[14] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[14], context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_1110_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[8] = context->gpr[14];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_1110_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[14] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[14], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[8] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[14] = 1 + context->gpr[14];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_1110_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[14] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[14], context);
	context->gpr[8] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[14] = 2 + context->gpr[14];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_1110_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[14] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[14], context);
	context->gpr[8] = context->scratch1;
	context->gpr[14] = 4 + context->gpr[14];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_1110_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[8] = ~context->gpr[14];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_1110_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[14] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[14] << 8;
	temp2 = 65280 & temp2;
	context->gpr[8] = context->gpr[14] & 4294901760;
	context->gpr[8] = temp1 | context->gpr[8];
	context->gpr[8] = temp2 | context->gpr[8];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_1110_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[14] >> 16;
	context->gpr[8] = context->gpr[14] << 16;
	context->gpr[8] = temp | context->gpr[8];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_1110_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[14]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[8] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_1110_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[8] = -context->gpr[14];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_1110_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[8] = context->gpr[14] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_1110_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[8] = context->gpr[14] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_1110_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[8] = (context->gpr[8] & ~65535) | ((context->gpr[14] & 255) & 128 ? (context->gpr[14] & 255) | 65280 : (context->gpr[14] & 255));
	context->gpr[8] = (context->gpr[8] & 65535) & 32768 ? (context->gpr[8] & 65535) | 4294901760 : (context->gpr[8] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_1110_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[8] = (context->gpr[14] & 65535) & 32768 ? (context->gpr[14] & 65535) | 4294901760 : (context->gpr[14] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_1111_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[15] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[15], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[8] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_1111_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[15] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[15], context);
	context->gpr[8] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_1111_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[15] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[15], context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_1111_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[8] = context->gpr[15];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_1111_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[15] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[15], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[8] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[15] = 1 + context->gpr[15];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_1111_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[15] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[15], context);
	context->gpr[8] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[15] = 2 + context->gpr[15];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_1111_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[15] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[15], context);
	context->gpr[8] = context->scratch1;
	context->gpr[15] = 4 + context->gpr[15];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_1111_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[8] = ~context->gpr[15];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_1111_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[15] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[15] << 8;
	temp2 = 65280 & temp2;
	context->gpr[8] = context->gpr[15] & 4294901760;
	context->gpr[8] = temp1 | context->gpr[8];
	context->gpr[8] = temp2 | context->gpr[8];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_1111_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[15] >> 16;
	context->gpr[8] = context->gpr[15] << 16;
	context->gpr[8] = temp | context->gpr[8];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_1111_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[15]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[8] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_1111_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[8] = -context->gpr[15];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_1111_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[8] = context->gpr[15] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_1111_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[8] = context->gpr[15] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_1111_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[8] = (context->gpr[8] & ~65535) | ((context->gpr[15] & 255) & 128 ? (context->gpr[15] & 255) | 65280 : (context->gpr[15] & 255));
	context->gpr[8] = (context->gpr[8] & 65535) & 32768 ? (context->gpr[8] & 65535) | 4294901760 : (context->gpr[8] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_1111_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[8] = (context->gpr[15] & 65535) & 32768 ? (context->gpr[15] & 65535) | 4294901760 : (context->gpr[15] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_0000_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[0] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[0], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[9] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_0000_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[0] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[0], context);
	context->gpr[9] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_0000_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[0] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[0], context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_0000_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[9] = context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_0000_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[0] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[0], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[9] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[0] = 1 + context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_0000_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[0] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[0], context);
	context->gpr[9] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[0] = 2 + context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_0000_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[0] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[0], context);
	context->gpr[9] = context->scratch1;
	context->gpr[0] = 4 + context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_0000_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[9] = ~context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_0000_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[0] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[0] << 8;
	temp2 = 65280 & temp2;
	context->gpr[9] = context->gpr[0] & 4294901760;
	context->gpr[9] = temp1 | context->gpr[9];
	context->gpr[9] = temp2 | context->gpr[9];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_0000_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[0] >> 16;
	context->gpr[9] = context->gpr[0] << 16;
	context->gpr[9] = temp | context->gpr[9];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_0000_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[0]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[9] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_0000_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[9] = -context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_0000_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[9] = context->gpr[0] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_0000_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[9] = context->gpr[0] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_0000_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[9] = (context->gpr[9] & ~65535) | ((context->gpr[0] & 255) & 128 ? (context->gpr[0] & 255) | 65280 : (context->gpr[0] & 255));
	context->gpr[9] = (context->gpr[9] & 65535) & 32768 ? (context->gpr[9] & 65535) | 4294901760 : (context->gpr[9] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_0000_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[9] = (context->gpr[0] & 65535) & 32768 ? (context->gpr[0] & 65535) | 4294901760 : (context->gpr[0] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_0001_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[1] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[1], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[9] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_0001_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[1] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[1], context);
	context->gpr[9] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_0001_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[1] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[1], context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_0001_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[9] = context->gpr[1];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_0001_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[1] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[1], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[9] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[1] = 1 + context->gpr[1];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_0001_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[1] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[1], context);
	context->gpr[9] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[1] = 2 + context->gpr[1];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_0001_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[1] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[1], context);
	context->gpr[9] = context->scratch1;
	context->gpr[1] = 4 + context->gpr[1];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_0001_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[9] = ~context->gpr[1];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_0001_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[1] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[1] << 8;
	temp2 = 65280 & temp2;
	context->gpr[9] = context->gpr[1] & 4294901760;
	context->gpr[9] = temp1 | context->gpr[9];
	context->gpr[9] = temp2 | context->gpr[9];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_0001_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[1] >> 16;
	context->gpr[9] = context->gpr[1] << 16;
	context->gpr[9] = temp | context->gpr[9];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_0001_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[1]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[9] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_0001_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[9] = -context->gpr[1];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_0001_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[9] = context->gpr[1] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_0001_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[9] = context->gpr[1] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_0001_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[9] = (context->gpr[9] & ~65535) | ((context->gpr[1] & 255) & 128 ? (context->gpr[1] & 255) | 65280 : (context->gpr[1] & 255));
	context->gpr[9] = (context->gpr[9] & 65535) & 32768 ? (context->gpr[9] & 65535) | 4294901760 : (context->gpr[9] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_0001_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[9] = (context->gpr[1] & 65535) & 32768 ? (context->gpr[1] & 65535) | 4294901760 : (context->gpr[1] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_0010_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[2] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[2], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[9] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_0010_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[2] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[2], context);
	context->gpr[9] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_0010_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[2] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[2], context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_0010_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[9] = context->gpr[2];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_0010_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[2] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[2], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[9] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[2] = 1 + context->gpr[2];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_0010_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[2] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[2], context);
	context->gpr[9] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[2] = 2 + context->gpr[2];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_0010_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[2] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[2], context);
	context->gpr[9] = context->scratch1;
	context->gpr[2] = 4 + context->gpr[2];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_0010_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[9] = ~context->gpr[2];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_0010_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[2] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[2] << 8;
	temp2 = 65280 & temp2;
	context->gpr[9] = context->gpr[2] & 4294901760;
	context->gpr[9] = temp1 | context->gpr[9];
	context->gpr[9] = temp2 | context->gpr[9];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_0010_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[2] >> 16;
	context->gpr[9] = context->gpr[2] << 16;
	context->gpr[9] = temp | context->gpr[9];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_0010_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[2]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[9] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_0010_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[9] = -context->gpr[2];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_0010_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[9] = context->gpr[2] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_0010_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[9] = context->gpr[2] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_0010_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[9] = (context->gpr[9] & ~65535) | ((context->gpr[2] & 255) & 128 ? (context->gpr[2] & 255) | 65280 : (context->gpr[2] & 255));
	context->gpr[9] = (context->gpr[9] & 65535) & 32768 ? (context->gpr[9] & 65535) | 4294901760 : (context->gpr[9] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_0010_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[9] = (context->gpr[2] & 65535) & 32768 ? (context->gpr[2] & 65535) | 4294901760 : (context->gpr[2] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_0011_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[3] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[3], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[9] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_0011_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[3] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[3], context);
	context->gpr[9] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_0011_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[3] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[3], context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_0011_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[9] = context->gpr[3];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_0011_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[3] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[3], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[9] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[3] = 1 + context->gpr[3];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_0011_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[3] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[3], context);
	context->gpr[9] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[3] = 2 + context->gpr[3];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_0011_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[3] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[3], context);
	context->gpr[9] = context->scratch1;
	context->gpr[3] = 4 + context->gpr[3];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_0011_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[9] = ~context->gpr[3];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_0011_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[3] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[3] << 8;
	temp2 = 65280 & temp2;
	context->gpr[9] = context->gpr[3] & 4294901760;
	context->gpr[9] = temp1 | context->gpr[9];
	context->gpr[9] = temp2 | context->gpr[9];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_0011_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[3] >> 16;
	context->gpr[9] = context->gpr[3] << 16;
	context->gpr[9] = temp | context->gpr[9];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_0011_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[3]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[9] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_0011_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[9] = -context->gpr[3];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_0011_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[9] = context->gpr[3] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_0011_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[9] = context->gpr[3] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_0011_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[9] = (context->gpr[9] & ~65535) | ((context->gpr[3] & 255) & 128 ? (context->gpr[3] & 255) | 65280 : (context->gpr[3] & 255));
	context->gpr[9] = (context->gpr[9] & 65535) & 32768 ? (context->gpr[9] & 65535) | 4294901760 : (context->gpr[9] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_0011_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[9] = (context->gpr[3] & 65535) & 32768 ? (context->gpr[3] & 65535) | 4294901760 : (context->gpr[3] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_0100_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[4] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[4], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[9] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_0100_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[4] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[4], context);
	context->gpr[9] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_0100_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[4] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[4], context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_0100_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[9] = context->gpr[4];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_0100_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[4] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[4], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[9] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[4] = 1 + context->gpr[4];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_0100_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[4] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[4], context);
	context->gpr[9] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[4] = 2 + context->gpr[4];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_0100_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[4] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[4], context);
	context->gpr[9] = context->scratch1;
	context->gpr[4] = 4 + context->gpr[4];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_0100_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[9] = ~context->gpr[4];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_0100_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[4] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[4] << 8;
	temp2 = 65280 & temp2;
	context->gpr[9] = context->gpr[4] & 4294901760;
	context->gpr[9] = temp1 | context->gpr[9];
	context->gpr[9] = temp2 | context->gpr[9];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_0100_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[4] >> 16;
	context->gpr[9] = context->gpr[4] << 16;
	context->gpr[9] = temp | context->gpr[9];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_0100_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[4]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[9] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_0100_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[9] = -context->gpr[4];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_0100_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[9] = context->gpr[4] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_0100_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[9] = context->gpr[4] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_0100_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[9] = (context->gpr[9] & ~65535) | ((context->gpr[4] & 255) & 128 ? (context->gpr[4] & 255) | 65280 : (context->gpr[4] & 255));
	context->gpr[9] = (context->gpr[9] & 65535) & 32768 ? (context->gpr[9] & 65535) | 4294901760 : (context->gpr[9] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_0100_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[9] = (context->gpr[4] & 65535) & 32768 ? (context->gpr[4] & 65535) | 4294901760 : (context->gpr[4] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_0101_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[5] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[5], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[9] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_0101_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[5] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[5], context);
	context->gpr[9] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_0101_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[5] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[5], context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_0101_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[9] = context->gpr[5];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_0101_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[5] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[5], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[9] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[5] = 1 + context->gpr[5];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_0101_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[5] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[5], context);
	context->gpr[9] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[5] = 2 + context->gpr[5];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_0101_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[5] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[5], context);
	context->gpr[9] = context->scratch1;
	context->gpr[5] = 4 + context->gpr[5];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_0101_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[9] = ~context->gpr[5];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_0101_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[5] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[5] << 8;
	temp2 = 65280 & temp2;
	context->gpr[9] = context->gpr[5] & 4294901760;
	context->gpr[9] = temp1 | context->gpr[9];
	context->gpr[9] = temp2 | context->gpr[9];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_0101_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[5] >> 16;
	context->gpr[9] = context->gpr[5] << 16;
	context->gpr[9] = temp | context->gpr[9];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_0101_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[5]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[9] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_0101_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[9] = -context->gpr[5];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_0101_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[9] = context->gpr[5] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_0101_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[9] = context->gpr[5] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_0101_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[9] = (context->gpr[9] & ~65535) | ((context->gpr[5] & 255) & 128 ? (context->gpr[5] & 255) | 65280 : (context->gpr[5] & 255));
	context->gpr[9] = (context->gpr[9] & 65535) & 32768 ? (context->gpr[9] & 65535) | 4294901760 : (context->gpr[9] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_0101_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[9] = (context->gpr[5] & 65535) & 32768 ? (context->gpr[5] & 65535) | 4294901760 : (context->gpr[5] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_0110_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[6] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[6], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[9] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_0110_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[6] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[6], context);
	context->gpr[9] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_0110_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[6] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[6], context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_0110_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[9] = context->gpr[6];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_0110_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[6] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[6], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[9] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[6] = 1 + context->gpr[6];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_0110_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[6] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[6], context);
	context->gpr[9] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[6] = 2 + context->gpr[6];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_0110_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[6] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[6], context);
	context->gpr[9] = context->scratch1;
	context->gpr[6] = 4 + context->gpr[6];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_0110_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[9] = ~context->gpr[6];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_0110_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[6] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[6] << 8;
	temp2 = 65280 & temp2;
	context->gpr[9] = context->gpr[6] & 4294901760;
	context->gpr[9] = temp1 | context->gpr[9];
	context->gpr[9] = temp2 | context->gpr[9];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_0110_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[6] >> 16;
	context->gpr[9] = context->gpr[6] << 16;
	context->gpr[9] = temp | context->gpr[9];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_0110_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[6]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[9] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_0110_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[9] = -context->gpr[6];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_0110_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[9] = context->gpr[6] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_0110_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[9] = context->gpr[6] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_0110_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[9] = (context->gpr[9] & ~65535) | ((context->gpr[6] & 255) & 128 ? (context->gpr[6] & 255) | 65280 : (context->gpr[6] & 255));
	context->gpr[9] = (context->gpr[9] & 65535) & 32768 ? (context->gpr[9] & 65535) | 4294901760 : (context->gpr[9] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_0110_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[9] = (context->gpr[6] & 65535) & 32768 ? (context->gpr[6] & 65535) | 4294901760 : (context->gpr[6] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_0111_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[7] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[7], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[9] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_0111_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[7] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[7], context);
	context->gpr[9] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_0111_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[7] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[7], context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_0111_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[9] = context->gpr[7];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_0111_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[7] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[7], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[9] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[7] = 1 + context->gpr[7];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_0111_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[7] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[7], context);
	context->gpr[9] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[7] = 2 + context->gpr[7];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_0111_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[7] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[7], context);
	context->gpr[9] = context->scratch1;
	context->gpr[7] = 4 + context->gpr[7];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_0111_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[9] = ~context->gpr[7];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_0111_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[7] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[7] << 8;
	temp2 = 65280 & temp2;
	context->gpr[9] = context->gpr[7] & 4294901760;
	context->gpr[9] = temp1 | context->gpr[9];
	context->gpr[9] = temp2 | context->gpr[9];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_0111_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[7] >> 16;
	context->gpr[9] = context->gpr[7] << 16;
	context->gpr[9] = temp | context->gpr[9];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_0111_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[7]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[9] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_0111_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[9] = -context->gpr[7];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_0111_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[9] = context->gpr[7] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_0111_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[9] = context->gpr[7] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_0111_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[9] = (context->gpr[9] & ~65535) | ((context->gpr[7] & 255) & 128 ? (context->gpr[7] & 255) | 65280 : (context->gpr[7] & 255));
	context->gpr[9] = (context->gpr[9] & 65535) & 32768 ? (context->gpr[9] & 65535) | 4294901760 : (context->gpr[9] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_0111_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[9] = (context->gpr[7] & 65535) & 32768 ? (context->gpr[7] & 65535) | 4294901760 : (context->gpr[7] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_1000_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[8] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[8], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[9] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_1000_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[8] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[8], context);
	context->gpr[9] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_1000_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[8] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[8], context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_1000_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[9] = context->gpr[8];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_1000_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[8] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[8], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[9] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[8] = 1 + context->gpr[8];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_1000_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[8] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[8], context);
	context->gpr[9] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[8] = 2 + context->gpr[8];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_1000_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[8] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[8], context);
	context->gpr[9] = context->scratch1;
	context->gpr[8] = 4 + context->gpr[8];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_1000_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[9] = ~context->gpr[8];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_1000_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[8] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[8] << 8;
	temp2 = 65280 & temp2;
	context->gpr[9] = context->gpr[8] & 4294901760;
	context->gpr[9] = temp1 | context->gpr[9];
	context->gpr[9] = temp2 | context->gpr[9];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_1000_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[8] >> 16;
	context->gpr[9] = context->gpr[8] << 16;
	context->gpr[9] = temp | context->gpr[9];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_1000_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[8]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[9] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_1000_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[9] = -context->gpr[8];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_1000_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[9] = context->gpr[8] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_1000_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[9] = context->gpr[8] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_1000_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[9] = (context->gpr[9] & ~65535) | ((context->gpr[8] & 255) & 128 ? (context->gpr[8] & 255) | 65280 : (context->gpr[8] & 255));
	context->gpr[9] = (context->gpr[9] & 65535) & 32768 ? (context->gpr[9] & 65535) | 4294901760 : (context->gpr[9] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_1000_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[9] = (context->gpr[8] & 65535) & 32768 ? (context->gpr[8] & 65535) | 4294901760 : (context->gpr[8] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_1001_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[9] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[9], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[9] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_1001_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[9] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[9], context);
	context->gpr[9] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_1001_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[9] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[9], context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_1001_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[9] = context->gpr[9];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_1001_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[9] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[9], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[9] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_1001_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[9] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[9], context);
	context->gpr[9] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_1001_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[9] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[9], context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_1001_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[9] = ~context->gpr[9];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_1001_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[9] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[9] << 8;
	temp2 = 65280 & temp2;
	context->gpr[9] = context->gpr[9] & 4294901760;
	context->gpr[9] = temp1 | context->gpr[9];
	context->gpr[9] = temp2 | context->gpr[9];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_1001_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[9] >> 16;
	context->gpr[9] = context->gpr[9] << 16;
	context->gpr[9] = temp | context->gpr[9];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_1001_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[9]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[9] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_1001_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[9] = -context->gpr[9];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_1001_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[9] = context->gpr[9] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_1001_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[9] = context->gpr[9] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_1001_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[9] = (context->gpr[9] & ~65535) | ((context->gpr[9] & 255) & 128 ? (context->gpr[9] & 255) | 65280 : (context->gpr[9] & 255));
	context->gpr[9] = (context->gpr[9] & 65535) & 32768 ? (context->gpr[9] & 65535) | 4294901760 : (context->gpr[9] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_1001_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[9] = (context->gpr[9] & 65535) & 32768 ? (context->gpr[9] & 65535) | 4294901760 : (context->gpr[9] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_1010_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[10] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[10], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[9] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_1010_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[10] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[10], context);
	context->gpr[9] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_1010_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[10] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[10], context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_1010_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[9] = context->gpr[10];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_1010_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[10] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[10], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[9] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[10] = 1 + context->gpr[10];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_1010_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[10] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[10], context);
	context->gpr[9] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[10] = 2 + context->gpr[10];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_1010_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[10] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[10], context);
	context->gpr[9] = context->scratch1;
	context->gpr[10] = 4 + context->gpr[10];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_1010_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[9] = ~context->gpr[10];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_1010_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[10] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[10] << 8;
	temp2 = 65280 & temp2;
	context->gpr[9] = context->gpr[10] & 4294901760;
	context->gpr[9] = temp1 | context->gpr[9];
	context->gpr[9] = temp2 | context->gpr[9];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_1010_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[10] >> 16;
	context->gpr[9] = context->gpr[10] << 16;
	context->gpr[9] = temp | context->gpr[9];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_1010_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[10]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[9] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_1010_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[9] = -context->gpr[10];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_1010_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[9] = context->gpr[10] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_1010_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[9] = context->gpr[10] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_1010_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[9] = (context->gpr[9] & ~65535) | ((context->gpr[10] & 255) & 128 ? (context->gpr[10] & 255) | 65280 : (context->gpr[10] & 255));
	context->gpr[9] = (context->gpr[9] & 65535) & 32768 ? (context->gpr[9] & 65535) | 4294901760 : (context->gpr[9] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_1010_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[9] = (context->gpr[10] & 65535) & 32768 ? (context->gpr[10] & 65535) | 4294901760 : (context->gpr[10] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_1011_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[11] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[11], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[9] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_1011_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[11] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[11], context);
	context->gpr[9] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_1011_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[11] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[11], context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_1011_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[9] = context->gpr[11];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_1011_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[11] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[11], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[9] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[11] = 1 + context->gpr[11];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_1011_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[11] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[11], context);
	context->gpr[9] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[11] = 2 + context->gpr[11];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_1011_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[11] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[11], context);
	context->gpr[9] = context->scratch1;
	context->gpr[11] = 4 + context->gpr[11];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_1011_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[9] = ~context->gpr[11];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_1011_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[11] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[11] << 8;
	temp2 = 65280 & temp2;
	context->gpr[9] = context->gpr[11] & 4294901760;
	context->gpr[9] = temp1 | context->gpr[9];
	context->gpr[9] = temp2 | context->gpr[9];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_1011_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[11] >> 16;
	context->gpr[9] = context->gpr[11] << 16;
	context->gpr[9] = temp | context->gpr[9];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_1011_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[11]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[9] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_1011_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[9] = -context->gpr[11];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_1011_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[9] = context->gpr[11] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_1011_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[9] = context->gpr[11] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_1011_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[9] = (context->gpr[9] & ~65535) | ((context->gpr[11] & 255) & 128 ? (context->gpr[11] & 255) | 65280 : (context->gpr[11] & 255));
	context->gpr[9] = (context->gpr[9] & 65535) & 32768 ? (context->gpr[9] & 65535) | 4294901760 : (context->gpr[9] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_1011_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[9] = (context->gpr[11] & 65535) & 32768 ? (context->gpr[11] & 65535) | 4294901760 : (context->gpr[11] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_1100_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[12] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[12], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[9] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_1100_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[12] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[12], context);
	context->gpr[9] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_1100_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[12] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[12], context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_1100_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[9] = context->gpr[12];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_1100_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[12] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[12], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[9] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[12] = 1 + context->gpr[12];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_1100_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[12] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[12], context);
	context->gpr[9] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[12] = 2 + context->gpr[12];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_1100_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[12] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[12], context);
	context->gpr[9] = context->scratch1;
	context->gpr[12] = 4 + context->gpr[12];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_1100_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[9] = ~context->gpr[12];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_1100_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[12] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[12] << 8;
	temp2 = 65280 & temp2;
	context->gpr[9] = context->gpr[12] & 4294901760;
	context->gpr[9] = temp1 | context->gpr[9];
	context->gpr[9] = temp2 | context->gpr[9];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_1100_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[12] >> 16;
	context->gpr[9] = context->gpr[12] << 16;
	context->gpr[9] = temp | context->gpr[9];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_1100_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[12]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[9] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_1100_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[9] = -context->gpr[12];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_1100_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[9] = context->gpr[12] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_1100_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[9] = context->gpr[12] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_1100_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[9] = (context->gpr[9] & ~65535) | ((context->gpr[12] & 255) & 128 ? (context->gpr[12] & 255) | 65280 : (context->gpr[12] & 255));
	context->gpr[9] = (context->gpr[9] & 65535) & 32768 ? (context->gpr[9] & 65535) | 4294901760 : (context->gpr[9] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_1100_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[9] = (context->gpr[12] & 65535) & 32768 ? (context->gpr[12] & 65535) | 4294901760 : (context->gpr[12] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_1101_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[13] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[13], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[9] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_1101_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[13] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[13], context);
	context->gpr[9] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_1101_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[13] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[13], context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_1101_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[9] = context->gpr[13];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_1101_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[13] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[13], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[9] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[13] = 1 + context->gpr[13];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_1101_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[13] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[13], context);
	context->gpr[9] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[13] = 2 + context->gpr[13];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_1101_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[13] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[13], context);
	context->gpr[9] = context->scratch1;
	context->gpr[13] = 4 + context->gpr[13];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_1101_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[9] = ~context->gpr[13];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_1101_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[13] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[13] << 8;
	temp2 = 65280 & temp2;
	context->gpr[9] = context->gpr[13] & 4294901760;
	context->gpr[9] = temp1 | context->gpr[9];
	context->gpr[9] = temp2 | context->gpr[9];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_1101_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[13] >> 16;
	context->gpr[9] = context->gpr[13] << 16;
	context->gpr[9] = temp | context->gpr[9];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_1101_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[13]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[9] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_1101_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[9] = -context->gpr[13];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_1101_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[9] = context->gpr[13] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_1101_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[9] = context->gpr[13] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_1101_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[9] = (context->gpr[9] & ~65535) | ((context->gpr[13] & 255) & 128 ? (context->gpr[13] & 255) | 65280 : (context->gpr[13] & 255));
	context->gpr[9] = (context->gpr[9] & 65535) & 32768 ? (context->gpr[9] & 65535) | 4294901760 : (context->gpr[9] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_1101_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[9] = (context->gpr[13] & 65535) & 32768 ? (context->gpr[13] & 65535) | 4294901760 : (context->gpr[13] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_1110_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[14] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[14], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[9] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_1110_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[14] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[14], context);
	context->gpr[9] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_1110_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[14] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[14], context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_1110_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[9] = context->gpr[14];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_1110_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[14] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[14], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[9] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[14] = 1 + context->gpr[14];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_1110_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[14] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[14], context);
	context->gpr[9] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[14] = 2 + context->gpr[14];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_1110_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[14] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[14], context);
	context->gpr[9] = context->scratch1;
	context->gpr[14] = 4 + context->gpr[14];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_1110_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[9] = ~context->gpr[14];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_1110_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[14] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[14] << 8;
	temp2 = 65280 & temp2;
	context->gpr[9] = context->gpr[14] & 4294901760;
	context->gpr[9] = temp1 | context->gpr[9];
	context->gpr[9] = temp2 | context->gpr[9];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_1110_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[14] >> 16;
	context->gpr[9] = context->gpr[14] << 16;
	context->gpr[9] = temp | context->gpr[9];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_1110_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[14]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[9] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_1110_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[9] = -context->gpr[14];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_1110_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[9] = context->gpr[14] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_1110_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[9] = context->gpr[14] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_1110_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[9] = (context->gpr[9] & ~65535) | ((context->gpr[14] & 255) & 128 ? (context->gpr[14] & 255) | 65280 : (context->gpr[14] & 255));
	context->gpr[9] = (context->gpr[9] & 65535) & 32768 ? (context->gpr[9] & 65535) | 4294901760 : (context->gpr[9] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_1110_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[9] = (context->gpr[14] & 65535) & 32768 ? (context->gpr[14] & 65535) | 4294901760 : (context->gpr[14] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_1111_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[15] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[15], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[9] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_1111_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[15] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[15], context);
	context->gpr[9] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_1111_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[15] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[15], context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_1111_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[9] = context->gpr[15];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_1111_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[15] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[15], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[9] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[15] = 1 + context->gpr[15];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_1111_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[15] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[15], context);
	context->gpr[9] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[15] = 2 + context->gpr[15];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_1111_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[15] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[15], context);
	context->gpr[9] = context->scratch1;
	context->gpr[15] = 4 + context->gpr[15];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_1111_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[9] = ~context->gpr[15];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_1111_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[15] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[15] << 8;
	temp2 = 65280 & temp2;
	context->gpr[9] = context->gpr[15] & 4294901760;
	context->gpr[9] = temp1 | context->gpr[9];
	context->gpr[9] = temp2 | context->gpr[9];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_1111_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[15] >> 16;
	context->gpr[9] = context->gpr[15] << 16;
	context->gpr[9] = temp | context->gpr[9];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_1111_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[15]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[9] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_1111_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[9] = -context->gpr[15];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_1111_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[9] = context->gpr[15] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_1111_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[9] = context->gpr[15] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_1111_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[9] = (context->gpr[9] & ~65535) | ((context->gpr[15] & 255) & 128 ? (context->gpr[15] & 255) | 65280 : (context->gpr[15] & 255));
	context->gpr[9] = (context->gpr[9] & 65535) & 32768 ? (context->gpr[9] & 65535) | 4294901760 : (context->gpr[9] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_1111_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[9] = (context->gpr[15] & 65535) & 32768 ? (context->gpr[15] & 65535) | 4294901760 : (context->gpr[15] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_0000_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[0] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[0], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[10] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_0000_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[0] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[0], context);
	context->gpr[10] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_0000_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[0] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[0], context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_0000_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[10] = context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_0000_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[0] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[0], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[10] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[0] = 1 + context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_0000_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[0] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[0], context);
	context->gpr[10] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[0] = 2 + context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_0000_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[0] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[0], context);
	context->gpr[10] = context->scratch1;
	context->gpr[0] = 4 + context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_0000_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[10] = ~context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_0000_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[0] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[0] << 8;
	temp2 = 65280 & temp2;
	context->gpr[10] = context->gpr[0] & 4294901760;
	context->gpr[10] = temp1 | context->gpr[10];
	context->gpr[10] = temp2 | context->gpr[10];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_0000_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[0] >> 16;
	context->gpr[10] = context->gpr[0] << 16;
	context->gpr[10] = temp | context->gpr[10];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_0000_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[0]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[10] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_0000_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[10] = -context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_0000_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[10] = context->gpr[0] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_0000_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[10] = context->gpr[0] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_0000_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[10] = (context->gpr[10] & ~65535) | ((context->gpr[0] & 255) & 128 ? (context->gpr[0] & 255) | 65280 : (context->gpr[0] & 255));
	context->gpr[10] = (context->gpr[10] & 65535) & 32768 ? (context->gpr[10] & 65535) | 4294901760 : (context->gpr[10] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_0000_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[10] = (context->gpr[0] & 65535) & 32768 ? (context->gpr[0] & 65535) | 4294901760 : (context->gpr[0] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_0001_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[1] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[1], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[10] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_0001_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[1] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[1], context);
	context->gpr[10] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_0001_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[1] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[1], context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_0001_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[10] = context->gpr[1];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_0001_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[1] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[1], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[10] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[1] = 1 + context->gpr[1];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_0001_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[1] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[1], context);
	context->gpr[10] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[1] = 2 + context->gpr[1];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_0001_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[1] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[1], context);
	context->gpr[10] = context->scratch1;
	context->gpr[1] = 4 + context->gpr[1];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_0001_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[10] = ~context->gpr[1];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_0001_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[1] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[1] << 8;
	temp2 = 65280 & temp2;
	context->gpr[10] = context->gpr[1] & 4294901760;
	context->gpr[10] = temp1 | context->gpr[10];
	context->gpr[10] = temp2 | context->gpr[10];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_0001_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[1] >> 16;
	context->gpr[10] = context->gpr[1] << 16;
	context->gpr[10] = temp | context->gpr[10];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_0001_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[1]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[10] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_0001_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[10] = -context->gpr[1];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_0001_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[10] = context->gpr[1] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_0001_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[10] = context->gpr[1] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_0001_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[10] = (context->gpr[10] & ~65535) | ((context->gpr[1] & 255) & 128 ? (context->gpr[1] & 255) | 65280 : (context->gpr[1] & 255));
	context->gpr[10] = (context->gpr[10] & 65535) & 32768 ? (context->gpr[10] & 65535) | 4294901760 : (context->gpr[10] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_0001_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[10] = (context->gpr[1] & 65535) & 32768 ? (context->gpr[1] & 65535) | 4294901760 : (context->gpr[1] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_0010_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[2] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[2], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[10] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_0010_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[2] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[2], context);
	context->gpr[10] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_0010_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[2] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[2], context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_0010_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[10] = context->gpr[2];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_0010_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[2] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[2], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[10] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[2] = 1 + context->gpr[2];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_0010_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[2] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[2], context);
	context->gpr[10] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[2] = 2 + context->gpr[2];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_0010_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[2] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[2], context);
	context->gpr[10] = context->scratch1;
	context->gpr[2] = 4 + context->gpr[2];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_0010_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[10] = ~context->gpr[2];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_0010_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[2] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[2] << 8;
	temp2 = 65280 & temp2;
	context->gpr[10] = context->gpr[2] & 4294901760;
	context->gpr[10] = temp1 | context->gpr[10];
	context->gpr[10] = temp2 | context->gpr[10];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_0010_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[2] >> 16;
	context->gpr[10] = context->gpr[2] << 16;
	context->gpr[10] = temp | context->gpr[10];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_0010_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[2]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[10] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_0010_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[10] = -context->gpr[2];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_0010_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[10] = context->gpr[2] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_0010_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[10] = context->gpr[2] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_0010_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[10] = (context->gpr[10] & ~65535) | ((context->gpr[2] & 255) & 128 ? (context->gpr[2] & 255) | 65280 : (context->gpr[2] & 255));
	context->gpr[10] = (context->gpr[10] & 65535) & 32768 ? (context->gpr[10] & 65535) | 4294901760 : (context->gpr[10] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_0010_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[10] = (context->gpr[2] & 65535) & 32768 ? (context->gpr[2] & 65535) | 4294901760 : (context->gpr[2] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_0011_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[3] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[3], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[10] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_0011_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[3] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[3], context);
	context->gpr[10] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_0011_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[3] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[3], context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_0011_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[10] = context->gpr[3];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_0011_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[3] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[3], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[10] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[3] = 1 + context->gpr[3];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_0011_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[3] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[3], context);
	context->gpr[10] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[3] = 2 + context->gpr[3];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_0011_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[3] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[3], context);
	context->gpr[10] = context->scratch1;
	context->gpr[3] = 4 + context->gpr[3];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_0011_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[10] = ~context->gpr[3];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_0011_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[3] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[3] << 8;
	temp2 = 65280 & temp2;
	context->gpr[10] = context->gpr[3] & 4294901760;
	context->gpr[10] = temp1 | context->gpr[10];
	context->gpr[10] = temp2 | context->gpr[10];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_0011_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[3] >> 16;
	context->gpr[10] = context->gpr[3] << 16;
	context->gpr[10] = temp | context->gpr[10];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_0011_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[3]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[10] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_0011_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[10] = -context->gpr[3];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_0011_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[10] = context->gpr[3] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_0011_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[10] = context->gpr[3] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_0011_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[10] = (context->gpr[10] & ~65535) | ((context->gpr[3] & 255) & 128 ? (context->gpr[3] & 255) | 65280 : (context->gpr[3] & 255));
	context->gpr[10] = (context->gpr[10] & 65535) & 32768 ? (context->gpr[10] & 65535) | 4294901760 : (context->gpr[10] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_0011_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[10] = (context->gpr[3] & 65535) & 32768 ? (context->gpr[3] & 65535) | 4294901760 : (context->gpr[3] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_0100_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[4] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[4], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[10] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_0100_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[4] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[4], context);
	context->gpr[10] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_0100_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[4] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[4], context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_0100_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[10] = context->gpr[4];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_0100_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[4] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[4], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[10] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[4] = 1 + context->gpr[4];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_0100_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[4] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[4], context);
	context->gpr[10] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[4] = 2 + context->gpr[4];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_0100_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[4] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[4], context);
	context->gpr[10] = context->scratch1;
	context->gpr[4] = 4 + context->gpr[4];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_0100_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[10] = ~context->gpr[4];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_0100_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[4] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[4] << 8;
	temp2 = 65280 & temp2;
	context->gpr[10] = context->gpr[4] & 4294901760;
	context->gpr[10] = temp1 | context->gpr[10];
	context->gpr[10] = temp2 | context->gpr[10];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_0100_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[4] >> 16;
	context->gpr[10] = context->gpr[4] << 16;
	context->gpr[10] = temp | context->gpr[10];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_0100_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[4]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[10] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_0100_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[10] = -context->gpr[4];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_0100_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[10] = context->gpr[4] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_0100_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[10] = context->gpr[4] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_0100_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[10] = (context->gpr[10] & ~65535) | ((context->gpr[4] & 255) & 128 ? (context->gpr[4] & 255) | 65280 : (context->gpr[4] & 255));
	context->gpr[10] = (context->gpr[10] & 65535) & 32768 ? (context->gpr[10] & 65535) | 4294901760 : (context->gpr[10] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_0100_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[10] = (context->gpr[4] & 65535) & 32768 ? (context->gpr[4] & 65535) | 4294901760 : (context->gpr[4] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_0101_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[5] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[5], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[10] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_0101_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[5] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[5], context);
	context->gpr[10] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_0101_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[5] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[5], context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_0101_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[10] = context->gpr[5];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_0101_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[5] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[5], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[10] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[5] = 1 + context->gpr[5];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_0101_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[5] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[5], context);
	context->gpr[10] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[5] = 2 + context->gpr[5];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_0101_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[5] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[5], context);
	context->gpr[10] = context->scratch1;
	context->gpr[5] = 4 + context->gpr[5];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_0101_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[10] = ~context->gpr[5];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_0101_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[5] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[5] << 8;
	temp2 = 65280 & temp2;
	context->gpr[10] = context->gpr[5] & 4294901760;
	context->gpr[10] = temp1 | context->gpr[10];
	context->gpr[10] = temp2 | context->gpr[10];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_0101_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[5] >> 16;
	context->gpr[10] = context->gpr[5] << 16;
	context->gpr[10] = temp | context->gpr[10];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_0101_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[5]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[10] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_0101_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[10] = -context->gpr[5];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_0101_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[10] = context->gpr[5] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_0101_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[10] = context->gpr[5] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_0101_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[10] = (context->gpr[10] & ~65535) | ((context->gpr[5] & 255) & 128 ? (context->gpr[5] & 255) | 65280 : (context->gpr[5] & 255));
	context->gpr[10] = (context->gpr[10] & 65535) & 32768 ? (context->gpr[10] & 65535) | 4294901760 : (context->gpr[10] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_0101_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[10] = (context->gpr[5] & 65535) & 32768 ? (context->gpr[5] & 65535) | 4294901760 : (context->gpr[5] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_0110_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[6] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[6], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[10] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_0110_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[6] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[6], context);
	context->gpr[10] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_0110_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[6] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[6], context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_0110_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[10] = context->gpr[6];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_0110_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[6] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[6], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[10] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[6] = 1 + context->gpr[6];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_0110_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[6] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[6], context);
	context->gpr[10] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[6] = 2 + context->gpr[6];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_0110_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[6] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[6], context);
	context->gpr[10] = context->scratch1;
	context->gpr[6] = 4 + context->gpr[6];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_0110_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[10] = ~context->gpr[6];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_0110_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[6] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[6] << 8;
	temp2 = 65280 & temp2;
	context->gpr[10] = context->gpr[6] & 4294901760;
	context->gpr[10] = temp1 | context->gpr[10];
	context->gpr[10] = temp2 | context->gpr[10];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_0110_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[6] >> 16;
	context->gpr[10] = context->gpr[6] << 16;
	context->gpr[10] = temp | context->gpr[10];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_0110_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[6]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[10] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_0110_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[10] = -context->gpr[6];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_0110_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[10] = context->gpr[6] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_0110_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[10] = context->gpr[6] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_0110_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[10] = (context->gpr[10] & ~65535) | ((context->gpr[6] & 255) & 128 ? (context->gpr[6] & 255) | 65280 : (context->gpr[6] & 255));
	context->gpr[10] = (context->gpr[10] & 65535) & 32768 ? (context->gpr[10] & 65535) | 4294901760 : (context->gpr[10] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_0110_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[10] = (context->gpr[6] & 65535) & 32768 ? (context->gpr[6] & 65535) | 4294901760 : (context->gpr[6] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_0111_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[7] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[7], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[10] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_0111_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[7] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[7], context);
	context->gpr[10] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_0111_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[7] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[7], context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_0111_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[10] = context->gpr[7];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_0111_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[7] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[7], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[10] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[7] = 1 + context->gpr[7];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_0111_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[7] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[7], context);
	context->gpr[10] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[7] = 2 + context->gpr[7];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_0111_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[7] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[7], context);
	context->gpr[10] = context->scratch1;
	context->gpr[7] = 4 + context->gpr[7];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_0111_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[10] = ~context->gpr[7];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_0111_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[7] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[7] << 8;
	temp2 = 65280 & temp2;
	context->gpr[10] = context->gpr[7] & 4294901760;
	context->gpr[10] = temp1 | context->gpr[10];
	context->gpr[10] = temp2 | context->gpr[10];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_0111_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[7] >> 16;
	context->gpr[10] = context->gpr[7] << 16;
	context->gpr[10] = temp | context->gpr[10];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_0111_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[7]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[10] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_0111_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[10] = -context->gpr[7];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_0111_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[10] = context->gpr[7] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_0111_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[10] = context->gpr[7] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_0111_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[10] = (context->gpr[10] & ~65535) | ((context->gpr[7] & 255) & 128 ? (context->gpr[7] & 255) | 65280 : (context->gpr[7] & 255));
	context->gpr[10] = (context->gpr[10] & 65535) & 32768 ? (context->gpr[10] & 65535) | 4294901760 : (context->gpr[10] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_0111_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[10] = (context->gpr[7] & 65535) & 32768 ? (context->gpr[7] & 65535) | 4294901760 : (context->gpr[7] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_1000_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[8] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[8], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[10] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_1000_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[8] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[8], context);
	context->gpr[10] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_1000_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[8] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[8], context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_1000_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[10] = context->gpr[8];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_1000_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[8] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[8], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[10] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[8] = 1 + context->gpr[8];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_1000_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[8] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[8], context);
	context->gpr[10] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[8] = 2 + context->gpr[8];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_1000_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[8] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[8], context);
	context->gpr[10] = context->scratch1;
	context->gpr[8] = 4 + context->gpr[8];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_1000_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[10] = ~context->gpr[8];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_1000_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[8] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[8] << 8;
	temp2 = 65280 & temp2;
	context->gpr[10] = context->gpr[8] & 4294901760;
	context->gpr[10] = temp1 | context->gpr[10];
	context->gpr[10] = temp2 | context->gpr[10];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_1000_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[8] >> 16;
	context->gpr[10] = context->gpr[8] << 16;
	context->gpr[10] = temp | context->gpr[10];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_1000_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[8]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[10] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_1000_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[10] = -context->gpr[8];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_1000_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[10] = context->gpr[8] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_1000_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[10] = context->gpr[8] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_1000_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[10] = (context->gpr[10] & ~65535) | ((context->gpr[8] & 255) & 128 ? (context->gpr[8] & 255) | 65280 : (context->gpr[8] & 255));
	context->gpr[10] = (context->gpr[10] & 65535) & 32768 ? (context->gpr[10] & 65535) | 4294901760 : (context->gpr[10] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_1000_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[10] = (context->gpr[8] & 65535) & 32768 ? (context->gpr[8] & 65535) | 4294901760 : (context->gpr[8] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_1001_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[9] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[9], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[10] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_1001_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[9] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[9], context);
	context->gpr[10] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_1001_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[9] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[9], context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_1001_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[10] = context->gpr[9];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_1001_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[9] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[9], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[10] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[9] = 1 + context->gpr[9];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_1001_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[9] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[9], context);
	context->gpr[10] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[9] = 2 + context->gpr[9];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_1001_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[9] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[9], context);
	context->gpr[10] = context->scratch1;
	context->gpr[9] = 4 + context->gpr[9];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_1001_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[10] = ~context->gpr[9];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_1001_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[9] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[9] << 8;
	temp2 = 65280 & temp2;
	context->gpr[10] = context->gpr[9] & 4294901760;
	context->gpr[10] = temp1 | context->gpr[10];
	context->gpr[10] = temp2 | context->gpr[10];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_1001_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[9] >> 16;
	context->gpr[10] = context->gpr[9] << 16;
	context->gpr[10] = temp | context->gpr[10];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_1001_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[9]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[10] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_1001_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[10] = -context->gpr[9];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_1001_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[10] = context->gpr[9] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_1001_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[10] = context->gpr[9] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_1001_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[10] = (context->gpr[10] & ~65535) | ((context->gpr[9] & 255) & 128 ? (context->gpr[9] & 255) | 65280 : (context->gpr[9] & 255));
	context->gpr[10] = (context->gpr[10] & 65535) & 32768 ? (context->gpr[10] & 65535) | 4294901760 : (context->gpr[10] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_1001_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[10] = (context->gpr[9] & 65535) & 32768 ? (context->gpr[9] & 65535) | 4294901760 : (context->gpr[9] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_1010_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[10] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[10], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[10] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_1010_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[10] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[10], context);
	context->gpr[10] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_1010_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[10] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[10], context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_1010_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[10] = context->gpr[10];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_1010_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[10] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[10], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[10] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_1010_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[10] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[10], context);
	context->gpr[10] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_1010_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[10] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[10], context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_1010_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[10] = ~context->gpr[10];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_1010_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[10] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[10] << 8;
	temp2 = 65280 & temp2;
	context->gpr[10] = context->gpr[10] & 4294901760;
	context->gpr[10] = temp1 | context->gpr[10];
	context->gpr[10] = temp2 | context->gpr[10];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_1010_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[10] >> 16;
	context->gpr[10] = context->gpr[10] << 16;
	context->gpr[10] = temp | context->gpr[10];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_1010_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[10]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[10] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_1010_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[10] = -context->gpr[10];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_1010_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[10] = context->gpr[10] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_1010_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[10] = context->gpr[10] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_1010_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[10] = (context->gpr[10] & ~65535) | ((context->gpr[10] & 255) & 128 ? (context->gpr[10] & 255) | 65280 : (context->gpr[10] & 255));
	context->gpr[10] = (context->gpr[10] & 65535) & 32768 ? (context->gpr[10] & 65535) | 4294901760 : (context->gpr[10] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_1010_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[10] = (context->gpr[10] & 65535) & 32768 ? (context->gpr[10] & 65535) | 4294901760 : (context->gpr[10] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_1011_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[11] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[11], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[10] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_1011_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[11] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[11], context);
	context->gpr[10] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_1011_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[11] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[11], context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_1011_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[10] = context->gpr[11];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_1011_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[11] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[11], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[10] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[11] = 1 + context->gpr[11];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_1011_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[11] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[11], context);
	context->gpr[10] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[11] = 2 + context->gpr[11];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_1011_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[11] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[11], context);
	context->gpr[10] = context->scratch1;
	context->gpr[11] = 4 + context->gpr[11];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_1011_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[10] = ~context->gpr[11];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_1011_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[11] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[11] << 8;
	temp2 = 65280 & temp2;
	context->gpr[10] = context->gpr[11] & 4294901760;
	context->gpr[10] = temp1 | context->gpr[10];
	context->gpr[10] = temp2 | context->gpr[10];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_1011_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[11] >> 16;
	context->gpr[10] = context->gpr[11] << 16;
	context->gpr[10] = temp | context->gpr[10];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_1011_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[11]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[10] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_1011_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[10] = -context->gpr[11];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_1011_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[10] = context->gpr[11] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_1011_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[10] = context->gpr[11] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_1011_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[10] = (context->gpr[10] & ~65535) | ((context->gpr[11] & 255) & 128 ? (context->gpr[11] & 255) | 65280 : (context->gpr[11] & 255));
	context->gpr[10] = (context->gpr[10] & 65535) & 32768 ? (context->gpr[10] & 65535) | 4294901760 : (context->gpr[10] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_1011_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[10] = (context->gpr[11] & 65535) & 32768 ? (context->gpr[11] & 65535) | 4294901760 : (context->gpr[11] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_1100_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[12] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[12], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[10] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_1100_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[12] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[12], context);
	context->gpr[10] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_1100_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[12] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[12], context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_1100_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[10] = context->gpr[12];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_1100_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[12] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[12], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[10] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[12] = 1 + context->gpr[12];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_1100_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[12] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[12], context);
	context->gpr[10] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[12] = 2 + context->gpr[12];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_1100_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[12] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[12], context);
	context->gpr[10] = context->scratch1;
	context->gpr[12] = 4 + context->gpr[12];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_1100_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[10] = ~context->gpr[12];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_1100_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[12] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[12] << 8;
	temp2 = 65280 & temp2;
	context->gpr[10] = context->gpr[12] & 4294901760;
	context->gpr[10] = temp1 | context->gpr[10];
	context->gpr[10] = temp2 | context->gpr[10];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_1100_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[12] >> 16;
	context->gpr[10] = context->gpr[12] << 16;
	context->gpr[10] = temp | context->gpr[10];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_1100_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[12]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[10] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_1100_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[10] = -context->gpr[12];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_1100_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[10] = context->gpr[12] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_1100_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[10] = context->gpr[12] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_1100_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[10] = (context->gpr[10] & ~65535) | ((context->gpr[12] & 255) & 128 ? (context->gpr[12] & 255) | 65280 : (context->gpr[12] & 255));
	context->gpr[10] = (context->gpr[10] & 65535) & 32768 ? (context->gpr[10] & 65535) | 4294901760 : (context->gpr[10] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_1100_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[10] = (context->gpr[12] & 65535) & 32768 ? (context->gpr[12] & 65535) | 4294901760 : (context->gpr[12] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_1101_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[13] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[13], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[10] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_1101_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[13] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[13], context);
	context->gpr[10] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_1101_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[13] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[13], context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_1101_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[10] = context->gpr[13];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_1101_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[13] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[13], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[10] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[13] = 1 + context->gpr[13];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_1101_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[13] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[13], context);
	context->gpr[10] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[13] = 2 + context->gpr[13];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_1101_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[13] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[13], context);
	context->gpr[10] = context->scratch1;
	context->gpr[13] = 4 + context->gpr[13];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_1101_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[10] = ~context->gpr[13];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_1101_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[13] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[13] << 8;
	temp2 = 65280 & temp2;
	context->gpr[10] = context->gpr[13] & 4294901760;
	context->gpr[10] = temp1 | context->gpr[10];
	context->gpr[10] = temp2 | context->gpr[10];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_1101_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[13] >> 16;
	context->gpr[10] = context->gpr[13] << 16;
	context->gpr[10] = temp | context->gpr[10];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_1101_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[13]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[10] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_1101_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[10] = -context->gpr[13];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_1101_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[10] = context->gpr[13] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_1101_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[10] = context->gpr[13] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_1101_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[10] = (context->gpr[10] & ~65535) | ((context->gpr[13] & 255) & 128 ? (context->gpr[13] & 255) | 65280 : (context->gpr[13] & 255));
	context->gpr[10] = (context->gpr[10] & 65535) & 32768 ? (context->gpr[10] & 65535) | 4294901760 : (context->gpr[10] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_1101_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[10] = (context->gpr[13] & 65535) & 32768 ? (context->gpr[13] & 65535) | 4294901760 : (context->gpr[13] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_1110_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[14] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[14], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[10] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_1110_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[14] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[14], context);
	context->gpr[10] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_1110_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[14] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[14], context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_1110_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[10] = context->gpr[14];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_1110_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[14] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[14], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[10] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[14] = 1 + context->gpr[14];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_1110_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[14] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[14], context);
	context->gpr[10] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[14] = 2 + context->gpr[14];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_1110_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[14] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[14], context);
	context->gpr[10] = context->scratch1;
	context->gpr[14] = 4 + context->gpr[14];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_1110_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[10] = ~context->gpr[14];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_1110_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[14] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[14] << 8;
	temp2 = 65280 & temp2;
	context->gpr[10] = context->gpr[14] & 4294901760;
	context->gpr[10] = temp1 | context->gpr[10];
	context->gpr[10] = temp2 | context->gpr[10];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_1110_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[14] >> 16;
	context->gpr[10] = context->gpr[14] << 16;
	context->gpr[10] = temp | context->gpr[10];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_1110_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[14]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[10] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_1110_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[10] = -context->gpr[14];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_1110_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[10] = context->gpr[14] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_1110_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[10] = context->gpr[14] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_1110_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[10] = (context->gpr[10] & ~65535) | ((context->gpr[14] & 255) & 128 ? (context->gpr[14] & 255) | 65280 : (context->gpr[14] & 255));
	context->gpr[10] = (context->gpr[10] & 65535) & 32768 ? (context->gpr[10] & 65535) | 4294901760 : (context->gpr[10] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_1110_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[10] = (context->gpr[14] & 65535) & 32768 ? (context->gpr[14] & 65535) | 4294901760 : (context->gpr[14] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_1111_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[15] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[15], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[10] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_1111_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[15] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[15], context);
	context->gpr[10] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_1111_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[15] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[15], context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_1111_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[10] = context->gpr[15];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_1111_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[15] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[15], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[10] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[15] = 1 + context->gpr[15];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_1111_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[15] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[15], context);
	context->gpr[10] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[15] = 2 + context->gpr[15];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_1111_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[15] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[15], context);
	context->gpr[10] = context->scratch1;
	context->gpr[15] = 4 + context->gpr[15];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_1111_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[10] = ~context->gpr[15];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_1111_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[15] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[15] << 8;
	temp2 = 65280 & temp2;
	context->gpr[10] = context->gpr[15] & 4294901760;
	context->gpr[10] = temp1 | context->gpr[10];
	context->gpr[10] = temp2 | context->gpr[10];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_1111_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[15] >> 16;
	context->gpr[10] = context->gpr[15] << 16;
	context->gpr[10] = temp | context->gpr[10];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_1111_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[15]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[10] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_1111_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[10] = -context->gpr[15];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_1111_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[10] = context->gpr[15] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_1111_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[10] = context->gpr[15] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_1111_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[10] = (context->gpr[10] & ~65535) | ((context->gpr[15] & 255) & 128 ? (context->gpr[15] & 255) | 65280 : (context->gpr[15] & 255));
	context->gpr[10] = (context->gpr[10] & 65535) & 32768 ? (context->gpr[10] & 65535) | 4294901760 : (context->gpr[10] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_1111_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[10] = (context->gpr[15] & 65535) & 32768 ? (context->gpr[15] & 65535) | 4294901760 : (context->gpr[15] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_0000_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[0] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[0], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[11] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_0000_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[0] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[0], context);
	context->gpr[11] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_0000_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[0] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[0], context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_0000_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[11] = context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_0000_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[0] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[0], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[11] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[0] = 1 + context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_0000_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[0] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[0], context);
	context->gpr[11] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[0] = 2 + context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_0000_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[0] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[0], context);
	context->gpr[11] = context->scratch1;
	context->gpr[0] = 4 + context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_0000_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[11] = ~context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_0000_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[0] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[0] << 8;
	temp2 = 65280 & temp2;
	context->gpr[11] = context->gpr[0] & 4294901760;
	context->gpr[11] = temp1 | context->gpr[11];
	context->gpr[11] = temp2 | context->gpr[11];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_0000_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[0] >> 16;
	context->gpr[11] = context->gpr[0] << 16;
	context->gpr[11] = temp | context->gpr[11];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_0000_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[0]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[11] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_0000_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[11] = -context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_0000_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[11] = context->gpr[0] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_0000_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[11] = context->gpr[0] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_0000_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[11] = (context->gpr[11] & ~65535) | ((context->gpr[0] & 255) & 128 ? (context->gpr[0] & 255) | 65280 : (context->gpr[0] & 255));
	context->gpr[11] = (context->gpr[11] & 65535) & 32768 ? (context->gpr[11] & 65535) | 4294901760 : (context->gpr[11] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_0000_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[11] = (context->gpr[0] & 65535) & 32768 ? (context->gpr[0] & 65535) | 4294901760 : (context->gpr[0] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_0001_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[1] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[1], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[11] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_0001_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[1] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[1], context);
	context->gpr[11] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_0001_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[1] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[1], context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_0001_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[11] = context->gpr[1];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_0001_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[1] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[1], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[11] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[1] = 1 + context->gpr[1];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_0001_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[1] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[1], context);
	context->gpr[11] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[1] = 2 + context->gpr[1];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_0001_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[1] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[1], context);
	context->gpr[11] = context->scratch1;
	context->gpr[1] = 4 + context->gpr[1];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_0001_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[11] = ~context->gpr[1];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_0001_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[1] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[1] << 8;
	temp2 = 65280 & temp2;
	context->gpr[11] = context->gpr[1] & 4294901760;
	context->gpr[11] = temp1 | context->gpr[11];
	context->gpr[11] = temp2 | context->gpr[11];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_0001_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[1] >> 16;
	context->gpr[11] = context->gpr[1] << 16;
	context->gpr[11] = temp | context->gpr[11];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_0001_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[1]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[11] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_0001_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[11] = -context->gpr[1];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_0001_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[11] = context->gpr[1] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_0001_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[11] = context->gpr[1] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_0001_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[11] = (context->gpr[11] & ~65535) | ((context->gpr[1] & 255) & 128 ? (context->gpr[1] & 255) | 65280 : (context->gpr[1] & 255));
	context->gpr[11] = (context->gpr[11] & 65535) & 32768 ? (context->gpr[11] & 65535) | 4294901760 : (context->gpr[11] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_0001_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[11] = (context->gpr[1] & 65535) & 32768 ? (context->gpr[1] & 65535) | 4294901760 : (context->gpr[1] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_0010_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[2] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[2], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[11] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_0010_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[2] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[2], context);
	context->gpr[11] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_0010_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[2] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[2], context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_0010_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[11] = context->gpr[2];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_0010_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[2] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[2], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[11] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[2] = 1 + context->gpr[2];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_0010_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[2] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[2], context);
	context->gpr[11] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[2] = 2 + context->gpr[2];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_0010_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[2] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[2], context);
	context->gpr[11] = context->scratch1;
	context->gpr[2] = 4 + context->gpr[2];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_0010_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[11] = ~context->gpr[2];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_0010_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[2] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[2] << 8;
	temp2 = 65280 & temp2;
	context->gpr[11] = context->gpr[2] & 4294901760;
	context->gpr[11] = temp1 | context->gpr[11];
	context->gpr[11] = temp2 | context->gpr[11];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_0010_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[2] >> 16;
	context->gpr[11] = context->gpr[2] << 16;
	context->gpr[11] = temp | context->gpr[11];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_0010_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[2]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[11] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_0010_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[11] = -context->gpr[2];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_0010_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[11] = context->gpr[2] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_0010_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[11] = context->gpr[2] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_0010_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[11] = (context->gpr[11] & ~65535) | ((context->gpr[2] & 255) & 128 ? (context->gpr[2] & 255) | 65280 : (context->gpr[2] & 255));
	context->gpr[11] = (context->gpr[11] & 65535) & 32768 ? (context->gpr[11] & 65535) | 4294901760 : (context->gpr[11] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_0010_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[11] = (context->gpr[2] & 65535) & 32768 ? (context->gpr[2] & 65535) | 4294901760 : (context->gpr[2] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_0011_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[3] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[3], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[11] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_0011_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[3] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[3], context);
	context->gpr[11] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_0011_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[3] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[3], context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_0011_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[11] = context->gpr[3];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_0011_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[3] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[3], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[11] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[3] = 1 + context->gpr[3];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_0011_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[3] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[3], context);
	context->gpr[11] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[3] = 2 + context->gpr[3];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_0011_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[3] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[3], context);
	context->gpr[11] = context->scratch1;
	context->gpr[3] = 4 + context->gpr[3];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_0011_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[11] = ~context->gpr[3];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_0011_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[3] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[3] << 8;
	temp2 = 65280 & temp2;
	context->gpr[11] = context->gpr[3] & 4294901760;
	context->gpr[11] = temp1 | context->gpr[11];
	context->gpr[11] = temp2 | context->gpr[11];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_0011_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[3] >> 16;
	context->gpr[11] = context->gpr[3] << 16;
	context->gpr[11] = temp | context->gpr[11];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_0011_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[3]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[11] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_0011_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[11] = -context->gpr[3];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_0011_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[11] = context->gpr[3] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_0011_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[11] = context->gpr[3] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_0011_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[11] = (context->gpr[11] & ~65535) | ((context->gpr[3] & 255) & 128 ? (context->gpr[3] & 255) | 65280 : (context->gpr[3] & 255));
	context->gpr[11] = (context->gpr[11] & 65535) & 32768 ? (context->gpr[11] & 65535) | 4294901760 : (context->gpr[11] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_0011_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[11] = (context->gpr[3] & 65535) & 32768 ? (context->gpr[3] & 65535) | 4294901760 : (context->gpr[3] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_0100_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[4] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[4], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[11] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_0100_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[4] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[4], context);
	context->gpr[11] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_0100_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[4] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[4], context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_0100_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[11] = context->gpr[4];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_0100_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[4] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[4], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[11] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[4] = 1 + context->gpr[4];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_0100_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[4] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[4], context);
	context->gpr[11] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[4] = 2 + context->gpr[4];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_0100_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[4] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[4], context);
	context->gpr[11] = context->scratch1;
	context->gpr[4] = 4 + context->gpr[4];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_0100_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[11] = ~context->gpr[4];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_0100_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[4] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[4] << 8;
	temp2 = 65280 & temp2;
	context->gpr[11] = context->gpr[4] & 4294901760;
	context->gpr[11] = temp1 | context->gpr[11];
	context->gpr[11] = temp2 | context->gpr[11];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_0100_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[4] >> 16;
	context->gpr[11] = context->gpr[4] << 16;
	context->gpr[11] = temp | context->gpr[11];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_0100_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[4]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[11] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_0100_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[11] = -context->gpr[4];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_0100_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[11] = context->gpr[4] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_0100_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[11] = context->gpr[4] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_0100_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[11] = (context->gpr[11] & ~65535) | ((context->gpr[4] & 255) & 128 ? (context->gpr[4] & 255) | 65280 : (context->gpr[4] & 255));
	context->gpr[11] = (context->gpr[11] & 65535) & 32768 ? (context->gpr[11] & 65535) | 4294901760 : (context->gpr[11] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_0100_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[11] = (context->gpr[4] & 65535) & 32768 ? (context->gpr[4] & 65535) | 4294901760 : (context->gpr[4] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_0101_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[5] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[5], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[11] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_0101_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[5] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[5], context);
	context->gpr[11] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_0101_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[5] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[5], context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_0101_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[11] = context->gpr[5];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_0101_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[5] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[5], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[11] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[5] = 1 + context->gpr[5];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_0101_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[5] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[5], context);
	context->gpr[11] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[5] = 2 + context->gpr[5];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_0101_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[5] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[5], context);
	context->gpr[11] = context->scratch1;
	context->gpr[5] = 4 + context->gpr[5];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_0101_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[11] = ~context->gpr[5];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_0101_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[5] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[5] << 8;
	temp2 = 65280 & temp2;
	context->gpr[11] = context->gpr[5] & 4294901760;
	context->gpr[11] = temp1 | context->gpr[11];
	context->gpr[11] = temp2 | context->gpr[11];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_0101_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[5] >> 16;
	context->gpr[11] = context->gpr[5] << 16;
	context->gpr[11] = temp | context->gpr[11];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_0101_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[5]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[11] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_0101_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[11] = -context->gpr[5];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_0101_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[11] = context->gpr[5] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_0101_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[11] = context->gpr[5] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_0101_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[11] = (context->gpr[11] & ~65535) | ((context->gpr[5] & 255) & 128 ? (context->gpr[5] & 255) | 65280 : (context->gpr[5] & 255));
	context->gpr[11] = (context->gpr[11] & 65535) & 32768 ? (context->gpr[11] & 65535) | 4294901760 : (context->gpr[11] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_0101_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[11] = (context->gpr[5] & 65535) & 32768 ? (context->gpr[5] & 65535) | 4294901760 : (context->gpr[5] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_0110_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[6] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[6], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[11] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_0110_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[6] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[6], context);
	context->gpr[11] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_0110_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[6] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[6], context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_0110_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[11] = context->gpr[6];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_0110_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[6] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[6], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[11] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[6] = 1 + context->gpr[6];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_0110_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[6] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[6], context);
	context->gpr[11] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[6] = 2 + context->gpr[6];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_0110_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[6] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[6], context);
	context->gpr[11] = context->scratch1;
	context->gpr[6] = 4 + context->gpr[6];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_0110_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[11] = ~context->gpr[6];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_0110_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[6] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[6] << 8;
	temp2 = 65280 & temp2;
	context->gpr[11] = context->gpr[6] & 4294901760;
	context->gpr[11] = temp1 | context->gpr[11];
	context->gpr[11] = temp2 | context->gpr[11];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_0110_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[6] >> 16;
	context->gpr[11] = context->gpr[6] << 16;
	context->gpr[11] = temp | context->gpr[11];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_0110_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[6]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[11] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_0110_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[11] = -context->gpr[6];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_0110_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[11] = context->gpr[6] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_0110_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[11] = context->gpr[6] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_0110_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[11] = (context->gpr[11] & ~65535) | ((context->gpr[6] & 255) & 128 ? (context->gpr[6] & 255) | 65280 : (context->gpr[6] & 255));
	context->gpr[11] = (context->gpr[11] & 65535) & 32768 ? (context->gpr[11] & 65535) | 4294901760 : (context->gpr[11] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_0110_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[11] = (context->gpr[6] & 65535) & 32768 ? (context->gpr[6] & 65535) | 4294901760 : (context->gpr[6] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_0111_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[7] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[7], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[11] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_0111_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[7] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[7], context);
	context->gpr[11] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_0111_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[7] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[7], context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_0111_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[11] = context->gpr[7];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_0111_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[7] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[7], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[11] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[7] = 1 + context->gpr[7];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_0111_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[7] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[7], context);
	context->gpr[11] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[7] = 2 + context->gpr[7];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_0111_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[7] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[7], context);
	context->gpr[11] = context->scratch1;
	context->gpr[7] = 4 + context->gpr[7];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_0111_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[11] = ~context->gpr[7];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_0111_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[7] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[7] << 8;
	temp2 = 65280 & temp2;
	context->gpr[11] = context->gpr[7] & 4294901760;
	context->gpr[11] = temp1 | context->gpr[11];
	context->gpr[11] = temp2 | context->gpr[11];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_0111_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[7] >> 16;
	context->gpr[11] = context->gpr[7] << 16;
	context->gpr[11] = temp | context->gpr[11];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_0111_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[7]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[11] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_0111_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[11] = -context->gpr[7];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_0111_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[11] = context->gpr[7] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_0111_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[11] = context->gpr[7] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_0111_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[11] = (context->gpr[11] & ~65535) | ((context->gpr[7] & 255) & 128 ? (context->gpr[7] & 255) | 65280 : (context->gpr[7] & 255));
	context->gpr[11] = (context->gpr[11] & 65535) & 32768 ? (context->gpr[11] & 65535) | 4294901760 : (context->gpr[11] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_0111_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[11] = (context->gpr[7] & 65535) & 32768 ? (context->gpr[7] & 65535) | 4294901760 : (context->gpr[7] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_1000_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[8] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[8], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[11] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_1000_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[8] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[8], context);
	context->gpr[11] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_1000_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[8] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[8], context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_1000_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[11] = context->gpr[8];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_1000_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[8] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[8], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[11] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[8] = 1 + context->gpr[8];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_1000_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[8] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[8], context);
	context->gpr[11] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[8] = 2 + context->gpr[8];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_1000_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[8] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[8], context);
	context->gpr[11] = context->scratch1;
	context->gpr[8] = 4 + context->gpr[8];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_1000_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[11] = ~context->gpr[8];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_1000_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[8] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[8] << 8;
	temp2 = 65280 & temp2;
	context->gpr[11] = context->gpr[8] & 4294901760;
	context->gpr[11] = temp1 | context->gpr[11];
	context->gpr[11] = temp2 | context->gpr[11];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_1000_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[8] >> 16;
	context->gpr[11] = context->gpr[8] << 16;
	context->gpr[11] = temp | context->gpr[11];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_1000_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[8]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[11] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_1000_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[11] = -context->gpr[8];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_1000_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[11] = context->gpr[8] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_1000_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[11] = context->gpr[8] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_1000_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[11] = (context->gpr[11] & ~65535) | ((context->gpr[8] & 255) & 128 ? (context->gpr[8] & 255) | 65280 : (context->gpr[8] & 255));
	context->gpr[11] = (context->gpr[11] & 65535) & 32768 ? (context->gpr[11] & 65535) | 4294901760 : (context->gpr[11] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_1000_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[11] = (context->gpr[8] & 65535) & 32768 ? (context->gpr[8] & 65535) | 4294901760 : (context->gpr[8] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_1001_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[9] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[9], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[11] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_1001_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[9] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[9], context);
	context->gpr[11] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_1001_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[9] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[9], context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_1001_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[11] = context->gpr[9];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_1001_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[9] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[9], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[11] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[9] = 1 + context->gpr[9];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_1001_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[9] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[9], context);
	context->gpr[11] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[9] = 2 + context->gpr[9];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_1001_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[9] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[9], context);
	context->gpr[11] = context->scratch1;
	context->gpr[9] = 4 + context->gpr[9];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_1001_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[11] = ~context->gpr[9];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_1001_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[9] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[9] << 8;
	temp2 = 65280 & temp2;
	context->gpr[11] = context->gpr[9] & 4294901760;
	context->gpr[11] = temp1 | context->gpr[11];
	context->gpr[11] = temp2 | context->gpr[11];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_1001_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[9] >> 16;
	context->gpr[11] = context->gpr[9] << 16;
	context->gpr[11] = temp | context->gpr[11];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_1001_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[9]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[11] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_1001_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[11] = -context->gpr[9];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_1001_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[11] = context->gpr[9] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_1001_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[11] = context->gpr[9] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_1001_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[11] = (context->gpr[11] & ~65535) | ((context->gpr[9] & 255) & 128 ? (context->gpr[9] & 255) | 65280 : (context->gpr[9] & 255));
	context->gpr[11] = (context->gpr[11] & 65535) & 32768 ? (context->gpr[11] & 65535) | 4294901760 : (context->gpr[11] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_1001_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[11] = (context->gpr[9] & 65535) & 32768 ? (context->gpr[9] & 65535) | 4294901760 : (context->gpr[9] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_1010_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[10] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[10], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[11] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_1010_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[10] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[10], context);
	context->gpr[11] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_1010_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[10] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[10], context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_1010_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[11] = context->gpr[10];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_1010_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[10] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[10], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[11] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[10] = 1 + context->gpr[10];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_1010_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[10] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[10], context);
	context->gpr[11] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[10] = 2 + context->gpr[10];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_1010_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[10] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[10], context);
	context->gpr[11] = context->scratch1;
	context->gpr[10] = 4 + context->gpr[10];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_1010_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[11] = ~context->gpr[10];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_1010_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[10] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[10] << 8;
	temp2 = 65280 & temp2;
	context->gpr[11] = context->gpr[10] & 4294901760;
	context->gpr[11] = temp1 | context->gpr[11];
	context->gpr[11] = temp2 | context->gpr[11];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_1010_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[10] >> 16;
	context->gpr[11] = context->gpr[10] << 16;
	context->gpr[11] = temp | context->gpr[11];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_1010_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[10]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[11] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_1010_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[11] = -context->gpr[10];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_1010_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[11] = context->gpr[10] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_1010_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[11] = context->gpr[10] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_1010_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[11] = (context->gpr[11] & ~65535) | ((context->gpr[10] & 255) & 128 ? (context->gpr[10] & 255) | 65280 : (context->gpr[10] & 255));
	context->gpr[11] = (context->gpr[11] & 65535) & 32768 ? (context->gpr[11] & 65535) | 4294901760 : (context->gpr[11] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_1010_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[11] = (context->gpr[10] & 65535) & 32768 ? (context->gpr[10] & 65535) | 4294901760 : (context->gpr[10] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_1011_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[11] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[11], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[11] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_1011_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[11] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[11], context);
	context->gpr[11] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_1011_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[11] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[11], context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_1011_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[11] = context->gpr[11];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_1011_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[11] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[11], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[11] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_1011_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[11] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[11], context);
	context->gpr[11] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_1011_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[11] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[11], context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_1011_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[11] = ~context->gpr[11];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_1011_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[11] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[11] << 8;
	temp2 = 65280 & temp2;
	context->gpr[11] = context->gpr[11] & 4294901760;
	context->gpr[11] = temp1 | context->gpr[11];
	context->gpr[11] = temp2 | context->gpr[11];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_1011_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[11] >> 16;
	context->gpr[11] = context->gpr[11] << 16;
	context->gpr[11] = temp | context->gpr[11];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_1011_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[11]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[11] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_1011_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[11] = -context->gpr[11];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_1011_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[11] = context->gpr[11] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_1011_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[11] = context->gpr[11] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_1011_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[11] = (context->gpr[11] & ~65535) | ((context->gpr[11] & 255) & 128 ? (context->gpr[11] & 255) | 65280 : (context->gpr[11] & 255));
	context->gpr[11] = (context->gpr[11] & 65535) & 32768 ? (context->gpr[11] & 65535) | 4294901760 : (context->gpr[11] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_1011_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[11] = (context->gpr[11] & 65535) & 32768 ? (context->gpr[11] & 65535) | 4294901760 : (context->gpr[11] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_1100_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[12] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[12], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[11] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_1100_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[12] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[12], context);
	context->gpr[11] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_1100_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[12] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[12], context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_1100_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[11] = context->gpr[12];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_1100_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[12] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[12], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[11] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[12] = 1 + context->gpr[12];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_1100_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[12] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[12], context);
	context->gpr[11] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[12] = 2 + context->gpr[12];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_1100_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[12] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[12], context);
	context->gpr[11] = context->scratch1;
	context->gpr[12] = 4 + context->gpr[12];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_1100_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[11] = ~context->gpr[12];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_1100_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[12] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[12] << 8;
	temp2 = 65280 & temp2;
	context->gpr[11] = context->gpr[12] & 4294901760;
	context->gpr[11] = temp1 | context->gpr[11];
	context->gpr[11] = temp2 | context->gpr[11];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_1100_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[12] >> 16;
	context->gpr[11] = context->gpr[12] << 16;
	context->gpr[11] = temp | context->gpr[11];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_1100_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[12]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[11] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_1100_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[11] = -context->gpr[12];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_1100_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[11] = context->gpr[12] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_1100_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[11] = context->gpr[12] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_1100_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[11] = (context->gpr[11] & ~65535) | ((context->gpr[12] & 255) & 128 ? (context->gpr[12] & 255) | 65280 : (context->gpr[12] & 255));
	context->gpr[11] = (context->gpr[11] & 65535) & 32768 ? (context->gpr[11] & 65535) | 4294901760 : (context->gpr[11] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_1100_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[11] = (context->gpr[12] & 65535) & 32768 ? (context->gpr[12] & 65535) | 4294901760 : (context->gpr[12] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_1101_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[13] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[13], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[11] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_1101_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[13] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[13], context);
	context->gpr[11] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_1101_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[13] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[13], context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_1101_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[11] = context->gpr[13];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_1101_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[13] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[13], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[11] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[13] = 1 + context->gpr[13];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_1101_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[13] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[13], context);
	context->gpr[11] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[13] = 2 + context->gpr[13];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_1101_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[13] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[13], context);
	context->gpr[11] = context->scratch1;
	context->gpr[13] = 4 + context->gpr[13];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_1101_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[11] = ~context->gpr[13];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_1101_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[13] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[13] << 8;
	temp2 = 65280 & temp2;
	context->gpr[11] = context->gpr[13] & 4294901760;
	context->gpr[11] = temp1 | context->gpr[11];
	context->gpr[11] = temp2 | context->gpr[11];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_1101_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[13] >> 16;
	context->gpr[11] = context->gpr[13] << 16;
	context->gpr[11] = temp | context->gpr[11];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_1101_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[13]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[11] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_1101_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[11] = -context->gpr[13];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_1101_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[11] = context->gpr[13] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_1101_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[11] = context->gpr[13] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_1101_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[11] = (context->gpr[11] & ~65535) | ((context->gpr[13] & 255) & 128 ? (context->gpr[13] & 255) | 65280 : (context->gpr[13] & 255));
	context->gpr[11] = (context->gpr[11] & 65535) & 32768 ? (context->gpr[11] & 65535) | 4294901760 : (context->gpr[11] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_1101_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[11] = (context->gpr[13] & 65535) & 32768 ? (context->gpr[13] & 65535) | 4294901760 : (context->gpr[13] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_1110_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[14] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[14], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[11] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_1110_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[14] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[14], context);
	context->gpr[11] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_1110_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[14] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[14], context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_1110_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[11] = context->gpr[14];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_1110_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[14] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[14], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[11] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[14] = 1 + context->gpr[14];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_1110_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[14] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[14], context);
	context->gpr[11] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[14] = 2 + context->gpr[14];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_1110_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[14] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[14], context);
	context->gpr[11] = context->scratch1;
	context->gpr[14] = 4 + context->gpr[14];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_1110_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[11] = ~context->gpr[14];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_1110_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[14] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[14] << 8;
	temp2 = 65280 & temp2;
	context->gpr[11] = context->gpr[14] & 4294901760;
	context->gpr[11] = temp1 | context->gpr[11];
	context->gpr[11] = temp2 | context->gpr[11];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_1110_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[14] >> 16;
	context->gpr[11] = context->gpr[14] << 16;
	context->gpr[11] = temp | context->gpr[11];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_1110_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[14]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[11] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_1110_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[11] = -context->gpr[14];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_1110_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[11] = context->gpr[14] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_1110_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[11] = context->gpr[14] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_1110_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[11] = (context->gpr[11] & ~65535) | ((context->gpr[14] & 255) & 128 ? (context->gpr[14] & 255) | 65280 : (context->gpr[14] & 255));
	context->gpr[11] = (context->gpr[11] & 65535) & 32768 ? (context->gpr[11] & 65535) | 4294901760 : (context->gpr[11] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_1110_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[11] = (context->gpr[14] & 65535) & 32768 ? (context->gpr[14] & 65535) | 4294901760 : (context->gpr[14] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_1111_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[15] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[15], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[11] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_1111_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[15] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[15], context);
	context->gpr[11] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_1111_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[15] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[15], context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_1111_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[11] = context->gpr[15];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_1111_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[15] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[15], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[11] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[15] = 1 + context->gpr[15];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_1111_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[15] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[15], context);
	context->gpr[11] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[15] = 2 + context->gpr[15];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_1111_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[15] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[15], context);
	context->gpr[11] = context->scratch1;
	context->gpr[15] = 4 + context->gpr[15];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_1111_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[11] = ~context->gpr[15];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_1111_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[15] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[15] << 8;
	temp2 = 65280 & temp2;
	context->gpr[11] = context->gpr[15] & 4294901760;
	context->gpr[11] = temp1 | context->gpr[11];
	context->gpr[11] = temp2 | context->gpr[11];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_1111_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[15] >> 16;
	context->gpr[11] = context->gpr[15] << 16;
	context->gpr[11] = temp | context->gpr[11];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_1111_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[15]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[11] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_1111_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[11] = -context->gpr[15];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_1111_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[11] = context->gpr[15] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_1111_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[11] = context->gpr[15] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_1111_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[11] = (context->gpr[11] & ~65535) | ((context->gpr[15] & 255) & 128 ? (context->gpr[15] & 255) | 65280 : (context->gpr[15] & 255));
	context->gpr[11] = (context->gpr[11] & 65535) & 32768 ? (context->gpr[11] & 65535) | 4294901760 : (context->gpr[11] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_1111_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[11] = (context->gpr[15] & 65535) & 32768 ? (context->gpr[15] & 65535) | 4294901760 : (context->gpr[15] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_0000_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[0] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[0], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[12] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_0000_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[0] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[0], context);
	context->gpr[12] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_0000_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[0] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[0], context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_0000_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[12] = context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_0000_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[0] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[0], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[12] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[0] = 1 + context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_0000_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[0] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[0], context);
	context->gpr[12] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[0] = 2 + context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_0000_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[0] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[0], context);
	context->gpr[12] = context->scratch1;
	context->gpr[0] = 4 + context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_0000_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[12] = ~context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_0000_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[0] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[0] << 8;
	temp2 = 65280 & temp2;
	context->gpr[12] = context->gpr[0] & 4294901760;
	context->gpr[12] = temp1 | context->gpr[12];
	context->gpr[12] = temp2 | context->gpr[12];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_0000_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[0] >> 16;
	context->gpr[12] = context->gpr[0] << 16;
	context->gpr[12] = temp | context->gpr[12];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_0000_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[0]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[12] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_0000_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[12] = -context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_0000_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[12] = context->gpr[0] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_0000_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[12] = context->gpr[0] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_0000_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[12] = (context->gpr[12] & ~65535) | ((context->gpr[0] & 255) & 128 ? (context->gpr[0] & 255) | 65280 : (context->gpr[0] & 255));
	context->gpr[12] = (context->gpr[12] & 65535) & 32768 ? (context->gpr[12] & 65535) | 4294901760 : (context->gpr[12] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_0000_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[12] = (context->gpr[0] & 65535) & 32768 ? (context->gpr[0] & 65535) | 4294901760 : (context->gpr[0] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_0001_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[1] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[1], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[12] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_0001_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[1] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[1], context);
	context->gpr[12] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_0001_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[1] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[1], context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_0001_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[12] = context->gpr[1];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_0001_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[1] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[1], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[12] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[1] = 1 + context->gpr[1];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_0001_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[1] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[1], context);
	context->gpr[12] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[1] = 2 + context->gpr[1];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_0001_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[1] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[1], context);
	context->gpr[12] = context->scratch1;
	context->gpr[1] = 4 + context->gpr[1];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_0001_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[12] = ~context->gpr[1];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_0001_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[1] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[1] << 8;
	temp2 = 65280 & temp2;
	context->gpr[12] = context->gpr[1] & 4294901760;
	context->gpr[12] = temp1 | context->gpr[12];
	context->gpr[12] = temp2 | context->gpr[12];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_0001_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[1] >> 16;
	context->gpr[12] = context->gpr[1] << 16;
	context->gpr[12] = temp | context->gpr[12];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_0001_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[1]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[12] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_0001_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[12] = -context->gpr[1];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_0001_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[12] = context->gpr[1] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_0001_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[12] = context->gpr[1] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_0001_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[12] = (context->gpr[12] & ~65535) | ((context->gpr[1] & 255) & 128 ? (context->gpr[1] & 255) | 65280 : (context->gpr[1] & 255));
	context->gpr[12] = (context->gpr[12] & 65535) & 32768 ? (context->gpr[12] & 65535) | 4294901760 : (context->gpr[12] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_0001_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[12] = (context->gpr[1] & 65535) & 32768 ? (context->gpr[1] & 65535) | 4294901760 : (context->gpr[1] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_0010_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[2] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[2], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[12] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_0010_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[2] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[2], context);
	context->gpr[12] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_0010_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[2] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[2], context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_0010_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[12] = context->gpr[2];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_0010_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[2] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[2], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[12] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[2] = 1 + context->gpr[2];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_0010_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[2] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[2], context);
	context->gpr[12] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[2] = 2 + context->gpr[2];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_0010_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[2] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[2], context);
	context->gpr[12] = context->scratch1;
	context->gpr[2] = 4 + context->gpr[2];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_0010_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[12] = ~context->gpr[2];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_0010_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[2] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[2] << 8;
	temp2 = 65280 & temp2;
	context->gpr[12] = context->gpr[2] & 4294901760;
	context->gpr[12] = temp1 | context->gpr[12];
	context->gpr[12] = temp2 | context->gpr[12];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_0010_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[2] >> 16;
	context->gpr[12] = context->gpr[2] << 16;
	context->gpr[12] = temp | context->gpr[12];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_0010_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[2]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[12] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_0010_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[12] = -context->gpr[2];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_0010_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[12] = context->gpr[2] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_0010_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[12] = context->gpr[2] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_0010_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[12] = (context->gpr[12] & ~65535) | ((context->gpr[2] & 255) & 128 ? (context->gpr[2] & 255) | 65280 : (context->gpr[2] & 255));
	context->gpr[12] = (context->gpr[12] & 65535) & 32768 ? (context->gpr[12] & 65535) | 4294901760 : (context->gpr[12] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_0010_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[12] = (context->gpr[2] & 65535) & 32768 ? (context->gpr[2] & 65535) | 4294901760 : (context->gpr[2] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_0011_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[3] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[3], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[12] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_0011_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[3] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[3], context);
	context->gpr[12] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_0011_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[3] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[3], context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_0011_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[12] = context->gpr[3];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_0011_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[3] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[3], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[12] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[3] = 1 + context->gpr[3];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_0011_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[3] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[3], context);
	context->gpr[12] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[3] = 2 + context->gpr[3];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_0011_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[3] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[3], context);
	context->gpr[12] = context->scratch1;
	context->gpr[3] = 4 + context->gpr[3];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_0011_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[12] = ~context->gpr[3];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_0011_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[3] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[3] << 8;
	temp2 = 65280 & temp2;
	context->gpr[12] = context->gpr[3] & 4294901760;
	context->gpr[12] = temp1 | context->gpr[12];
	context->gpr[12] = temp2 | context->gpr[12];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_0011_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[3] >> 16;
	context->gpr[12] = context->gpr[3] << 16;
	context->gpr[12] = temp | context->gpr[12];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_0011_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[3]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[12] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_0011_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[12] = -context->gpr[3];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_0011_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[12] = context->gpr[3] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_0011_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[12] = context->gpr[3] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_0011_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[12] = (context->gpr[12] & ~65535) | ((context->gpr[3] & 255) & 128 ? (context->gpr[3] & 255) | 65280 : (context->gpr[3] & 255));
	context->gpr[12] = (context->gpr[12] & 65535) & 32768 ? (context->gpr[12] & 65535) | 4294901760 : (context->gpr[12] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_0011_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[12] = (context->gpr[3] & 65535) & 32768 ? (context->gpr[3] & 65535) | 4294901760 : (context->gpr[3] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_0100_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[4] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[4], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[12] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_0100_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[4] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[4], context);
	context->gpr[12] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_0100_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[4] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[4], context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_0100_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[12] = context->gpr[4];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_0100_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[4] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[4], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[12] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[4] = 1 + context->gpr[4];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_0100_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[4] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[4], context);
	context->gpr[12] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[4] = 2 + context->gpr[4];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_0100_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[4] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[4], context);
	context->gpr[12] = context->scratch1;
	context->gpr[4] = 4 + context->gpr[4];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_0100_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[12] = ~context->gpr[4];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_0100_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[4] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[4] << 8;
	temp2 = 65280 & temp2;
	context->gpr[12] = context->gpr[4] & 4294901760;
	context->gpr[12] = temp1 | context->gpr[12];
	context->gpr[12] = temp2 | context->gpr[12];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_0100_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[4] >> 16;
	context->gpr[12] = context->gpr[4] << 16;
	context->gpr[12] = temp | context->gpr[12];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_0100_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[4]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[12] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_0100_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[12] = -context->gpr[4];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_0100_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[12] = context->gpr[4] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_0100_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[12] = context->gpr[4] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_0100_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[12] = (context->gpr[12] & ~65535) | ((context->gpr[4] & 255) & 128 ? (context->gpr[4] & 255) | 65280 : (context->gpr[4] & 255));
	context->gpr[12] = (context->gpr[12] & 65535) & 32768 ? (context->gpr[12] & 65535) | 4294901760 : (context->gpr[12] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_0100_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[12] = (context->gpr[4] & 65535) & 32768 ? (context->gpr[4] & 65535) | 4294901760 : (context->gpr[4] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_0101_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[5] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[5], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[12] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_0101_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[5] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[5], context);
	context->gpr[12] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_0101_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[5] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[5], context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_0101_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[12] = context->gpr[5];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_0101_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[5] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[5], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[12] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[5] = 1 + context->gpr[5];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_0101_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[5] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[5], context);
	context->gpr[12] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[5] = 2 + context->gpr[5];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_0101_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[5] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[5], context);
	context->gpr[12] = context->scratch1;
	context->gpr[5] = 4 + context->gpr[5];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_0101_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[12] = ~context->gpr[5];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_0101_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[5] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[5] << 8;
	temp2 = 65280 & temp2;
	context->gpr[12] = context->gpr[5] & 4294901760;
	context->gpr[12] = temp1 | context->gpr[12];
	context->gpr[12] = temp2 | context->gpr[12];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_0101_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[5] >> 16;
	context->gpr[12] = context->gpr[5] << 16;
	context->gpr[12] = temp | context->gpr[12];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_0101_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[5]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[12] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_0101_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[12] = -context->gpr[5];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_0101_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[12] = context->gpr[5] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_0101_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[12] = context->gpr[5] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_0101_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[12] = (context->gpr[12] & ~65535) | ((context->gpr[5] & 255) & 128 ? (context->gpr[5] & 255) | 65280 : (context->gpr[5] & 255));
	context->gpr[12] = (context->gpr[12] & 65535) & 32768 ? (context->gpr[12] & 65535) | 4294901760 : (context->gpr[12] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_0101_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[12] = (context->gpr[5] & 65535) & 32768 ? (context->gpr[5] & 65535) | 4294901760 : (context->gpr[5] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_0110_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[6] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[6], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[12] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_0110_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[6] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[6], context);
	context->gpr[12] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_0110_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[6] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[6], context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_0110_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[12] = context->gpr[6];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_0110_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[6] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[6], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[12] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[6] = 1 + context->gpr[6];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_0110_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[6] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[6], context);
	context->gpr[12] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[6] = 2 + context->gpr[6];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_0110_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[6] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[6], context);
	context->gpr[12] = context->scratch1;
	context->gpr[6] = 4 + context->gpr[6];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_0110_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[12] = ~context->gpr[6];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_0110_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[6] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[6] << 8;
	temp2 = 65280 & temp2;
	context->gpr[12] = context->gpr[6] & 4294901760;
	context->gpr[12] = temp1 | context->gpr[12];
	context->gpr[12] = temp2 | context->gpr[12];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_0110_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[6] >> 16;
	context->gpr[12] = context->gpr[6] << 16;
	context->gpr[12] = temp | context->gpr[12];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_0110_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[6]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[12] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_0110_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[12] = -context->gpr[6];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_0110_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[12] = context->gpr[6] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_0110_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[12] = context->gpr[6] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_0110_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[12] = (context->gpr[12] & ~65535) | ((context->gpr[6] & 255) & 128 ? (context->gpr[6] & 255) | 65280 : (context->gpr[6] & 255));
	context->gpr[12] = (context->gpr[12] & 65535) & 32768 ? (context->gpr[12] & 65535) | 4294901760 : (context->gpr[12] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_0110_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[12] = (context->gpr[6] & 65535) & 32768 ? (context->gpr[6] & 65535) | 4294901760 : (context->gpr[6] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_0111_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[7] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[7], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[12] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_0111_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[7] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[7], context);
	context->gpr[12] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_0111_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[7] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[7], context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_0111_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[12] = context->gpr[7];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_0111_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[7] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[7], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[12] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[7] = 1 + context->gpr[7];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_0111_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[7] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[7], context);
	context->gpr[12] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[7] = 2 + context->gpr[7];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_0111_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[7] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[7], context);
	context->gpr[12] = context->scratch1;
	context->gpr[7] = 4 + context->gpr[7];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_0111_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[12] = ~context->gpr[7];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_0111_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[7] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[7] << 8;
	temp2 = 65280 & temp2;
	context->gpr[12] = context->gpr[7] & 4294901760;
	context->gpr[12] = temp1 | context->gpr[12];
	context->gpr[12] = temp2 | context->gpr[12];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_0111_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[7] >> 16;
	context->gpr[12] = context->gpr[7] << 16;
	context->gpr[12] = temp | context->gpr[12];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_0111_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[7]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[12] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_0111_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[12] = -context->gpr[7];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_0111_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[12] = context->gpr[7] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_0111_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[12] = context->gpr[7] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_0111_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[12] = (context->gpr[12] & ~65535) | ((context->gpr[7] & 255) & 128 ? (context->gpr[7] & 255) | 65280 : (context->gpr[7] & 255));
	context->gpr[12] = (context->gpr[12] & 65535) & 32768 ? (context->gpr[12] & 65535) | 4294901760 : (context->gpr[12] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_0111_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[12] = (context->gpr[7] & 65535) & 32768 ? (context->gpr[7] & 65535) | 4294901760 : (context->gpr[7] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_1000_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[8] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[8], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[12] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_1000_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[8] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[8], context);
	context->gpr[12] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_1000_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[8] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[8], context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_1000_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[12] = context->gpr[8];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_1000_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[8] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[8], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[12] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[8] = 1 + context->gpr[8];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_1000_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[8] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[8], context);
	context->gpr[12] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[8] = 2 + context->gpr[8];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_1000_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[8] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[8], context);
	context->gpr[12] = context->scratch1;
	context->gpr[8] = 4 + context->gpr[8];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_1000_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[12] = ~context->gpr[8];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_1000_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[8] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[8] << 8;
	temp2 = 65280 & temp2;
	context->gpr[12] = context->gpr[8] & 4294901760;
	context->gpr[12] = temp1 | context->gpr[12];
	context->gpr[12] = temp2 | context->gpr[12];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_1000_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[8] >> 16;
	context->gpr[12] = context->gpr[8] << 16;
	context->gpr[12] = temp | context->gpr[12];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_1000_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[8]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[12] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_1000_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[12] = -context->gpr[8];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_1000_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[12] = context->gpr[8] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_1000_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[12] = context->gpr[8] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_1000_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[12] = (context->gpr[12] & ~65535) | ((context->gpr[8] & 255) & 128 ? (context->gpr[8] & 255) | 65280 : (context->gpr[8] & 255));
	context->gpr[12] = (context->gpr[12] & 65535) & 32768 ? (context->gpr[12] & 65535) | 4294901760 : (context->gpr[12] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_1000_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[12] = (context->gpr[8] & 65535) & 32768 ? (context->gpr[8] & 65535) | 4294901760 : (context->gpr[8] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_1001_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[9] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[9], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[12] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_1001_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[9] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[9], context);
	context->gpr[12] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_1001_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[9] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[9], context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_1001_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[12] = context->gpr[9];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_1001_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[9] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[9], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[12] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[9] = 1 + context->gpr[9];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_1001_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[9] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[9], context);
	context->gpr[12] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[9] = 2 + context->gpr[9];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_1001_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[9] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[9], context);
	context->gpr[12] = context->scratch1;
	context->gpr[9] = 4 + context->gpr[9];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_1001_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[12] = ~context->gpr[9];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_1001_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[9] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[9] << 8;
	temp2 = 65280 & temp2;
	context->gpr[12] = context->gpr[9] & 4294901760;
	context->gpr[12] = temp1 | context->gpr[12];
	context->gpr[12] = temp2 | context->gpr[12];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_1001_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[9] >> 16;
	context->gpr[12] = context->gpr[9] << 16;
	context->gpr[12] = temp | context->gpr[12];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_1001_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[9]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[12] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_1001_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[12] = -context->gpr[9];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_1001_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[12] = context->gpr[9] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_1001_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[12] = context->gpr[9] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_1001_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[12] = (context->gpr[12] & ~65535) | ((context->gpr[9] & 255) & 128 ? (context->gpr[9] & 255) | 65280 : (context->gpr[9] & 255));
	context->gpr[12] = (context->gpr[12] & 65535) & 32768 ? (context->gpr[12] & 65535) | 4294901760 : (context->gpr[12] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_1001_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[12] = (context->gpr[9] & 65535) & 32768 ? (context->gpr[9] & 65535) | 4294901760 : (context->gpr[9] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_1010_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[10] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[10], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[12] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_1010_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[10] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[10], context);
	context->gpr[12] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_1010_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[10] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[10], context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_1010_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[12] = context->gpr[10];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_1010_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[10] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[10], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[12] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[10] = 1 + context->gpr[10];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_1010_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[10] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[10], context);
	context->gpr[12] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[10] = 2 + context->gpr[10];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_1010_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[10] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[10], context);
	context->gpr[12] = context->scratch1;
	context->gpr[10] = 4 + context->gpr[10];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_1010_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[12] = ~context->gpr[10];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_1010_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[10] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[10] << 8;
	temp2 = 65280 & temp2;
	context->gpr[12] = context->gpr[10] & 4294901760;
	context->gpr[12] = temp1 | context->gpr[12];
	context->gpr[12] = temp2 | context->gpr[12];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_1010_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[10] >> 16;
	context->gpr[12] = context->gpr[10] << 16;
	context->gpr[12] = temp | context->gpr[12];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_1010_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[10]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[12] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_1010_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[12] = -context->gpr[10];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_1010_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[12] = context->gpr[10] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_1010_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[12] = context->gpr[10] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_1010_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[12] = (context->gpr[12] & ~65535) | ((context->gpr[10] & 255) & 128 ? (context->gpr[10] & 255) | 65280 : (context->gpr[10] & 255));
	context->gpr[12] = (context->gpr[12] & 65535) & 32768 ? (context->gpr[12] & 65535) | 4294901760 : (context->gpr[12] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_1010_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[12] = (context->gpr[10] & 65535) & 32768 ? (context->gpr[10] & 65535) | 4294901760 : (context->gpr[10] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_1011_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[11] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[11], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[12] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_1011_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[11] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[11], context);
	context->gpr[12] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_1011_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[11] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[11], context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_1011_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[12] = context->gpr[11];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_1011_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[11] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[11], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[12] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[11] = 1 + context->gpr[11];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_1011_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[11] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[11], context);
	context->gpr[12] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[11] = 2 + context->gpr[11];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_1011_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[11] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[11], context);
	context->gpr[12] = context->scratch1;
	context->gpr[11] = 4 + context->gpr[11];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_1011_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[12] = ~context->gpr[11];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_1011_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[11] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[11] << 8;
	temp2 = 65280 & temp2;
	context->gpr[12] = context->gpr[11] & 4294901760;
	context->gpr[12] = temp1 | context->gpr[12];
	context->gpr[12] = temp2 | context->gpr[12];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_1011_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[11] >> 16;
	context->gpr[12] = context->gpr[11] << 16;
	context->gpr[12] = temp | context->gpr[12];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_1011_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[11]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[12] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_1011_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[12] = -context->gpr[11];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_1011_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[12] = context->gpr[11] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_1011_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[12] = context->gpr[11] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_1011_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[12] = (context->gpr[12] & ~65535) | ((context->gpr[11] & 255) & 128 ? (context->gpr[11] & 255) | 65280 : (context->gpr[11] & 255));
	context->gpr[12] = (context->gpr[12] & 65535) & 32768 ? (context->gpr[12] & 65535) | 4294901760 : (context->gpr[12] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_1011_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[12] = (context->gpr[11] & 65535) & 32768 ? (context->gpr[11] & 65535) | 4294901760 : (context->gpr[11] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_1100_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[12] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[12], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[12] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_1100_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[12] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[12], context);
	context->gpr[12] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_1100_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[12] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[12], context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_1100_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[12] = context->gpr[12];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_1100_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[12] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[12], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[12] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_1100_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[12] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[12], context);
	context->gpr[12] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_1100_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[12] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[12], context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_1100_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[12] = ~context->gpr[12];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_1100_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[12] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[12] << 8;
	temp2 = 65280 & temp2;
	context->gpr[12] = context->gpr[12] & 4294901760;
	context->gpr[12] = temp1 | context->gpr[12];
	context->gpr[12] = temp2 | context->gpr[12];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_1100_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[12] >> 16;
	context->gpr[12] = context->gpr[12] << 16;
	context->gpr[12] = temp | context->gpr[12];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_1100_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[12]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[12] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_1100_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[12] = -context->gpr[12];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_1100_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[12] = context->gpr[12] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_1100_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[12] = context->gpr[12] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_1100_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[12] = (context->gpr[12] & ~65535) | ((context->gpr[12] & 255) & 128 ? (context->gpr[12] & 255) | 65280 : (context->gpr[12] & 255));
	context->gpr[12] = (context->gpr[12] & 65535) & 32768 ? (context->gpr[12] & 65535) | 4294901760 : (context->gpr[12] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_1100_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[12] = (context->gpr[12] & 65535) & 32768 ? (context->gpr[12] & 65535) | 4294901760 : (context->gpr[12] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_1101_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[13] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[13], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[12] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_1101_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[13] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[13], context);
	context->gpr[12] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_1101_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[13] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[13], context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_1101_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[12] = context->gpr[13];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_1101_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[13] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[13], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[12] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[13] = 1 + context->gpr[13];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_1101_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[13] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[13], context);
	context->gpr[12] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[13] = 2 + context->gpr[13];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_1101_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[13] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[13], context);
	context->gpr[12] = context->scratch1;
	context->gpr[13] = 4 + context->gpr[13];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_1101_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[12] = ~context->gpr[13];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_1101_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[13] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[13] << 8;
	temp2 = 65280 & temp2;
	context->gpr[12] = context->gpr[13] & 4294901760;
	context->gpr[12] = temp1 | context->gpr[12];
	context->gpr[12] = temp2 | context->gpr[12];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_1101_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[13] >> 16;
	context->gpr[12] = context->gpr[13] << 16;
	context->gpr[12] = temp | context->gpr[12];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_1101_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[13]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[12] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_1101_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[12] = -context->gpr[13];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_1101_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[12] = context->gpr[13] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_1101_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[12] = context->gpr[13] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_1101_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[12] = (context->gpr[12] & ~65535) | ((context->gpr[13] & 255) & 128 ? (context->gpr[13] & 255) | 65280 : (context->gpr[13] & 255));
	context->gpr[12] = (context->gpr[12] & 65535) & 32768 ? (context->gpr[12] & 65535) | 4294901760 : (context->gpr[12] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_1101_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[12] = (context->gpr[13] & 65535) & 32768 ? (context->gpr[13] & 65535) | 4294901760 : (context->gpr[13] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_1110_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[14] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[14], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[12] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_1110_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[14] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[14], context);
	context->gpr[12] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_1110_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[14] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[14], context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_1110_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[12] = context->gpr[14];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_1110_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[14] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[14], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[12] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[14] = 1 + context->gpr[14];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_1110_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[14] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[14], context);
	context->gpr[12] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[14] = 2 + context->gpr[14];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_1110_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[14] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[14], context);
	context->gpr[12] = context->scratch1;
	context->gpr[14] = 4 + context->gpr[14];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_1110_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[12] = ~context->gpr[14];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_1110_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[14] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[14] << 8;
	temp2 = 65280 & temp2;
	context->gpr[12] = context->gpr[14] & 4294901760;
	context->gpr[12] = temp1 | context->gpr[12];
	context->gpr[12] = temp2 | context->gpr[12];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_1110_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[14] >> 16;
	context->gpr[12] = context->gpr[14] << 16;
	context->gpr[12] = temp | context->gpr[12];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_1110_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[14]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[12] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_1110_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[12] = -context->gpr[14];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_1110_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[12] = context->gpr[14] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_1110_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[12] = context->gpr[14] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_1110_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[12] = (context->gpr[12] & ~65535) | ((context->gpr[14] & 255) & 128 ? (context->gpr[14] & 255) | 65280 : (context->gpr[14] & 255));
	context->gpr[12] = (context->gpr[12] & 65535) & 32768 ? (context->gpr[12] & 65535) | 4294901760 : (context->gpr[12] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_1110_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[12] = (context->gpr[14] & 65535) & 32768 ? (context->gpr[14] & 65535) | 4294901760 : (context->gpr[14] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_1111_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[15] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[15], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[12] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_1111_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[15] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[15], context);
	context->gpr[12] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_1111_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[15] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[15], context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_1111_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[12] = context->gpr[15];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_1111_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[15] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[15], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[12] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[15] = 1 + context->gpr[15];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_1111_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[15] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[15], context);
	context->gpr[12] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[15] = 2 + context->gpr[15];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_1111_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[15] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[15], context);
	context->gpr[12] = context->scratch1;
	context->gpr[15] = 4 + context->gpr[15];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_1111_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[12] = ~context->gpr[15];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_1111_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[15] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[15] << 8;
	temp2 = 65280 & temp2;
	context->gpr[12] = context->gpr[15] & 4294901760;
	context->gpr[12] = temp1 | context->gpr[12];
	context->gpr[12] = temp2 | context->gpr[12];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_1111_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[15] >> 16;
	context->gpr[12] = context->gpr[15] << 16;
	context->gpr[12] = temp | context->gpr[12];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_1111_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[15]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[12] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_1111_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[12] = -context->gpr[15];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_1111_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[12] = context->gpr[15] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_1111_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[12] = context->gpr[15] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_1111_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[12] = (context->gpr[12] & ~65535) | ((context->gpr[15] & 255) & 128 ? (context->gpr[15] & 255) | 65280 : (context->gpr[15] & 255));
	context->gpr[12] = (context->gpr[12] & 65535) & 32768 ? (context->gpr[12] & 65535) | 4294901760 : (context->gpr[12] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_1111_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[12] = (context->gpr[15] & 65535) & 32768 ? (context->gpr[15] & 65535) | 4294901760 : (context->gpr[15] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_0000_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[0] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[0], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[13] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_0000_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[0] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[0], context);
	context->gpr[13] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_0000_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[0] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[0], context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_0000_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[13] = context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_0000_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[0] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[0], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[13] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[0] = 1 + context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_0000_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[0] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[0], context);
	context->gpr[13] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[0] = 2 + context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_0000_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[0] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[0], context);
	context->gpr[13] = context->scratch1;
	context->gpr[0] = 4 + context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_0000_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[13] = ~context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_0000_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[0] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[0] << 8;
	temp2 = 65280 & temp2;
	context->gpr[13] = context->gpr[0] & 4294901760;
	context->gpr[13] = temp1 | context->gpr[13];
	context->gpr[13] = temp2 | context->gpr[13];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_0000_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[0] >> 16;
	context->gpr[13] = context->gpr[0] << 16;
	context->gpr[13] = temp | context->gpr[13];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_0000_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[0]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[13] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_0000_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[13] = -context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_0000_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[13] = context->gpr[0] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_0000_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[13] = context->gpr[0] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_0000_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[13] = (context->gpr[13] & ~65535) | ((context->gpr[0] & 255) & 128 ? (context->gpr[0] & 255) | 65280 : (context->gpr[0] & 255));
	context->gpr[13] = (context->gpr[13] & 65535) & 32768 ? (context->gpr[13] & 65535) | 4294901760 : (context->gpr[13] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_0000_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[13] = (context->gpr[0] & 65535) & 32768 ? (context->gpr[0] & 65535) | 4294901760 : (context->gpr[0] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_0001_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[1] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[1], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[13] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_0001_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[1] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[1], context);
	context->gpr[13] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_0001_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[1] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[1], context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_0001_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[13] = context->gpr[1];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_0001_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[1] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[1], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[13] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[1] = 1 + context->gpr[1];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_0001_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[1] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[1], context);
	context->gpr[13] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[1] = 2 + context->gpr[1];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_0001_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[1] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[1], context);
	context->gpr[13] = context->scratch1;
	context->gpr[1] = 4 + context->gpr[1];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_0001_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[13] = ~context->gpr[1];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_0001_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[1] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[1] << 8;
	temp2 = 65280 & temp2;
	context->gpr[13] = context->gpr[1] & 4294901760;
	context->gpr[13] = temp1 | context->gpr[13];
	context->gpr[13] = temp2 | context->gpr[13];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_0001_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[1] >> 16;
	context->gpr[13] = context->gpr[1] << 16;
	context->gpr[13] = temp | context->gpr[13];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_0001_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[1]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[13] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_0001_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[13] = -context->gpr[1];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_0001_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[13] = context->gpr[1] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_0001_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[13] = context->gpr[1] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_0001_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[13] = (context->gpr[13] & ~65535) | ((context->gpr[1] & 255) & 128 ? (context->gpr[1] & 255) | 65280 : (context->gpr[1] & 255));
	context->gpr[13] = (context->gpr[13] & 65535) & 32768 ? (context->gpr[13] & 65535) | 4294901760 : (context->gpr[13] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_0001_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[13] = (context->gpr[1] & 65535) & 32768 ? (context->gpr[1] & 65535) | 4294901760 : (context->gpr[1] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_0010_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[2] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[2], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[13] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_0010_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[2] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[2], context);
	context->gpr[13] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_0010_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[2] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[2], context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_0010_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[13] = context->gpr[2];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_0010_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[2] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[2], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[13] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[2] = 1 + context->gpr[2];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_0010_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[2] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[2], context);
	context->gpr[13] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[2] = 2 + context->gpr[2];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_0010_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[2] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[2], context);
	context->gpr[13] = context->scratch1;
	context->gpr[2] = 4 + context->gpr[2];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_0010_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[13] = ~context->gpr[2];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_0010_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[2] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[2] << 8;
	temp2 = 65280 & temp2;
	context->gpr[13] = context->gpr[2] & 4294901760;
	context->gpr[13] = temp1 | context->gpr[13];
	context->gpr[13] = temp2 | context->gpr[13];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_0010_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[2] >> 16;
	context->gpr[13] = context->gpr[2] << 16;
	context->gpr[13] = temp | context->gpr[13];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_0010_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[2]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[13] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_0010_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[13] = -context->gpr[2];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_0010_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[13] = context->gpr[2] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_0010_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[13] = context->gpr[2] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_0010_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[13] = (context->gpr[13] & ~65535) | ((context->gpr[2] & 255) & 128 ? (context->gpr[2] & 255) | 65280 : (context->gpr[2] & 255));
	context->gpr[13] = (context->gpr[13] & 65535) & 32768 ? (context->gpr[13] & 65535) | 4294901760 : (context->gpr[13] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_0010_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[13] = (context->gpr[2] & 65535) & 32768 ? (context->gpr[2] & 65535) | 4294901760 : (context->gpr[2] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_0011_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[3] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[3], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[13] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_0011_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[3] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[3], context);
	context->gpr[13] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_0011_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[3] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[3], context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_0011_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[13] = context->gpr[3];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_0011_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[3] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[3], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[13] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[3] = 1 + context->gpr[3];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_0011_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[3] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[3], context);
	context->gpr[13] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[3] = 2 + context->gpr[3];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_0011_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[3] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[3], context);
	context->gpr[13] = context->scratch1;
	context->gpr[3] = 4 + context->gpr[3];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_0011_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[13] = ~context->gpr[3];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_0011_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[3] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[3] << 8;
	temp2 = 65280 & temp2;
	context->gpr[13] = context->gpr[3] & 4294901760;
	context->gpr[13] = temp1 | context->gpr[13];
	context->gpr[13] = temp2 | context->gpr[13];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_0011_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[3] >> 16;
	context->gpr[13] = context->gpr[3] << 16;
	context->gpr[13] = temp | context->gpr[13];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_0011_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[3]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[13] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_0011_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[13] = -context->gpr[3];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_0011_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[13] = context->gpr[3] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_0011_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[13] = context->gpr[3] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_0011_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[13] = (context->gpr[13] & ~65535) | ((context->gpr[3] & 255) & 128 ? (context->gpr[3] & 255) | 65280 : (context->gpr[3] & 255));
	context->gpr[13] = (context->gpr[13] & 65535) & 32768 ? (context->gpr[13] & 65535) | 4294901760 : (context->gpr[13] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_0011_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[13] = (context->gpr[3] & 65535) & 32768 ? (context->gpr[3] & 65535) | 4294901760 : (context->gpr[3] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_0100_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[4] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[4], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[13] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_0100_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[4] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[4], context);
	context->gpr[13] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_0100_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[4] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[4], context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_0100_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[13] = context->gpr[4];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_0100_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[4] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[4], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[13] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[4] = 1 + context->gpr[4];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_0100_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[4] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[4], context);
	context->gpr[13] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[4] = 2 + context->gpr[4];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_0100_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[4] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[4], context);
	context->gpr[13] = context->scratch1;
	context->gpr[4] = 4 + context->gpr[4];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_0100_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[13] = ~context->gpr[4];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_0100_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[4] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[4] << 8;
	temp2 = 65280 & temp2;
	context->gpr[13] = context->gpr[4] & 4294901760;
	context->gpr[13] = temp1 | context->gpr[13];
	context->gpr[13] = temp2 | context->gpr[13];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_0100_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[4] >> 16;
	context->gpr[13] = context->gpr[4] << 16;
	context->gpr[13] = temp | context->gpr[13];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_0100_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[4]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[13] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_0100_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[13] = -context->gpr[4];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_0100_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[13] = context->gpr[4] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_0100_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[13] = context->gpr[4] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_0100_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[13] = (context->gpr[13] & ~65535) | ((context->gpr[4] & 255) & 128 ? (context->gpr[4] & 255) | 65280 : (context->gpr[4] & 255));
	context->gpr[13] = (context->gpr[13] & 65535) & 32768 ? (context->gpr[13] & 65535) | 4294901760 : (context->gpr[13] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_0100_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[13] = (context->gpr[4] & 65535) & 32768 ? (context->gpr[4] & 65535) | 4294901760 : (context->gpr[4] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_0101_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[5] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[5], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[13] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_0101_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[5] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[5], context);
	context->gpr[13] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_0101_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[5] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[5], context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_0101_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[13] = context->gpr[5];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_0101_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[5] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[5], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[13] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[5] = 1 + context->gpr[5];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_0101_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[5] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[5], context);
	context->gpr[13] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[5] = 2 + context->gpr[5];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_0101_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[5] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[5], context);
	context->gpr[13] = context->scratch1;
	context->gpr[5] = 4 + context->gpr[5];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_0101_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[13] = ~context->gpr[5];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_0101_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[5] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[5] << 8;
	temp2 = 65280 & temp2;
	context->gpr[13] = context->gpr[5] & 4294901760;
	context->gpr[13] = temp1 | context->gpr[13];
	context->gpr[13] = temp2 | context->gpr[13];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_0101_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[5] >> 16;
	context->gpr[13] = context->gpr[5] << 16;
	context->gpr[13] = temp | context->gpr[13];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_0101_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[5]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[13] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_0101_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[13] = -context->gpr[5];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_0101_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[13] = context->gpr[5] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_0101_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[13] = context->gpr[5] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_0101_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[13] = (context->gpr[13] & ~65535) | ((context->gpr[5] & 255) & 128 ? (context->gpr[5] & 255) | 65280 : (context->gpr[5] & 255));
	context->gpr[13] = (context->gpr[13] & 65535) & 32768 ? (context->gpr[13] & 65535) | 4294901760 : (context->gpr[13] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_0101_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[13] = (context->gpr[5] & 65535) & 32768 ? (context->gpr[5] & 65535) | 4294901760 : (context->gpr[5] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_0110_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[6] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[6], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[13] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_0110_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[6] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[6], context);
	context->gpr[13] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_0110_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[6] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[6], context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_0110_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[13] = context->gpr[6];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_0110_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[6] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[6], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[13] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[6] = 1 + context->gpr[6];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_0110_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[6] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[6], context);
	context->gpr[13] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[6] = 2 + context->gpr[6];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_0110_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[6] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[6], context);
	context->gpr[13] = context->scratch1;
	context->gpr[6] = 4 + context->gpr[6];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_0110_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[13] = ~context->gpr[6];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_0110_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[6] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[6] << 8;
	temp2 = 65280 & temp2;
	context->gpr[13] = context->gpr[6] & 4294901760;
	context->gpr[13] = temp1 | context->gpr[13];
	context->gpr[13] = temp2 | context->gpr[13];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_0110_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[6] >> 16;
	context->gpr[13] = context->gpr[6] << 16;
	context->gpr[13] = temp | context->gpr[13];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_0110_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[6]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[13] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_0110_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[13] = -context->gpr[6];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_0110_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[13] = context->gpr[6] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_0110_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[13] = context->gpr[6] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_0110_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[13] = (context->gpr[13] & ~65535) | ((context->gpr[6] & 255) & 128 ? (context->gpr[6] & 255) | 65280 : (context->gpr[6] & 255));
	context->gpr[13] = (context->gpr[13] & 65535) & 32768 ? (context->gpr[13] & 65535) | 4294901760 : (context->gpr[13] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_0110_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[13] = (context->gpr[6] & 65535) & 32768 ? (context->gpr[6] & 65535) | 4294901760 : (context->gpr[6] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_0111_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[7] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[7], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[13] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_0111_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[7] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[7], context);
	context->gpr[13] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_0111_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[7] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[7], context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_0111_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[13] = context->gpr[7];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_0111_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[7] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[7], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[13] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[7] = 1 + context->gpr[7];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_0111_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[7] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[7], context);
	context->gpr[13] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[7] = 2 + context->gpr[7];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_0111_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[7] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[7], context);
	context->gpr[13] = context->scratch1;
	context->gpr[7] = 4 + context->gpr[7];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_0111_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[13] = ~context->gpr[7];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_0111_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[7] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[7] << 8;
	temp2 = 65280 & temp2;
	context->gpr[13] = context->gpr[7] & 4294901760;
	context->gpr[13] = temp1 | context->gpr[13];
	context->gpr[13] = temp2 | context->gpr[13];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_0111_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[7] >> 16;
	context->gpr[13] = context->gpr[7] << 16;
	context->gpr[13] = temp | context->gpr[13];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_0111_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[7]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[13] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_0111_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[13] = -context->gpr[7];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_0111_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[13] = context->gpr[7] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_0111_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[13] = context->gpr[7] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_0111_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[13] = (context->gpr[13] & ~65535) | ((context->gpr[7] & 255) & 128 ? (context->gpr[7] & 255) | 65280 : (context->gpr[7] & 255));
	context->gpr[13] = (context->gpr[13] & 65535) & 32768 ? (context->gpr[13] & 65535) | 4294901760 : (context->gpr[13] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_0111_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[13] = (context->gpr[7] & 65535) & 32768 ? (context->gpr[7] & 65535) | 4294901760 : (context->gpr[7] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_1000_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[8] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[8], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[13] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_1000_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[8] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[8], context);
	context->gpr[13] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_1000_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[8] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[8], context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_1000_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[13] = context->gpr[8];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_1000_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[8] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[8], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[13] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[8] = 1 + context->gpr[8];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_1000_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[8] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[8], context);
	context->gpr[13] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[8] = 2 + context->gpr[8];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_1000_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[8] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[8], context);
	context->gpr[13] = context->scratch1;
	context->gpr[8] = 4 + context->gpr[8];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_1000_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[13] = ~context->gpr[8];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_1000_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[8] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[8] << 8;
	temp2 = 65280 & temp2;
	context->gpr[13] = context->gpr[8] & 4294901760;
	context->gpr[13] = temp1 | context->gpr[13];
	context->gpr[13] = temp2 | context->gpr[13];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_1000_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[8] >> 16;
	context->gpr[13] = context->gpr[8] << 16;
	context->gpr[13] = temp | context->gpr[13];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_1000_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[8]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[13] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_1000_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[13] = -context->gpr[8];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_1000_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[13] = context->gpr[8] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_1000_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[13] = context->gpr[8] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_1000_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[13] = (context->gpr[13] & ~65535) | ((context->gpr[8] & 255) & 128 ? (context->gpr[8] & 255) | 65280 : (context->gpr[8] & 255));
	context->gpr[13] = (context->gpr[13] & 65535) & 32768 ? (context->gpr[13] & 65535) | 4294901760 : (context->gpr[13] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_1000_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[13] = (context->gpr[8] & 65535) & 32768 ? (context->gpr[8] & 65535) | 4294901760 : (context->gpr[8] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_1001_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[9] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[9], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[13] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_1001_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[9] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[9], context);
	context->gpr[13] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_1001_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[9] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[9], context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_1001_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[13] = context->gpr[9];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_1001_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[9] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[9], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[13] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[9] = 1 + context->gpr[9];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_1001_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[9] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[9], context);
	context->gpr[13] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[9] = 2 + context->gpr[9];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_1001_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[9] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[9], context);
	context->gpr[13] = context->scratch1;
	context->gpr[9] = 4 + context->gpr[9];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_1001_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[13] = ~context->gpr[9];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_1001_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[9] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[9] << 8;
	temp2 = 65280 & temp2;
	context->gpr[13] = context->gpr[9] & 4294901760;
	context->gpr[13] = temp1 | context->gpr[13];
	context->gpr[13] = temp2 | context->gpr[13];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_1001_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[9] >> 16;
	context->gpr[13] = context->gpr[9] << 16;
	context->gpr[13] = temp | context->gpr[13];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_1001_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[9]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[13] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_1001_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[13] = -context->gpr[9];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_1001_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[13] = context->gpr[9] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_1001_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[13] = context->gpr[9] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_1001_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[13] = (context->gpr[13] & ~65535) | ((context->gpr[9] & 255) & 128 ? (context->gpr[9] & 255) | 65280 : (context->gpr[9] & 255));
	context->gpr[13] = (context->gpr[13] & 65535) & 32768 ? (context->gpr[13] & 65535) | 4294901760 : (context->gpr[13] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_1001_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[13] = (context->gpr[9] & 65535) & 32768 ? (context->gpr[9] & 65535) | 4294901760 : (context->gpr[9] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_1010_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[10] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[10], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[13] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_1010_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[10] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[10], context);
	context->gpr[13] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_1010_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[10] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[10], context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_1010_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[13] = context->gpr[10];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_1010_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[10] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[10], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[13] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[10] = 1 + context->gpr[10];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_1010_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[10] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[10], context);
	context->gpr[13] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[10] = 2 + context->gpr[10];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_1010_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[10] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[10], context);
	context->gpr[13] = context->scratch1;
	context->gpr[10] = 4 + context->gpr[10];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_1010_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[13] = ~context->gpr[10];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_1010_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[10] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[10] << 8;
	temp2 = 65280 & temp2;
	context->gpr[13] = context->gpr[10] & 4294901760;
	context->gpr[13] = temp1 | context->gpr[13];
	context->gpr[13] = temp2 | context->gpr[13];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_1010_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[10] >> 16;
	context->gpr[13] = context->gpr[10] << 16;
	context->gpr[13] = temp | context->gpr[13];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_1010_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[10]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[13] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_1010_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[13] = -context->gpr[10];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_1010_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[13] = context->gpr[10] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_1010_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[13] = context->gpr[10] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_1010_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[13] = (context->gpr[13] & ~65535) | ((context->gpr[10] & 255) & 128 ? (context->gpr[10] & 255) | 65280 : (context->gpr[10] & 255));
	context->gpr[13] = (context->gpr[13] & 65535) & 32768 ? (context->gpr[13] & 65535) | 4294901760 : (context->gpr[13] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_1010_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[13] = (context->gpr[10] & 65535) & 32768 ? (context->gpr[10] & 65535) | 4294901760 : (context->gpr[10] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_1011_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[11] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[11], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[13] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_1011_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[11] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[11], context);
	context->gpr[13] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_1011_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[11] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[11], context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_1011_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[13] = context->gpr[11];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_1011_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[11] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[11], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[13] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[11] = 1 + context->gpr[11];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_1011_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[11] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[11], context);
	context->gpr[13] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[11] = 2 + context->gpr[11];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_1011_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[11] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[11], context);
	context->gpr[13] = context->scratch1;
	context->gpr[11] = 4 + context->gpr[11];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_1011_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[13] = ~context->gpr[11];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_1011_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[11] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[11] << 8;
	temp2 = 65280 & temp2;
	context->gpr[13] = context->gpr[11] & 4294901760;
	context->gpr[13] = temp1 | context->gpr[13];
	context->gpr[13] = temp2 | context->gpr[13];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_1011_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[11] >> 16;
	context->gpr[13] = context->gpr[11] << 16;
	context->gpr[13] = temp | context->gpr[13];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_1011_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[11]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[13] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_1011_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[13] = -context->gpr[11];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_1011_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[13] = context->gpr[11] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_1011_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[13] = context->gpr[11] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_1011_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[13] = (context->gpr[13] & ~65535) | ((context->gpr[11] & 255) & 128 ? (context->gpr[11] & 255) | 65280 : (context->gpr[11] & 255));
	context->gpr[13] = (context->gpr[13] & 65535) & 32768 ? (context->gpr[13] & 65535) | 4294901760 : (context->gpr[13] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_1011_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[13] = (context->gpr[11] & 65535) & 32768 ? (context->gpr[11] & 65535) | 4294901760 : (context->gpr[11] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_1100_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[12] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[12], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[13] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_1100_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[12] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[12], context);
	context->gpr[13] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_1100_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[12] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[12], context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_1100_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[13] = context->gpr[12];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_1100_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[12] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[12], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[13] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[12] = 1 + context->gpr[12];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_1100_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[12] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[12], context);
	context->gpr[13] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[12] = 2 + context->gpr[12];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_1100_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[12] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[12], context);
	context->gpr[13] = context->scratch1;
	context->gpr[12] = 4 + context->gpr[12];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_1100_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[13] = ~context->gpr[12];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_1100_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[12] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[12] << 8;
	temp2 = 65280 & temp2;
	context->gpr[13] = context->gpr[12] & 4294901760;
	context->gpr[13] = temp1 | context->gpr[13];
	context->gpr[13] = temp2 | context->gpr[13];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_1100_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[12] >> 16;
	context->gpr[13] = context->gpr[12] << 16;
	context->gpr[13] = temp | context->gpr[13];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_1100_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[12]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[13] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_1100_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[13] = -context->gpr[12];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_1100_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[13] = context->gpr[12] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_1100_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[13] = context->gpr[12] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_1100_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[13] = (context->gpr[13] & ~65535) | ((context->gpr[12] & 255) & 128 ? (context->gpr[12] & 255) | 65280 : (context->gpr[12] & 255));
	context->gpr[13] = (context->gpr[13] & 65535) & 32768 ? (context->gpr[13] & 65535) | 4294901760 : (context->gpr[13] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_1100_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[13] = (context->gpr[12] & 65535) & 32768 ? (context->gpr[12] & 65535) | 4294901760 : (context->gpr[12] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_1101_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[13] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[13], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[13] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_1101_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[13] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[13], context);
	context->gpr[13] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_1101_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[13] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[13], context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_1101_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[13] = context->gpr[13];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_1101_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[13] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[13], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[13] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_1101_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[13] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[13], context);
	context->gpr[13] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_1101_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[13] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[13], context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_1101_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[13] = ~context->gpr[13];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_1101_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[13] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[13] << 8;
	temp2 = 65280 & temp2;
	context->gpr[13] = context->gpr[13] & 4294901760;
	context->gpr[13] = temp1 | context->gpr[13];
	context->gpr[13] = temp2 | context->gpr[13];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_1101_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[13] >> 16;
	context->gpr[13] = context->gpr[13] << 16;
	context->gpr[13] = temp | context->gpr[13];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_1101_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[13]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[13] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_1101_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[13] = -context->gpr[13];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_1101_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[13] = context->gpr[13] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_1101_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[13] = context->gpr[13] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_1101_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[13] = (context->gpr[13] & ~65535) | ((context->gpr[13] & 255) & 128 ? (context->gpr[13] & 255) | 65280 : (context->gpr[13] & 255));
	context->gpr[13] = (context->gpr[13] & 65535) & 32768 ? (context->gpr[13] & 65535) | 4294901760 : (context->gpr[13] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_1101_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[13] = (context->gpr[13] & 65535) & 32768 ? (context->gpr[13] & 65535) | 4294901760 : (context->gpr[13] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_1110_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[14] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[14], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[13] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_1110_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[14] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[14], context);
	context->gpr[13] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_1110_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[14] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[14], context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_1110_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[13] = context->gpr[14];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_1110_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[14] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[14], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[13] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[14] = 1 + context->gpr[14];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_1110_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[14] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[14], context);
	context->gpr[13] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[14] = 2 + context->gpr[14];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_1110_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[14] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[14], context);
	context->gpr[13] = context->scratch1;
	context->gpr[14] = 4 + context->gpr[14];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_1110_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[13] = ~context->gpr[14];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_1110_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[14] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[14] << 8;
	temp2 = 65280 & temp2;
	context->gpr[13] = context->gpr[14] & 4294901760;
	context->gpr[13] = temp1 | context->gpr[13];
	context->gpr[13] = temp2 | context->gpr[13];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_1110_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[14] >> 16;
	context->gpr[13] = context->gpr[14] << 16;
	context->gpr[13] = temp | context->gpr[13];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_1110_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[14]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[13] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_1110_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[13] = -context->gpr[14];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_1110_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[13] = context->gpr[14] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_1110_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[13] = context->gpr[14] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_1110_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[13] = (context->gpr[13] & ~65535) | ((context->gpr[14] & 255) & 128 ? (context->gpr[14] & 255) | 65280 : (context->gpr[14] & 255));
	context->gpr[13] = (context->gpr[13] & 65535) & 32768 ? (context->gpr[13] & 65535) | 4294901760 : (context->gpr[13] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_1110_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[13] = (context->gpr[14] & 65535) & 32768 ? (context->gpr[14] & 65535) | 4294901760 : (context->gpr[14] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_1111_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[15] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[15], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[13] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_1111_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[15] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[15], context);
	context->gpr[13] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_1111_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[15] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[15], context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_1111_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[13] = context->gpr[15];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_1111_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[15] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[15], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[13] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[15] = 1 + context->gpr[15];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_1111_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[15] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[15], context);
	context->gpr[13] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[15] = 2 + context->gpr[15];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_1111_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[15] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[15], context);
	context->gpr[13] = context->scratch1;
	context->gpr[15] = 4 + context->gpr[15];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_1111_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[13] = ~context->gpr[15];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_1111_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[15] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[15] << 8;
	temp2 = 65280 & temp2;
	context->gpr[13] = context->gpr[15] & 4294901760;
	context->gpr[13] = temp1 | context->gpr[13];
	context->gpr[13] = temp2 | context->gpr[13];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_1111_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[15] >> 16;
	context->gpr[13] = context->gpr[15] << 16;
	context->gpr[13] = temp | context->gpr[13];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_1111_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[15]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[13] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_1111_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[13] = -context->gpr[15];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_1111_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[13] = context->gpr[15] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_1111_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[13] = context->gpr[15] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_1111_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[13] = (context->gpr[13] & ~65535) | ((context->gpr[15] & 255) & 128 ? (context->gpr[15] & 255) | 65280 : (context->gpr[15] & 255));
	context->gpr[13] = (context->gpr[13] & 65535) & 32768 ? (context->gpr[13] & 65535) | 4294901760 : (context->gpr[13] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_1111_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[13] = (context->gpr[15] & 65535) & 32768 ? (context->gpr[15] & 65535) | 4294901760 : (context->gpr[15] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_0000_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[0] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[0], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[14] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_0000_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[0] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[0], context);
	context->gpr[14] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_0000_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[0] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[0], context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_0000_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[14] = context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_0000_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[0] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[0], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[14] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[0] = 1 + context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_0000_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[0] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[0], context);
	context->gpr[14] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[0] = 2 + context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_0000_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[0] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[0], context);
	context->gpr[14] = context->scratch1;
	context->gpr[0] = 4 + context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_0000_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[14] = ~context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_0000_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[0] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[0] << 8;
	temp2 = 65280 & temp2;
	context->gpr[14] = context->gpr[0] & 4294901760;
	context->gpr[14] = temp1 | context->gpr[14];
	context->gpr[14] = temp2 | context->gpr[14];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_0000_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[0] >> 16;
	context->gpr[14] = context->gpr[0] << 16;
	context->gpr[14] = temp | context->gpr[14];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_0000_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[0]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[14] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_0000_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[14] = -context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_0000_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[14] = context->gpr[0] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_0000_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[14] = context->gpr[0] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_0000_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[14] = (context->gpr[14] & ~65535) | ((context->gpr[0] & 255) & 128 ? (context->gpr[0] & 255) | 65280 : (context->gpr[0] & 255));
	context->gpr[14] = (context->gpr[14] & 65535) & 32768 ? (context->gpr[14] & 65535) | 4294901760 : (context->gpr[14] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_0000_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[14] = (context->gpr[0] & 65535) & 32768 ? (context->gpr[0] & 65535) | 4294901760 : (context->gpr[0] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_0001_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[1] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[1], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[14] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_0001_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[1] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[1], context);
	context->gpr[14] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_0001_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[1] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[1], context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_0001_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[14] = context->gpr[1];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_0001_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[1] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[1], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[14] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[1] = 1 + context->gpr[1];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_0001_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[1] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[1], context);
	context->gpr[14] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[1] = 2 + context->gpr[1];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_0001_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[1] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[1], context);
	context->gpr[14] = context->scratch1;
	context->gpr[1] = 4 + context->gpr[1];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_0001_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[14] = ~context->gpr[1];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_0001_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[1] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[1] << 8;
	temp2 = 65280 & temp2;
	context->gpr[14] = context->gpr[1] & 4294901760;
	context->gpr[14] = temp1 | context->gpr[14];
	context->gpr[14] = temp2 | context->gpr[14];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_0001_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[1] >> 16;
	context->gpr[14] = context->gpr[1] << 16;
	context->gpr[14] = temp | context->gpr[14];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_0001_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[1]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[14] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_0001_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[14] = -context->gpr[1];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_0001_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[14] = context->gpr[1] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_0001_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[14] = context->gpr[1] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_0001_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[14] = (context->gpr[14] & ~65535) | ((context->gpr[1] & 255) & 128 ? (context->gpr[1] & 255) | 65280 : (context->gpr[1] & 255));
	context->gpr[14] = (context->gpr[14] & 65535) & 32768 ? (context->gpr[14] & 65535) | 4294901760 : (context->gpr[14] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_0001_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[14] = (context->gpr[1] & 65535) & 32768 ? (context->gpr[1] & 65535) | 4294901760 : (context->gpr[1] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_0010_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[2] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[2], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[14] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_0010_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[2] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[2], context);
	context->gpr[14] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_0010_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[2] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[2], context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_0010_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[14] = context->gpr[2];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_0010_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[2] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[2], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[14] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[2] = 1 + context->gpr[2];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_0010_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[2] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[2], context);
	context->gpr[14] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[2] = 2 + context->gpr[2];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_0010_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[2] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[2], context);
	context->gpr[14] = context->scratch1;
	context->gpr[2] = 4 + context->gpr[2];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_0010_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[14] = ~context->gpr[2];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_0010_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[2] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[2] << 8;
	temp2 = 65280 & temp2;
	context->gpr[14] = context->gpr[2] & 4294901760;
	context->gpr[14] = temp1 | context->gpr[14];
	context->gpr[14] = temp2 | context->gpr[14];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_0010_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[2] >> 16;
	context->gpr[14] = context->gpr[2] << 16;
	context->gpr[14] = temp | context->gpr[14];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_0010_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[2]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[14] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_0010_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[14] = -context->gpr[2];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_0010_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[14] = context->gpr[2] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_0010_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[14] = context->gpr[2] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_0010_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[14] = (context->gpr[14] & ~65535) | ((context->gpr[2] & 255) & 128 ? (context->gpr[2] & 255) | 65280 : (context->gpr[2] & 255));
	context->gpr[14] = (context->gpr[14] & 65535) & 32768 ? (context->gpr[14] & 65535) | 4294901760 : (context->gpr[14] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_0010_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[14] = (context->gpr[2] & 65535) & 32768 ? (context->gpr[2] & 65535) | 4294901760 : (context->gpr[2] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_0011_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[3] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[3], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[14] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_0011_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[3] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[3], context);
	context->gpr[14] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_0011_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[3] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[3], context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_0011_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[14] = context->gpr[3];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_0011_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[3] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[3], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[14] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[3] = 1 + context->gpr[3];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_0011_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[3] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[3], context);
	context->gpr[14] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[3] = 2 + context->gpr[3];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_0011_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[3] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[3], context);
	context->gpr[14] = context->scratch1;
	context->gpr[3] = 4 + context->gpr[3];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_0011_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[14] = ~context->gpr[3];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_0011_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[3] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[3] << 8;
	temp2 = 65280 & temp2;
	context->gpr[14] = context->gpr[3] & 4294901760;
	context->gpr[14] = temp1 | context->gpr[14];
	context->gpr[14] = temp2 | context->gpr[14];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_0011_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[3] >> 16;
	context->gpr[14] = context->gpr[3] << 16;
	context->gpr[14] = temp | context->gpr[14];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_0011_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[3]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[14] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_0011_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[14] = -context->gpr[3];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_0011_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[14] = context->gpr[3] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_0011_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[14] = context->gpr[3] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_0011_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[14] = (context->gpr[14] & ~65535) | ((context->gpr[3] & 255) & 128 ? (context->gpr[3] & 255) | 65280 : (context->gpr[3] & 255));
	context->gpr[14] = (context->gpr[14] & 65535) & 32768 ? (context->gpr[14] & 65535) | 4294901760 : (context->gpr[14] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_0011_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[14] = (context->gpr[3] & 65535) & 32768 ? (context->gpr[3] & 65535) | 4294901760 : (context->gpr[3] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_0100_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[4] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[4], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[14] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_0100_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[4] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[4], context);
	context->gpr[14] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_0100_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[4] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[4], context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_0100_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[14] = context->gpr[4];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_0100_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[4] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[4], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[14] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[4] = 1 + context->gpr[4];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_0100_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[4] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[4], context);
	context->gpr[14] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[4] = 2 + context->gpr[4];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_0100_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[4] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[4], context);
	context->gpr[14] = context->scratch1;
	context->gpr[4] = 4 + context->gpr[4];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_0100_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[14] = ~context->gpr[4];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_0100_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[4] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[4] << 8;
	temp2 = 65280 & temp2;
	context->gpr[14] = context->gpr[4] & 4294901760;
	context->gpr[14] = temp1 | context->gpr[14];
	context->gpr[14] = temp2 | context->gpr[14];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_0100_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[4] >> 16;
	context->gpr[14] = context->gpr[4] << 16;
	context->gpr[14] = temp | context->gpr[14];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_0100_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[4]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[14] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_0100_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[14] = -context->gpr[4];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_0100_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[14] = context->gpr[4] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_0100_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[14] = context->gpr[4] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_0100_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[14] = (context->gpr[14] & ~65535) | ((context->gpr[4] & 255) & 128 ? (context->gpr[4] & 255) | 65280 : (context->gpr[4] & 255));
	context->gpr[14] = (context->gpr[14] & 65535) & 32768 ? (context->gpr[14] & 65535) | 4294901760 : (context->gpr[14] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_0100_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[14] = (context->gpr[4] & 65535) & 32768 ? (context->gpr[4] & 65535) | 4294901760 : (context->gpr[4] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_0101_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[5] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[5], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[14] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_0101_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[5] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[5], context);
	context->gpr[14] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_0101_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[5] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[5], context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_0101_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[14] = context->gpr[5];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_0101_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[5] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[5], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[14] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[5] = 1 + context->gpr[5];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_0101_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[5] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[5], context);
	context->gpr[14] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[5] = 2 + context->gpr[5];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_0101_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[5] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[5], context);
	context->gpr[14] = context->scratch1;
	context->gpr[5] = 4 + context->gpr[5];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_0101_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[14] = ~context->gpr[5];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_0101_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[5] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[5] << 8;
	temp2 = 65280 & temp2;
	context->gpr[14] = context->gpr[5] & 4294901760;
	context->gpr[14] = temp1 | context->gpr[14];
	context->gpr[14] = temp2 | context->gpr[14];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_0101_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[5] >> 16;
	context->gpr[14] = context->gpr[5] << 16;
	context->gpr[14] = temp | context->gpr[14];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_0101_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[5]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[14] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_0101_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[14] = -context->gpr[5];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_0101_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[14] = context->gpr[5] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_0101_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[14] = context->gpr[5] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_0101_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[14] = (context->gpr[14] & ~65535) | ((context->gpr[5] & 255) & 128 ? (context->gpr[5] & 255) | 65280 : (context->gpr[5] & 255));
	context->gpr[14] = (context->gpr[14] & 65535) & 32768 ? (context->gpr[14] & 65535) | 4294901760 : (context->gpr[14] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_0101_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[14] = (context->gpr[5] & 65535) & 32768 ? (context->gpr[5] & 65535) | 4294901760 : (context->gpr[5] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_0110_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[6] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[6], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[14] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_0110_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[6] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[6], context);
	context->gpr[14] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_0110_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[6] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[6], context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_0110_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[14] = context->gpr[6];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_0110_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[6] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[6], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[14] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[6] = 1 + context->gpr[6];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_0110_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[6] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[6], context);
	context->gpr[14] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[6] = 2 + context->gpr[6];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_0110_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[6] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[6], context);
	context->gpr[14] = context->scratch1;
	context->gpr[6] = 4 + context->gpr[6];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_0110_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[14] = ~context->gpr[6];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_0110_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[6] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[6] << 8;
	temp2 = 65280 & temp2;
	context->gpr[14] = context->gpr[6] & 4294901760;
	context->gpr[14] = temp1 | context->gpr[14];
	context->gpr[14] = temp2 | context->gpr[14];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_0110_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[6] >> 16;
	context->gpr[14] = context->gpr[6] << 16;
	context->gpr[14] = temp | context->gpr[14];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_0110_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[6]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[14] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_0110_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[14] = -context->gpr[6];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_0110_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[14] = context->gpr[6] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_0110_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[14] = context->gpr[6] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_0110_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[14] = (context->gpr[14] & ~65535) | ((context->gpr[6] & 255) & 128 ? (context->gpr[6] & 255) | 65280 : (context->gpr[6] & 255));
	context->gpr[14] = (context->gpr[14] & 65535) & 32768 ? (context->gpr[14] & 65535) | 4294901760 : (context->gpr[14] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_0110_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[14] = (context->gpr[6] & 65535) & 32768 ? (context->gpr[6] & 65535) | 4294901760 : (context->gpr[6] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_0111_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[7] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[7], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[14] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_0111_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[7] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[7], context);
	context->gpr[14] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_0111_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[7] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[7], context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_0111_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[14] = context->gpr[7];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_0111_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[7] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[7], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[14] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[7] = 1 + context->gpr[7];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_0111_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[7] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[7], context);
	context->gpr[14] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[7] = 2 + context->gpr[7];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_0111_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[7] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[7], context);
	context->gpr[14] = context->scratch1;
	context->gpr[7] = 4 + context->gpr[7];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_0111_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[14] = ~context->gpr[7];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_0111_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[7] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[7] << 8;
	temp2 = 65280 & temp2;
	context->gpr[14] = context->gpr[7] & 4294901760;
	context->gpr[14] = temp1 | context->gpr[14];
	context->gpr[14] = temp2 | context->gpr[14];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_0111_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[7] >> 16;
	context->gpr[14] = context->gpr[7] << 16;
	context->gpr[14] = temp | context->gpr[14];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_0111_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[7]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[14] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_0111_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[14] = -context->gpr[7];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_0111_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[14] = context->gpr[7] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_0111_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[14] = context->gpr[7] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_0111_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[14] = (context->gpr[14] & ~65535) | ((context->gpr[7] & 255) & 128 ? (context->gpr[7] & 255) | 65280 : (context->gpr[7] & 255));
	context->gpr[14] = (context->gpr[14] & 65535) & 32768 ? (context->gpr[14] & 65535) | 4294901760 : (context->gpr[14] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_0111_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[14] = (context->gpr[7] & 65535) & 32768 ? (context->gpr[7] & 65535) | 4294901760 : (context->gpr[7] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_1000_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[8] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[8], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[14] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_1000_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[8] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[8], context);
	context->gpr[14] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_1000_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[8] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[8], context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_1000_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[14] = context->gpr[8];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_1000_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[8] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[8], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[14] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[8] = 1 + context->gpr[8];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_1000_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[8] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[8], context);
	context->gpr[14] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[8] = 2 + context->gpr[8];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_1000_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[8] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[8], context);
	context->gpr[14] = context->scratch1;
	context->gpr[8] = 4 + context->gpr[8];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_1000_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[14] = ~context->gpr[8];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_1000_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[8] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[8] << 8;
	temp2 = 65280 & temp2;
	context->gpr[14] = context->gpr[8] & 4294901760;
	context->gpr[14] = temp1 | context->gpr[14];
	context->gpr[14] = temp2 | context->gpr[14];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_1000_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[8] >> 16;
	context->gpr[14] = context->gpr[8] << 16;
	context->gpr[14] = temp | context->gpr[14];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_1000_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[8]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[14] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_1000_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[14] = -context->gpr[8];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_1000_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[14] = context->gpr[8] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_1000_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[14] = context->gpr[8] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_1000_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[14] = (context->gpr[14] & ~65535) | ((context->gpr[8] & 255) & 128 ? (context->gpr[8] & 255) | 65280 : (context->gpr[8] & 255));
	context->gpr[14] = (context->gpr[14] & 65535) & 32768 ? (context->gpr[14] & 65535) | 4294901760 : (context->gpr[14] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_1000_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[14] = (context->gpr[8] & 65535) & 32768 ? (context->gpr[8] & 65535) | 4294901760 : (context->gpr[8] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_1001_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[9] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[9], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[14] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_1001_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[9] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[9], context);
	context->gpr[14] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_1001_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[9] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[9], context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_1001_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[14] = context->gpr[9];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_1001_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[9] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[9], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[14] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[9] = 1 + context->gpr[9];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_1001_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[9] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[9], context);
	context->gpr[14] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[9] = 2 + context->gpr[9];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_1001_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[9] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[9], context);
	context->gpr[14] = context->scratch1;
	context->gpr[9] = 4 + context->gpr[9];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_1001_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[14] = ~context->gpr[9];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_1001_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[9] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[9] << 8;
	temp2 = 65280 & temp2;
	context->gpr[14] = context->gpr[9] & 4294901760;
	context->gpr[14] = temp1 | context->gpr[14];
	context->gpr[14] = temp2 | context->gpr[14];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_1001_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[9] >> 16;
	context->gpr[14] = context->gpr[9] << 16;
	context->gpr[14] = temp | context->gpr[14];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_1001_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[9]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[14] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_1001_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[14] = -context->gpr[9];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_1001_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[14] = context->gpr[9] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_1001_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[14] = context->gpr[9] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_1001_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[14] = (context->gpr[14] & ~65535) | ((context->gpr[9] & 255) & 128 ? (context->gpr[9] & 255) | 65280 : (context->gpr[9] & 255));
	context->gpr[14] = (context->gpr[14] & 65535) & 32768 ? (context->gpr[14] & 65535) | 4294901760 : (context->gpr[14] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_1001_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[14] = (context->gpr[9] & 65535) & 32768 ? (context->gpr[9] & 65535) | 4294901760 : (context->gpr[9] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_1010_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[10] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[10], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[14] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_1010_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[10] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[10], context);
	context->gpr[14] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_1010_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[10] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[10], context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_1010_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[14] = context->gpr[10];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_1010_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[10] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[10], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[14] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[10] = 1 + context->gpr[10];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_1010_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[10] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[10], context);
	context->gpr[14] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[10] = 2 + context->gpr[10];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_1010_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[10] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[10], context);
	context->gpr[14] = context->scratch1;
	context->gpr[10] = 4 + context->gpr[10];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_1010_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[14] = ~context->gpr[10];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_1010_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[10] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[10] << 8;
	temp2 = 65280 & temp2;
	context->gpr[14] = context->gpr[10] & 4294901760;
	context->gpr[14] = temp1 | context->gpr[14];
	context->gpr[14] = temp2 | context->gpr[14];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_1010_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[10] >> 16;
	context->gpr[14] = context->gpr[10] << 16;
	context->gpr[14] = temp | context->gpr[14];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_1010_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[10]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[14] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_1010_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[14] = -context->gpr[10];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_1010_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[14] = context->gpr[10] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_1010_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[14] = context->gpr[10] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_1010_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[14] = (context->gpr[14] & ~65535) | ((context->gpr[10] & 255) & 128 ? (context->gpr[10] & 255) | 65280 : (context->gpr[10] & 255));
	context->gpr[14] = (context->gpr[14] & 65535) & 32768 ? (context->gpr[14] & 65535) | 4294901760 : (context->gpr[14] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_1010_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[14] = (context->gpr[10] & 65535) & 32768 ? (context->gpr[10] & 65535) | 4294901760 : (context->gpr[10] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_1011_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[11] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[11], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[14] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_1011_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[11] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[11], context);
	context->gpr[14] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_1011_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[11] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[11], context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_1011_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[14] = context->gpr[11];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_1011_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[11] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[11], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[14] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[11] = 1 + context->gpr[11];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_1011_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[11] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[11], context);
	context->gpr[14] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[11] = 2 + context->gpr[11];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_1011_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[11] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[11], context);
	context->gpr[14] = context->scratch1;
	context->gpr[11] = 4 + context->gpr[11];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_1011_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[14] = ~context->gpr[11];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_1011_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[11] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[11] << 8;
	temp2 = 65280 & temp2;
	context->gpr[14] = context->gpr[11] & 4294901760;
	context->gpr[14] = temp1 | context->gpr[14];
	context->gpr[14] = temp2 | context->gpr[14];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_1011_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[11] >> 16;
	context->gpr[14] = context->gpr[11] << 16;
	context->gpr[14] = temp | context->gpr[14];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_1011_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[11]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[14] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_1011_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[14] = -context->gpr[11];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_1011_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[14] = context->gpr[11] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_1011_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[14] = context->gpr[11] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_1011_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[14] = (context->gpr[14] & ~65535) | ((context->gpr[11] & 255) & 128 ? (context->gpr[11] & 255) | 65280 : (context->gpr[11] & 255));
	context->gpr[14] = (context->gpr[14] & 65535) & 32768 ? (context->gpr[14] & 65535) | 4294901760 : (context->gpr[14] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_1011_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[14] = (context->gpr[11] & 65535) & 32768 ? (context->gpr[11] & 65535) | 4294901760 : (context->gpr[11] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_1100_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[12] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[12], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[14] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_1100_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[12] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[12], context);
	context->gpr[14] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_1100_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[12] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[12], context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_1100_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[14] = context->gpr[12];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_1100_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[12] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[12], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[14] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[12] = 1 + context->gpr[12];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_1100_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[12] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[12], context);
	context->gpr[14] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[12] = 2 + context->gpr[12];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_1100_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[12] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[12], context);
	context->gpr[14] = context->scratch1;
	context->gpr[12] = 4 + context->gpr[12];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_1100_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[14] = ~context->gpr[12];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_1100_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[12] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[12] << 8;
	temp2 = 65280 & temp2;
	context->gpr[14] = context->gpr[12] & 4294901760;
	context->gpr[14] = temp1 | context->gpr[14];
	context->gpr[14] = temp2 | context->gpr[14];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_1100_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[12] >> 16;
	context->gpr[14] = context->gpr[12] << 16;
	context->gpr[14] = temp | context->gpr[14];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_1100_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[12]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[14] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_1100_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[14] = -context->gpr[12];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_1100_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[14] = context->gpr[12] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_1100_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[14] = context->gpr[12] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_1100_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[14] = (context->gpr[14] & ~65535) | ((context->gpr[12] & 255) & 128 ? (context->gpr[12] & 255) | 65280 : (context->gpr[12] & 255));
	context->gpr[14] = (context->gpr[14] & 65535) & 32768 ? (context->gpr[14] & 65535) | 4294901760 : (context->gpr[14] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_1100_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[14] = (context->gpr[12] & 65535) & 32768 ? (context->gpr[12] & 65535) | 4294901760 : (context->gpr[12] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_1101_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[13] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[13], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[14] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_1101_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[13] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[13], context);
	context->gpr[14] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_1101_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[13] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[13], context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_1101_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[14] = context->gpr[13];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_1101_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[13] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[13], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[14] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[13] = 1 + context->gpr[13];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_1101_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[13] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[13], context);
	context->gpr[14] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[13] = 2 + context->gpr[13];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_1101_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[13] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[13], context);
	context->gpr[14] = context->scratch1;
	context->gpr[13] = 4 + context->gpr[13];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_1101_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[14] = ~context->gpr[13];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_1101_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[13] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[13] << 8;
	temp2 = 65280 & temp2;
	context->gpr[14] = context->gpr[13] & 4294901760;
	context->gpr[14] = temp1 | context->gpr[14];
	context->gpr[14] = temp2 | context->gpr[14];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_1101_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[13] >> 16;
	context->gpr[14] = context->gpr[13] << 16;
	context->gpr[14] = temp | context->gpr[14];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_1101_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[13]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[14] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_1101_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[14] = -context->gpr[13];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_1101_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[14] = context->gpr[13] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_1101_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[14] = context->gpr[13] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_1101_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[14] = (context->gpr[14] & ~65535) | ((context->gpr[13] & 255) & 128 ? (context->gpr[13] & 255) | 65280 : (context->gpr[13] & 255));
	context->gpr[14] = (context->gpr[14] & 65535) & 32768 ? (context->gpr[14] & 65535) | 4294901760 : (context->gpr[14] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_1101_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[14] = (context->gpr[13] & 65535) & 32768 ? (context->gpr[13] & 65535) | 4294901760 : (context->gpr[13] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_1110_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[14] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[14], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[14] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_1110_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[14] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[14], context);
	context->gpr[14] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_1110_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[14] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[14], context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_1110_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[14] = context->gpr[14];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_1110_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[14] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[14], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[14] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_1110_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[14] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[14], context);
	context->gpr[14] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_1110_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[14] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[14], context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_1110_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[14] = ~context->gpr[14];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_1110_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[14] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[14] << 8;
	temp2 = 65280 & temp2;
	context->gpr[14] = context->gpr[14] & 4294901760;
	context->gpr[14] = temp1 | context->gpr[14];
	context->gpr[14] = temp2 | context->gpr[14];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_1110_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[14] >> 16;
	context->gpr[14] = context->gpr[14] << 16;
	context->gpr[14] = temp | context->gpr[14];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_1110_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[14]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[14] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_1110_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[14] = -context->gpr[14];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_1110_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[14] = context->gpr[14] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_1110_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[14] = context->gpr[14] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_1110_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[14] = (context->gpr[14] & ~65535) | ((context->gpr[14] & 255) & 128 ? (context->gpr[14] & 255) | 65280 : (context->gpr[14] & 255));
	context->gpr[14] = (context->gpr[14] & 65535) & 32768 ? (context->gpr[14] & 65535) | 4294901760 : (context->gpr[14] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_1110_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[14] = (context->gpr[14] & 65535) & 32768 ? (context->gpr[14] & 65535) | 4294901760 : (context->gpr[14] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_1111_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[15] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[15], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[14] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_1111_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[15] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[15], context);
	context->gpr[14] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_1111_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[15] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[15], context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_1111_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[14] = context->gpr[15];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_1111_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[15] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[15], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[14] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[15] = 1 + context->gpr[15];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_1111_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[15] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[15], context);
	context->gpr[14] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[15] = 2 + context->gpr[15];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_1111_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[15] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[15], context);
	context->gpr[14] = context->scratch1;
	context->gpr[15] = 4 + context->gpr[15];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_1111_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[14] = ~context->gpr[15];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_1111_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[15] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[15] << 8;
	temp2 = 65280 & temp2;
	context->gpr[14] = context->gpr[15] & 4294901760;
	context->gpr[14] = temp1 | context->gpr[14];
	context->gpr[14] = temp2 | context->gpr[14];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_1111_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[15] >> 16;
	context->gpr[14] = context->gpr[15] << 16;
	context->gpr[14] = temp | context->gpr[14];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_1111_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[15]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[14] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_1111_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[14] = -context->gpr[15];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_1111_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[14] = context->gpr[15] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_1111_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[14] = context->gpr[15] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_1111_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[14] = (context->gpr[14] & ~65535) | ((context->gpr[15] & 255) & 128 ? (context->gpr[15] & 255) | 65280 : (context->gpr[15] & 255));
	context->gpr[14] = (context->gpr[14] & 65535) & 32768 ? (context->gpr[14] & 65535) | 4294901760 : (context->gpr[14] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_1111_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[14] = (context->gpr[15] & 65535) & 32768 ? (context->gpr[15] & 65535) | 4294901760 : (context->gpr[15] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_0000_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[0] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[0], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[15] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_0000_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[0] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[0], context);
	context->gpr[15] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_0000_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[0] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[0], context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_0000_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[15] = context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_0000_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[0] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[0], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[15] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[0] = 1 + context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_0000_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[0] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[0], context);
	context->gpr[15] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[0] = 2 + context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_0000_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[0] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[0], context);
	context->gpr[15] = context->scratch1;
	context->gpr[0] = 4 + context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_0000_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[15] = ~context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_0000_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[0] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[0] << 8;
	temp2 = 65280 & temp2;
	context->gpr[15] = context->gpr[0] & 4294901760;
	context->gpr[15] = temp1 | context->gpr[15];
	context->gpr[15] = temp2 | context->gpr[15];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_0000_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[0] >> 16;
	context->gpr[15] = context->gpr[0] << 16;
	context->gpr[15] = temp | context->gpr[15];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_0000_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[0]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[15] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_0000_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[15] = -context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_0000_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[15] = context->gpr[0] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_0000_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[15] = context->gpr[0] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_0000_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[15] = (context->gpr[15] & ~65535) | ((context->gpr[0] & 255) & 128 ? (context->gpr[0] & 255) | 65280 : (context->gpr[0] & 255));
	context->gpr[15] = (context->gpr[15] & 65535) & 32768 ? (context->gpr[15] & 65535) | 4294901760 : (context->gpr[15] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_0000_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[15] = (context->gpr[0] & 65535) & 32768 ? (context->gpr[0] & 65535) | 4294901760 : (context->gpr[0] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_0001_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[1] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[1], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[15] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_0001_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[1] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[1], context);
	context->gpr[15] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_0001_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[1] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[1], context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_0001_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[15] = context->gpr[1];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_0001_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[1] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[1], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[15] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[1] = 1 + context->gpr[1];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_0001_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[1] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[1], context);
	context->gpr[15] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[1] = 2 + context->gpr[1];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_0001_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[1] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[1], context);
	context->gpr[15] = context->scratch1;
	context->gpr[1] = 4 + context->gpr[1];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_0001_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[15] = ~context->gpr[1];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_0001_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[1] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[1] << 8;
	temp2 = 65280 & temp2;
	context->gpr[15] = context->gpr[1] & 4294901760;
	context->gpr[15] = temp1 | context->gpr[15];
	context->gpr[15] = temp2 | context->gpr[15];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_0001_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[1] >> 16;
	context->gpr[15] = context->gpr[1] << 16;
	context->gpr[15] = temp | context->gpr[15];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_0001_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[1]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[15] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_0001_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[15] = -context->gpr[1];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_0001_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[15] = context->gpr[1] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_0001_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[15] = context->gpr[1] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_0001_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[15] = (context->gpr[15] & ~65535) | ((context->gpr[1] & 255) & 128 ? (context->gpr[1] & 255) | 65280 : (context->gpr[1] & 255));
	context->gpr[15] = (context->gpr[15] & 65535) & 32768 ? (context->gpr[15] & 65535) | 4294901760 : (context->gpr[15] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_0001_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[15] = (context->gpr[1] & 65535) & 32768 ? (context->gpr[1] & 65535) | 4294901760 : (context->gpr[1] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_0010_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[2] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[2], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[15] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_0010_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[2] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[2], context);
	context->gpr[15] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_0010_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[2] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[2], context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_0010_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[15] = context->gpr[2];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_0010_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[2] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[2], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[15] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[2] = 1 + context->gpr[2];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_0010_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[2] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[2], context);
	context->gpr[15] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[2] = 2 + context->gpr[2];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_0010_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[2] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[2], context);
	context->gpr[15] = context->scratch1;
	context->gpr[2] = 4 + context->gpr[2];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_0010_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[15] = ~context->gpr[2];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_0010_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[2] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[2] << 8;
	temp2 = 65280 & temp2;
	context->gpr[15] = context->gpr[2] & 4294901760;
	context->gpr[15] = temp1 | context->gpr[15];
	context->gpr[15] = temp2 | context->gpr[15];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_0010_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[2] >> 16;
	context->gpr[15] = context->gpr[2] << 16;
	context->gpr[15] = temp | context->gpr[15];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_0010_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[2]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[15] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_0010_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[15] = -context->gpr[2];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_0010_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[15] = context->gpr[2] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_0010_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[15] = context->gpr[2] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_0010_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[15] = (context->gpr[15] & ~65535) | ((context->gpr[2] & 255) & 128 ? (context->gpr[2] & 255) | 65280 : (context->gpr[2] & 255));
	context->gpr[15] = (context->gpr[15] & 65535) & 32768 ? (context->gpr[15] & 65535) | 4294901760 : (context->gpr[15] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_0010_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[15] = (context->gpr[2] & 65535) & 32768 ? (context->gpr[2] & 65535) | 4294901760 : (context->gpr[2] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_0011_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[3] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[3], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[15] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_0011_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[3] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[3], context);
	context->gpr[15] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_0011_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[3] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[3], context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_0011_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[15] = context->gpr[3];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_0011_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[3] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[3], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[15] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[3] = 1 + context->gpr[3];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_0011_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[3] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[3], context);
	context->gpr[15] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[3] = 2 + context->gpr[3];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_0011_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[3] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[3], context);
	context->gpr[15] = context->scratch1;
	context->gpr[3] = 4 + context->gpr[3];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_0011_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[15] = ~context->gpr[3];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_0011_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[3] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[3] << 8;
	temp2 = 65280 & temp2;
	context->gpr[15] = context->gpr[3] & 4294901760;
	context->gpr[15] = temp1 | context->gpr[15];
	context->gpr[15] = temp2 | context->gpr[15];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_0011_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[3] >> 16;
	context->gpr[15] = context->gpr[3] << 16;
	context->gpr[15] = temp | context->gpr[15];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_0011_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[3]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[15] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_0011_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[15] = -context->gpr[3];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_0011_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[15] = context->gpr[3] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_0011_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[15] = context->gpr[3] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_0011_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[15] = (context->gpr[15] & ~65535) | ((context->gpr[3] & 255) & 128 ? (context->gpr[3] & 255) | 65280 : (context->gpr[3] & 255));
	context->gpr[15] = (context->gpr[15] & 65535) & 32768 ? (context->gpr[15] & 65535) | 4294901760 : (context->gpr[15] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_0011_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[15] = (context->gpr[3] & 65535) & 32768 ? (context->gpr[3] & 65535) | 4294901760 : (context->gpr[3] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_0100_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[4] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[4], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[15] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_0100_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[4] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[4], context);
	context->gpr[15] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_0100_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[4] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[4], context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_0100_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[15] = context->gpr[4];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_0100_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[4] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[4], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[15] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[4] = 1 + context->gpr[4];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_0100_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[4] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[4], context);
	context->gpr[15] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[4] = 2 + context->gpr[4];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_0100_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[4] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[4], context);
	context->gpr[15] = context->scratch1;
	context->gpr[4] = 4 + context->gpr[4];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_0100_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[15] = ~context->gpr[4];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_0100_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[4] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[4] << 8;
	temp2 = 65280 & temp2;
	context->gpr[15] = context->gpr[4] & 4294901760;
	context->gpr[15] = temp1 | context->gpr[15];
	context->gpr[15] = temp2 | context->gpr[15];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_0100_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[4] >> 16;
	context->gpr[15] = context->gpr[4] << 16;
	context->gpr[15] = temp | context->gpr[15];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_0100_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[4]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[15] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_0100_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[15] = -context->gpr[4];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_0100_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[15] = context->gpr[4] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_0100_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[15] = context->gpr[4] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_0100_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[15] = (context->gpr[15] & ~65535) | ((context->gpr[4] & 255) & 128 ? (context->gpr[4] & 255) | 65280 : (context->gpr[4] & 255));
	context->gpr[15] = (context->gpr[15] & 65535) & 32768 ? (context->gpr[15] & 65535) | 4294901760 : (context->gpr[15] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_0100_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[15] = (context->gpr[4] & 65535) & 32768 ? (context->gpr[4] & 65535) | 4294901760 : (context->gpr[4] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_0101_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[5] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[5], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[15] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_0101_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[5] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[5], context);
	context->gpr[15] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_0101_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[5] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[5], context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_0101_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[15] = context->gpr[5];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_0101_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[5] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[5], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[15] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[5] = 1 + context->gpr[5];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_0101_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[5] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[5], context);
	context->gpr[15] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[5] = 2 + context->gpr[5];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_0101_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[5] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[5], context);
	context->gpr[15] = context->scratch1;
	context->gpr[5] = 4 + context->gpr[5];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_0101_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[15] = ~context->gpr[5];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_0101_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[5] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[5] << 8;
	temp2 = 65280 & temp2;
	context->gpr[15] = context->gpr[5] & 4294901760;
	context->gpr[15] = temp1 | context->gpr[15];
	context->gpr[15] = temp2 | context->gpr[15];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_0101_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[5] >> 16;
	context->gpr[15] = context->gpr[5] << 16;
	context->gpr[15] = temp | context->gpr[15];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_0101_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[5]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[15] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_0101_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[15] = -context->gpr[5];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_0101_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[15] = context->gpr[5] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_0101_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[15] = context->gpr[5] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_0101_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[15] = (context->gpr[15] & ~65535) | ((context->gpr[5] & 255) & 128 ? (context->gpr[5] & 255) | 65280 : (context->gpr[5] & 255));
	context->gpr[15] = (context->gpr[15] & 65535) & 32768 ? (context->gpr[15] & 65535) | 4294901760 : (context->gpr[15] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_0101_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[15] = (context->gpr[5] & 65535) & 32768 ? (context->gpr[5] & 65535) | 4294901760 : (context->gpr[5] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_0110_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[6] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[6], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[15] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_0110_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[6] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[6], context);
	context->gpr[15] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_0110_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[6] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[6], context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_0110_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[15] = context->gpr[6];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_0110_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[6] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[6], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[15] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[6] = 1 + context->gpr[6];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_0110_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[6] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[6], context);
	context->gpr[15] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[6] = 2 + context->gpr[6];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_0110_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[6] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[6], context);
	context->gpr[15] = context->scratch1;
	context->gpr[6] = 4 + context->gpr[6];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_0110_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[15] = ~context->gpr[6];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_0110_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[6] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[6] << 8;
	temp2 = 65280 & temp2;
	context->gpr[15] = context->gpr[6] & 4294901760;
	context->gpr[15] = temp1 | context->gpr[15];
	context->gpr[15] = temp2 | context->gpr[15];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_0110_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[6] >> 16;
	context->gpr[15] = context->gpr[6] << 16;
	context->gpr[15] = temp | context->gpr[15];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_0110_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[6]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[15] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_0110_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[15] = -context->gpr[6];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_0110_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[15] = context->gpr[6] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_0110_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[15] = context->gpr[6] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_0110_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[15] = (context->gpr[15] & ~65535) | ((context->gpr[6] & 255) & 128 ? (context->gpr[6] & 255) | 65280 : (context->gpr[6] & 255));
	context->gpr[15] = (context->gpr[15] & 65535) & 32768 ? (context->gpr[15] & 65535) | 4294901760 : (context->gpr[15] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_0110_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[15] = (context->gpr[6] & 65535) & 32768 ? (context->gpr[6] & 65535) | 4294901760 : (context->gpr[6] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_0111_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[7] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[7], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[15] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_0111_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[7] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[7], context);
	context->gpr[15] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_0111_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[7] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[7], context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_0111_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[15] = context->gpr[7];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_0111_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[7] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[7], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[15] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[7] = 1 + context->gpr[7];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_0111_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[7] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[7], context);
	context->gpr[15] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[7] = 2 + context->gpr[7];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_0111_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[7] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[7], context);
	context->gpr[15] = context->scratch1;
	context->gpr[7] = 4 + context->gpr[7];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_0111_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[15] = ~context->gpr[7];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_0111_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[7] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[7] << 8;
	temp2 = 65280 & temp2;
	context->gpr[15] = context->gpr[7] & 4294901760;
	context->gpr[15] = temp1 | context->gpr[15];
	context->gpr[15] = temp2 | context->gpr[15];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_0111_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[7] >> 16;
	context->gpr[15] = context->gpr[7] << 16;
	context->gpr[15] = temp | context->gpr[15];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_0111_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[7]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[15] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_0111_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[15] = -context->gpr[7];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_0111_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[15] = context->gpr[7] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_0111_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[15] = context->gpr[7] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_0111_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[15] = (context->gpr[15] & ~65535) | ((context->gpr[7] & 255) & 128 ? (context->gpr[7] & 255) | 65280 : (context->gpr[7] & 255));
	context->gpr[15] = (context->gpr[15] & 65535) & 32768 ? (context->gpr[15] & 65535) | 4294901760 : (context->gpr[15] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_0111_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[15] = (context->gpr[7] & 65535) & 32768 ? (context->gpr[7] & 65535) | 4294901760 : (context->gpr[7] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_1000_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[8] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[8], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[15] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_1000_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[8] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[8], context);
	context->gpr[15] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_1000_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[8] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[8], context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_1000_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[15] = context->gpr[8];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_1000_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[8] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[8], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[15] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[8] = 1 + context->gpr[8];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_1000_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[8] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[8], context);
	context->gpr[15] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[8] = 2 + context->gpr[8];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_1000_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[8] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[8], context);
	context->gpr[15] = context->scratch1;
	context->gpr[8] = 4 + context->gpr[8];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_1000_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[15] = ~context->gpr[8];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_1000_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[8] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[8] << 8;
	temp2 = 65280 & temp2;
	context->gpr[15] = context->gpr[8] & 4294901760;
	context->gpr[15] = temp1 | context->gpr[15];
	context->gpr[15] = temp2 | context->gpr[15];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_1000_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[8] >> 16;
	context->gpr[15] = context->gpr[8] << 16;
	context->gpr[15] = temp | context->gpr[15];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_1000_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[8]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[15] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_1000_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[15] = -context->gpr[8];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_1000_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[15] = context->gpr[8] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_1000_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[15] = context->gpr[8] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_1000_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[15] = (context->gpr[15] & ~65535) | ((context->gpr[8] & 255) & 128 ? (context->gpr[8] & 255) | 65280 : (context->gpr[8] & 255));
	context->gpr[15] = (context->gpr[15] & 65535) & 32768 ? (context->gpr[15] & 65535) | 4294901760 : (context->gpr[15] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_1000_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[15] = (context->gpr[8] & 65535) & 32768 ? (context->gpr[8] & 65535) | 4294901760 : (context->gpr[8] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_1001_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[9] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[9], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[15] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_1001_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[9] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[9], context);
	context->gpr[15] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_1001_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[9] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[9], context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_1001_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[15] = context->gpr[9];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_1001_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[9] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[9], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[15] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[9] = 1 + context->gpr[9];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_1001_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[9] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[9], context);
	context->gpr[15] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[9] = 2 + context->gpr[9];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_1001_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[9] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[9], context);
	context->gpr[15] = context->scratch1;
	context->gpr[9] = 4 + context->gpr[9];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_1001_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[15] = ~context->gpr[9];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_1001_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[9] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[9] << 8;
	temp2 = 65280 & temp2;
	context->gpr[15] = context->gpr[9] & 4294901760;
	context->gpr[15] = temp1 | context->gpr[15];
	context->gpr[15] = temp2 | context->gpr[15];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_1001_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[9] >> 16;
	context->gpr[15] = context->gpr[9] << 16;
	context->gpr[15] = temp | context->gpr[15];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_1001_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[9]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[15] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_1001_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[15] = -context->gpr[9];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_1001_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[15] = context->gpr[9] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_1001_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[15] = context->gpr[9] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_1001_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[15] = (context->gpr[15] & ~65535) | ((context->gpr[9] & 255) & 128 ? (context->gpr[9] & 255) | 65280 : (context->gpr[9] & 255));
	context->gpr[15] = (context->gpr[15] & 65535) & 32768 ? (context->gpr[15] & 65535) | 4294901760 : (context->gpr[15] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_1001_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[15] = (context->gpr[9] & 65535) & 32768 ? (context->gpr[9] & 65535) | 4294901760 : (context->gpr[9] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_1010_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[10] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[10], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[15] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_1010_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[10] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[10], context);
	context->gpr[15] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_1010_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[10] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[10], context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_1010_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[15] = context->gpr[10];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_1010_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[10] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[10], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[15] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[10] = 1 + context->gpr[10];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_1010_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[10] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[10], context);
	context->gpr[15] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[10] = 2 + context->gpr[10];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_1010_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[10] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[10], context);
	context->gpr[15] = context->scratch1;
	context->gpr[10] = 4 + context->gpr[10];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_1010_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[15] = ~context->gpr[10];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_1010_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[10] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[10] << 8;
	temp2 = 65280 & temp2;
	context->gpr[15] = context->gpr[10] & 4294901760;
	context->gpr[15] = temp1 | context->gpr[15];
	context->gpr[15] = temp2 | context->gpr[15];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_1010_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[10] >> 16;
	context->gpr[15] = context->gpr[10] << 16;
	context->gpr[15] = temp | context->gpr[15];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_1010_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[10]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[15] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_1010_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[15] = -context->gpr[10];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_1010_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[15] = context->gpr[10] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_1010_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[15] = context->gpr[10] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_1010_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[15] = (context->gpr[15] & ~65535) | ((context->gpr[10] & 255) & 128 ? (context->gpr[10] & 255) | 65280 : (context->gpr[10] & 255));
	context->gpr[15] = (context->gpr[15] & 65535) & 32768 ? (context->gpr[15] & 65535) | 4294901760 : (context->gpr[15] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_1010_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[15] = (context->gpr[10] & 65535) & 32768 ? (context->gpr[10] & 65535) | 4294901760 : (context->gpr[10] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_1011_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[11] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[11], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[15] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_1011_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[11] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[11], context);
	context->gpr[15] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_1011_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[11] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[11], context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_1011_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[15] = context->gpr[11];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_1011_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[11] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[11], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[15] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[11] = 1 + context->gpr[11];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_1011_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[11] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[11], context);
	context->gpr[15] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[11] = 2 + context->gpr[11];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_1011_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[11] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[11], context);
	context->gpr[15] = context->scratch1;
	context->gpr[11] = 4 + context->gpr[11];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_1011_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[15] = ~context->gpr[11];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_1011_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[11] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[11] << 8;
	temp2 = 65280 & temp2;
	context->gpr[15] = context->gpr[11] & 4294901760;
	context->gpr[15] = temp1 | context->gpr[15];
	context->gpr[15] = temp2 | context->gpr[15];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_1011_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[11] >> 16;
	context->gpr[15] = context->gpr[11] << 16;
	context->gpr[15] = temp | context->gpr[15];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_1011_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[11]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[15] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_1011_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[15] = -context->gpr[11];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_1011_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[15] = context->gpr[11] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_1011_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[15] = context->gpr[11] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_1011_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[15] = (context->gpr[15] & ~65535) | ((context->gpr[11] & 255) & 128 ? (context->gpr[11] & 255) | 65280 : (context->gpr[11] & 255));
	context->gpr[15] = (context->gpr[15] & 65535) & 32768 ? (context->gpr[15] & 65535) | 4294901760 : (context->gpr[15] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_1011_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[15] = (context->gpr[11] & 65535) & 32768 ? (context->gpr[11] & 65535) | 4294901760 : (context->gpr[11] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_1100_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[12] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[12], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[15] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_1100_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[12] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[12], context);
	context->gpr[15] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_1100_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[12] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[12], context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_1100_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[15] = context->gpr[12];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_1100_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[12] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[12], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[15] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[12] = 1 + context->gpr[12];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_1100_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[12] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[12], context);
	context->gpr[15] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[12] = 2 + context->gpr[12];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_1100_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[12] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[12], context);
	context->gpr[15] = context->scratch1;
	context->gpr[12] = 4 + context->gpr[12];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_1100_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[15] = ~context->gpr[12];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_1100_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[12] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[12] << 8;
	temp2 = 65280 & temp2;
	context->gpr[15] = context->gpr[12] & 4294901760;
	context->gpr[15] = temp1 | context->gpr[15];
	context->gpr[15] = temp2 | context->gpr[15];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_1100_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[12] >> 16;
	context->gpr[15] = context->gpr[12] << 16;
	context->gpr[15] = temp | context->gpr[15];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_1100_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[12]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[15] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_1100_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[15] = -context->gpr[12];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_1100_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[15] = context->gpr[12] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_1100_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[15] = context->gpr[12] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_1100_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[15] = (context->gpr[15] & ~65535) | ((context->gpr[12] & 255) & 128 ? (context->gpr[12] & 255) | 65280 : (context->gpr[12] & 255));
	context->gpr[15] = (context->gpr[15] & 65535) & 32768 ? (context->gpr[15] & 65535) | 4294901760 : (context->gpr[15] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_1100_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[15] = (context->gpr[12] & 65535) & 32768 ? (context->gpr[12] & 65535) | 4294901760 : (context->gpr[12] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_1101_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[13] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[13], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[15] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_1101_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[13] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[13], context);
	context->gpr[15] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_1101_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[13] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[13], context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_1101_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[15] = context->gpr[13];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_1101_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[13] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[13], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[15] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[13] = 1 + context->gpr[13];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_1101_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[13] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[13], context);
	context->gpr[15] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[13] = 2 + context->gpr[13];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_1101_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[13] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[13], context);
	context->gpr[15] = context->scratch1;
	context->gpr[13] = 4 + context->gpr[13];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_1101_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[15] = ~context->gpr[13];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_1101_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[13] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[13] << 8;
	temp2 = 65280 & temp2;
	context->gpr[15] = context->gpr[13] & 4294901760;
	context->gpr[15] = temp1 | context->gpr[15];
	context->gpr[15] = temp2 | context->gpr[15];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_1101_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[13] >> 16;
	context->gpr[15] = context->gpr[13] << 16;
	context->gpr[15] = temp | context->gpr[15];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_1101_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[13]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[15] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_1101_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[15] = -context->gpr[13];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_1101_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[15] = context->gpr[13] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_1101_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[15] = context->gpr[13] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_1101_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[15] = (context->gpr[15] & ~65535) | ((context->gpr[13] & 255) & 128 ? (context->gpr[13] & 255) | 65280 : (context->gpr[13] & 255));
	context->gpr[15] = (context->gpr[15] & 65535) & 32768 ? (context->gpr[15] & 65535) | 4294901760 : (context->gpr[15] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_1101_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[15] = (context->gpr[13] & 65535) & 32768 ? (context->gpr[13] & 65535) | 4294901760 : (context->gpr[13] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_1110_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[14] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[14], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[15] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_1110_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[14] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[14], context);
	context->gpr[15] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_1110_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[14] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[14], context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_1110_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[15] = context->gpr[14];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_1110_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[14] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[14], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[15] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[14] = 1 + context->gpr[14];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_1110_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[14] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[14], context);
	context->gpr[15] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->gpr[14] = 2 + context->gpr[14];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_1110_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[14] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[14], context);
	context->gpr[15] = context->scratch1;
	context->gpr[14] = 4 + context->gpr[14];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_1110_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[15] = ~context->gpr[14];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_1110_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[14] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[14] << 8;
	temp2 = 65280 & temp2;
	context->gpr[15] = context->gpr[14] & 4294901760;
	context->gpr[15] = temp1 | context->gpr[15];
	context->gpr[15] = temp2 | context->gpr[15];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_1110_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[14] >> 16;
	context->gpr[15] = context->gpr[14] << 16;
	context->gpr[15] = temp | context->gpr[15];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_1110_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[14]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[15] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_1110_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[15] = -context->gpr[14];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_1110_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[15] = context->gpr[14] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_1110_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[15] = context->gpr[14] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_1110_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[15] = (context->gpr[15] & ~65535) | ((context->gpr[14] & 255) & 128 ? (context->gpr[14] & 255) | 65280 : (context->gpr[14] & 255));
	context->gpr[15] = (context->gpr[15] & 65535) & 32768 ? (context->gpr[15] & 65535) | 4294901760 : (context->gpr[15] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_1110_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[15] = (context->gpr[14] & 65535) & 32768 ? (context->gpr[14] & 65535) | 4294901760 : (context->gpr[14] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_b_M_1111_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[15] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[15], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[15] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_w_M_1111_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[15] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[15], context);
	context->gpr[15] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_rm_rn_l_M_1111_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[15] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[15], context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_rm_rn_M_1111_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[15] = context->gpr[15];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_b_M_1111_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read8_tmp = context->gpr[15] >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->gpr[15], context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[15] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_w_M_1111_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read16_tmp = context->gpr[15] >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->gpr[15], context);
	context->gpr[15] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_postinc_rm_rn_l_M_1111_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t cmp_tmp32__;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->did_mem = 1;
	sh2_read32_tmp = context->gpr[15] >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->gpr[15], context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void not_M_1111_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[15] = ~context->gpr[15];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_b_M_1111_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp1;
	uint32_t temp2;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp1 = context->gpr[15] >> 8;
	temp1 = 255 & temp1;
	temp2 = context->gpr[15] << 8;
	temp2 = 65280 & temp2;
	context->gpr[15] = context->gpr[15] & 4294901760;
	context->gpr[15] = temp1 | context->gpr[15];
	context->gpr[15] = temp2 | context->gpr[15];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void swap_w_M_1111_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[15] >> 16;
	context->gpr[15] = context->gpr[15] << 16;
	context->gpr[15] = temp | context->gpr[15];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void negc_M_1111_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	gen_tmp64__ = ((uint64_t)0) - ((uint64_t)context->gpr[15]) - (context->t ? ((uint64_t)1) : ((uint64_t)0));
	context->t = gen_tmp64__ >> 25 & 128U;
	context->gpr[15] = gen_tmp64__;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void neg_M_1111_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[15] = -context->gpr[15];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_b_M_1111_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[15] = context->gpr[15] & 255;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void extu_w_M_1111_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[15] = context->gpr[15] & 65535;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_b_M_1111_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[15] = (context->gpr[15] & ~65535) | ((context->gpr[15] & 255) & 128 ? (context->gpr[15] & 255) | 65280 : (context->gpr[15] & 255));
	context->gpr[15] = (context->gpr[15] & 65535) & 32768 ? (context->gpr[15] & 65535) | 4294901760 : (context->gpr[15] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void exts_w_M_1111_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[15] = (context->gpr[15] & 65535) & 32768 ? (context->gpr[15] & 65535) | 4294901760 : (context->gpr[15] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_imm_rn_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t imm;
	uint16_t I = context->prefetch_cur & 255;
	context->cycles += context->opts->gen.clock_divider * 1;
	imm = (imm & ~65535) | ((I & 255) & 128 ? (I & 255) | 65280 : (I & 255));
	imm = (imm & 65535) & 32768 ? (imm & 65535) | 4294901760 : (imm & 65535);
	context->gpr[0] = imm + context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_imm_rn_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t imm;
	uint16_t I = context->prefetch_cur & 255;
	context->cycles += context->opts->gen.clock_divider * 1;
	imm = (imm & ~65535) | ((I & 255) & 128 ? (I & 255) | 65280 : (I & 255));
	imm = (imm & 65535) & 32768 ? (imm & 65535) | 4294901760 : (imm & 65535);
	context->gpr[1] = imm + context->gpr[1];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_imm_rn_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t imm;
	uint16_t I = context->prefetch_cur & 255;
	context->cycles += context->opts->gen.clock_divider * 1;
	imm = (imm & ~65535) | ((I & 255) & 128 ? (I & 255) | 65280 : (I & 255));
	imm = (imm & 65535) & 32768 ? (imm & 65535) | 4294901760 : (imm & 65535);
	context->gpr[2] = imm + context->gpr[2];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_imm_rn_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t imm;
	uint16_t I = context->prefetch_cur & 255;
	context->cycles += context->opts->gen.clock_divider * 1;
	imm = (imm & ~65535) | ((I & 255) & 128 ? (I & 255) | 65280 : (I & 255));
	imm = (imm & 65535) & 32768 ? (imm & 65535) | 4294901760 : (imm & 65535);
	context->gpr[3] = imm + context->gpr[3];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_imm_rn_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t imm;
	uint16_t I = context->prefetch_cur & 255;
	context->cycles += context->opts->gen.clock_divider * 1;
	imm = (imm & ~65535) | ((I & 255) & 128 ? (I & 255) | 65280 : (I & 255));
	imm = (imm & 65535) & 32768 ? (imm & 65535) | 4294901760 : (imm & 65535);
	context->gpr[4] = imm + context->gpr[4];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_imm_rn_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t imm;
	uint16_t I = context->prefetch_cur & 255;
	context->cycles += context->opts->gen.clock_divider * 1;
	imm = (imm & ~65535) | ((I & 255) & 128 ? (I & 255) | 65280 : (I & 255));
	imm = (imm & 65535) & 32768 ? (imm & 65535) | 4294901760 : (imm & 65535);
	context->gpr[5] = imm + context->gpr[5];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_imm_rn_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t imm;
	uint16_t I = context->prefetch_cur & 255;
	context->cycles += context->opts->gen.clock_divider * 1;
	imm = (imm & ~65535) | ((I & 255) & 128 ? (I & 255) | 65280 : (I & 255));
	imm = (imm & 65535) & 32768 ? (imm & 65535) | 4294901760 : (imm & 65535);
	context->gpr[6] = imm + context->gpr[6];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_imm_rn_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t imm;
	uint16_t I = context->prefetch_cur & 255;
	context->cycles += context->opts->gen.clock_divider * 1;
	imm = (imm & ~65535) | ((I & 255) & 128 ? (I & 255) | 65280 : (I & 255));
	imm = (imm & 65535) & 32768 ? (imm & 65535) | 4294901760 : (imm & 65535);
	context->gpr[7] = imm + context->gpr[7];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_imm_rn_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t imm;
	uint16_t I = context->prefetch_cur & 255;
	context->cycles += context->opts->gen.clock_divider * 1;
	imm = (imm & ~65535) | ((I & 255) & 128 ? (I & 255) | 65280 : (I & 255));
	imm = (imm & 65535) & 32768 ? (imm & 65535) | 4294901760 : (imm & 65535);
	context->gpr[8] = imm + context->gpr[8];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_imm_rn_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t imm;
	uint16_t I = context->prefetch_cur & 255;
	context->cycles += context->opts->gen.clock_divider * 1;
	imm = (imm & ~65535) | ((I & 255) & 128 ? (I & 255) | 65280 : (I & 255));
	imm = (imm & 65535) & 32768 ? (imm & 65535) | 4294901760 : (imm & 65535);
	context->gpr[9] = imm + context->gpr[9];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_imm_rn_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t imm;
	uint16_t I = context->prefetch_cur & 255;
	context->cycles += context->opts->gen.clock_divider * 1;
	imm = (imm & ~65535) | ((I & 255) & 128 ? (I & 255) | 65280 : (I & 255));
	imm = (imm & 65535) & 32768 ? (imm & 65535) | 4294901760 : (imm & 65535);
	context->gpr[10] = imm + context->gpr[10];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_imm_rn_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t imm;
	uint16_t I = context->prefetch_cur & 255;
	context->cycles += context->opts->gen.clock_divider * 1;
	imm = (imm & ~65535) | ((I & 255) & 128 ? (I & 255) | 65280 : (I & 255));
	imm = (imm & 65535) & 32768 ? (imm & 65535) | 4294901760 : (imm & 65535);
	context->gpr[11] = imm + context->gpr[11];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_imm_rn_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t imm;
	uint16_t I = context->prefetch_cur & 255;
	context->cycles += context->opts->gen.clock_divider * 1;
	imm = (imm & ~65535) | ((I & 255) & 128 ? (I & 255) | 65280 : (I & 255));
	imm = (imm & 65535) & 32768 ? (imm & 65535) | 4294901760 : (imm & 65535);
	context->gpr[12] = imm + context->gpr[12];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_imm_rn_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t imm;
	uint16_t I = context->prefetch_cur & 255;
	context->cycles += context->opts->gen.clock_divider * 1;
	imm = (imm & ~65535) | ((I & 255) & 128 ? (I & 255) | 65280 : (I & 255));
	imm = (imm & 65535) & 32768 ? (imm & 65535) | 4294901760 : (imm & 65535);
	context->gpr[13] = imm + context->gpr[13];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_imm_rn_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t imm;
	uint16_t I = context->prefetch_cur & 255;
	context->cycles += context->opts->gen.clock_divider * 1;
	imm = (imm & ~65535) | ((I & 255) & 128 ? (I & 255) | 65280 : (I & 255));
	imm = (imm & 65535) & 32768 ? (imm & 65535) | 4294901760 : (imm & 65535);
	context->gpr[14] = imm + context->gpr[14];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void add_imm_rn_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t imm;
	uint16_t I = context->prefetch_cur & 255;
	context->cycles += context->opts->gen.clock_divider * 1;
	imm = (imm & ~65535) | ((I & 255) & 128 ? (I & 255) | 65280 : (I & 255));
	imm = (imm & 65535) & 32768 ? (imm & 65535) | 4294901760 : (imm & 65535);
	context->gpr[15] = imm + context->gpr[15];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_0000_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0 + context->gpr[0];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_0001_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 1 + context->gpr[0];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_0010_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 2 + context->gpr[0];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_0011_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 3 + context->gpr[0];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_0100_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4 + context->gpr[0];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_0101_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 5 + context->gpr[0];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_0110_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 6 + context->gpr[0];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_0111_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 7 + context->gpr[0];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_1000_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8 + context->gpr[0];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_1001_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 9 + context->gpr[0];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_1010_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 10 + context->gpr[0];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_1011_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 11 + context->gpr[0];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_1100_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12 + context->gpr[0];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_1101_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 13 + context->gpr[0];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_1110_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 14 + context->gpr[0];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_1111_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 15 + context->gpr[0];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_0000_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0 + context->gpr[1];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_0001_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 1 + context->gpr[1];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_0010_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 2 + context->gpr[1];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_0011_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 3 + context->gpr[1];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_0100_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4 + context->gpr[1];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_0101_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 5 + context->gpr[1];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_0110_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 6 + context->gpr[1];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_0111_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 7 + context->gpr[1];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_1000_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8 + context->gpr[1];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_1001_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 9 + context->gpr[1];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_1010_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 10 + context->gpr[1];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_1011_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 11 + context->gpr[1];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_1100_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12 + context->gpr[1];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_1101_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 13 + context->gpr[1];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_1110_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 14 + context->gpr[1];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_1111_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 15 + context->gpr[1];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_0000_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0 + context->gpr[2];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_0001_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 1 + context->gpr[2];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_0010_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 2 + context->gpr[2];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_0011_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 3 + context->gpr[2];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_0100_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4 + context->gpr[2];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_0101_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 5 + context->gpr[2];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_0110_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 6 + context->gpr[2];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_0111_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 7 + context->gpr[2];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_1000_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8 + context->gpr[2];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_1001_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 9 + context->gpr[2];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_1010_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 10 + context->gpr[2];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_1011_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 11 + context->gpr[2];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_1100_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12 + context->gpr[2];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_1101_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 13 + context->gpr[2];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_1110_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 14 + context->gpr[2];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_1111_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 15 + context->gpr[2];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_0000_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0 + context->gpr[3];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_0001_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 1 + context->gpr[3];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_0010_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 2 + context->gpr[3];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_0011_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 3 + context->gpr[3];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_0100_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4 + context->gpr[3];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_0101_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 5 + context->gpr[3];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_0110_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 6 + context->gpr[3];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_0111_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 7 + context->gpr[3];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_1000_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8 + context->gpr[3];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_1001_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 9 + context->gpr[3];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_1010_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 10 + context->gpr[3];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_1011_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 11 + context->gpr[3];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_1100_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12 + context->gpr[3];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_1101_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 13 + context->gpr[3];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_1110_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 14 + context->gpr[3];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_1111_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 15 + context->gpr[3];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_0000_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0 + context->gpr[4];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_0001_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 1 + context->gpr[4];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_0010_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 2 + context->gpr[4];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_0011_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 3 + context->gpr[4];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_0100_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4 + context->gpr[4];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_0101_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 5 + context->gpr[4];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_0110_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 6 + context->gpr[4];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_0111_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 7 + context->gpr[4];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_1000_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8 + context->gpr[4];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_1001_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 9 + context->gpr[4];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_1010_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 10 + context->gpr[4];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_1011_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 11 + context->gpr[4];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_1100_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12 + context->gpr[4];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_1101_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 13 + context->gpr[4];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_1110_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 14 + context->gpr[4];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_1111_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 15 + context->gpr[4];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_0000_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0 + context->gpr[5];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_0001_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 1 + context->gpr[5];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_0010_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 2 + context->gpr[5];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_0011_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 3 + context->gpr[5];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_0100_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4 + context->gpr[5];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_0101_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 5 + context->gpr[5];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_0110_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 6 + context->gpr[5];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_0111_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 7 + context->gpr[5];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_1000_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8 + context->gpr[5];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_1001_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 9 + context->gpr[5];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_1010_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 10 + context->gpr[5];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_1011_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 11 + context->gpr[5];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_1100_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12 + context->gpr[5];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_1101_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 13 + context->gpr[5];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_1110_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 14 + context->gpr[5];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_1111_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 15 + context->gpr[5];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_0000_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0 + context->gpr[6];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_0001_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 1 + context->gpr[6];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_0010_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 2 + context->gpr[6];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_0011_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 3 + context->gpr[6];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_0100_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4 + context->gpr[6];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_0101_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 5 + context->gpr[6];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_0110_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 6 + context->gpr[6];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_0111_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 7 + context->gpr[6];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_1000_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8 + context->gpr[6];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_1001_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 9 + context->gpr[6];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_1010_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 10 + context->gpr[6];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_1011_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 11 + context->gpr[6];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_1100_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12 + context->gpr[6];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_1101_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 13 + context->gpr[6];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_1110_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 14 + context->gpr[6];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_1111_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 15 + context->gpr[6];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_0000_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0 + context->gpr[7];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_0001_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 1 + context->gpr[7];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_0010_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 2 + context->gpr[7];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_0011_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 3 + context->gpr[7];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_0100_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4 + context->gpr[7];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_0101_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 5 + context->gpr[7];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_0110_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 6 + context->gpr[7];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_0111_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 7 + context->gpr[7];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_1000_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8 + context->gpr[7];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_1001_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 9 + context->gpr[7];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_1010_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 10 + context->gpr[7];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_1011_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 11 + context->gpr[7];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_1100_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12 + context->gpr[7];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_1101_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 13 + context->gpr[7];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_1110_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 14 + context->gpr[7];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_1111_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 15 + context->gpr[7];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_0000_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0 + context->gpr[8];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_0001_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 1 + context->gpr[8];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_0010_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 2 + context->gpr[8];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_0011_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 3 + context->gpr[8];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_0100_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4 + context->gpr[8];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_0101_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 5 + context->gpr[8];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_0110_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 6 + context->gpr[8];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_0111_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 7 + context->gpr[8];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_1000_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8 + context->gpr[8];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_1001_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 9 + context->gpr[8];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_1010_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 10 + context->gpr[8];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_1011_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 11 + context->gpr[8];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_1100_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12 + context->gpr[8];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_1101_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 13 + context->gpr[8];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_1110_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 14 + context->gpr[8];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_1111_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 15 + context->gpr[8];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_0000_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0 + context->gpr[9];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_0001_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 1 + context->gpr[9];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_0010_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 2 + context->gpr[9];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_0011_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 3 + context->gpr[9];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_0100_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4 + context->gpr[9];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_0101_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 5 + context->gpr[9];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_0110_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 6 + context->gpr[9];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_0111_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 7 + context->gpr[9];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_1000_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8 + context->gpr[9];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_1001_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 9 + context->gpr[9];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_1010_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 10 + context->gpr[9];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_1011_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 11 + context->gpr[9];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_1100_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12 + context->gpr[9];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_1101_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 13 + context->gpr[9];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_1110_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 14 + context->gpr[9];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_1111_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 15 + context->gpr[9];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_0000_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0 + context->gpr[10];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_0001_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 1 + context->gpr[10];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_0010_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 2 + context->gpr[10];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_0011_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 3 + context->gpr[10];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_0100_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4 + context->gpr[10];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_0101_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 5 + context->gpr[10];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_0110_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 6 + context->gpr[10];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_0111_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 7 + context->gpr[10];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_1000_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8 + context->gpr[10];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_1001_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 9 + context->gpr[10];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_1010_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 10 + context->gpr[10];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_1011_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 11 + context->gpr[10];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_1100_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12 + context->gpr[10];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_1101_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 13 + context->gpr[10];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_1110_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 14 + context->gpr[10];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_1111_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 15 + context->gpr[10];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_0000_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0 + context->gpr[11];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_0001_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 1 + context->gpr[11];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_0010_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 2 + context->gpr[11];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_0011_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 3 + context->gpr[11];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_0100_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4 + context->gpr[11];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_0101_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 5 + context->gpr[11];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_0110_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 6 + context->gpr[11];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_0111_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 7 + context->gpr[11];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_1000_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8 + context->gpr[11];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_1001_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 9 + context->gpr[11];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_1010_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 10 + context->gpr[11];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_1011_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 11 + context->gpr[11];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_1100_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12 + context->gpr[11];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_1101_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 13 + context->gpr[11];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_1110_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 14 + context->gpr[11];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_1111_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 15 + context->gpr[11];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_0000_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0 + context->gpr[12];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_0001_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 1 + context->gpr[12];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_0010_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 2 + context->gpr[12];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_0011_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 3 + context->gpr[12];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_0100_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4 + context->gpr[12];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_0101_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 5 + context->gpr[12];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_0110_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 6 + context->gpr[12];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_0111_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 7 + context->gpr[12];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_1000_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8 + context->gpr[12];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_1001_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 9 + context->gpr[12];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_1010_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 10 + context->gpr[12];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_1011_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 11 + context->gpr[12];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_1100_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12 + context->gpr[12];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_1101_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 13 + context->gpr[12];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_1110_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 14 + context->gpr[12];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_1111_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 15 + context->gpr[12];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_0000_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0 + context->gpr[13];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_0001_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 1 + context->gpr[13];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_0010_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 2 + context->gpr[13];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_0011_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 3 + context->gpr[13];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_0100_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4 + context->gpr[13];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_0101_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 5 + context->gpr[13];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_0110_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 6 + context->gpr[13];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_0111_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 7 + context->gpr[13];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_1000_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8 + context->gpr[13];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_1001_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 9 + context->gpr[13];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_1010_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 10 + context->gpr[13];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_1011_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 11 + context->gpr[13];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_1100_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12 + context->gpr[13];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_1101_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 13 + context->gpr[13];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_1110_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 14 + context->gpr[13];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_1111_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 15 + context->gpr[13];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_0000_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0 + context->gpr[14];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_0001_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 1 + context->gpr[14];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_0010_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 2 + context->gpr[14];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_0011_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 3 + context->gpr[14];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_0100_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4 + context->gpr[14];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_0101_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 5 + context->gpr[14];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_0110_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 6 + context->gpr[14];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_0111_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 7 + context->gpr[14];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_1000_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8 + context->gpr[14];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_1001_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 9 + context->gpr[14];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_1010_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 10 + context->gpr[14];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_1011_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 11 + context->gpr[14];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_1100_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12 + context->gpr[14];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_1101_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 13 + context->gpr[14];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_1110_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 14 + context->gpr[14];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_1111_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 15 + context->gpr[14];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_0000_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0 + context->gpr[15];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_0001_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 1 + context->gpr[15];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_0010_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 2 + context->gpr[15];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_0011_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 3 + context->gpr[15];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_0100_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4 + context->gpr[15];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_0101_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 5 + context->gpr[15];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_0110_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 6 + context->gpr[15];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_0111_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 7 + context->gpr[15];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_1000_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8 + context->gpr[15];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_1001_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 9 + context->gpr[15];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_1010_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 10 + context->gpr[15];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_1011_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 11 + context->gpr[15];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_1100_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12 + context->gpr[15];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_1101_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 13 + context->gpr[15];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_1110_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 14 + context->gpr[15];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_b_D_1111_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 15 + context->gpr[15];
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_0000_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[0] + 0;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_0001_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 2;
	context->scratch2 = context->gpr[0] + 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_0010_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[0] + 4;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_0011_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 6;
	context->scratch2 = context->gpr[0] + 6;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_0100_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[0] + 8;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_0101_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 10;
	context->scratch2 = context->gpr[0] + 10;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_0110_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[0] + 12;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_0111_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 14;
	context->scratch2 = context->gpr[0] + 14;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_1000_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[0] + 16;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_1001_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 18;
	context->scratch2 = context->gpr[0] + 18;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_1010_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[0] + 20;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_1011_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 22;
	context->scratch2 = context->gpr[0] + 22;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_1100_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[0] + 24;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_1101_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 26;
	context->scratch2 = context->gpr[0] + 26;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_1110_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[0] + 28;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_1111_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 30;
	context->scratch2 = context->gpr[0] + 30;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_0000_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[1] + 0;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_0001_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 2;
	context->scratch2 = context->gpr[1] + 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_0010_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[1] + 4;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_0011_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 6;
	context->scratch2 = context->gpr[1] + 6;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_0100_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[1] + 8;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_0101_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 10;
	context->scratch2 = context->gpr[1] + 10;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_0110_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[1] + 12;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_0111_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 14;
	context->scratch2 = context->gpr[1] + 14;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_1000_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[1] + 16;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_1001_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 18;
	context->scratch2 = context->gpr[1] + 18;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_1010_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[1] + 20;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_1011_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 22;
	context->scratch2 = context->gpr[1] + 22;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_1100_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[1] + 24;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_1101_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 26;
	context->scratch2 = context->gpr[1] + 26;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_1110_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[1] + 28;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_1111_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 30;
	context->scratch2 = context->gpr[1] + 30;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_0000_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[2] + 0;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_0001_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 2;
	context->scratch2 = context->gpr[2] + 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_0010_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[2] + 4;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_0011_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 6;
	context->scratch2 = context->gpr[2] + 6;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_0100_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[2] + 8;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_0101_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 10;
	context->scratch2 = context->gpr[2] + 10;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_0110_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[2] + 12;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_0111_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 14;
	context->scratch2 = context->gpr[2] + 14;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_1000_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[2] + 16;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_1001_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 18;
	context->scratch2 = context->gpr[2] + 18;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_1010_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[2] + 20;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_1011_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 22;
	context->scratch2 = context->gpr[2] + 22;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_1100_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[2] + 24;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_1101_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 26;
	context->scratch2 = context->gpr[2] + 26;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_1110_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[2] + 28;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_1111_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 30;
	context->scratch2 = context->gpr[2] + 30;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_0000_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[3] + 0;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_0001_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 2;
	context->scratch2 = context->gpr[3] + 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_0010_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[3] + 4;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_0011_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 6;
	context->scratch2 = context->gpr[3] + 6;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_0100_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[3] + 8;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_0101_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 10;
	context->scratch2 = context->gpr[3] + 10;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_0110_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[3] + 12;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_0111_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 14;
	context->scratch2 = context->gpr[3] + 14;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_1000_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[3] + 16;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_1001_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 18;
	context->scratch2 = context->gpr[3] + 18;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_1010_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[3] + 20;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_1011_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 22;
	context->scratch2 = context->gpr[3] + 22;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_1100_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[3] + 24;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_1101_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 26;
	context->scratch2 = context->gpr[3] + 26;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_1110_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[3] + 28;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_1111_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 30;
	context->scratch2 = context->gpr[3] + 30;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_0000_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[4] + 0;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_0001_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 2;
	context->scratch2 = context->gpr[4] + 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_0010_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[4] + 4;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_0011_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 6;
	context->scratch2 = context->gpr[4] + 6;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_0100_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[4] + 8;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_0101_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 10;
	context->scratch2 = context->gpr[4] + 10;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_0110_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[4] + 12;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_0111_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 14;
	context->scratch2 = context->gpr[4] + 14;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_1000_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[4] + 16;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_1001_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 18;
	context->scratch2 = context->gpr[4] + 18;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_1010_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[4] + 20;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_1011_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 22;
	context->scratch2 = context->gpr[4] + 22;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_1100_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[4] + 24;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_1101_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 26;
	context->scratch2 = context->gpr[4] + 26;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_1110_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[4] + 28;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_1111_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 30;
	context->scratch2 = context->gpr[4] + 30;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_0000_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[5] + 0;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_0001_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 2;
	context->scratch2 = context->gpr[5] + 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_0010_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[5] + 4;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_0011_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 6;
	context->scratch2 = context->gpr[5] + 6;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_0100_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[5] + 8;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_0101_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 10;
	context->scratch2 = context->gpr[5] + 10;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_0110_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[5] + 12;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_0111_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 14;
	context->scratch2 = context->gpr[5] + 14;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_1000_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[5] + 16;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_1001_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 18;
	context->scratch2 = context->gpr[5] + 18;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_1010_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[5] + 20;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_1011_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 22;
	context->scratch2 = context->gpr[5] + 22;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_1100_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[5] + 24;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_1101_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 26;
	context->scratch2 = context->gpr[5] + 26;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_1110_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[5] + 28;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_1111_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 30;
	context->scratch2 = context->gpr[5] + 30;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_0000_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[6] + 0;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_0001_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 2;
	context->scratch2 = context->gpr[6] + 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_0010_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[6] + 4;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_0011_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 6;
	context->scratch2 = context->gpr[6] + 6;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_0100_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[6] + 8;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_0101_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 10;
	context->scratch2 = context->gpr[6] + 10;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_0110_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[6] + 12;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_0111_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 14;
	context->scratch2 = context->gpr[6] + 14;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_1000_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[6] + 16;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_1001_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 18;
	context->scratch2 = context->gpr[6] + 18;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_1010_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[6] + 20;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_1011_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 22;
	context->scratch2 = context->gpr[6] + 22;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_1100_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[6] + 24;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_1101_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 26;
	context->scratch2 = context->gpr[6] + 26;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_1110_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[6] + 28;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_1111_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 30;
	context->scratch2 = context->gpr[6] + 30;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_0000_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[7] + 0;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_0001_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 2;
	context->scratch2 = context->gpr[7] + 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_0010_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[7] + 4;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_0011_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 6;
	context->scratch2 = context->gpr[7] + 6;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_0100_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[7] + 8;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_0101_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 10;
	context->scratch2 = context->gpr[7] + 10;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_0110_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[7] + 12;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_0111_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 14;
	context->scratch2 = context->gpr[7] + 14;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_1000_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[7] + 16;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_1001_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 18;
	context->scratch2 = context->gpr[7] + 18;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_1010_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[7] + 20;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_1011_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 22;
	context->scratch2 = context->gpr[7] + 22;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_1100_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[7] + 24;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_1101_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 26;
	context->scratch2 = context->gpr[7] + 26;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_1110_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[7] + 28;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_1111_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 30;
	context->scratch2 = context->gpr[7] + 30;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_0000_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[8] + 0;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_0001_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 2;
	context->scratch2 = context->gpr[8] + 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_0010_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[8] + 4;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_0011_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 6;
	context->scratch2 = context->gpr[8] + 6;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_0100_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[8] + 8;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_0101_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 10;
	context->scratch2 = context->gpr[8] + 10;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_0110_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[8] + 12;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_0111_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 14;
	context->scratch2 = context->gpr[8] + 14;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_1000_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[8] + 16;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_1001_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 18;
	context->scratch2 = context->gpr[8] + 18;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_1010_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[8] + 20;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_1011_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 22;
	context->scratch2 = context->gpr[8] + 22;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_1100_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[8] + 24;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_1101_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 26;
	context->scratch2 = context->gpr[8] + 26;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_1110_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[8] + 28;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_1111_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 30;
	context->scratch2 = context->gpr[8] + 30;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_0000_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[9] + 0;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_0001_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 2;
	context->scratch2 = context->gpr[9] + 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_0010_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[9] + 4;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_0011_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 6;
	context->scratch2 = context->gpr[9] + 6;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_0100_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[9] + 8;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_0101_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 10;
	context->scratch2 = context->gpr[9] + 10;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_0110_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[9] + 12;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_0111_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 14;
	context->scratch2 = context->gpr[9] + 14;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_1000_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[9] + 16;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_1001_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 18;
	context->scratch2 = context->gpr[9] + 18;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_1010_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[9] + 20;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_1011_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 22;
	context->scratch2 = context->gpr[9] + 22;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_1100_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[9] + 24;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_1101_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 26;
	context->scratch2 = context->gpr[9] + 26;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_1110_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[9] + 28;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_1111_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 30;
	context->scratch2 = context->gpr[9] + 30;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_0000_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[10] + 0;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_0001_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 2;
	context->scratch2 = context->gpr[10] + 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_0010_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[10] + 4;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_0011_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 6;
	context->scratch2 = context->gpr[10] + 6;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_0100_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[10] + 8;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_0101_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 10;
	context->scratch2 = context->gpr[10] + 10;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_0110_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[10] + 12;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_0111_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 14;
	context->scratch2 = context->gpr[10] + 14;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_1000_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[10] + 16;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_1001_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 18;
	context->scratch2 = context->gpr[10] + 18;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_1010_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[10] + 20;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_1011_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 22;
	context->scratch2 = context->gpr[10] + 22;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_1100_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[10] + 24;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_1101_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 26;
	context->scratch2 = context->gpr[10] + 26;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_1110_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[10] + 28;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_1111_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 30;
	context->scratch2 = context->gpr[10] + 30;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_0000_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[11] + 0;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_0001_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 2;
	context->scratch2 = context->gpr[11] + 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_0010_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[11] + 4;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_0011_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 6;
	context->scratch2 = context->gpr[11] + 6;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_0100_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[11] + 8;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_0101_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 10;
	context->scratch2 = context->gpr[11] + 10;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_0110_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[11] + 12;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_0111_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 14;
	context->scratch2 = context->gpr[11] + 14;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_1000_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[11] + 16;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_1001_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 18;
	context->scratch2 = context->gpr[11] + 18;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_1010_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[11] + 20;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_1011_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 22;
	context->scratch2 = context->gpr[11] + 22;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_1100_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[11] + 24;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_1101_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 26;
	context->scratch2 = context->gpr[11] + 26;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_1110_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[11] + 28;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_1111_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 30;
	context->scratch2 = context->gpr[11] + 30;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_0000_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[12] + 0;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_0001_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 2;
	context->scratch2 = context->gpr[12] + 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_0010_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[12] + 4;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_0011_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 6;
	context->scratch2 = context->gpr[12] + 6;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_0100_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[12] + 8;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_0101_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 10;
	context->scratch2 = context->gpr[12] + 10;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_0110_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[12] + 12;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_0111_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 14;
	context->scratch2 = context->gpr[12] + 14;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_1000_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[12] + 16;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_1001_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 18;
	context->scratch2 = context->gpr[12] + 18;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_1010_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[12] + 20;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_1011_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 22;
	context->scratch2 = context->gpr[12] + 22;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_1100_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[12] + 24;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_1101_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 26;
	context->scratch2 = context->gpr[12] + 26;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_1110_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[12] + 28;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_1111_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 30;
	context->scratch2 = context->gpr[12] + 30;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_0000_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[13] + 0;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_0001_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 2;
	context->scratch2 = context->gpr[13] + 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_0010_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[13] + 4;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_0011_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 6;
	context->scratch2 = context->gpr[13] + 6;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_0100_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[13] + 8;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_0101_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 10;
	context->scratch2 = context->gpr[13] + 10;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_0110_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[13] + 12;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_0111_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 14;
	context->scratch2 = context->gpr[13] + 14;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_1000_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[13] + 16;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_1001_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 18;
	context->scratch2 = context->gpr[13] + 18;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_1010_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[13] + 20;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_1011_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 22;
	context->scratch2 = context->gpr[13] + 22;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_1100_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[13] + 24;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_1101_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 26;
	context->scratch2 = context->gpr[13] + 26;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_1110_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[13] + 28;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_1111_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 30;
	context->scratch2 = context->gpr[13] + 30;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_0000_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[14] + 0;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_0001_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 2;
	context->scratch2 = context->gpr[14] + 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_0010_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[14] + 4;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_0011_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 6;
	context->scratch2 = context->gpr[14] + 6;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_0100_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[14] + 8;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_0101_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 10;
	context->scratch2 = context->gpr[14] + 10;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_0110_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[14] + 12;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_0111_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 14;
	context->scratch2 = context->gpr[14] + 14;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_1000_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[14] + 16;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_1001_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 18;
	context->scratch2 = context->gpr[14] + 18;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_1010_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[14] + 20;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_1011_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 22;
	context->scratch2 = context->gpr[14] + 22;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_1100_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[14] + 24;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_1101_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 26;
	context->scratch2 = context->gpr[14] + 26;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_1110_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[14] + 28;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_1111_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 30;
	context->scratch2 = context->gpr[14] + 30;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_0000_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 0;
	context->scratch2 = context->gpr[15] + 0;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_0001_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 2;
	context->scratch2 = context->gpr[15] + 2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_0010_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 4;
	context->scratch2 = context->gpr[15] + 4;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_0011_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 6;
	context->scratch2 = context->gpr[15] + 6;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_0100_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 8;
	context->scratch2 = context->gpr[15] + 8;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_0101_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 10;
	context->scratch2 = context->gpr[15] + 10;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_0110_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 12;
	context->scratch2 = context->gpr[15] + 12;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_0111_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 14;
	context->scratch2 = context->gpr[15] + 14;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_1000_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 16;
	context->scratch2 = context->gpr[15] + 16;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_1001_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 18;
	context->scratch2 = context->gpr[15] + 18;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_1010_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 20;
	context->scratch2 = context->gpr[15] + 20;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_1011_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 22;
	context->scratch2 = context->gpr[15] + 22;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_1100_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 24;
	context->scratch2 = context->gpr[15] + 24;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_1101_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 26;
	context->scratch2 = context->gpr[15] + 26;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_1110_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 28;
	context->scratch2 = context->gpr[15] + 28;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_rn_w_D_1111_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = 30;
	context->scratch2 = context->gpr[15] + 30;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_0000_M_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0 + context->gpr[0];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_0001_M_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 1 + context->gpr[0];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_0010_M_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 2 + context->gpr[0];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_0011_M_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 3 + context->gpr[0];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_0100_M_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4 + context->gpr[0];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_0101_M_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 5 + context->gpr[0];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_0110_M_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 6 + context->gpr[0];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_0111_M_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 7 + context->gpr[0];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_1000_M_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8 + context->gpr[0];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_1001_M_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 9 + context->gpr[0];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_1010_M_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 10 + context->gpr[0];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_1011_M_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 11 + context->gpr[0];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_1100_M_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12 + context->gpr[0];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_1101_M_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 13 + context->gpr[0];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_1110_M_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 14 + context->gpr[0];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_1111_M_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 15 + context->gpr[0];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_0000_M_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0 + context->gpr[1];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_0001_M_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 1 + context->gpr[1];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_0010_M_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 2 + context->gpr[1];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_0011_M_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 3 + context->gpr[1];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_0100_M_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4 + context->gpr[1];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_0101_M_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 5 + context->gpr[1];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_0110_M_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 6 + context->gpr[1];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_0111_M_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 7 + context->gpr[1];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_1000_M_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8 + context->gpr[1];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_1001_M_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 9 + context->gpr[1];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_1010_M_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 10 + context->gpr[1];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_1011_M_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 11 + context->gpr[1];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_1100_M_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12 + context->gpr[1];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_1101_M_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 13 + context->gpr[1];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_1110_M_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 14 + context->gpr[1];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_1111_M_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 15 + context->gpr[1];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_0000_M_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0 + context->gpr[2];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_0001_M_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 1 + context->gpr[2];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_0010_M_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 2 + context->gpr[2];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_0011_M_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 3 + context->gpr[2];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_0100_M_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4 + context->gpr[2];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_0101_M_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 5 + context->gpr[2];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_0110_M_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 6 + context->gpr[2];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_0111_M_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 7 + context->gpr[2];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_1000_M_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8 + context->gpr[2];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_1001_M_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 9 + context->gpr[2];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_1010_M_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 10 + context->gpr[2];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_1011_M_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 11 + context->gpr[2];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_1100_M_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12 + context->gpr[2];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_1101_M_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 13 + context->gpr[2];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_1110_M_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 14 + context->gpr[2];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_1111_M_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 15 + context->gpr[2];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_0000_M_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0 + context->gpr[3];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_0001_M_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 1 + context->gpr[3];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_0010_M_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 2 + context->gpr[3];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_0011_M_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 3 + context->gpr[3];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_0100_M_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4 + context->gpr[3];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_0101_M_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 5 + context->gpr[3];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_0110_M_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 6 + context->gpr[3];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_0111_M_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 7 + context->gpr[3];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_1000_M_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8 + context->gpr[3];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_1001_M_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 9 + context->gpr[3];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_1010_M_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 10 + context->gpr[3];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_1011_M_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 11 + context->gpr[3];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_1100_M_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12 + context->gpr[3];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_1101_M_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 13 + context->gpr[3];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_1110_M_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 14 + context->gpr[3];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_1111_M_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 15 + context->gpr[3];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_0000_M_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0 + context->gpr[4];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_0001_M_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 1 + context->gpr[4];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_0010_M_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 2 + context->gpr[4];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_0011_M_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 3 + context->gpr[4];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_0100_M_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4 + context->gpr[4];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_0101_M_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 5 + context->gpr[4];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_0110_M_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 6 + context->gpr[4];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_0111_M_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 7 + context->gpr[4];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_1000_M_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8 + context->gpr[4];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_1001_M_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 9 + context->gpr[4];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_1010_M_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 10 + context->gpr[4];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_1011_M_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 11 + context->gpr[4];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_1100_M_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12 + context->gpr[4];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_1101_M_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 13 + context->gpr[4];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_1110_M_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 14 + context->gpr[4];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_1111_M_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 15 + context->gpr[4];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_0000_M_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0 + context->gpr[5];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_0001_M_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 1 + context->gpr[5];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_0010_M_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 2 + context->gpr[5];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_0011_M_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 3 + context->gpr[5];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_0100_M_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4 + context->gpr[5];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_0101_M_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 5 + context->gpr[5];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_0110_M_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 6 + context->gpr[5];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_0111_M_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 7 + context->gpr[5];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_1000_M_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8 + context->gpr[5];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_1001_M_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 9 + context->gpr[5];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_1010_M_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 10 + context->gpr[5];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_1011_M_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 11 + context->gpr[5];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_1100_M_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12 + context->gpr[5];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_1101_M_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 13 + context->gpr[5];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_1110_M_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 14 + context->gpr[5];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_1111_M_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 15 + context->gpr[5];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_0000_M_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0 + context->gpr[6];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_0001_M_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 1 + context->gpr[6];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_0010_M_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 2 + context->gpr[6];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_0011_M_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 3 + context->gpr[6];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_0100_M_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4 + context->gpr[6];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_0101_M_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 5 + context->gpr[6];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_0110_M_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 6 + context->gpr[6];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_0111_M_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 7 + context->gpr[6];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_1000_M_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8 + context->gpr[6];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_1001_M_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 9 + context->gpr[6];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_1010_M_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 10 + context->gpr[6];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_1011_M_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 11 + context->gpr[6];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_1100_M_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12 + context->gpr[6];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_1101_M_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 13 + context->gpr[6];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_1110_M_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 14 + context->gpr[6];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_1111_M_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 15 + context->gpr[6];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_0000_M_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0 + context->gpr[7];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_0001_M_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 1 + context->gpr[7];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_0010_M_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 2 + context->gpr[7];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_0011_M_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 3 + context->gpr[7];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_0100_M_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4 + context->gpr[7];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_0101_M_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 5 + context->gpr[7];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_0110_M_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 6 + context->gpr[7];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_0111_M_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 7 + context->gpr[7];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_1000_M_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8 + context->gpr[7];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_1001_M_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 9 + context->gpr[7];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_1010_M_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 10 + context->gpr[7];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_1011_M_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 11 + context->gpr[7];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_1100_M_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12 + context->gpr[7];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_1101_M_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 13 + context->gpr[7];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_1110_M_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 14 + context->gpr[7];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_1111_M_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 15 + context->gpr[7];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_0000_M_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0 + context->gpr[8];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_0001_M_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 1 + context->gpr[8];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_0010_M_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 2 + context->gpr[8];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_0011_M_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 3 + context->gpr[8];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_0100_M_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4 + context->gpr[8];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_0101_M_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 5 + context->gpr[8];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_0110_M_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 6 + context->gpr[8];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_0111_M_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 7 + context->gpr[8];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_1000_M_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8 + context->gpr[8];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_1001_M_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 9 + context->gpr[8];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_1010_M_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 10 + context->gpr[8];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_1011_M_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 11 + context->gpr[8];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_1100_M_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12 + context->gpr[8];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_1101_M_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 13 + context->gpr[8];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_1110_M_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 14 + context->gpr[8];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_1111_M_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 15 + context->gpr[8];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_0000_M_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0 + context->gpr[9];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_0001_M_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 1 + context->gpr[9];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_0010_M_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 2 + context->gpr[9];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_0011_M_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 3 + context->gpr[9];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_0100_M_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4 + context->gpr[9];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_0101_M_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 5 + context->gpr[9];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_0110_M_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 6 + context->gpr[9];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_0111_M_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 7 + context->gpr[9];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_1000_M_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8 + context->gpr[9];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_1001_M_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 9 + context->gpr[9];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_1010_M_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 10 + context->gpr[9];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_1011_M_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 11 + context->gpr[9];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_1100_M_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12 + context->gpr[9];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_1101_M_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 13 + context->gpr[9];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_1110_M_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 14 + context->gpr[9];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_1111_M_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 15 + context->gpr[9];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_0000_M_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0 + context->gpr[10];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_0001_M_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 1 + context->gpr[10];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_0010_M_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 2 + context->gpr[10];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_0011_M_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 3 + context->gpr[10];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_0100_M_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4 + context->gpr[10];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_0101_M_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 5 + context->gpr[10];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_0110_M_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 6 + context->gpr[10];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_0111_M_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 7 + context->gpr[10];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_1000_M_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8 + context->gpr[10];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_1001_M_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 9 + context->gpr[10];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_1010_M_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 10 + context->gpr[10];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_1011_M_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 11 + context->gpr[10];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_1100_M_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12 + context->gpr[10];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_1101_M_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 13 + context->gpr[10];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_1110_M_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 14 + context->gpr[10];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_1111_M_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 15 + context->gpr[10];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_0000_M_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0 + context->gpr[11];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_0001_M_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 1 + context->gpr[11];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_0010_M_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 2 + context->gpr[11];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_0011_M_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 3 + context->gpr[11];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_0100_M_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4 + context->gpr[11];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_0101_M_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 5 + context->gpr[11];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_0110_M_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 6 + context->gpr[11];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_0111_M_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 7 + context->gpr[11];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_1000_M_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8 + context->gpr[11];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_1001_M_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 9 + context->gpr[11];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_1010_M_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 10 + context->gpr[11];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_1011_M_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 11 + context->gpr[11];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_1100_M_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12 + context->gpr[11];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_1101_M_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 13 + context->gpr[11];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_1110_M_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 14 + context->gpr[11];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_1111_M_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 15 + context->gpr[11];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_0000_M_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0 + context->gpr[12];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_0001_M_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 1 + context->gpr[12];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_0010_M_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 2 + context->gpr[12];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_0011_M_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 3 + context->gpr[12];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_0100_M_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4 + context->gpr[12];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_0101_M_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 5 + context->gpr[12];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_0110_M_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 6 + context->gpr[12];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_0111_M_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 7 + context->gpr[12];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_1000_M_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8 + context->gpr[12];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_1001_M_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 9 + context->gpr[12];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_1010_M_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 10 + context->gpr[12];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_1011_M_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 11 + context->gpr[12];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_1100_M_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12 + context->gpr[12];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_1101_M_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 13 + context->gpr[12];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_1110_M_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 14 + context->gpr[12];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_1111_M_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 15 + context->gpr[12];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_0000_M_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0 + context->gpr[13];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_0001_M_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 1 + context->gpr[13];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_0010_M_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 2 + context->gpr[13];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_0011_M_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 3 + context->gpr[13];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_0100_M_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4 + context->gpr[13];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_0101_M_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 5 + context->gpr[13];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_0110_M_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 6 + context->gpr[13];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_0111_M_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 7 + context->gpr[13];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_1000_M_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8 + context->gpr[13];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_1001_M_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 9 + context->gpr[13];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_1010_M_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 10 + context->gpr[13];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_1011_M_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 11 + context->gpr[13];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_1100_M_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12 + context->gpr[13];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_1101_M_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 13 + context->gpr[13];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_1110_M_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 14 + context->gpr[13];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_1111_M_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 15 + context->gpr[13];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_0000_M_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0 + context->gpr[14];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_0001_M_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 1 + context->gpr[14];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_0010_M_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 2 + context->gpr[14];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_0011_M_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 3 + context->gpr[14];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_0100_M_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4 + context->gpr[14];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_0101_M_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 5 + context->gpr[14];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_0110_M_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 6 + context->gpr[14];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_0111_M_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 7 + context->gpr[14];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_1000_M_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8 + context->gpr[14];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_1001_M_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 9 + context->gpr[14];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_1010_M_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 10 + context->gpr[14];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_1011_M_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 11 + context->gpr[14];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_1100_M_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12 + context->gpr[14];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_1101_M_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 13 + context->gpr[14];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_1110_M_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 14 + context->gpr[14];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_1111_M_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 15 + context->gpr[14];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_0000_M_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0 + context->gpr[15];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_0001_M_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 1 + context->gpr[15];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_0010_M_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 2 + context->gpr[15];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_0011_M_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 3 + context->gpr[15];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_0100_M_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4 + context->gpr[15];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_0101_M_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 5 + context->gpr[15];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_0110_M_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 6 + context->gpr[15];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_0111_M_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 7 + context->gpr[15];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_1000_M_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8 + context->gpr[15];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_1001_M_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 9 + context->gpr[15];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_1010_M_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 10 + context->gpr[15];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_1011_M_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 11 + context->gpr[15];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_1100_M_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12 + context->gpr[15];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_1101_M_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 13 + context->gpr[15];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_1110_M_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 14 + context->gpr[15];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_b_D_1111_M_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 15 + context->gpr[15];
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_0000_M_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[0] + 0;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_0001_M_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 2;
	context->scratch1 = context->gpr[0] + 2;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_0010_M_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[0] + 4;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_0011_M_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 6;
	context->scratch1 = context->gpr[0] + 6;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_0100_M_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[0] + 8;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_0101_M_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 10;
	context->scratch1 = context->gpr[0] + 10;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_0110_M_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[0] + 12;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_0111_M_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 14;
	context->scratch1 = context->gpr[0] + 14;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_1000_M_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[0] + 16;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_1001_M_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 18;
	context->scratch1 = context->gpr[0] + 18;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_1010_M_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[0] + 20;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_1011_M_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 22;
	context->scratch1 = context->gpr[0] + 22;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_1100_M_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[0] + 24;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_1101_M_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 26;
	context->scratch1 = context->gpr[0] + 26;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_1110_M_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[0] + 28;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_1111_M_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 30;
	context->scratch1 = context->gpr[0] + 30;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_0000_M_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[1] + 0;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_0001_M_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 2;
	context->scratch1 = context->gpr[1] + 2;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_0010_M_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[1] + 4;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_0011_M_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 6;
	context->scratch1 = context->gpr[1] + 6;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_0100_M_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[1] + 8;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_0101_M_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 10;
	context->scratch1 = context->gpr[1] + 10;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_0110_M_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[1] + 12;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_0111_M_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 14;
	context->scratch1 = context->gpr[1] + 14;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_1000_M_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[1] + 16;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_1001_M_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 18;
	context->scratch1 = context->gpr[1] + 18;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_1010_M_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[1] + 20;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_1011_M_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 22;
	context->scratch1 = context->gpr[1] + 22;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_1100_M_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[1] + 24;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_1101_M_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 26;
	context->scratch1 = context->gpr[1] + 26;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_1110_M_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[1] + 28;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_1111_M_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 30;
	context->scratch1 = context->gpr[1] + 30;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_0000_M_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[2] + 0;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_0001_M_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 2;
	context->scratch1 = context->gpr[2] + 2;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_0010_M_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[2] + 4;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_0011_M_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 6;
	context->scratch1 = context->gpr[2] + 6;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_0100_M_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[2] + 8;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_0101_M_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 10;
	context->scratch1 = context->gpr[2] + 10;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_0110_M_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[2] + 12;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_0111_M_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 14;
	context->scratch1 = context->gpr[2] + 14;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_1000_M_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[2] + 16;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_1001_M_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 18;
	context->scratch1 = context->gpr[2] + 18;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_1010_M_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[2] + 20;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_1011_M_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 22;
	context->scratch1 = context->gpr[2] + 22;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_1100_M_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[2] + 24;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_1101_M_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 26;
	context->scratch1 = context->gpr[2] + 26;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_1110_M_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[2] + 28;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_1111_M_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 30;
	context->scratch1 = context->gpr[2] + 30;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_0000_M_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[3] + 0;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_0001_M_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 2;
	context->scratch1 = context->gpr[3] + 2;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_0010_M_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[3] + 4;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_0011_M_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 6;
	context->scratch1 = context->gpr[3] + 6;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_0100_M_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[3] + 8;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_0101_M_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 10;
	context->scratch1 = context->gpr[3] + 10;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_0110_M_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[3] + 12;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_0111_M_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 14;
	context->scratch1 = context->gpr[3] + 14;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_1000_M_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[3] + 16;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_1001_M_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 18;
	context->scratch1 = context->gpr[3] + 18;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_1010_M_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[3] + 20;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_1011_M_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 22;
	context->scratch1 = context->gpr[3] + 22;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_1100_M_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[3] + 24;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_1101_M_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 26;
	context->scratch1 = context->gpr[3] + 26;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_1110_M_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[3] + 28;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_1111_M_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 30;
	context->scratch1 = context->gpr[3] + 30;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_0000_M_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[4] + 0;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_0001_M_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 2;
	context->scratch1 = context->gpr[4] + 2;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_0010_M_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[4] + 4;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_0011_M_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 6;
	context->scratch1 = context->gpr[4] + 6;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_0100_M_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[4] + 8;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_0101_M_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 10;
	context->scratch1 = context->gpr[4] + 10;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_0110_M_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[4] + 12;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_0111_M_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 14;
	context->scratch1 = context->gpr[4] + 14;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_1000_M_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[4] + 16;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_1001_M_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 18;
	context->scratch1 = context->gpr[4] + 18;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_1010_M_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[4] + 20;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_1011_M_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 22;
	context->scratch1 = context->gpr[4] + 22;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_1100_M_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[4] + 24;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_1101_M_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 26;
	context->scratch1 = context->gpr[4] + 26;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_1110_M_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[4] + 28;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_1111_M_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 30;
	context->scratch1 = context->gpr[4] + 30;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_0000_M_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[5] + 0;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_0001_M_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 2;
	context->scratch1 = context->gpr[5] + 2;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_0010_M_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[5] + 4;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_0011_M_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 6;
	context->scratch1 = context->gpr[5] + 6;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_0100_M_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[5] + 8;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_0101_M_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 10;
	context->scratch1 = context->gpr[5] + 10;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_0110_M_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[5] + 12;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_0111_M_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 14;
	context->scratch1 = context->gpr[5] + 14;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_1000_M_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[5] + 16;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_1001_M_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 18;
	context->scratch1 = context->gpr[5] + 18;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_1010_M_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[5] + 20;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_1011_M_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 22;
	context->scratch1 = context->gpr[5] + 22;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_1100_M_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[5] + 24;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_1101_M_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 26;
	context->scratch1 = context->gpr[5] + 26;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_1110_M_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[5] + 28;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_1111_M_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 30;
	context->scratch1 = context->gpr[5] + 30;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_0000_M_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[6] + 0;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_0001_M_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 2;
	context->scratch1 = context->gpr[6] + 2;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_0010_M_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[6] + 4;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_0011_M_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 6;
	context->scratch1 = context->gpr[6] + 6;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_0100_M_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[6] + 8;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_0101_M_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 10;
	context->scratch1 = context->gpr[6] + 10;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_0110_M_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[6] + 12;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_0111_M_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 14;
	context->scratch1 = context->gpr[6] + 14;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_1000_M_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[6] + 16;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_1001_M_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 18;
	context->scratch1 = context->gpr[6] + 18;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_1010_M_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[6] + 20;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_1011_M_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 22;
	context->scratch1 = context->gpr[6] + 22;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_1100_M_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[6] + 24;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_1101_M_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 26;
	context->scratch1 = context->gpr[6] + 26;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_1110_M_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[6] + 28;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_1111_M_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 30;
	context->scratch1 = context->gpr[6] + 30;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_0000_M_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[7] + 0;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_0001_M_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 2;
	context->scratch1 = context->gpr[7] + 2;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_0010_M_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[7] + 4;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_0011_M_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 6;
	context->scratch1 = context->gpr[7] + 6;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_0100_M_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[7] + 8;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_0101_M_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 10;
	context->scratch1 = context->gpr[7] + 10;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_0110_M_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[7] + 12;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_0111_M_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 14;
	context->scratch1 = context->gpr[7] + 14;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_1000_M_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[7] + 16;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_1001_M_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 18;
	context->scratch1 = context->gpr[7] + 18;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_1010_M_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[7] + 20;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_1011_M_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 22;
	context->scratch1 = context->gpr[7] + 22;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_1100_M_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[7] + 24;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_1101_M_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 26;
	context->scratch1 = context->gpr[7] + 26;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_1110_M_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[7] + 28;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_1111_M_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 30;
	context->scratch1 = context->gpr[7] + 30;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_0000_M_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[8] + 0;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_0001_M_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 2;
	context->scratch1 = context->gpr[8] + 2;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_0010_M_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[8] + 4;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_0011_M_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 6;
	context->scratch1 = context->gpr[8] + 6;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_0100_M_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[8] + 8;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_0101_M_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 10;
	context->scratch1 = context->gpr[8] + 10;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_0110_M_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[8] + 12;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_0111_M_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 14;
	context->scratch1 = context->gpr[8] + 14;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_1000_M_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[8] + 16;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_1001_M_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 18;
	context->scratch1 = context->gpr[8] + 18;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_1010_M_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[8] + 20;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_1011_M_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 22;
	context->scratch1 = context->gpr[8] + 22;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_1100_M_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[8] + 24;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_1101_M_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 26;
	context->scratch1 = context->gpr[8] + 26;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_1110_M_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[8] + 28;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_1111_M_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 30;
	context->scratch1 = context->gpr[8] + 30;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_0000_M_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[9] + 0;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_0001_M_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 2;
	context->scratch1 = context->gpr[9] + 2;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_0010_M_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[9] + 4;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_0011_M_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 6;
	context->scratch1 = context->gpr[9] + 6;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_0100_M_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[9] + 8;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_0101_M_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 10;
	context->scratch1 = context->gpr[9] + 10;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_0110_M_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[9] + 12;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_0111_M_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 14;
	context->scratch1 = context->gpr[9] + 14;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_1000_M_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[9] + 16;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_1001_M_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 18;
	context->scratch1 = context->gpr[9] + 18;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_1010_M_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[9] + 20;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_1011_M_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 22;
	context->scratch1 = context->gpr[9] + 22;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_1100_M_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[9] + 24;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_1101_M_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 26;
	context->scratch1 = context->gpr[9] + 26;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_1110_M_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[9] + 28;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_1111_M_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 30;
	context->scratch1 = context->gpr[9] + 30;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_0000_M_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[10] + 0;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_0001_M_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 2;
	context->scratch1 = context->gpr[10] + 2;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_0010_M_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[10] + 4;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_0011_M_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 6;
	context->scratch1 = context->gpr[10] + 6;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_0100_M_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[10] + 8;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_0101_M_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 10;
	context->scratch1 = context->gpr[10] + 10;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_0110_M_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[10] + 12;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_0111_M_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 14;
	context->scratch1 = context->gpr[10] + 14;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_1000_M_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[10] + 16;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_1001_M_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 18;
	context->scratch1 = context->gpr[10] + 18;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_1010_M_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[10] + 20;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_1011_M_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 22;
	context->scratch1 = context->gpr[10] + 22;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_1100_M_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[10] + 24;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_1101_M_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 26;
	context->scratch1 = context->gpr[10] + 26;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_1110_M_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[10] + 28;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_1111_M_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 30;
	context->scratch1 = context->gpr[10] + 30;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_0000_M_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[11] + 0;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_0001_M_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 2;
	context->scratch1 = context->gpr[11] + 2;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_0010_M_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[11] + 4;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_0011_M_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 6;
	context->scratch1 = context->gpr[11] + 6;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_0100_M_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[11] + 8;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_0101_M_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 10;
	context->scratch1 = context->gpr[11] + 10;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_0110_M_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[11] + 12;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_0111_M_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 14;
	context->scratch1 = context->gpr[11] + 14;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_1000_M_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[11] + 16;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_1001_M_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 18;
	context->scratch1 = context->gpr[11] + 18;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_1010_M_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[11] + 20;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_1011_M_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 22;
	context->scratch1 = context->gpr[11] + 22;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_1100_M_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[11] + 24;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_1101_M_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 26;
	context->scratch1 = context->gpr[11] + 26;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_1110_M_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[11] + 28;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_1111_M_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 30;
	context->scratch1 = context->gpr[11] + 30;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_0000_M_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[12] + 0;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_0001_M_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 2;
	context->scratch1 = context->gpr[12] + 2;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_0010_M_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[12] + 4;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_0011_M_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 6;
	context->scratch1 = context->gpr[12] + 6;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_0100_M_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[12] + 8;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_0101_M_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 10;
	context->scratch1 = context->gpr[12] + 10;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_0110_M_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[12] + 12;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_0111_M_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 14;
	context->scratch1 = context->gpr[12] + 14;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_1000_M_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[12] + 16;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_1001_M_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 18;
	context->scratch1 = context->gpr[12] + 18;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_1010_M_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[12] + 20;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_1011_M_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 22;
	context->scratch1 = context->gpr[12] + 22;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_1100_M_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[12] + 24;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_1101_M_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 26;
	context->scratch1 = context->gpr[12] + 26;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_1110_M_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[12] + 28;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_1111_M_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 30;
	context->scratch1 = context->gpr[12] + 30;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_0000_M_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[13] + 0;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_0001_M_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 2;
	context->scratch1 = context->gpr[13] + 2;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_0010_M_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[13] + 4;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_0011_M_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 6;
	context->scratch1 = context->gpr[13] + 6;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_0100_M_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[13] + 8;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_0101_M_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 10;
	context->scratch1 = context->gpr[13] + 10;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_0110_M_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[13] + 12;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_0111_M_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 14;
	context->scratch1 = context->gpr[13] + 14;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_1000_M_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[13] + 16;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_1001_M_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 18;
	context->scratch1 = context->gpr[13] + 18;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_1010_M_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[13] + 20;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_1011_M_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 22;
	context->scratch1 = context->gpr[13] + 22;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_1100_M_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[13] + 24;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_1101_M_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 26;
	context->scratch1 = context->gpr[13] + 26;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_1110_M_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[13] + 28;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_1111_M_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 30;
	context->scratch1 = context->gpr[13] + 30;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_0000_M_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[14] + 0;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_0001_M_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 2;
	context->scratch1 = context->gpr[14] + 2;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_0010_M_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[14] + 4;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_0011_M_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 6;
	context->scratch1 = context->gpr[14] + 6;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_0100_M_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[14] + 8;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_0101_M_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 10;
	context->scratch1 = context->gpr[14] + 10;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_0110_M_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[14] + 12;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_0111_M_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 14;
	context->scratch1 = context->gpr[14] + 14;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_1000_M_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[14] + 16;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_1001_M_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 18;
	context->scratch1 = context->gpr[14] + 18;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_1010_M_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[14] + 20;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_1011_M_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 22;
	context->scratch1 = context->gpr[14] + 22;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_1100_M_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[14] + 24;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_1101_M_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 26;
	context->scratch1 = context->gpr[14] + 26;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_1110_M_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[14] + 28;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_1111_M_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 30;
	context->scratch1 = context->gpr[14] + 30;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_0000_M_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 0;
	context->scratch1 = context->gpr[15] + 0;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_0001_M_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 2;
	context->scratch1 = context->gpr[15] + 2;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_0010_M_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 4;
	context->scratch1 = context->gpr[15] + 4;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_0011_M_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 6;
	context->scratch1 = context->gpr[15] + 6;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_0100_M_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 8;
	context->scratch1 = context->gpr[15] + 8;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_0101_M_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 10;
	context->scratch1 = context->gpr[15] + 10;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_0110_M_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 12;
	context->scratch1 = context->gpr[15] + 12;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_0111_M_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 14;
	context->scratch1 = context->gpr[15] + 14;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_1000_M_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 16;
	context->scratch1 = context->gpr[15] + 16;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_1001_M_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 18;
	context->scratch1 = context->gpr[15] + 18;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_1010_M_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 20;
	context->scratch1 = context->gpr[15] + 20;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_1011_M_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 22;
	context->scratch1 = context->gpr[15] + 22;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_1100_M_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 24;
	context->scratch1 = context->gpr[15] + 24;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_1101_M_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 26;
	context->scratch1 = context->gpr[15] + 26;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_1110_M_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 28;
	context->scratch1 = context->gpr[15] + 28;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_rm_r0_w_D_1111_M_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = 30;
	context->scratch1 = context->gpr[15] + 30;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void cmpeq_imm_r0(sh2_context *context, uint32_t target_cycle)
{
	uint32_t cmp_tmp32__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t imm;
	uint16_t I = context->prefetch_cur & 255;
	context->cycles += context->opts->gen.clock_divider * 1;
	imm = (imm & ~65535) | ((I & 255) & 128 ? (I & 255) | 65280 : (I & 255));
	imm = (imm & 65535) & 32768 ? (imm & 65535) | 4294901760 : (imm & 65535);
	cmp_tmp32__ = context->gpr[0] - imm;
	context->t = cmp_tmp32__ == 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_00000000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (0 & 128 ? 0 | 65280 : 0);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_00000001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (1 & 128 ? 1 | 65280 : 1);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_00000010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (2 & 128 ? 2 | 65280 : 2);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_00000011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (3 & 128 ? 3 | 65280 : 3);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_00000100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (4 & 128 ? 4 | 65280 : 4);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_00000101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (5 & 128 ? 5 | 65280 : 5);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_00000110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (6 & 128 ? 6 | 65280 : 6);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_00000111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (7 & 128 ? 7 | 65280 : 7);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_00001000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (8 & 128 ? 8 | 65280 : 8);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_00001001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (9 & 128 ? 9 | 65280 : 9);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_00001010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (10 & 128 ? 10 | 65280 : 10);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_00001011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (11 & 128 ? 11 | 65280 : 11);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_00001100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (12 & 128 ? 12 | 65280 : 12);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_00001101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (13 & 128 ? 13 | 65280 : 13);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_00001110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (14 & 128 ? 14 | 65280 : 14);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_00001111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (15 & 128 ? 15 | 65280 : 15);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_00010000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (16 & 128 ? 16 | 65280 : 16);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_00010001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (17 & 128 ? 17 | 65280 : 17);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_00010010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (18 & 128 ? 18 | 65280 : 18);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_00010011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (19 & 128 ? 19 | 65280 : 19);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_00010100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (20 & 128 ? 20 | 65280 : 20);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_00010101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (21 & 128 ? 21 | 65280 : 21);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_00010110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (22 & 128 ? 22 | 65280 : 22);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_00010111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (23 & 128 ? 23 | 65280 : 23);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_00011000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (24 & 128 ? 24 | 65280 : 24);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_00011001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (25 & 128 ? 25 | 65280 : 25);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_00011010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (26 & 128 ? 26 | 65280 : 26);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_00011011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (27 & 128 ? 27 | 65280 : 27);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_00011100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (28 & 128 ? 28 | 65280 : 28);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_00011101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (29 & 128 ? 29 | 65280 : 29);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_00011110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (30 & 128 ? 30 | 65280 : 30);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_00011111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (31 & 128 ? 31 | 65280 : 31);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_00100000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (32 & 128 ? 32 | 65280 : 32);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_00100001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (33 & 128 ? 33 | 65280 : 33);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_00100010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (34 & 128 ? 34 | 65280 : 34);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_00100011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (35 & 128 ? 35 | 65280 : 35);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_00100100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (36 & 128 ? 36 | 65280 : 36);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_00100101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (37 & 128 ? 37 | 65280 : 37);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_00100110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (38 & 128 ? 38 | 65280 : 38);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_00100111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (39 & 128 ? 39 | 65280 : 39);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_00101000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (40 & 128 ? 40 | 65280 : 40);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_00101001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (41 & 128 ? 41 | 65280 : 41);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_00101010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (42 & 128 ? 42 | 65280 : 42);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_00101011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (43 & 128 ? 43 | 65280 : 43);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_00101100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (44 & 128 ? 44 | 65280 : 44);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_00101101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (45 & 128 ? 45 | 65280 : 45);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_00101110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (46 & 128 ? 46 | 65280 : 46);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_00101111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (47 & 128 ? 47 | 65280 : 47);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_00110000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (48 & 128 ? 48 | 65280 : 48);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_00110001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (49 & 128 ? 49 | 65280 : 49);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_00110010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (50 & 128 ? 50 | 65280 : 50);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_00110011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (51 & 128 ? 51 | 65280 : 51);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_00110100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (52 & 128 ? 52 | 65280 : 52);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_00110101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (53 & 128 ? 53 | 65280 : 53);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_00110110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (54 & 128 ? 54 | 65280 : 54);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_00110111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (55 & 128 ? 55 | 65280 : 55);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_00111000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (56 & 128 ? 56 | 65280 : 56);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_00111001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (57 & 128 ? 57 | 65280 : 57);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_00111010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (58 & 128 ? 58 | 65280 : 58);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_00111011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (59 & 128 ? 59 | 65280 : 59);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_00111100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (60 & 128 ? 60 | 65280 : 60);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_00111101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (61 & 128 ? 61 | 65280 : 61);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_00111110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (62 & 128 ? 62 | 65280 : 62);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_00111111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (63 & 128 ? 63 | 65280 : 63);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_01000000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (64 & 128 ? 64 | 65280 : 64);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_01000001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (65 & 128 ? 65 | 65280 : 65);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_01000010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (66 & 128 ? 66 | 65280 : 66);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_01000011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (67 & 128 ? 67 | 65280 : 67);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_01000100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (68 & 128 ? 68 | 65280 : 68);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_01000101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (69 & 128 ? 69 | 65280 : 69);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_01000110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (70 & 128 ? 70 | 65280 : 70);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_01000111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (71 & 128 ? 71 | 65280 : 71);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_01001000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (72 & 128 ? 72 | 65280 : 72);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_01001001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (73 & 128 ? 73 | 65280 : 73);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_01001010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (74 & 128 ? 74 | 65280 : 74);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_01001011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (75 & 128 ? 75 | 65280 : 75);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_01001100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (76 & 128 ? 76 | 65280 : 76);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_01001101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (77 & 128 ? 77 | 65280 : 77);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_01001110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (78 & 128 ? 78 | 65280 : 78);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_01001111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (79 & 128 ? 79 | 65280 : 79);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_01010000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (80 & 128 ? 80 | 65280 : 80);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_01010001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (81 & 128 ? 81 | 65280 : 81);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_01010010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (82 & 128 ? 82 | 65280 : 82);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_01010011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (83 & 128 ? 83 | 65280 : 83);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_01010100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (84 & 128 ? 84 | 65280 : 84);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_01010101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (85 & 128 ? 85 | 65280 : 85);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_01010110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (86 & 128 ? 86 | 65280 : 86);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_01010111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (87 & 128 ? 87 | 65280 : 87);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_01011000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (88 & 128 ? 88 | 65280 : 88);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_01011001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (89 & 128 ? 89 | 65280 : 89);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_01011010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (90 & 128 ? 90 | 65280 : 90);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_01011011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (91 & 128 ? 91 | 65280 : 91);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_01011100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (92 & 128 ? 92 | 65280 : 92);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_01011101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (93 & 128 ? 93 | 65280 : 93);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_01011110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (94 & 128 ? 94 | 65280 : 94);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_01011111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (95 & 128 ? 95 | 65280 : 95);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_01100000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (96 & 128 ? 96 | 65280 : 96);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_01100001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (97 & 128 ? 97 | 65280 : 97);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_01100010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (98 & 128 ? 98 | 65280 : 98);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_01100011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (99 & 128 ? 99 | 65280 : 99);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_01100100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (100 & 128 ? 100 | 65280 : 100);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_01100101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (101 & 128 ? 101 | 65280 : 101);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_01100110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (102 & 128 ? 102 | 65280 : 102);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_01100111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (103 & 128 ? 103 | 65280 : 103);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_01101000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (104 & 128 ? 104 | 65280 : 104);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_01101001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (105 & 128 ? 105 | 65280 : 105);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_01101010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (106 & 128 ? 106 | 65280 : 106);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_01101011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (107 & 128 ? 107 | 65280 : 107);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_01101100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (108 & 128 ? 108 | 65280 : 108);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_01101101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (109 & 128 ? 109 | 65280 : 109);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_01101110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (110 & 128 ? 110 | 65280 : 110);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_01101111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (111 & 128 ? 111 | 65280 : 111);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_01110000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (112 & 128 ? 112 | 65280 : 112);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_01110001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (113 & 128 ? 113 | 65280 : 113);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_01110010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (114 & 128 ? 114 | 65280 : 114);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_01110011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (115 & 128 ? 115 | 65280 : 115);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_01110100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (116 & 128 ? 116 | 65280 : 116);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_01110101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (117 & 128 ? 117 | 65280 : 117);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_01110110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (118 & 128 ? 118 | 65280 : 118);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_01110111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (119 & 128 ? 119 | 65280 : 119);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_01111000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (120 & 128 ? 120 | 65280 : 120);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_01111001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (121 & 128 ? 121 | 65280 : 121);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_01111010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (122 & 128 ? 122 | 65280 : 122);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_01111011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (123 & 128 ? 123 | 65280 : 123);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_01111100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (124 & 128 ? 124 | 65280 : 124);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_01111101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (125 & 128 ? 125 | 65280 : 125);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_01111110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (126 & 128 ? 126 | 65280 : 126);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_01111111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (127 & 128 ? 127 | 65280 : 127);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_10000000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (128 & 128 ? 128 | 65280 : 128);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_10000001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (129 & 128 ? 129 | 65280 : 129);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_10000010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (130 & 128 ? 130 | 65280 : 130);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_10000011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (131 & 128 ? 131 | 65280 : 131);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_10000100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (132 & 128 ? 132 | 65280 : 132);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_10000101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (133 & 128 ? 133 | 65280 : 133);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_10000110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (134 & 128 ? 134 | 65280 : 134);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_10000111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (135 & 128 ? 135 | 65280 : 135);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_10001000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (136 & 128 ? 136 | 65280 : 136);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_10001001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (137 & 128 ? 137 | 65280 : 137);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_10001010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (138 & 128 ? 138 | 65280 : 138);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_10001011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (139 & 128 ? 139 | 65280 : 139);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_10001100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (140 & 128 ? 140 | 65280 : 140);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_10001101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (141 & 128 ? 141 | 65280 : 141);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_10001110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (142 & 128 ? 142 | 65280 : 142);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_10001111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (143 & 128 ? 143 | 65280 : 143);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_10010000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (144 & 128 ? 144 | 65280 : 144);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_10010001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (145 & 128 ? 145 | 65280 : 145);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_10010010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (146 & 128 ? 146 | 65280 : 146);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_10010011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (147 & 128 ? 147 | 65280 : 147);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_10010100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (148 & 128 ? 148 | 65280 : 148);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_10010101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (149 & 128 ? 149 | 65280 : 149);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_10010110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (150 & 128 ? 150 | 65280 : 150);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_10010111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (151 & 128 ? 151 | 65280 : 151);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_10011000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (152 & 128 ? 152 | 65280 : 152);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_10011001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (153 & 128 ? 153 | 65280 : 153);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_10011010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (154 & 128 ? 154 | 65280 : 154);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_10011011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (155 & 128 ? 155 | 65280 : 155);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_10011100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (156 & 128 ? 156 | 65280 : 156);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_10011101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (157 & 128 ? 157 | 65280 : 157);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_10011110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (158 & 128 ? 158 | 65280 : 158);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_10011111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (159 & 128 ? 159 | 65280 : 159);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_10100000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (160 & 128 ? 160 | 65280 : 160);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_10100001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (161 & 128 ? 161 | 65280 : 161);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_10100010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (162 & 128 ? 162 | 65280 : 162);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_10100011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (163 & 128 ? 163 | 65280 : 163);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_10100100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (164 & 128 ? 164 | 65280 : 164);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_10100101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (165 & 128 ? 165 | 65280 : 165);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_10100110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (166 & 128 ? 166 | 65280 : 166);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_10100111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (167 & 128 ? 167 | 65280 : 167);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_10101000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (168 & 128 ? 168 | 65280 : 168);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_10101001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (169 & 128 ? 169 | 65280 : 169);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_10101010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (170 & 128 ? 170 | 65280 : 170);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_10101011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (171 & 128 ? 171 | 65280 : 171);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_10101100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (172 & 128 ? 172 | 65280 : 172);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_10101101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (173 & 128 ? 173 | 65280 : 173);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_10101110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (174 & 128 ? 174 | 65280 : 174);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_10101111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (175 & 128 ? 175 | 65280 : 175);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_10110000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (176 & 128 ? 176 | 65280 : 176);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_10110001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (177 & 128 ? 177 | 65280 : 177);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_10110010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (178 & 128 ? 178 | 65280 : 178);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_10110011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (179 & 128 ? 179 | 65280 : 179);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_10110100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (180 & 128 ? 180 | 65280 : 180);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_10110101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (181 & 128 ? 181 | 65280 : 181);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_10110110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (182 & 128 ? 182 | 65280 : 182);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_10110111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (183 & 128 ? 183 | 65280 : 183);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_10111000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (184 & 128 ? 184 | 65280 : 184);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_10111001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (185 & 128 ? 185 | 65280 : 185);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_10111010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (186 & 128 ? 186 | 65280 : 186);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_10111011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (187 & 128 ? 187 | 65280 : 187);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_10111100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (188 & 128 ? 188 | 65280 : 188);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_10111101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (189 & 128 ? 189 | 65280 : 189);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_10111110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (190 & 128 ? 190 | 65280 : 190);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_10111111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (191 & 128 ? 191 | 65280 : 191);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_11000000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (192 & 128 ? 192 | 65280 : 192);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_11000001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (193 & 128 ? 193 | 65280 : 193);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_11000010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (194 & 128 ? 194 | 65280 : 194);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_11000011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (195 & 128 ? 195 | 65280 : 195);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_11000100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (196 & 128 ? 196 | 65280 : 196);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_11000101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (197 & 128 ? 197 | 65280 : 197);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_11000110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (198 & 128 ? 198 | 65280 : 198);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_11000111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (199 & 128 ? 199 | 65280 : 199);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_11001000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (200 & 128 ? 200 | 65280 : 200);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_11001001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (201 & 128 ? 201 | 65280 : 201);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_11001010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (202 & 128 ? 202 | 65280 : 202);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_11001011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (203 & 128 ? 203 | 65280 : 203);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_11001100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (204 & 128 ? 204 | 65280 : 204);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_11001101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (205 & 128 ? 205 | 65280 : 205);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_11001110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (206 & 128 ? 206 | 65280 : 206);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_11001111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (207 & 128 ? 207 | 65280 : 207);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_11010000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (208 & 128 ? 208 | 65280 : 208);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_11010001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (209 & 128 ? 209 | 65280 : 209);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_11010010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (210 & 128 ? 210 | 65280 : 210);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_11010011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (211 & 128 ? 211 | 65280 : 211);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_11010100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (212 & 128 ? 212 | 65280 : 212);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_11010101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (213 & 128 ? 213 | 65280 : 213);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_11010110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (214 & 128 ? 214 | 65280 : 214);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_11010111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (215 & 128 ? 215 | 65280 : 215);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_11011000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (216 & 128 ? 216 | 65280 : 216);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_11011001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (217 & 128 ? 217 | 65280 : 217);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_11011010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (218 & 128 ? 218 | 65280 : 218);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_11011011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (219 & 128 ? 219 | 65280 : 219);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_11011100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (220 & 128 ? 220 | 65280 : 220);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_11011101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (221 & 128 ? 221 | 65280 : 221);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_11011110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (222 & 128 ? 222 | 65280 : 222);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_11011111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (223 & 128 ? 223 | 65280 : 223);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_11100000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (224 & 128 ? 224 | 65280 : 224);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_11100001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (225 & 128 ? 225 | 65280 : 225);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_11100010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (226 & 128 ? 226 | 65280 : 226);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_11100011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (227 & 128 ? 227 | 65280 : 227);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_11100100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (228 & 128 ? 228 | 65280 : 228);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_11100101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (229 & 128 ? 229 | 65280 : 229);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_11100110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (230 & 128 ? 230 | 65280 : 230);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_11100111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (231 & 128 ? 231 | 65280 : 231);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_11101000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (232 & 128 ? 232 | 65280 : 232);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_11101001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (233 & 128 ? 233 | 65280 : 233);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_11101010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (234 & 128 ? 234 | 65280 : 234);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_11101011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (235 & 128 ? 235 | 65280 : 235);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_11101100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (236 & 128 ? 236 | 65280 : 236);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_11101101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (237 & 128 ? 237 | 65280 : 237);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_11101110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (238 & 128 ? 238 | 65280 : 238);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_11101111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (239 & 128 ? 239 | 65280 : 239);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_11110000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (240 & 128 ? 240 | 65280 : 240);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_11110001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (241 & 128 ? 241 | 65280 : 241);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_11110010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (242 & 128 ? 242 | 65280 : 242);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_11110011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (243 & 128 ? 243 | 65280 : 243);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_11110100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (244 & 128 ? 244 | 65280 : 244);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_11110101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (245 & 128 ? 245 | 65280 : 245);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_11110110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (246 & 128 ? 246 | 65280 : 246);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_11110111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (247 & 128 ? 247 | 65280 : 247);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_11111000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (248 & 128 ? 248 | 65280 : 248);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_11111001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (249 & 128 ? 249 | 65280 : 249);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_11111010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (250 & 128 ? 250 | 65280 : 250);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_11111011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (251 & 128 ? 251 | 65280 : 251);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_11111100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (252 & 128 ? 252 | 65280 : 252);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_11111101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (253 & 128 ? 253 | 65280 : 253);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_11111110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (254 & 128 ? 254 | 65280 : 254);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_D_11111111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (255 & 128 ? 255 | 65280 : 255);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_00000000(sh2_context *context, uint32_t target_cycle)
{
	uint8_t cmp_tmp8__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (0 & 128 ? 0 | 65280 : 0);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_00000001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (1 & 128 ? 1 | 65280 : 1);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_00000010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (2 & 128 ? 2 | 65280 : 2);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_00000011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (3 & 128 ? 3 | 65280 : 3);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_00000100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (4 & 128 ? 4 | 65280 : 4);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_00000101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (5 & 128 ? 5 | 65280 : 5);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_00000110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (6 & 128 ? 6 | 65280 : 6);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_00000111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (7 & 128 ? 7 | 65280 : 7);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_00001000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (8 & 128 ? 8 | 65280 : 8);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_00001001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (9 & 128 ? 9 | 65280 : 9);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_00001010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (10 & 128 ? 10 | 65280 : 10);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_00001011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (11 & 128 ? 11 | 65280 : 11);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_00001100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (12 & 128 ? 12 | 65280 : 12);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_00001101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (13 & 128 ? 13 | 65280 : 13);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_00001110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (14 & 128 ? 14 | 65280 : 14);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_00001111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (15 & 128 ? 15 | 65280 : 15);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_00010000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (16 & 128 ? 16 | 65280 : 16);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_00010001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (17 & 128 ? 17 | 65280 : 17);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_00010010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (18 & 128 ? 18 | 65280 : 18);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_00010011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (19 & 128 ? 19 | 65280 : 19);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_00010100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (20 & 128 ? 20 | 65280 : 20);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_00010101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (21 & 128 ? 21 | 65280 : 21);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_00010110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (22 & 128 ? 22 | 65280 : 22);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_00010111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (23 & 128 ? 23 | 65280 : 23);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_00011000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (24 & 128 ? 24 | 65280 : 24);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_00011001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (25 & 128 ? 25 | 65280 : 25);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_00011010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (26 & 128 ? 26 | 65280 : 26);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_00011011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (27 & 128 ? 27 | 65280 : 27);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_00011100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (28 & 128 ? 28 | 65280 : 28);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_00011101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (29 & 128 ? 29 | 65280 : 29);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_00011110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (30 & 128 ? 30 | 65280 : 30);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_00011111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (31 & 128 ? 31 | 65280 : 31);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_00100000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (32 & 128 ? 32 | 65280 : 32);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_00100001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (33 & 128 ? 33 | 65280 : 33);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_00100010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (34 & 128 ? 34 | 65280 : 34);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_00100011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (35 & 128 ? 35 | 65280 : 35);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_00100100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (36 & 128 ? 36 | 65280 : 36);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_00100101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (37 & 128 ? 37 | 65280 : 37);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_00100110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (38 & 128 ? 38 | 65280 : 38);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_00100111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (39 & 128 ? 39 | 65280 : 39);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_00101000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (40 & 128 ? 40 | 65280 : 40);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_00101001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (41 & 128 ? 41 | 65280 : 41);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_00101010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (42 & 128 ? 42 | 65280 : 42);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_00101011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (43 & 128 ? 43 | 65280 : 43);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_00101100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (44 & 128 ? 44 | 65280 : 44);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_00101101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (45 & 128 ? 45 | 65280 : 45);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_00101110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (46 & 128 ? 46 | 65280 : 46);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_00101111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (47 & 128 ? 47 | 65280 : 47);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_00110000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (48 & 128 ? 48 | 65280 : 48);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_00110001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (49 & 128 ? 49 | 65280 : 49);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_00110010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (50 & 128 ? 50 | 65280 : 50);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_00110011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (51 & 128 ? 51 | 65280 : 51);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_00110100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (52 & 128 ? 52 | 65280 : 52);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_00110101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (53 & 128 ? 53 | 65280 : 53);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_00110110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (54 & 128 ? 54 | 65280 : 54);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_00110111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (55 & 128 ? 55 | 65280 : 55);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_00111000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (56 & 128 ? 56 | 65280 : 56);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_00111001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (57 & 128 ? 57 | 65280 : 57);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_00111010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (58 & 128 ? 58 | 65280 : 58);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_00111011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (59 & 128 ? 59 | 65280 : 59);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_00111100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (60 & 128 ? 60 | 65280 : 60);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_00111101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (61 & 128 ? 61 | 65280 : 61);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_00111110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (62 & 128 ? 62 | 65280 : 62);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_00111111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (63 & 128 ? 63 | 65280 : 63);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_01000000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (64 & 128 ? 64 | 65280 : 64);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_01000001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (65 & 128 ? 65 | 65280 : 65);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_01000010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (66 & 128 ? 66 | 65280 : 66);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_01000011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (67 & 128 ? 67 | 65280 : 67);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_01000100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (68 & 128 ? 68 | 65280 : 68);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_01000101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (69 & 128 ? 69 | 65280 : 69);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_01000110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (70 & 128 ? 70 | 65280 : 70);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_01000111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (71 & 128 ? 71 | 65280 : 71);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_01001000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (72 & 128 ? 72 | 65280 : 72);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_01001001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (73 & 128 ? 73 | 65280 : 73);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_01001010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (74 & 128 ? 74 | 65280 : 74);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_01001011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (75 & 128 ? 75 | 65280 : 75);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_01001100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (76 & 128 ? 76 | 65280 : 76);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_01001101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (77 & 128 ? 77 | 65280 : 77);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_01001110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (78 & 128 ? 78 | 65280 : 78);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_01001111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (79 & 128 ? 79 | 65280 : 79);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_01010000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (80 & 128 ? 80 | 65280 : 80);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_01010001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (81 & 128 ? 81 | 65280 : 81);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_01010010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (82 & 128 ? 82 | 65280 : 82);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_01010011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (83 & 128 ? 83 | 65280 : 83);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_01010100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (84 & 128 ? 84 | 65280 : 84);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_01010101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (85 & 128 ? 85 | 65280 : 85);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_01010110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (86 & 128 ? 86 | 65280 : 86);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_01010111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (87 & 128 ? 87 | 65280 : 87);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_01011000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (88 & 128 ? 88 | 65280 : 88);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_01011001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (89 & 128 ? 89 | 65280 : 89);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_01011010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (90 & 128 ? 90 | 65280 : 90);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_01011011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (91 & 128 ? 91 | 65280 : 91);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_01011100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (92 & 128 ? 92 | 65280 : 92);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_01011101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (93 & 128 ? 93 | 65280 : 93);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_01011110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (94 & 128 ? 94 | 65280 : 94);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_01011111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (95 & 128 ? 95 | 65280 : 95);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_01100000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (96 & 128 ? 96 | 65280 : 96);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_01100001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (97 & 128 ? 97 | 65280 : 97);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_01100010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (98 & 128 ? 98 | 65280 : 98);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_01100011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (99 & 128 ? 99 | 65280 : 99);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_01100100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (100 & 128 ? 100 | 65280 : 100);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_01100101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (101 & 128 ? 101 | 65280 : 101);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_01100110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (102 & 128 ? 102 | 65280 : 102);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_01100111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (103 & 128 ? 103 | 65280 : 103);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_01101000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (104 & 128 ? 104 | 65280 : 104);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_01101001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (105 & 128 ? 105 | 65280 : 105);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_01101010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (106 & 128 ? 106 | 65280 : 106);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_01101011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (107 & 128 ? 107 | 65280 : 107);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_01101100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (108 & 128 ? 108 | 65280 : 108);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_01101101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (109 & 128 ? 109 | 65280 : 109);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_01101110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (110 & 128 ? 110 | 65280 : 110);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_01101111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (111 & 128 ? 111 | 65280 : 111);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_01110000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (112 & 128 ? 112 | 65280 : 112);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_01110001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (113 & 128 ? 113 | 65280 : 113);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_01110010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (114 & 128 ? 114 | 65280 : 114);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_01110011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (115 & 128 ? 115 | 65280 : 115);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_01110100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (116 & 128 ? 116 | 65280 : 116);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_01110101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (117 & 128 ? 117 | 65280 : 117);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_01110110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (118 & 128 ? 118 | 65280 : 118);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_01110111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (119 & 128 ? 119 | 65280 : 119);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_01111000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (120 & 128 ? 120 | 65280 : 120);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_01111001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (121 & 128 ? 121 | 65280 : 121);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_01111010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (122 & 128 ? 122 | 65280 : 122);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_01111011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (123 & 128 ? 123 | 65280 : 123);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_01111100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (124 & 128 ? 124 | 65280 : 124);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_01111101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (125 & 128 ? 125 | 65280 : 125);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_01111110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (126 & 128 ? 126 | 65280 : 126);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_01111111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (127 & 128 ? 127 | 65280 : 127);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_10000000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (128 & 128 ? 128 | 65280 : 128);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_10000001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (129 & 128 ? 129 | 65280 : 129);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_10000010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (130 & 128 ? 130 | 65280 : 130);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_10000011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (131 & 128 ? 131 | 65280 : 131);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_10000100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (132 & 128 ? 132 | 65280 : 132);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_10000101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (133 & 128 ? 133 | 65280 : 133);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_10000110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (134 & 128 ? 134 | 65280 : 134);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_10000111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (135 & 128 ? 135 | 65280 : 135);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_10001000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (136 & 128 ? 136 | 65280 : 136);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_10001001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (137 & 128 ? 137 | 65280 : 137);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_10001010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (138 & 128 ? 138 | 65280 : 138);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_10001011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (139 & 128 ? 139 | 65280 : 139);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_10001100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (140 & 128 ? 140 | 65280 : 140);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_10001101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (141 & 128 ? 141 | 65280 : 141);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_10001110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (142 & 128 ? 142 | 65280 : 142);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_10001111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (143 & 128 ? 143 | 65280 : 143);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_10010000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (144 & 128 ? 144 | 65280 : 144);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_10010001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (145 & 128 ? 145 | 65280 : 145);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_10010010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (146 & 128 ? 146 | 65280 : 146);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_10010011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (147 & 128 ? 147 | 65280 : 147);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_10010100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (148 & 128 ? 148 | 65280 : 148);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_10010101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (149 & 128 ? 149 | 65280 : 149);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_10010110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (150 & 128 ? 150 | 65280 : 150);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_10010111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (151 & 128 ? 151 | 65280 : 151);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_10011000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (152 & 128 ? 152 | 65280 : 152);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_10011001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (153 & 128 ? 153 | 65280 : 153);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_10011010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (154 & 128 ? 154 | 65280 : 154);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_10011011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (155 & 128 ? 155 | 65280 : 155);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_10011100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (156 & 128 ? 156 | 65280 : 156);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_10011101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (157 & 128 ? 157 | 65280 : 157);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_10011110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (158 & 128 ? 158 | 65280 : 158);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_10011111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (159 & 128 ? 159 | 65280 : 159);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_10100000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (160 & 128 ? 160 | 65280 : 160);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_10100001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (161 & 128 ? 161 | 65280 : 161);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_10100010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (162 & 128 ? 162 | 65280 : 162);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_10100011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (163 & 128 ? 163 | 65280 : 163);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_10100100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (164 & 128 ? 164 | 65280 : 164);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_10100101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (165 & 128 ? 165 | 65280 : 165);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_10100110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (166 & 128 ? 166 | 65280 : 166);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_10100111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (167 & 128 ? 167 | 65280 : 167);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_10101000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (168 & 128 ? 168 | 65280 : 168);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_10101001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (169 & 128 ? 169 | 65280 : 169);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_10101010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (170 & 128 ? 170 | 65280 : 170);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_10101011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (171 & 128 ? 171 | 65280 : 171);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_10101100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (172 & 128 ? 172 | 65280 : 172);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_10101101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (173 & 128 ? 173 | 65280 : 173);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_10101110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (174 & 128 ? 174 | 65280 : 174);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_10101111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (175 & 128 ? 175 | 65280 : 175);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_10110000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (176 & 128 ? 176 | 65280 : 176);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_10110001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (177 & 128 ? 177 | 65280 : 177);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_10110010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (178 & 128 ? 178 | 65280 : 178);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_10110011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (179 & 128 ? 179 | 65280 : 179);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_10110100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (180 & 128 ? 180 | 65280 : 180);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_10110101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (181 & 128 ? 181 | 65280 : 181);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_10110110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (182 & 128 ? 182 | 65280 : 182);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_10110111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (183 & 128 ? 183 | 65280 : 183);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_10111000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (184 & 128 ? 184 | 65280 : 184);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_10111001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (185 & 128 ? 185 | 65280 : 185);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_10111010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (186 & 128 ? 186 | 65280 : 186);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_10111011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (187 & 128 ? 187 | 65280 : 187);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_10111100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (188 & 128 ? 188 | 65280 : 188);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_10111101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (189 & 128 ? 189 | 65280 : 189);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_10111110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (190 & 128 ? 190 | 65280 : 190);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_10111111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (191 & 128 ? 191 | 65280 : 191);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_11000000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (192 & 128 ? 192 | 65280 : 192);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_11000001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (193 & 128 ? 193 | 65280 : 193);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_11000010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (194 & 128 ? 194 | 65280 : 194);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_11000011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (195 & 128 ? 195 | 65280 : 195);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_11000100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (196 & 128 ? 196 | 65280 : 196);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_11000101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (197 & 128 ? 197 | 65280 : 197);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_11000110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (198 & 128 ? 198 | 65280 : 198);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_11000111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (199 & 128 ? 199 | 65280 : 199);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_11001000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (200 & 128 ? 200 | 65280 : 200);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_11001001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (201 & 128 ? 201 | 65280 : 201);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_11001010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (202 & 128 ? 202 | 65280 : 202);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_11001011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (203 & 128 ? 203 | 65280 : 203);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_11001100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (204 & 128 ? 204 | 65280 : 204);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_11001101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (205 & 128 ? 205 | 65280 : 205);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_11001110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (206 & 128 ? 206 | 65280 : 206);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_11001111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (207 & 128 ? 207 | 65280 : 207);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_11010000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (208 & 128 ? 208 | 65280 : 208);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_11010001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (209 & 128 ? 209 | 65280 : 209);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_11010010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (210 & 128 ? 210 | 65280 : 210);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_11010011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (211 & 128 ? 211 | 65280 : 211);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_11010100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (212 & 128 ? 212 | 65280 : 212);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_11010101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (213 & 128 ? 213 | 65280 : 213);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_11010110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (214 & 128 ? 214 | 65280 : 214);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_11010111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (215 & 128 ? 215 | 65280 : 215);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_11011000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (216 & 128 ? 216 | 65280 : 216);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_11011001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (217 & 128 ? 217 | 65280 : 217);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_11011010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (218 & 128 ? 218 | 65280 : 218);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_11011011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (219 & 128 ? 219 | 65280 : 219);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_11011100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (220 & 128 ? 220 | 65280 : 220);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_11011101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (221 & 128 ? 221 | 65280 : 221);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_11011110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (222 & 128 ? 222 | 65280 : 222);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_11011111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (223 & 128 ? 223 | 65280 : 223);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_11100000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (224 & 128 ? 224 | 65280 : 224);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_11100001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (225 & 128 ? 225 | 65280 : 225);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_11100010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (226 & 128 ? 226 | 65280 : 226);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_11100011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (227 & 128 ? 227 | 65280 : 227);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_11100100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (228 & 128 ? 228 | 65280 : 228);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_11100101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (229 & 128 ? 229 | 65280 : 229);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_11100110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (230 & 128 ? 230 | 65280 : 230);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_11100111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (231 & 128 ? 231 | 65280 : 231);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_11101000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (232 & 128 ? 232 | 65280 : 232);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_11101001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (233 & 128 ? 233 | 65280 : 233);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_11101010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (234 & 128 ? 234 | 65280 : 234);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_11101011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (235 & 128 ? 235 | 65280 : 235);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_11101100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (236 & 128 ? 236 | 65280 : 236);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_11101101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (237 & 128 ? 237 | 65280 : 237);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_11101110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (238 & 128 ? 238 | 65280 : 238);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_11101111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (239 & 128 ? 239 | 65280 : 239);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_11110000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (240 & 128 ? 240 | 65280 : 240);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_11110001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (241 & 128 ? 241 | 65280 : 241);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_11110010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (242 & 128 ? 242 | 65280 : 242);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_11110011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (243 & 128 ? 243 | 65280 : 243);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_11110100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (244 & 128 ? 244 | 65280 : 244);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_11110101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (245 & 128 ? 245 | 65280 : 245);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_11110110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (246 & 128 ? 246 | 65280 : 246);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_11110111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (247 & 128 ? 247 | 65280 : 247);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_11111000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (248 & 128 ? 248 | 65280 : 248);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_11111001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (249 & 128 ? 249 | 65280 : 249);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_11111010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (250 & 128 ? 250 | 65280 : 250);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_11111011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (251 & 128 ? 251 | 65280 : 251);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_11111100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (252 & 128 ? 252 | 65280 : 252);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_11111101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (253 & 128 ? 253 | 65280 : 253);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_11111110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (254 & 128 ? 254 | 65280 : 254);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bf_D_11111111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (255 & 128 ? 255 | 65280 : 255);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = disp + context->pc;
	context->pc = 2 + context->pc;
	context->prefetch_full = 0;
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bt_s_D_00000000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (0 & 128 ? 0 | 65280 : 0);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_00000001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (1 & 128 ? 1 | 65280 : 1);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_00000010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (2 & 128 ? 2 | 65280 : 2);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_00000011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (3 & 128 ? 3 | 65280 : 3);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_00000100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (4 & 128 ? 4 | 65280 : 4);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_00000101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (5 & 128 ? 5 | 65280 : 5);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_00000110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (6 & 128 ? 6 | 65280 : 6);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_00000111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (7 & 128 ? 7 | 65280 : 7);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_00001000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (8 & 128 ? 8 | 65280 : 8);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_00001001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (9 & 128 ? 9 | 65280 : 9);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_00001010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (10 & 128 ? 10 | 65280 : 10);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_00001011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (11 & 128 ? 11 | 65280 : 11);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_00001100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (12 & 128 ? 12 | 65280 : 12);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_00001101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (13 & 128 ? 13 | 65280 : 13);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_00001110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (14 & 128 ? 14 | 65280 : 14);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_00001111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (15 & 128 ? 15 | 65280 : 15);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_00010000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (16 & 128 ? 16 | 65280 : 16);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_00010001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (17 & 128 ? 17 | 65280 : 17);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_00010010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (18 & 128 ? 18 | 65280 : 18);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_00010011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (19 & 128 ? 19 | 65280 : 19);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_00010100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (20 & 128 ? 20 | 65280 : 20);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_00010101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (21 & 128 ? 21 | 65280 : 21);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_00010110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (22 & 128 ? 22 | 65280 : 22);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_00010111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (23 & 128 ? 23 | 65280 : 23);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_00011000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (24 & 128 ? 24 | 65280 : 24);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_00011001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (25 & 128 ? 25 | 65280 : 25);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_00011010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (26 & 128 ? 26 | 65280 : 26);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_00011011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (27 & 128 ? 27 | 65280 : 27);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_00011100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (28 & 128 ? 28 | 65280 : 28);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_00011101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (29 & 128 ? 29 | 65280 : 29);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_00011110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (30 & 128 ? 30 | 65280 : 30);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_00011111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (31 & 128 ? 31 | 65280 : 31);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_00100000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (32 & 128 ? 32 | 65280 : 32);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_00100001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (33 & 128 ? 33 | 65280 : 33);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_00100010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (34 & 128 ? 34 | 65280 : 34);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_00100011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (35 & 128 ? 35 | 65280 : 35);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_00100100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (36 & 128 ? 36 | 65280 : 36);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_00100101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (37 & 128 ? 37 | 65280 : 37);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_00100110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (38 & 128 ? 38 | 65280 : 38);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_00100111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (39 & 128 ? 39 | 65280 : 39);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_00101000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (40 & 128 ? 40 | 65280 : 40);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_00101001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (41 & 128 ? 41 | 65280 : 41);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_00101010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (42 & 128 ? 42 | 65280 : 42);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_00101011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (43 & 128 ? 43 | 65280 : 43);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_00101100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (44 & 128 ? 44 | 65280 : 44);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_00101101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (45 & 128 ? 45 | 65280 : 45);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_00101110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (46 & 128 ? 46 | 65280 : 46);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_00101111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (47 & 128 ? 47 | 65280 : 47);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_00110000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (48 & 128 ? 48 | 65280 : 48);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_00110001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (49 & 128 ? 49 | 65280 : 49);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_00110010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (50 & 128 ? 50 | 65280 : 50);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_00110011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (51 & 128 ? 51 | 65280 : 51);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_00110100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (52 & 128 ? 52 | 65280 : 52);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_00110101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (53 & 128 ? 53 | 65280 : 53);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_00110110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (54 & 128 ? 54 | 65280 : 54);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_00110111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (55 & 128 ? 55 | 65280 : 55);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_00111000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (56 & 128 ? 56 | 65280 : 56);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_00111001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (57 & 128 ? 57 | 65280 : 57);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_00111010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (58 & 128 ? 58 | 65280 : 58);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_00111011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (59 & 128 ? 59 | 65280 : 59);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_00111100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (60 & 128 ? 60 | 65280 : 60);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_00111101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (61 & 128 ? 61 | 65280 : 61);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_00111110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (62 & 128 ? 62 | 65280 : 62);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_00111111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (63 & 128 ? 63 | 65280 : 63);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_01000000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (64 & 128 ? 64 | 65280 : 64);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_01000001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (65 & 128 ? 65 | 65280 : 65);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_01000010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (66 & 128 ? 66 | 65280 : 66);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_01000011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (67 & 128 ? 67 | 65280 : 67);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_01000100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (68 & 128 ? 68 | 65280 : 68);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_01000101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (69 & 128 ? 69 | 65280 : 69);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_01000110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (70 & 128 ? 70 | 65280 : 70);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_01000111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (71 & 128 ? 71 | 65280 : 71);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_01001000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (72 & 128 ? 72 | 65280 : 72);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_01001001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (73 & 128 ? 73 | 65280 : 73);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_01001010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (74 & 128 ? 74 | 65280 : 74);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_01001011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (75 & 128 ? 75 | 65280 : 75);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_01001100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (76 & 128 ? 76 | 65280 : 76);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_01001101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (77 & 128 ? 77 | 65280 : 77);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_01001110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (78 & 128 ? 78 | 65280 : 78);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_01001111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (79 & 128 ? 79 | 65280 : 79);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_01010000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (80 & 128 ? 80 | 65280 : 80);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_01010001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (81 & 128 ? 81 | 65280 : 81);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_01010010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (82 & 128 ? 82 | 65280 : 82);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_01010011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (83 & 128 ? 83 | 65280 : 83);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_01010100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (84 & 128 ? 84 | 65280 : 84);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_01010101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (85 & 128 ? 85 | 65280 : 85);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_01010110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (86 & 128 ? 86 | 65280 : 86);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_01010111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (87 & 128 ? 87 | 65280 : 87);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_01011000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (88 & 128 ? 88 | 65280 : 88);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_01011001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (89 & 128 ? 89 | 65280 : 89);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_01011010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (90 & 128 ? 90 | 65280 : 90);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_01011011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (91 & 128 ? 91 | 65280 : 91);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_01011100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (92 & 128 ? 92 | 65280 : 92);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_01011101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (93 & 128 ? 93 | 65280 : 93);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_01011110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (94 & 128 ? 94 | 65280 : 94);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_01011111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (95 & 128 ? 95 | 65280 : 95);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_01100000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (96 & 128 ? 96 | 65280 : 96);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_01100001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (97 & 128 ? 97 | 65280 : 97);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_01100010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (98 & 128 ? 98 | 65280 : 98);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_01100011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (99 & 128 ? 99 | 65280 : 99);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_01100100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (100 & 128 ? 100 | 65280 : 100);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_01100101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (101 & 128 ? 101 | 65280 : 101);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_01100110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (102 & 128 ? 102 | 65280 : 102);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_01100111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (103 & 128 ? 103 | 65280 : 103);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_01101000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (104 & 128 ? 104 | 65280 : 104);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_01101001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (105 & 128 ? 105 | 65280 : 105);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_01101010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (106 & 128 ? 106 | 65280 : 106);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_01101011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (107 & 128 ? 107 | 65280 : 107);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_01101100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (108 & 128 ? 108 | 65280 : 108);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_01101101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (109 & 128 ? 109 | 65280 : 109);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_01101110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (110 & 128 ? 110 | 65280 : 110);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_01101111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (111 & 128 ? 111 | 65280 : 111);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_01110000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (112 & 128 ? 112 | 65280 : 112);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_01110001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (113 & 128 ? 113 | 65280 : 113);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_01110010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (114 & 128 ? 114 | 65280 : 114);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_01110011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (115 & 128 ? 115 | 65280 : 115);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_01110100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (116 & 128 ? 116 | 65280 : 116);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_01110101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (117 & 128 ? 117 | 65280 : 117);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_01110110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (118 & 128 ? 118 | 65280 : 118);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_01110111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (119 & 128 ? 119 | 65280 : 119);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_01111000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (120 & 128 ? 120 | 65280 : 120);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_01111001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (121 & 128 ? 121 | 65280 : 121);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_01111010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (122 & 128 ? 122 | 65280 : 122);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_01111011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (123 & 128 ? 123 | 65280 : 123);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_01111100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (124 & 128 ? 124 | 65280 : 124);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_01111101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (125 & 128 ? 125 | 65280 : 125);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_01111110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (126 & 128 ? 126 | 65280 : 126);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_01111111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (127 & 128 ? 127 | 65280 : 127);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_10000000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (128 & 128 ? 128 | 65280 : 128);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_10000001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (129 & 128 ? 129 | 65280 : 129);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_10000010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (130 & 128 ? 130 | 65280 : 130);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_10000011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (131 & 128 ? 131 | 65280 : 131);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_10000100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (132 & 128 ? 132 | 65280 : 132);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_10000101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (133 & 128 ? 133 | 65280 : 133);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_10000110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (134 & 128 ? 134 | 65280 : 134);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_10000111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (135 & 128 ? 135 | 65280 : 135);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_10001000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (136 & 128 ? 136 | 65280 : 136);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_10001001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (137 & 128 ? 137 | 65280 : 137);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_10001010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (138 & 128 ? 138 | 65280 : 138);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_10001011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (139 & 128 ? 139 | 65280 : 139);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_10001100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (140 & 128 ? 140 | 65280 : 140);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_10001101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (141 & 128 ? 141 | 65280 : 141);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_10001110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (142 & 128 ? 142 | 65280 : 142);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_10001111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (143 & 128 ? 143 | 65280 : 143);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_10010000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (144 & 128 ? 144 | 65280 : 144);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_10010001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (145 & 128 ? 145 | 65280 : 145);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_10010010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (146 & 128 ? 146 | 65280 : 146);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_10010011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (147 & 128 ? 147 | 65280 : 147);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_10010100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (148 & 128 ? 148 | 65280 : 148);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_10010101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (149 & 128 ? 149 | 65280 : 149);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_10010110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (150 & 128 ? 150 | 65280 : 150);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_10010111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (151 & 128 ? 151 | 65280 : 151);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_10011000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (152 & 128 ? 152 | 65280 : 152);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_10011001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (153 & 128 ? 153 | 65280 : 153);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_10011010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (154 & 128 ? 154 | 65280 : 154);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_10011011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (155 & 128 ? 155 | 65280 : 155);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_10011100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (156 & 128 ? 156 | 65280 : 156);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_10011101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (157 & 128 ? 157 | 65280 : 157);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_10011110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (158 & 128 ? 158 | 65280 : 158);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_10011111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (159 & 128 ? 159 | 65280 : 159);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_10100000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (160 & 128 ? 160 | 65280 : 160);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_10100001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (161 & 128 ? 161 | 65280 : 161);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_10100010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (162 & 128 ? 162 | 65280 : 162);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_10100011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (163 & 128 ? 163 | 65280 : 163);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_10100100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (164 & 128 ? 164 | 65280 : 164);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_10100101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (165 & 128 ? 165 | 65280 : 165);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_10100110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (166 & 128 ? 166 | 65280 : 166);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_10100111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (167 & 128 ? 167 | 65280 : 167);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_10101000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (168 & 128 ? 168 | 65280 : 168);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_10101001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (169 & 128 ? 169 | 65280 : 169);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_10101010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (170 & 128 ? 170 | 65280 : 170);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_10101011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (171 & 128 ? 171 | 65280 : 171);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_10101100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (172 & 128 ? 172 | 65280 : 172);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_10101101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (173 & 128 ? 173 | 65280 : 173);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_10101110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (174 & 128 ? 174 | 65280 : 174);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_10101111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (175 & 128 ? 175 | 65280 : 175);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_10110000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (176 & 128 ? 176 | 65280 : 176);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_10110001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (177 & 128 ? 177 | 65280 : 177);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_10110010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (178 & 128 ? 178 | 65280 : 178);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_10110011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (179 & 128 ? 179 | 65280 : 179);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_10110100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (180 & 128 ? 180 | 65280 : 180);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_10110101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (181 & 128 ? 181 | 65280 : 181);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_10110110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (182 & 128 ? 182 | 65280 : 182);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_10110111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (183 & 128 ? 183 | 65280 : 183);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_10111000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (184 & 128 ? 184 | 65280 : 184);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_10111001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (185 & 128 ? 185 | 65280 : 185);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_10111010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (186 & 128 ? 186 | 65280 : 186);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_10111011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (187 & 128 ? 187 | 65280 : 187);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_10111100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (188 & 128 ? 188 | 65280 : 188);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_10111101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (189 & 128 ? 189 | 65280 : 189);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_10111110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (190 & 128 ? 190 | 65280 : 190);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_10111111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (191 & 128 ? 191 | 65280 : 191);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_11000000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (192 & 128 ? 192 | 65280 : 192);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_11000001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (193 & 128 ? 193 | 65280 : 193);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_11000010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (194 & 128 ? 194 | 65280 : 194);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_11000011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (195 & 128 ? 195 | 65280 : 195);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_11000100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (196 & 128 ? 196 | 65280 : 196);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_11000101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (197 & 128 ? 197 | 65280 : 197);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_11000110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (198 & 128 ? 198 | 65280 : 198);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_11000111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (199 & 128 ? 199 | 65280 : 199);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_11001000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (200 & 128 ? 200 | 65280 : 200);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_11001001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (201 & 128 ? 201 | 65280 : 201);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_11001010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (202 & 128 ? 202 | 65280 : 202);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_11001011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (203 & 128 ? 203 | 65280 : 203);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_11001100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (204 & 128 ? 204 | 65280 : 204);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_11001101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (205 & 128 ? 205 | 65280 : 205);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_11001110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (206 & 128 ? 206 | 65280 : 206);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_11001111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (207 & 128 ? 207 | 65280 : 207);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_11010000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (208 & 128 ? 208 | 65280 : 208);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_11010001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (209 & 128 ? 209 | 65280 : 209);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_11010010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (210 & 128 ? 210 | 65280 : 210);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_11010011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (211 & 128 ? 211 | 65280 : 211);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_11010100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (212 & 128 ? 212 | 65280 : 212);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_11010101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (213 & 128 ? 213 | 65280 : 213);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_11010110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (214 & 128 ? 214 | 65280 : 214);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_11010111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (215 & 128 ? 215 | 65280 : 215);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_11011000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (216 & 128 ? 216 | 65280 : 216);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_11011001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (217 & 128 ? 217 | 65280 : 217);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_11011010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (218 & 128 ? 218 | 65280 : 218);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_11011011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (219 & 128 ? 219 | 65280 : 219);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_11011100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (220 & 128 ? 220 | 65280 : 220);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_11011101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (221 & 128 ? 221 | 65280 : 221);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_11011110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (222 & 128 ? 222 | 65280 : 222);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_11011111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (223 & 128 ? 223 | 65280 : 223);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_11100000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (224 & 128 ? 224 | 65280 : 224);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_11100001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (225 & 128 ? 225 | 65280 : 225);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_11100010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (226 & 128 ? 226 | 65280 : 226);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_11100011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (227 & 128 ? 227 | 65280 : 227);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_11100100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (228 & 128 ? 228 | 65280 : 228);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_11100101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (229 & 128 ? 229 | 65280 : 229);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_11100110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (230 & 128 ? 230 | 65280 : 230);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_11100111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (231 & 128 ? 231 | 65280 : 231);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_11101000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (232 & 128 ? 232 | 65280 : 232);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_11101001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (233 & 128 ? 233 | 65280 : 233);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_11101010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (234 & 128 ? 234 | 65280 : 234);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_11101011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (235 & 128 ? 235 | 65280 : 235);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_11101100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (236 & 128 ? 236 | 65280 : 236);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_11101101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (237 & 128 ? 237 | 65280 : 237);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_11101110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (238 & 128 ? 238 | 65280 : 238);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_11101111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (239 & 128 ? 239 | 65280 : 239);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_11110000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (240 & 128 ? 240 | 65280 : 240);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_11110001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (241 & 128 ? 241 | 65280 : 241);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_11110010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (242 & 128 ? 242 | 65280 : 242);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_11110011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (243 & 128 ? 243 | 65280 : 243);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_11110100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (244 & 128 ? 244 | 65280 : 244);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_11110101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (245 & 128 ? 245 | 65280 : 245);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_11110110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (246 & 128 ? 246 | 65280 : 246);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_11110111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (247 & 128 ? 247 | 65280 : 247);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_11111000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (248 & 128 ? 248 | 65280 : 248);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_11111001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (249 & 128 ? 249 | 65280 : 249);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_11111010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (250 & 128 ? 250 | 65280 : 250);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_11111011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (251 & 128 ? 251 | 65280 : 251);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_11111100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (252 & 128 ? 252 | 65280 : 252);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_11111101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (253 & 128 ? 253 | 65280 : 253);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_11111110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (254 & 128 ? 254 | 65280 : 254);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bt_s_D_11111111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t) {
	disp = (disp & ~65535) | (255 & 128 ? 255 | 65280 : 255);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_00000000(sh2_context *context, uint32_t target_cycle)
{
	uint8_t cmp_tmp8__;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (0 & 128 ? 0 | 65280 : 0);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_00000001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (1 & 128 ? 1 | 65280 : 1);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_00000010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (2 & 128 ? 2 | 65280 : 2);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_00000011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (3 & 128 ? 3 | 65280 : 3);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_00000100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (4 & 128 ? 4 | 65280 : 4);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_00000101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (5 & 128 ? 5 | 65280 : 5);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_00000110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (6 & 128 ? 6 | 65280 : 6);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_00000111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (7 & 128 ? 7 | 65280 : 7);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_00001000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (8 & 128 ? 8 | 65280 : 8);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_00001001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (9 & 128 ? 9 | 65280 : 9);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_00001010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (10 & 128 ? 10 | 65280 : 10);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_00001011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (11 & 128 ? 11 | 65280 : 11);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_00001100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (12 & 128 ? 12 | 65280 : 12);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_00001101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (13 & 128 ? 13 | 65280 : 13);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_00001110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (14 & 128 ? 14 | 65280 : 14);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_00001111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (15 & 128 ? 15 | 65280 : 15);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_00010000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (16 & 128 ? 16 | 65280 : 16);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_00010001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (17 & 128 ? 17 | 65280 : 17);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_00010010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (18 & 128 ? 18 | 65280 : 18);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_00010011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (19 & 128 ? 19 | 65280 : 19);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_00010100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (20 & 128 ? 20 | 65280 : 20);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_00010101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (21 & 128 ? 21 | 65280 : 21);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_00010110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (22 & 128 ? 22 | 65280 : 22);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_00010111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (23 & 128 ? 23 | 65280 : 23);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_00011000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (24 & 128 ? 24 | 65280 : 24);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_00011001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (25 & 128 ? 25 | 65280 : 25);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_00011010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (26 & 128 ? 26 | 65280 : 26);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_00011011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (27 & 128 ? 27 | 65280 : 27);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_00011100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (28 & 128 ? 28 | 65280 : 28);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_00011101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (29 & 128 ? 29 | 65280 : 29);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_00011110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (30 & 128 ? 30 | 65280 : 30);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_00011111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (31 & 128 ? 31 | 65280 : 31);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_00100000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (32 & 128 ? 32 | 65280 : 32);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_00100001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (33 & 128 ? 33 | 65280 : 33);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_00100010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (34 & 128 ? 34 | 65280 : 34);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_00100011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (35 & 128 ? 35 | 65280 : 35);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_00100100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (36 & 128 ? 36 | 65280 : 36);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_00100101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (37 & 128 ? 37 | 65280 : 37);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_00100110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (38 & 128 ? 38 | 65280 : 38);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_00100111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (39 & 128 ? 39 | 65280 : 39);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_00101000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (40 & 128 ? 40 | 65280 : 40);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_00101001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (41 & 128 ? 41 | 65280 : 41);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_00101010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (42 & 128 ? 42 | 65280 : 42);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_00101011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (43 & 128 ? 43 | 65280 : 43);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_00101100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (44 & 128 ? 44 | 65280 : 44);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_00101101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (45 & 128 ? 45 | 65280 : 45);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_00101110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (46 & 128 ? 46 | 65280 : 46);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_00101111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (47 & 128 ? 47 | 65280 : 47);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_00110000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (48 & 128 ? 48 | 65280 : 48);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_00110001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (49 & 128 ? 49 | 65280 : 49);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_00110010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (50 & 128 ? 50 | 65280 : 50);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_00110011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (51 & 128 ? 51 | 65280 : 51);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_00110100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (52 & 128 ? 52 | 65280 : 52);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_00110101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (53 & 128 ? 53 | 65280 : 53);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_00110110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (54 & 128 ? 54 | 65280 : 54);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_00110111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (55 & 128 ? 55 | 65280 : 55);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_00111000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (56 & 128 ? 56 | 65280 : 56);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_00111001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (57 & 128 ? 57 | 65280 : 57);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_00111010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (58 & 128 ? 58 | 65280 : 58);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_00111011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (59 & 128 ? 59 | 65280 : 59);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_00111100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (60 & 128 ? 60 | 65280 : 60);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_00111101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (61 & 128 ? 61 | 65280 : 61);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_00111110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (62 & 128 ? 62 | 65280 : 62);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_00111111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (63 & 128 ? 63 | 65280 : 63);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_01000000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (64 & 128 ? 64 | 65280 : 64);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_01000001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (65 & 128 ? 65 | 65280 : 65);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_01000010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (66 & 128 ? 66 | 65280 : 66);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_01000011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (67 & 128 ? 67 | 65280 : 67);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_01000100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (68 & 128 ? 68 | 65280 : 68);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_01000101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (69 & 128 ? 69 | 65280 : 69);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_01000110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (70 & 128 ? 70 | 65280 : 70);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_01000111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (71 & 128 ? 71 | 65280 : 71);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_01001000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (72 & 128 ? 72 | 65280 : 72);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_01001001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (73 & 128 ? 73 | 65280 : 73);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_01001010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (74 & 128 ? 74 | 65280 : 74);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_01001011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (75 & 128 ? 75 | 65280 : 75);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_01001100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (76 & 128 ? 76 | 65280 : 76);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_01001101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (77 & 128 ? 77 | 65280 : 77);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_01001110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (78 & 128 ? 78 | 65280 : 78);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_01001111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (79 & 128 ? 79 | 65280 : 79);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_01010000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (80 & 128 ? 80 | 65280 : 80);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_01010001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (81 & 128 ? 81 | 65280 : 81);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_01010010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (82 & 128 ? 82 | 65280 : 82);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_01010011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (83 & 128 ? 83 | 65280 : 83);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_01010100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (84 & 128 ? 84 | 65280 : 84);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_01010101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (85 & 128 ? 85 | 65280 : 85);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_01010110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (86 & 128 ? 86 | 65280 : 86);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_01010111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (87 & 128 ? 87 | 65280 : 87);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_01011000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (88 & 128 ? 88 | 65280 : 88);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_01011001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (89 & 128 ? 89 | 65280 : 89);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_01011010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (90 & 128 ? 90 | 65280 : 90);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_01011011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (91 & 128 ? 91 | 65280 : 91);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_01011100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (92 & 128 ? 92 | 65280 : 92);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_01011101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (93 & 128 ? 93 | 65280 : 93);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_01011110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (94 & 128 ? 94 | 65280 : 94);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_01011111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (95 & 128 ? 95 | 65280 : 95);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_01100000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (96 & 128 ? 96 | 65280 : 96);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_01100001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (97 & 128 ? 97 | 65280 : 97);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_01100010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (98 & 128 ? 98 | 65280 : 98);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_01100011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (99 & 128 ? 99 | 65280 : 99);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_01100100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (100 & 128 ? 100 | 65280 : 100);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_01100101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (101 & 128 ? 101 | 65280 : 101);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_01100110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (102 & 128 ? 102 | 65280 : 102);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_01100111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (103 & 128 ? 103 | 65280 : 103);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_01101000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (104 & 128 ? 104 | 65280 : 104);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_01101001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (105 & 128 ? 105 | 65280 : 105);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_01101010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (106 & 128 ? 106 | 65280 : 106);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_01101011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (107 & 128 ? 107 | 65280 : 107);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_01101100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (108 & 128 ? 108 | 65280 : 108);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_01101101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (109 & 128 ? 109 | 65280 : 109);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_01101110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (110 & 128 ? 110 | 65280 : 110);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_01101111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (111 & 128 ? 111 | 65280 : 111);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_01110000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (112 & 128 ? 112 | 65280 : 112);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_01110001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (113 & 128 ? 113 | 65280 : 113);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_01110010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (114 & 128 ? 114 | 65280 : 114);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_01110011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (115 & 128 ? 115 | 65280 : 115);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_01110100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (116 & 128 ? 116 | 65280 : 116);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_01110101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (117 & 128 ? 117 | 65280 : 117);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_01110110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (118 & 128 ? 118 | 65280 : 118);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_01110111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (119 & 128 ? 119 | 65280 : 119);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_01111000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (120 & 128 ? 120 | 65280 : 120);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_01111001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (121 & 128 ? 121 | 65280 : 121);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_01111010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (122 & 128 ? 122 | 65280 : 122);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_01111011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (123 & 128 ? 123 | 65280 : 123);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_01111100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (124 & 128 ? 124 | 65280 : 124);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_01111101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (125 & 128 ? 125 | 65280 : 125);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_01111110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (126 & 128 ? 126 | 65280 : 126);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_01111111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (127 & 128 ? 127 | 65280 : 127);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_10000000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (128 & 128 ? 128 | 65280 : 128);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_10000001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (129 & 128 ? 129 | 65280 : 129);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_10000010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (130 & 128 ? 130 | 65280 : 130);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_10000011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (131 & 128 ? 131 | 65280 : 131);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_10000100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (132 & 128 ? 132 | 65280 : 132);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_10000101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (133 & 128 ? 133 | 65280 : 133);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_10000110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (134 & 128 ? 134 | 65280 : 134);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_10000111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (135 & 128 ? 135 | 65280 : 135);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_10001000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (136 & 128 ? 136 | 65280 : 136);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_10001001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (137 & 128 ? 137 | 65280 : 137);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_10001010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (138 & 128 ? 138 | 65280 : 138);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_10001011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (139 & 128 ? 139 | 65280 : 139);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_10001100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (140 & 128 ? 140 | 65280 : 140);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_10001101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (141 & 128 ? 141 | 65280 : 141);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_10001110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (142 & 128 ? 142 | 65280 : 142);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_10001111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (143 & 128 ? 143 | 65280 : 143);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_10010000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (144 & 128 ? 144 | 65280 : 144);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_10010001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (145 & 128 ? 145 | 65280 : 145);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_10010010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (146 & 128 ? 146 | 65280 : 146);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_10010011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (147 & 128 ? 147 | 65280 : 147);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_10010100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (148 & 128 ? 148 | 65280 : 148);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_10010101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (149 & 128 ? 149 | 65280 : 149);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_10010110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (150 & 128 ? 150 | 65280 : 150);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_10010111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (151 & 128 ? 151 | 65280 : 151);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_10011000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (152 & 128 ? 152 | 65280 : 152);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_10011001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (153 & 128 ? 153 | 65280 : 153);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_10011010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (154 & 128 ? 154 | 65280 : 154);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_10011011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (155 & 128 ? 155 | 65280 : 155);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_10011100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (156 & 128 ? 156 | 65280 : 156);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_10011101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (157 & 128 ? 157 | 65280 : 157);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_10011110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (158 & 128 ? 158 | 65280 : 158);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_10011111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (159 & 128 ? 159 | 65280 : 159);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_10100000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (160 & 128 ? 160 | 65280 : 160);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_10100001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (161 & 128 ? 161 | 65280 : 161);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_10100010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (162 & 128 ? 162 | 65280 : 162);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_10100011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (163 & 128 ? 163 | 65280 : 163);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_10100100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (164 & 128 ? 164 | 65280 : 164);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_10100101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (165 & 128 ? 165 | 65280 : 165);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_10100110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (166 & 128 ? 166 | 65280 : 166);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_10100111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (167 & 128 ? 167 | 65280 : 167);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_10101000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (168 & 128 ? 168 | 65280 : 168);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_10101001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (169 & 128 ? 169 | 65280 : 169);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_10101010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (170 & 128 ? 170 | 65280 : 170);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_10101011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (171 & 128 ? 171 | 65280 : 171);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_10101100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (172 & 128 ? 172 | 65280 : 172);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_10101101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (173 & 128 ? 173 | 65280 : 173);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_10101110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (174 & 128 ? 174 | 65280 : 174);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_10101111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (175 & 128 ? 175 | 65280 : 175);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_10110000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (176 & 128 ? 176 | 65280 : 176);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_10110001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (177 & 128 ? 177 | 65280 : 177);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_10110010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (178 & 128 ? 178 | 65280 : 178);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_10110011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (179 & 128 ? 179 | 65280 : 179);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_10110100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (180 & 128 ? 180 | 65280 : 180);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_10110101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (181 & 128 ? 181 | 65280 : 181);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_10110110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (182 & 128 ? 182 | 65280 : 182);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_10110111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (183 & 128 ? 183 | 65280 : 183);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_10111000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (184 & 128 ? 184 | 65280 : 184);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_10111001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (185 & 128 ? 185 | 65280 : 185);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_10111010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (186 & 128 ? 186 | 65280 : 186);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_10111011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (187 & 128 ? 187 | 65280 : 187);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_10111100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (188 & 128 ? 188 | 65280 : 188);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_10111101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (189 & 128 ? 189 | 65280 : 189);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_10111110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (190 & 128 ? 190 | 65280 : 190);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_10111111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (191 & 128 ? 191 | 65280 : 191);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_11000000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (192 & 128 ? 192 | 65280 : 192);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_11000001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (193 & 128 ? 193 | 65280 : 193);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_11000010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (194 & 128 ? 194 | 65280 : 194);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_11000011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (195 & 128 ? 195 | 65280 : 195);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_11000100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (196 & 128 ? 196 | 65280 : 196);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_11000101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (197 & 128 ? 197 | 65280 : 197);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_11000110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (198 & 128 ? 198 | 65280 : 198);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_11000111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (199 & 128 ? 199 | 65280 : 199);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_11001000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (200 & 128 ? 200 | 65280 : 200);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_11001001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (201 & 128 ? 201 | 65280 : 201);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_11001010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (202 & 128 ? 202 | 65280 : 202);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_11001011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (203 & 128 ? 203 | 65280 : 203);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_11001100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (204 & 128 ? 204 | 65280 : 204);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_11001101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (205 & 128 ? 205 | 65280 : 205);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_11001110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (206 & 128 ? 206 | 65280 : 206);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_11001111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (207 & 128 ? 207 | 65280 : 207);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_11010000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (208 & 128 ? 208 | 65280 : 208);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_11010001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (209 & 128 ? 209 | 65280 : 209);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_11010010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (210 & 128 ? 210 | 65280 : 210);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_11010011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (211 & 128 ? 211 | 65280 : 211);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_11010100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (212 & 128 ? 212 | 65280 : 212);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_11010101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (213 & 128 ? 213 | 65280 : 213);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_11010110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (214 & 128 ? 214 | 65280 : 214);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_11010111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (215 & 128 ? 215 | 65280 : 215);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_11011000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (216 & 128 ? 216 | 65280 : 216);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_11011001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (217 & 128 ? 217 | 65280 : 217);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_11011010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (218 & 128 ? 218 | 65280 : 218);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_11011011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (219 & 128 ? 219 | 65280 : 219);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_11011100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (220 & 128 ? 220 | 65280 : 220);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_11011101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (221 & 128 ? 221 | 65280 : 221);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_11011110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (222 & 128 ? 222 | 65280 : 222);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_11011111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (223 & 128 ? 223 | 65280 : 223);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_11100000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (224 & 128 ? 224 | 65280 : 224);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_11100001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (225 & 128 ? 225 | 65280 : 225);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_11100010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (226 & 128 ? 226 | 65280 : 226);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_11100011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (227 & 128 ? 227 | 65280 : 227);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_11100100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (228 & 128 ? 228 | 65280 : 228);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_11100101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (229 & 128 ? 229 | 65280 : 229);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_11100110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (230 & 128 ? 230 | 65280 : 230);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_11100111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (231 & 128 ? 231 | 65280 : 231);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_11101000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (232 & 128 ? 232 | 65280 : 232);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_11101001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (233 & 128 ? 233 | 65280 : 233);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_11101010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (234 & 128 ? 234 | 65280 : 234);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_11101011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (235 & 128 ? 235 | 65280 : 235);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_11101100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (236 & 128 ? 236 | 65280 : 236);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_11101101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (237 & 128 ? 237 | 65280 : 237);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_11101110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (238 & 128 ? 238 | 65280 : 238);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_11101111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (239 & 128 ? 239 | 65280 : 239);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_11110000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (240 & 128 ? 240 | 65280 : 240);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_11110001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (241 & 128 ? 241 | 65280 : 241);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_11110010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (242 & 128 ? 242 | 65280 : 242);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_11110011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (243 & 128 ? 243 | 65280 : 243);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_11110100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (244 & 128 ? 244 | 65280 : 244);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_11110101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (245 & 128 ? 245 | 65280 : 245);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_11110110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (246 & 128 ? 246 | 65280 : 246);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_11110111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (247 & 128 ? 247 | 65280 : 247);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_11111000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (248 & 128 ? 248 | 65280 : 248);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_11111001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (249 & 128 ? 249 | 65280 : 249);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_11111010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (250 & 128 ? 250 | 65280 : 250);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_11111011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (251 & 128 ? 251 | 65280 : 251);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_11111100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (252 & 128 ? 252 | 65280 : 252);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_11111101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (253 & 128 ? 253 | 65280 : 253);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_11111110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (254 & 128 ? 254 | 65280 : 254);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void bf_s_D_11111111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t disp;
	uint8_t cmp_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 1;
	if (context->t == 0) {
	disp = (disp & ~65535) | (255 & 128 ? 255 | 65280 : 255);
	disp = (disp & 65535) & 32768 ? (disp & 65535) | 4294901760 : (disp & 65535);
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
	} else {
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	}
}
static void mov_disp_w_pc_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint16_t D = context->prefetch_cur & 255;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = D << 1;
	context->scratch1 = context->pc + context->scratch1;
	context->scratch1 = 4 + context->scratch1;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_disp_w_pc_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint16_t D = context->prefetch_cur & 255;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = D << 1;
	context->scratch1 = context->pc + context->scratch1;
	context->scratch1 = 4 + context->scratch1;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[1] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_disp_w_pc_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint16_t D = context->prefetch_cur & 255;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = D << 1;
	context->scratch1 = context->pc + context->scratch1;
	context->scratch1 = 4 + context->scratch1;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[2] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_disp_w_pc_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint16_t D = context->prefetch_cur & 255;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = D << 1;
	context->scratch1 = context->pc + context->scratch1;
	context->scratch1 = 4 + context->scratch1;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[3] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_disp_w_pc_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint16_t D = context->prefetch_cur & 255;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = D << 1;
	context->scratch1 = context->pc + context->scratch1;
	context->scratch1 = 4 + context->scratch1;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[4] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_disp_w_pc_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint16_t D = context->prefetch_cur & 255;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = D << 1;
	context->scratch1 = context->pc + context->scratch1;
	context->scratch1 = 4 + context->scratch1;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[5] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_disp_w_pc_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint16_t D = context->prefetch_cur & 255;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = D << 1;
	context->scratch1 = context->pc + context->scratch1;
	context->scratch1 = 4 + context->scratch1;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[6] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_disp_w_pc_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint16_t D = context->prefetch_cur & 255;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = D << 1;
	context->scratch1 = context->pc + context->scratch1;
	context->scratch1 = 4 + context->scratch1;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[7] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_disp_w_pc_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint16_t D = context->prefetch_cur & 255;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = D << 1;
	context->scratch1 = context->pc + context->scratch1;
	context->scratch1 = 4 + context->scratch1;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[8] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_disp_w_pc_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint16_t D = context->prefetch_cur & 255;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = D << 1;
	context->scratch1 = context->pc + context->scratch1;
	context->scratch1 = 4 + context->scratch1;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[9] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_disp_w_pc_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint16_t D = context->prefetch_cur & 255;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = D << 1;
	context->scratch1 = context->pc + context->scratch1;
	context->scratch1 = 4 + context->scratch1;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[10] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_disp_w_pc_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint16_t D = context->prefetch_cur & 255;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = D << 1;
	context->scratch1 = context->pc + context->scratch1;
	context->scratch1 = 4 + context->scratch1;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[11] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_disp_w_pc_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint16_t D = context->prefetch_cur & 255;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = D << 1;
	context->scratch1 = context->pc + context->scratch1;
	context->scratch1 = 4 + context->scratch1;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[12] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_disp_w_pc_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint16_t D = context->prefetch_cur & 255;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = D << 1;
	context->scratch1 = context->pc + context->scratch1;
	context->scratch1 = 4 + context->scratch1;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[13] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_disp_w_pc_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint16_t D = context->prefetch_cur & 255;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = D << 1;
	context->scratch1 = context->pc + context->scratch1;
	context->scratch1 = 4 + context->scratch1;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[14] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_disp_w_pc_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint16_t D = context->prefetch_cur & 255;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = D << 1;
	context->scratch1 = context->pc + context->scratch1;
	context->scratch1 = 4 + context->scratch1;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[15] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void bra(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t disp;
	uint32_t temp;
	uint16_t D = context->prefetch_cur & 4095;
	context->cycles += context->opts->gen.clock_divider * 1;
	disp = D;
	temp = disp & 2048;
	if (temp) {
	disp = 4294963200 | disp;
	}
	disp = disp << 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
}
static void bsr(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t disp;
	uint32_t temp;
	uint16_t D = context->prefetch_cur & 4095;
	context->cycles += context->opts->gen.clock_divider * 1;
	disp = D;
	temp = disp & 2048;
	if (temp) {
	disp = 4294963200 | disp;
	}
	disp = disp << 1;
	context->pr = context->pc + 4;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	}
	context->delay_slot = 1;
	context->did_mem = 0;
	context->pc = disp + context->pc;
	context->cycles += context->opts->gen.clock_divider * 1;
}
static void store_r0_disp_gpr_b(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint16_t D = context->prefetch_cur & 255;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = D + context->gbr;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_gpr_w(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write16_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint16_t D = context->prefetch_cur & 255;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = D << 1;
	context->scratch2 = context->gbr + context->scratch2;
	sh2_write16_tmp = context->scratch2 >> 29;
	context->write16[sh2_write16_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void store_r0_disp_gpr_l(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint16_t D = context->prefetch_cur & 255;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch2 = D << 2;
	context->scratch2 = context->gbr + context->scratch2;
	sh2_write32_tmp = context->scratch2 >> 29;
	context->write32[sh2_write32_tmp](context->scratch2, context, context->gpr[0]);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void trapa(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint16_t I = context->prefetch_cur & 255;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->gpr[15] = context->gpr[15] - 4;
	context->sr = 240 & context->sr;
	if (context->t) {
	context->sr = 1 | context->sr;
	}
	if (context->s) {
	context->sr = 2 | context->sr;
	}
	if (context->q) {
	context->sr = 256 | context->sr;
	}
	if (context->m) {
	context->sr = 512 | context->sr;
	}
	sh2_write32_tmp = context->gpr[15] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[15], context, context->sr);
	context->did_mem = 1;
	context->cycles += context->opts->gen.clock_divider * 2;
	context->gpr[15] = context->gpr[15] - 4;
	context->scratch1 = context->pc + 2;
	sh2_write32_tmp = context->gpr[15] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[15], context, context->scratch1);
	context->did_mem = 1;
	context->scratch1 = I << 2;
	context->scratch1 = context->vbr + context->scratch1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->pc = context->scratch1 - 2;
	context->cycles += context->opts->gen.clock_divider * 3;
	context->prefetch_full = 0;
	context->pc = 2 + context->pc;
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_gbr_r0_b(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint16_t D = context->prefetch_cur & 255;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = D + context->gbr;
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_gbr_r0_w(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint16_t D = context->prefetch_cur & 255;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = D << 1;
	context->scratch1 = context->gbr + context->scratch1;
	context->did_mem = 1;
	sh2_read16_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->scratch1, context);
	context->gpr[0] = (context->scratch1 & 65535) & 32768 ? (context->scratch1 & 65535) | 4294901760 : (context->scratch1 & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void load_disp_gbr_r0_l(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint16_t D = context->prefetch_cur & 255;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = D << 2;
	context->scratch1 = context->gbr + context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mova(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint16_t D = context->prefetch_cur & 255;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[0] = D << 2;
	context->gpr[0] = context->pc + context->gpr[0];
	context->gpr[0] = 4 + context->gpr[0];
	context->gpr[0] = 4294967292 & context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_imm_r0(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t temp;
	uint16_t I = context->prefetch_cur & 255;
	context->cycles += context->opts->gen.clock_divider * 1;
	temp = context->gpr[0] & I;
	context->t = !temp;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void andi_r0(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint16_t I = context->prefetch_cur & 255;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[0] = I & context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_imm_r0(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint16_t I = context->prefetch_cur & 255;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[0] = I ^ context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_imm_r0(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint16_t I = context->prefetch_cur & 255;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[0] = I | context->gpr[0];
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void tst_imm_r0_gbr(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint16_t I = context->prefetch_cur & 255;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gbr;
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->cycles += context->opts->gen.clock_divider * 2;
	context->scratch1 = I & context->scratch1;
	context->t = !context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void andi_r0_gbr(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint16_t I = context->prefetch_cur & 255;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gbr;
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->cycles += context->opts->gen.clock_divider * 2;
	context->scratch1 = I & context->scratch1;
	context->scratch2 = context->gpr[0] + context->gbr;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->scratch1);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void xor_imm_r0_gbr(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint16_t I = context->prefetch_cur & 255;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gbr;
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->cycles += context->opts->gen.clock_divider * 2;
	context->scratch1 = I ^ context->scratch1;
	context->scratch2 = context->gpr[0] + context->gbr;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->scratch1);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void or_imm_r0_gbr(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read8_tmp;
	uint32_t sh2_write8_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint16_t I = context->prefetch_cur & 255;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->gpr[0] + context->gbr;
	context->did_mem = 1;
	sh2_read8_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read8[sh2_read8_tmp](context->scratch1, context);
	context->cycles += context->opts->gen.clock_divider * 2;
	context->scratch1 = I | context->scratch1;
	context->scratch2 = context->gpr[0] + context->gbr;
	sh2_write8_tmp = context->scratch2 >> 29;
	context->write8[sh2_write8_tmp](context->scratch2, context, context->scratch1);
	context->did_mem = 1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_disp_l_pc_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint16_t D = context->prefetch_cur & 255;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = D << 2;
	context->scratch1 = context->pc + context->scratch1;
	context->scratch1 = 4 + context->scratch1;
	context->scratch1 = 4294967292 & context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[0] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_disp_l_pc_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint16_t D = context->prefetch_cur & 255;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = D << 2;
	context->scratch1 = context->pc + context->scratch1;
	context->scratch1 = 4 + context->scratch1;
	context->scratch1 = 4294967292 & context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[1] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_disp_l_pc_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint16_t D = context->prefetch_cur & 255;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = D << 2;
	context->scratch1 = context->pc + context->scratch1;
	context->scratch1 = 4 + context->scratch1;
	context->scratch1 = 4294967292 & context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[2] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_disp_l_pc_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint16_t D = context->prefetch_cur & 255;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = D << 2;
	context->scratch1 = context->pc + context->scratch1;
	context->scratch1 = 4 + context->scratch1;
	context->scratch1 = 4294967292 & context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[3] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_disp_l_pc_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint16_t D = context->prefetch_cur & 255;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = D << 2;
	context->scratch1 = context->pc + context->scratch1;
	context->scratch1 = 4 + context->scratch1;
	context->scratch1 = 4294967292 & context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[4] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_disp_l_pc_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint16_t D = context->prefetch_cur & 255;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = D << 2;
	context->scratch1 = context->pc + context->scratch1;
	context->scratch1 = 4 + context->scratch1;
	context->scratch1 = 4294967292 & context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[5] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_disp_l_pc_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint16_t D = context->prefetch_cur & 255;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = D << 2;
	context->scratch1 = context->pc + context->scratch1;
	context->scratch1 = 4 + context->scratch1;
	context->scratch1 = 4294967292 & context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[6] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_disp_l_pc_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint16_t D = context->prefetch_cur & 255;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = D << 2;
	context->scratch1 = context->pc + context->scratch1;
	context->scratch1 = 4 + context->scratch1;
	context->scratch1 = 4294967292 & context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[7] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_disp_l_pc_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint16_t D = context->prefetch_cur & 255;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = D << 2;
	context->scratch1 = context->pc + context->scratch1;
	context->scratch1 = 4 + context->scratch1;
	context->scratch1 = 4294967292 & context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[8] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_disp_l_pc_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint16_t D = context->prefetch_cur & 255;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = D << 2;
	context->scratch1 = context->pc + context->scratch1;
	context->scratch1 = 4 + context->scratch1;
	context->scratch1 = 4294967292 & context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[9] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_disp_l_pc_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint16_t D = context->prefetch_cur & 255;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = D << 2;
	context->scratch1 = context->pc + context->scratch1;
	context->scratch1 = 4 + context->scratch1;
	context->scratch1 = 4294967292 & context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[10] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_disp_l_pc_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint16_t D = context->prefetch_cur & 255;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = D << 2;
	context->scratch1 = context->pc + context->scratch1;
	context->scratch1 = 4 + context->scratch1;
	context->scratch1 = 4294967292 & context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[11] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_disp_l_pc_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint16_t D = context->prefetch_cur & 255;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = D << 2;
	context->scratch1 = context->pc + context->scratch1;
	context->scratch1 = 4 + context->scratch1;
	context->scratch1 = 4294967292 & context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[12] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_disp_l_pc_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint16_t D = context->prefetch_cur & 255;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = D << 2;
	context->scratch1 = context->pc + context->scratch1;
	context->scratch1 = 4 + context->scratch1;
	context->scratch1 = 4294967292 & context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[13] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_disp_l_pc_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint16_t D = context->prefetch_cur & 255;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = D << 2;
	context->scratch1 = context->pc + context->scratch1;
	context->scratch1 = 4 + context->scratch1;
	context->scratch1 = 4294967292 & context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[14] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_disp_l_pc_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint16_t D = context->prefetch_cur & 255;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->scratch1 = D << 2;
	context->scratch1 = context->pc + context->scratch1;
	context->scratch1 = 4 + context->scratch1;
	context->scratch1 = 4294967292 & context->scratch1;
	context->did_mem = 1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_imm_N_0000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint16_t I = context->prefetch_cur & 255;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[0] = (context->gpr[0] & ~65535) | ((I & 255) & 128 ? (I & 255) | 65280 : (I & 255));
	context->gpr[0] = (context->gpr[0] & 65535) & 32768 ? (context->gpr[0] & 65535) | 4294901760 : (context->gpr[0] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_imm_N_0001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint16_t I = context->prefetch_cur & 255;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[1] = (context->gpr[1] & ~65535) | ((I & 255) & 128 ? (I & 255) | 65280 : (I & 255));
	context->gpr[1] = (context->gpr[1] & 65535) & 32768 ? (context->gpr[1] & 65535) | 4294901760 : (context->gpr[1] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_imm_N_0010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint16_t I = context->prefetch_cur & 255;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[2] = (context->gpr[2] & ~65535) | ((I & 255) & 128 ? (I & 255) | 65280 : (I & 255));
	context->gpr[2] = (context->gpr[2] & 65535) & 32768 ? (context->gpr[2] & 65535) | 4294901760 : (context->gpr[2] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_imm_N_0011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint16_t I = context->prefetch_cur & 255;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[3] = (context->gpr[3] & ~65535) | ((I & 255) & 128 ? (I & 255) | 65280 : (I & 255));
	context->gpr[3] = (context->gpr[3] & 65535) & 32768 ? (context->gpr[3] & 65535) | 4294901760 : (context->gpr[3] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_imm_N_0100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint16_t I = context->prefetch_cur & 255;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[4] = (context->gpr[4] & ~65535) | ((I & 255) & 128 ? (I & 255) | 65280 : (I & 255));
	context->gpr[4] = (context->gpr[4] & 65535) & 32768 ? (context->gpr[4] & 65535) | 4294901760 : (context->gpr[4] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_imm_N_0101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint16_t I = context->prefetch_cur & 255;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[5] = (context->gpr[5] & ~65535) | ((I & 255) & 128 ? (I & 255) | 65280 : (I & 255));
	context->gpr[5] = (context->gpr[5] & 65535) & 32768 ? (context->gpr[5] & 65535) | 4294901760 : (context->gpr[5] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_imm_N_0110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint16_t I = context->prefetch_cur & 255;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[6] = (context->gpr[6] & ~65535) | ((I & 255) & 128 ? (I & 255) | 65280 : (I & 255));
	context->gpr[6] = (context->gpr[6] & 65535) & 32768 ? (context->gpr[6] & 65535) | 4294901760 : (context->gpr[6] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_imm_N_0111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint16_t I = context->prefetch_cur & 255;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[7] = (context->gpr[7] & ~65535) | ((I & 255) & 128 ? (I & 255) | 65280 : (I & 255));
	context->gpr[7] = (context->gpr[7] & 65535) & 32768 ? (context->gpr[7] & 65535) | 4294901760 : (context->gpr[7] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_imm_N_1000(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint16_t I = context->prefetch_cur & 255;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[8] = (context->gpr[8] & ~65535) | ((I & 255) & 128 ? (I & 255) | 65280 : (I & 255));
	context->gpr[8] = (context->gpr[8] & 65535) & 32768 ? (context->gpr[8] & 65535) | 4294901760 : (context->gpr[8] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_imm_N_1001(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint16_t I = context->prefetch_cur & 255;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[9] = (context->gpr[9] & ~65535) | ((I & 255) & 128 ? (I & 255) | 65280 : (I & 255));
	context->gpr[9] = (context->gpr[9] & 65535) & 32768 ? (context->gpr[9] & 65535) | 4294901760 : (context->gpr[9] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_imm_N_1010(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint16_t I = context->prefetch_cur & 255;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[10] = (context->gpr[10] & ~65535) | ((I & 255) & 128 ? (I & 255) | 65280 : (I & 255));
	context->gpr[10] = (context->gpr[10] & 65535) & 32768 ? (context->gpr[10] & 65535) | 4294901760 : (context->gpr[10] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_imm_N_1011(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint16_t I = context->prefetch_cur & 255;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[11] = (context->gpr[11] & ~65535) | ((I & 255) & 128 ? (I & 255) | 65280 : (I & 255));
	context->gpr[11] = (context->gpr[11] & 65535) & 32768 ? (context->gpr[11] & 65535) | 4294901760 : (context->gpr[11] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_imm_N_1100(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint16_t I = context->prefetch_cur & 255;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[12] = (context->gpr[12] & ~65535) | ((I & 255) & 128 ? (I & 255) | 65280 : (I & 255));
	context->gpr[12] = (context->gpr[12] & 65535) & 32768 ? (context->gpr[12] & 65535) | 4294901760 : (context->gpr[12] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_imm_N_1101(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint16_t I = context->prefetch_cur & 255;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[13] = (context->gpr[13] & ~65535) | ((I & 255) & 128 ? (I & 255) | 65280 : (I & 255));
	context->gpr[13] = (context->gpr[13] & 65535) & 32768 ? (context->gpr[13] & 65535) | 4294901760 : (context->gpr[13] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_imm_N_1110(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint16_t I = context->prefetch_cur & 255;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[14] = (context->gpr[14] & ~65535) | ((I & 255) & 128 ? (I & 255) | 65280 : (I & 255));
	context->gpr[14] = (context->gpr[14] & 65535) & 32768 ? (context->gpr[14] & 65535) | 4294901760 : (context->gpr[14] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void mov_imm_N_1111(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_read16_tmp;
	uint32_t sh2_read32_tmp;
	uint16_t I = context->prefetch_cur & 255;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[15] = (context->gpr[15] & ~65535) | ((I & 255) & 128 ? (I & 255) | 65280 : (I & 255));
	context->gpr[15] = (context->gpr[15] & 65535) & 32768 ? (context->gpr[15] & 65535) | 4294901760 : (context->gpr[15] & 65535);
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}
static void unimplemented(sh2_context *context, uint32_t target_cycle)
{
	fatal_error("Unimplemented instruction: %X, pc=%X\n", context->prefetch_cur, context->pc);
}

static impl_fun impl_main[65536] = {
	unimplemented,
	unimplemented,
	stc_sr_rn_N_0000,
	bsrf_M_0000,
	store_rm_r0_rn_indexed_b_M_0000_N_0000,
	store_rm_r0_rn_indexed_w_M_0000_N_0000,
	store_rm_r0_rn_indexed_l_M_0000_N_0000,
	mul_l_M_0000_N_0000,
	clrt,
	nop,
	sts_mach_rn_N_0000,
	sh2_rts,
	load_r0_rm_indexed_rn_b_M_0000_N_0000,
	load_r0_rm_indexed_rn_w_M_0000_N_0000,
	load_r0_rm_indexed_rn_l_M_0000_N_0000,
	mac_l_M_0000_N_0000,
	unimplemented,
	unimplemented,
	stc_gbr_rn_N_0000,
	unimplemented,
	store_rm_r0_rn_indexed_b_M_0001_N_0000,
	store_rm_r0_rn_indexed_w_M_0001_N_0000,
	store_rm_r0_rn_indexed_l_M_0001_N_0000,
	mul_l_M_0001_N_0000,
	sett,
	div0u,
	sts_macl_rn_N_0000,
	sleep,
	load_r0_rm_indexed_rn_b_M_0001_N_0000,
	load_r0_rm_indexed_rn_w_M_0001_N_0000,
	load_r0_rm_indexed_rn_l_M_0001_N_0000,
	mac_l_M_0001_N_0000,
	unimplemented,
	unimplemented,
	stc_vbr_rn_N_0000,
	braf_M_0000,
	store_rm_r0_rn_indexed_b_M_0010_N_0000,
	store_rm_r0_rn_indexed_w_M_0010_N_0000,
	store_rm_r0_rn_indexed_l_M_0010_N_0000,
	mul_l_M_0010_N_0000,
	clrmac,
	movt_N_0000,
	sts_pr_rn_N_0000,
	rte,
	load_r0_rm_indexed_rn_b_M_0010_N_0000,
	load_r0_rm_indexed_rn_w_M_0010_N_0000,
	load_r0_rm_indexed_rn_l_M_0010_N_0000,
	mac_l_M_0010_N_0000,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	store_rm_r0_rn_indexed_b_M_0011_N_0000,
	store_rm_r0_rn_indexed_w_M_0011_N_0000,
	store_rm_r0_rn_indexed_l_M_0011_N_0000,
	mul_l_M_0011_N_0000,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_0011_N_0000,
	load_r0_rm_indexed_rn_w_M_0011_N_0000,
	load_r0_rm_indexed_rn_l_M_0011_N_0000,
	mac_l_M_0011_N_0000,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	store_rm_r0_rn_indexed_b_M_0100_N_0000,
	store_rm_r0_rn_indexed_w_M_0100_N_0000,
	store_rm_r0_rn_indexed_l_M_0100_N_0000,
	mul_l_M_0100_N_0000,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_0100_N_0000,
	load_r0_rm_indexed_rn_w_M_0100_N_0000,
	load_r0_rm_indexed_rn_l_M_0100_N_0000,
	mac_l_M_0100_N_0000,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	store_rm_r0_rn_indexed_b_M_0101_N_0000,
	store_rm_r0_rn_indexed_w_M_0101_N_0000,
	store_rm_r0_rn_indexed_l_M_0101_N_0000,
	mul_l_M_0101_N_0000,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_0101_N_0000,
	load_r0_rm_indexed_rn_w_M_0101_N_0000,
	load_r0_rm_indexed_rn_l_M_0101_N_0000,
	mac_l_M_0101_N_0000,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	store_rm_r0_rn_indexed_b_M_0110_N_0000,
	store_rm_r0_rn_indexed_w_M_0110_N_0000,
	store_rm_r0_rn_indexed_l_M_0110_N_0000,
	mul_l_M_0110_N_0000,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_0110_N_0000,
	load_r0_rm_indexed_rn_w_M_0110_N_0000,
	load_r0_rm_indexed_rn_l_M_0110_N_0000,
	mac_l_M_0110_N_0000,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	store_rm_r0_rn_indexed_b_M_0111_N_0000,
	store_rm_r0_rn_indexed_w_M_0111_N_0000,
	store_rm_r0_rn_indexed_l_M_0111_N_0000,
	mul_l_M_0111_N_0000,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_0111_N_0000,
	load_r0_rm_indexed_rn_w_M_0111_N_0000,
	load_r0_rm_indexed_rn_l_M_0111_N_0000,
	mac_l_M_0111_N_0000,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	store_rm_r0_rn_indexed_b_M_1000_N_0000,
	store_rm_r0_rn_indexed_w_M_1000_N_0000,
	store_rm_r0_rn_indexed_l_M_1000_N_0000,
	mul_l_M_1000_N_0000,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_1000_N_0000,
	load_r0_rm_indexed_rn_w_M_1000_N_0000,
	load_r0_rm_indexed_rn_l_M_1000_N_0000,
	mac_l_M_1000_N_0000,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	store_rm_r0_rn_indexed_b_M_1001_N_0000,
	store_rm_r0_rn_indexed_w_M_1001_N_0000,
	store_rm_r0_rn_indexed_l_M_1001_N_0000,
	mul_l_M_1001_N_0000,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_1001_N_0000,
	load_r0_rm_indexed_rn_w_M_1001_N_0000,
	load_r0_rm_indexed_rn_l_M_1001_N_0000,
	mac_l_M_1001_N_0000,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	store_rm_r0_rn_indexed_b_M_1010_N_0000,
	store_rm_r0_rn_indexed_w_M_1010_N_0000,
	store_rm_r0_rn_indexed_l_M_1010_N_0000,
	mul_l_M_1010_N_0000,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_1010_N_0000,
	load_r0_rm_indexed_rn_w_M_1010_N_0000,
	load_r0_rm_indexed_rn_l_M_1010_N_0000,
	mac_l_M_1010_N_0000,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	store_rm_r0_rn_indexed_b_M_1011_N_0000,
	store_rm_r0_rn_indexed_w_M_1011_N_0000,
	store_rm_r0_rn_indexed_l_M_1011_N_0000,
	mul_l_M_1011_N_0000,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_1011_N_0000,
	load_r0_rm_indexed_rn_w_M_1011_N_0000,
	load_r0_rm_indexed_rn_l_M_1011_N_0000,
	mac_l_M_1011_N_0000,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	store_rm_r0_rn_indexed_b_M_1100_N_0000,
	store_rm_r0_rn_indexed_w_M_1100_N_0000,
	store_rm_r0_rn_indexed_l_M_1100_N_0000,
	mul_l_M_1100_N_0000,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_1100_N_0000,
	load_r0_rm_indexed_rn_w_M_1100_N_0000,
	load_r0_rm_indexed_rn_l_M_1100_N_0000,
	mac_l_M_1100_N_0000,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	store_rm_r0_rn_indexed_b_M_1101_N_0000,
	store_rm_r0_rn_indexed_w_M_1101_N_0000,
	store_rm_r0_rn_indexed_l_M_1101_N_0000,
	mul_l_M_1101_N_0000,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_1101_N_0000,
	load_r0_rm_indexed_rn_w_M_1101_N_0000,
	load_r0_rm_indexed_rn_l_M_1101_N_0000,
	mac_l_M_1101_N_0000,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	store_rm_r0_rn_indexed_b_M_1110_N_0000,
	store_rm_r0_rn_indexed_w_M_1110_N_0000,
	store_rm_r0_rn_indexed_l_M_1110_N_0000,
	mul_l_M_1110_N_0000,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_1110_N_0000,
	load_r0_rm_indexed_rn_w_M_1110_N_0000,
	load_r0_rm_indexed_rn_l_M_1110_N_0000,
	mac_l_M_1110_N_0000,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	store_rm_r0_rn_indexed_b_M_1111_N_0000,
	store_rm_r0_rn_indexed_w_M_1111_N_0000,
	store_rm_r0_rn_indexed_l_M_1111_N_0000,
	mul_l_M_1111_N_0000,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_1111_N_0000,
	load_r0_rm_indexed_rn_w_M_1111_N_0000,
	load_r0_rm_indexed_rn_l_M_1111_N_0000,
	mac_l_M_1111_N_0000,
	unimplemented,
	unimplemented,
	stc_sr_rn_N_0001,
	bsrf_M_0001,
	store_rm_r0_rn_indexed_b_M_0000_N_0001,
	store_rm_r0_rn_indexed_w_M_0000_N_0001,
	store_rm_r0_rn_indexed_l_M_0000_N_0001,
	mul_l_M_0000_N_0001,
	unimplemented,
	unimplemented,
	sts_mach_rn_N_0001,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_0000_N_0001,
	load_r0_rm_indexed_rn_w_M_0000_N_0001,
	load_r0_rm_indexed_rn_l_M_0000_N_0001,
	mac_l_M_0000_N_0001,
	unimplemented,
	unimplemented,
	stc_gbr_rn_N_0001,
	unimplemented,
	store_rm_r0_rn_indexed_b_M_0001_N_0001,
	store_rm_r0_rn_indexed_w_M_0001_N_0001,
	store_rm_r0_rn_indexed_l_M_0001_N_0001,
	mul_l_M_0001_N_0001,
	unimplemented,
	unimplemented,
	sts_macl_rn_N_0001,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_0001_N_0001,
	load_r0_rm_indexed_rn_w_M_0001_N_0001,
	load_r0_rm_indexed_rn_l_M_0001_N_0001,
	mac_l_M_0001_N_0001,
	unimplemented,
	unimplemented,
	stc_vbr_rn_N_0001,
	braf_M_0001,
	store_rm_r0_rn_indexed_b_M_0010_N_0001,
	store_rm_r0_rn_indexed_w_M_0010_N_0001,
	store_rm_r0_rn_indexed_l_M_0010_N_0001,
	mul_l_M_0010_N_0001,
	unimplemented,
	movt_N_0001,
	sts_pr_rn_N_0001,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_0010_N_0001,
	load_r0_rm_indexed_rn_w_M_0010_N_0001,
	load_r0_rm_indexed_rn_l_M_0010_N_0001,
	mac_l_M_0010_N_0001,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	store_rm_r0_rn_indexed_b_M_0011_N_0001,
	store_rm_r0_rn_indexed_w_M_0011_N_0001,
	store_rm_r0_rn_indexed_l_M_0011_N_0001,
	mul_l_M_0011_N_0001,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_0011_N_0001,
	load_r0_rm_indexed_rn_w_M_0011_N_0001,
	load_r0_rm_indexed_rn_l_M_0011_N_0001,
	mac_l_M_0011_N_0001,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	store_rm_r0_rn_indexed_b_M_0100_N_0001,
	store_rm_r0_rn_indexed_w_M_0100_N_0001,
	store_rm_r0_rn_indexed_l_M_0100_N_0001,
	mul_l_M_0100_N_0001,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_0100_N_0001,
	load_r0_rm_indexed_rn_w_M_0100_N_0001,
	load_r0_rm_indexed_rn_l_M_0100_N_0001,
	mac_l_M_0100_N_0001,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	store_rm_r0_rn_indexed_b_M_0101_N_0001,
	store_rm_r0_rn_indexed_w_M_0101_N_0001,
	store_rm_r0_rn_indexed_l_M_0101_N_0001,
	mul_l_M_0101_N_0001,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_0101_N_0001,
	load_r0_rm_indexed_rn_w_M_0101_N_0001,
	load_r0_rm_indexed_rn_l_M_0101_N_0001,
	mac_l_M_0101_N_0001,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	store_rm_r0_rn_indexed_b_M_0110_N_0001,
	store_rm_r0_rn_indexed_w_M_0110_N_0001,
	store_rm_r0_rn_indexed_l_M_0110_N_0001,
	mul_l_M_0110_N_0001,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_0110_N_0001,
	load_r0_rm_indexed_rn_w_M_0110_N_0001,
	load_r0_rm_indexed_rn_l_M_0110_N_0001,
	mac_l_M_0110_N_0001,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	store_rm_r0_rn_indexed_b_M_0111_N_0001,
	store_rm_r0_rn_indexed_w_M_0111_N_0001,
	store_rm_r0_rn_indexed_l_M_0111_N_0001,
	mul_l_M_0111_N_0001,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_0111_N_0001,
	load_r0_rm_indexed_rn_w_M_0111_N_0001,
	load_r0_rm_indexed_rn_l_M_0111_N_0001,
	mac_l_M_0111_N_0001,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	store_rm_r0_rn_indexed_b_M_1000_N_0001,
	store_rm_r0_rn_indexed_w_M_1000_N_0001,
	store_rm_r0_rn_indexed_l_M_1000_N_0001,
	mul_l_M_1000_N_0001,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_1000_N_0001,
	load_r0_rm_indexed_rn_w_M_1000_N_0001,
	load_r0_rm_indexed_rn_l_M_1000_N_0001,
	mac_l_M_1000_N_0001,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	store_rm_r0_rn_indexed_b_M_1001_N_0001,
	store_rm_r0_rn_indexed_w_M_1001_N_0001,
	store_rm_r0_rn_indexed_l_M_1001_N_0001,
	mul_l_M_1001_N_0001,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_1001_N_0001,
	load_r0_rm_indexed_rn_w_M_1001_N_0001,
	load_r0_rm_indexed_rn_l_M_1001_N_0001,
	mac_l_M_1001_N_0001,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	store_rm_r0_rn_indexed_b_M_1010_N_0001,
	store_rm_r0_rn_indexed_w_M_1010_N_0001,
	store_rm_r0_rn_indexed_l_M_1010_N_0001,
	mul_l_M_1010_N_0001,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_1010_N_0001,
	load_r0_rm_indexed_rn_w_M_1010_N_0001,
	load_r0_rm_indexed_rn_l_M_1010_N_0001,
	mac_l_M_1010_N_0001,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	store_rm_r0_rn_indexed_b_M_1011_N_0001,
	store_rm_r0_rn_indexed_w_M_1011_N_0001,
	store_rm_r0_rn_indexed_l_M_1011_N_0001,
	mul_l_M_1011_N_0001,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_1011_N_0001,
	load_r0_rm_indexed_rn_w_M_1011_N_0001,
	load_r0_rm_indexed_rn_l_M_1011_N_0001,
	mac_l_M_1011_N_0001,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	store_rm_r0_rn_indexed_b_M_1100_N_0001,
	store_rm_r0_rn_indexed_w_M_1100_N_0001,
	store_rm_r0_rn_indexed_l_M_1100_N_0001,
	mul_l_M_1100_N_0001,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_1100_N_0001,
	load_r0_rm_indexed_rn_w_M_1100_N_0001,
	load_r0_rm_indexed_rn_l_M_1100_N_0001,
	mac_l_M_1100_N_0001,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	store_rm_r0_rn_indexed_b_M_1101_N_0001,
	store_rm_r0_rn_indexed_w_M_1101_N_0001,
	store_rm_r0_rn_indexed_l_M_1101_N_0001,
	mul_l_M_1101_N_0001,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_1101_N_0001,
	load_r0_rm_indexed_rn_w_M_1101_N_0001,
	load_r0_rm_indexed_rn_l_M_1101_N_0001,
	mac_l_M_1101_N_0001,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	store_rm_r0_rn_indexed_b_M_1110_N_0001,
	store_rm_r0_rn_indexed_w_M_1110_N_0001,
	store_rm_r0_rn_indexed_l_M_1110_N_0001,
	mul_l_M_1110_N_0001,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_1110_N_0001,
	load_r0_rm_indexed_rn_w_M_1110_N_0001,
	load_r0_rm_indexed_rn_l_M_1110_N_0001,
	mac_l_M_1110_N_0001,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	store_rm_r0_rn_indexed_b_M_1111_N_0001,
	store_rm_r0_rn_indexed_w_M_1111_N_0001,
	store_rm_r0_rn_indexed_l_M_1111_N_0001,
	mul_l_M_1111_N_0001,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_1111_N_0001,
	load_r0_rm_indexed_rn_w_M_1111_N_0001,
	load_r0_rm_indexed_rn_l_M_1111_N_0001,
	mac_l_M_1111_N_0001,
	unimplemented,
	unimplemented,
	stc_sr_rn_N_0010,
	bsrf_M_0010,
	store_rm_r0_rn_indexed_b_M_0000_N_0010,
	store_rm_r0_rn_indexed_w_M_0000_N_0010,
	store_rm_r0_rn_indexed_l_M_0000_N_0010,
	mul_l_M_0000_N_0010,
	unimplemented,
	unimplemented,
	sts_mach_rn_N_0010,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_0000_N_0010,
	load_r0_rm_indexed_rn_w_M_0000_N_0010,
	load_r0_rm_indexed_rn_l_M_0000_N_0010,
	mac_l_M_0000_N_0010,
	unimplemented,
	unimplemented,
	stc_gbr_rn_N_0010,
	unimplemented,
	store_rm_r0_rn_indexed_b_M_0001_N_0010,
	store_rm_r0_rn_indexed_w_M_0001_N_0010,
	store_rm_r0_rn_indexed_l_M_0001_N_0010,
	mul_l_M_0001_N_0010,
	unimplemented,
	unimplemented,
	sts_macl_rn_N_0010,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_0001_N_0010,
	load_r0_rm_indexed_rn_w_M_0001_N_0010,
	load_r0_rm_indexed_rn_l_M_0001_N_0010,
	mac_l_M_0001_N_0010,
	unimplemented,
	unimplemented,
	stc_vbr_rn_N_0010,
	braf_M_0010,
	store_rm_r0_rn_indexed_b_M_0010_N_0010,
	store_rm_r0_rn_indexed_w_M_0010_N_0010,
	store_rm_r0_rn_indexed_l_M_0010_N_0010,
	mul_l_M_0010_N_0010,
	unimplemented,
	movt_N_0010,
	sts_pr_rn_N_0010,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_0010_N_0010,
	load_r0_rm_indexed_rn_w_M_0010_N_0010,
	load_r0_rm_indexed_rn_l_M_0010_N_0010,
	mac_l_M_0010_N_0010,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	store_rm_r0_rn_indexed_b_M_0011_N_0010,
	store_rm_r0_rn_indexed_w_M_0011_N_0010,
	store_rm_r0_rn_indexed_l_M_0011_N_0010,
	mul_l_M_0011_N_0010,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_0011_N_0010,
	load_r0_rm_indexed_rn_w_M_0011_N_0010,
	load_r0_rm_indexed_rn_l_M_0011_N_0010,
	mac_l_M_0011_N_0010,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	store_rm_r0_rn_indexed_b_M_0100_N_0010,
	store_rm_r0_rn_indexed_w_M_0100_N_0010,
	store_rm_r0_rn_indexed_l_M_0100_N_0010,
	mul_l_M_0100_N_0010,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_0100_N_0010,
	load_r0_rm_indexed_rn_w_M_0100_N_0010,
	load_r0_rm_indexed_rn_l_M_0100_N_0010,
	mac_l_M_0100_N_0010,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	store_rm_r0_rn_indexed_b_M_0101_N_0010,
	store_rm_r0_rn_indexed_w_M_0101_N_0010,
	store_rm_r0_rn_indexed_l_M_0101_N_0010,
	mul_l_M_0101_N_0010,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_0101_N_0010,
	load_r0_rm_indexed_rn_w_M_0101_N_0010,
	load_r0_rm_indexed_rn_l_M_0101_N_0010,
	mac_l_M_0101_N_0010,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	store_rm_r0_rn_indexed_b_M_0110_N_0010,
	store_rm_r0_rn_indexed_w_M_0110_N_0010,
	store_rm_r0_rn_indexed_l_M_0110_N_0010,
	mul_l_M_0110_N_0010,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_0110_N_0010,
	load_r0_rm_indexed_rn_w_M_0110_N_0010,
	load_r0_rm_indexed_rn_l_M_0110_N_0010,
	mac_l_M_0110_N_0010,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	store_rm_r0_rn_indexed_b_M_0111_N_0010,
	store_rm_r0_rn_indexed_w_M_0111_N_0010,
	store_rm_r0_rn_indexed_l_M_0111_N_0010,
	mul_l_M_0111_N_0010,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_0111_N_0010,
	load_r0_rm_indexed_rn_w_M_0111_N_0010,
	load_r0_rm_indexed_rn_l_M_0111_N_0010,
	mac_l_M_0111_N_0010,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	store_rm_r0_rn_indexed_b_M_1000_N_0010,
	store_rm_r0_rn_indexed_w_M_1000_N_0010,
	store_rm_r0_rn_indexed_l_M_1000_N_0010,
	mul_l_M_1000_N_0010,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_1000_N_0010,
	load_r0_rm_indexed_rn_w_M_1000_N_0010,
	load_r0_rm_indexed_rn_l_M_1000_N_0010,
	mac_l_M_1000_N_0010,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	store_rm_r0_rn_indexed_b_M_1001_N_0010,
	store_rm_r0_rn_indexed_w_M_1001_N_0010,
	store_rm_r0_rn_indexed_l_M_1001_N_0010,
	mul_l_M_1001_N_0010,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_1001_N_0010,
	load_r0_rm_indexed_rn_w_M_1001_N_0010,
	load_r0_rm_indexed_rn_l_M_1001_N_0010,
	mac_l_M_1001_N_0010,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	store_rm_r0_rn_indexed_b_M_1010_N_0010,
	store_rm_r0_rn_indexed_w_M_1010_N_0010,
	store_rm_r0_rn_indexed_l_M_1010_N_0010,
	mul_l_M_1010_N_0010,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_1010_N_0010,
	load_r0_rm_indexed_rn_w_M_1010_N_0010,
	load_r0_rm_indexed_rn_l_M_1010_N_0010,
	mac_l_M_1010_N_0010,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	store_rm_r0_rn_indexed_b_M_1011_N_0010,
	store_rm_r0_rn_indexed_w_M_1011_N_0010,
	store_rm_r0_rn_indexed_l_M_1011_N_0010,
	mul_l_M_1011_N_0010,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_1011_N_0010,
	load_r0_rm_indexed_rn_w_M_1011_N_0010,
	load_r0_rm_indexed_rn_l_M_1011_N_0010,
	mac_l_M_1011_N_0010,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	store_rm_r0_rn_indexed_b_M_1100_N_0010,
	store_rm_r0_rn_indexed_w_M_1100_N_0010,
	store_rm_r0_rn_indexed_l_M_1100_N_0010,
	mul_l_M_1100_N_0010,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_1100_N_0010,
	load_r0_rm_indexed_rn_w_M_1100_N_0010,
	load_r0_rm_indexed_rn_l_M_1100_N_0010,
	mac_l_M_1100_N_0010,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	store_rm_r0_rn_indexed_b_M_1101_N_0010,
	store_rm_r0_rn_indexed_w_M_1101_N_0010,
	store_rm_r0_rn_indexed_l_M_1101_N_0010,
	mul_l_M_1101_N_0010,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_1101_N_0010,
	load_r0_rm_indexed_rn_w_M_1101_N_0010,
	load_r0_rm_indexed_rn_l_M_1101_N_0010,
	mac_l_M_1101_N_0010,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	store_rm_r0_rn_indexed_b_M_1110_N_0010,
	store_rm_r0_rn_indexed_w_M_1110_N_0010,
	store_rm_r0_rn_indexed_l_M_1110_N_0010,
	mul_l_M_1110_N_0010,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_1110_N_0010,
	load_r0_rm_indexed_rn_w_M_1110_N_0010,
	load_r0_rm_indexed_rn_l_M_1110_N_0010,
	mac_l_M_1110_N_0010,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	store_rm_r0_rn_indexed_b_M_1111_N_0010,
	store_rm_r0_rn_indexed_w_M_1111_N_0010,
	store_rm_r0_rn_indexed_l_M_1111_N_0010,
	mul_l_M_1111_N_0010,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_1111_N_0010,
	load_r0_rm_indexed_rn_w_M_1111_N_0010,
	load_r0_rm_indexed_rn_l_M_1111_N_0010,
	mac_l_M_1111_N_0010,
	unimplemented,
	unimplemented,
	stc_sr_rn_N_0011,
	bsrf_M_0011,
	store_rm_r0_rn_indexed_b_M_0000_N_0011,
	store_rm_r0_rn_indexed_w_M_0000_N_0011,
	store_rm_r0_rn_indexed_l_M_0000_N_0011,
	mul_l_M_0000_N_0011,
	unimplemented,
	unimplemented,
	sts_mach_rn_N_0011,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_0000_N_0011,
	load_r0_rm_indexed_rn_w_M_0000_N_0011,
	load_r0_rm_indexed_rn_l_M_0000_N_0011,
	mac_l_M_0000_N_0011,
	unimplemented,
	unimplemented,
	stc_gbr_rn_N_0011,
	unimplemented,
	store_rm_r0_rn_indexed_b_M_0001_N_0011,
	store_rm_r0_rn_indexed_w_M_0001_N_0011,
	store_rm_r0_rn_indexed_l_M_0001_N_0011,
	mul_l_M_0001_N_0011,
	unimplemented,
	unimplemented,
	sts_macl_rn_N_0011,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_0001_N_0011,
	load_r0_rm_indexed_rn_w_M_0001_N_0011,
	load_r0_rm_indexed_rn_l_M_0001_N_0011,
	mac_l_M_0001_N_0011,
	unimplemented,
	unimplemented,
	stc_vbr_rn_N_0011,
	braf_M_0011,
	store_rm_r0_rn_indexed_b_M_0010_N_0011,
	store_rm_r0_rn_indexed_w_M_0010_N_0011,
	store_rm_r0_rn_indexed_l_M_0010_N_0011,
	mul_l_M_0010_N_0011,
	unimplemented,
	movt_N_0011,
	sts_pr_rn_N_0011,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_0010_N_0011,
	load_r0_rm_indexed_rn_w_M_0010_N_0011,
	load_r0_rm_indexed_rn_l_M_0010_N_0011,
	mac_l_M_0010_N_0011,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	store_rm_r0_rn_indexed_b_M_0011_N_0011,
	store_rm_r0_rn_indexed_w_M_0011_N_0011,
	store_rm_r0_rn_indexed_l_M_0011_N_0011,
	mul_l_M_0011_N_0011,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_0011_N_0011,
	load_r0_rm_indexed_rn_w_M_0011_N_0011,
	load_r0_rm_indexed_rn_l_M_0011_N_0011,
	mac_l_M_0011_N_0011,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	store_rm_r0_rn_indexed_b_M_0100_N_0011,
	store_rm_r0_rn_indexed_w_M_0100_N_0011,
	store_rm_r0_rn_indexed_l_M_0100_N_0011,
	mul_l_M_0100_N_0011,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_0100_N_0011,
	load_r0_rm_indexed_rn_w_M_0100_N_0011,
	load_r0_rm_indexed_rn_l_M_0100_N_0011,
	mac_l_M_0100_N_0011,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	store_rm_r0_rn_indexed_b_M_0101_N_0011,
	store_rm_r0_rn_indexed_w_M_0101_N_0011,
	store_rm_r0_rn_indexed_l_M_0101_N_0011,
	mul_l_M_0101_N_0011,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_0101_N_0011,
	load_r0_rm_indexed_rn_w_M_0101_N_0011,
	load_r0_rm_indexed_rn_l_M_0101_N_0011,
	mac_l_M_0101_N_0011,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	store_rm_r0_rn_indexed_b_M_0110_N_0011,
	store_rm_r0_rn_indexed_w_M_0110_N_0011,
	store_rm_r0_rn_indexed_l_M_0110_N_0011,
	mul_l_M_0110_N_0011,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_0110_N_0011,
	load_r0_rm_indexed_rn_w_M_0110_N_0011,
	load_r0_rm_indexed_rn_l_M_0110_N_0011,
	mac_l_M_0110_N_0011,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	store_rm_r0_rn_indexed_b_M_0111_N_0011,
	store_rm_r0_rn_indexed_w_M_0111_N_0011,
	store_rm_r0_rn_indexed_l_M_0111_N_0011,
	mul_l_M_0111_N_0011,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_0111_N_0011,
	load_r0_rm_indexed_rn_w_M_0111_N_0011,
	load_r0_rm_indexed_rn_l_M_0111_N_0011,
	mac_l_M_0111_N_0011,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	store_rm_r0_rn_indexed_b_M_1000_N_0011,
	store_rm_r0_rn_indexed_w_M_1000_N_0011,
	store_rm_r0_rn_indexed_l_M_1000_N_0011,
	mul_l_M_1000_N_0011,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_1000_N_0011,
	load_r0_rm_indexed_rn_w_M_1000_N_0011,
	load_r0_rm_indexed_rn_l_M_1000_N_0011,
	mac_l_M_1000_N_0011,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	store_rm_r0_rn_indexed_b_M_1001_N_0011,
	store_rm_r0_rn_indexed_w_M_1001_N_0011,
	store_rm_r0_rn_indexed_l_M_1001_N_0011,
	mul_l_M_1001_N_0011,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_1001_N_0011,
	load_r0_rm_indexed_rn_w_M_1001_N_0011,
	load_r0_rm_indexed_rn_l_M_1001_N_0011,
	mac_l_M_1001_N_0011,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	store_rm_r0_rn_indexed_b_M_1010_N_0011,
	store_rm_r0_rn_indexed_w_M_1010_N_0011,
	store_rm_r0_rn_indexed_l_M_1010_N_0011,
	mul_l_M_1010_N_0011,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_1010_N_0011,
	load_r0_rm_indexed_rn_w_M_1010_N_0011,
	load_r0_rm_indexed_rn_l_M_1010_N_0011,
	mac_l_M_1010_N_0011,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	store_rm_r0_rn_indexed_b_M_1011_N_0011,
	store_rm_r0_rn_indexed_w_M_1011_N_0011,
	store_rm_r0_rn_indexed_l_M_1011_N_0011,
	mul_l_M_1011_N_0011,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_1011_N_0011,
	load_r0_rm_indexed_rn_w_M_1011_N_0011,
	load_r0_rm_indexed_rn_l_M_1011_N_0011,
	mac_l_M_1011_N_0011,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	store_rm_r0_rn_indexed_b_M_1100_N_0011,
	store_rm_r0_rn_indexed_w_M_1100_N_0011,
	store_rm_r0_rn_indexed_l_M_1100_N_0011,
	mul_l_M_1100_N_0011,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_1100_N_0011,
	load_r0_rm_indexed_rn_w_M_1100_N_0011,
	load_r0_rm_indexed_rn_l_M_1100_N_0011,
	mac_l_M_1100_N_0011,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	store_rm_r0_rn_indexed_b_M_1101_N_0011,
	store_rm_r0_rn_indexed_w_M_1101_N_0011,
	store_rm_r0_rn_indexed_l_M_1101_N_0011,
	mul_l_M_1101_N_0011,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_1101_N_0011,
	load_r0_rm_indexed_rn_w_M_1101_N_0011,
	load_r0_rm_indexed_rn_l_M_1101_N_0011,
	mac_l_M_1101_N_0011,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	store_rm_r0_rn_indexed_b_M_1110_N_0011,
	store_rm_r0_rn_indexed_w_M_1110_N_0011,
	store_rm_r0_rn_indexed_l_M_1110_N_0011,
	mul_l_M_1110_N_0011,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_1110_N_0011,
	load_r0_rm_indexed_rn_w_M_1110_N_0011,
	load_r0_rm_indexed_rn_l_M_1110_N_0011,
	mac_l_M_1110_N_0011,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	store_rm_r0_rn_indexed_b_M_1111_N_0011,
	store_rm_r0_rn_indexed_w_M_1111_N_0011,
	store_rm_r0_rn_indexed_l_M_1111_N_0011,
	mul_l_M_1111_N_0011,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_1111_N_0011,
	load_r0_rm_indexed_rn_w_M_1111_N_0011,
	load_r0_rm_indexed_rn_l_M_1111_N_0011,
	mac_l_M_1111_N_0011,
	unimplemented,
	unimplemented,
	stc_sr_rn_N_0100,
	bsrf_M_0100,
	store_rm_r0_rn_indexed_b_M_0000_N_0100,
	store_rm_r0_rn_indexed_w_M_0000_N_0100,
	store_rm_r0_rn_indexed_l_M_0000_N_0100,
	mul_l_M_0000_N_0100,
	unimplemented,
	unimplemented,
	sts_mach_rn_N_0100,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_0000_N_0100,
	load_r0_rm_indexed_rn_w_M_0000_N_0100,
	load_r0_rm_indexed_rn_l_M_0000_N_0100,
	mac_l_M_0000_N_0100,
	unimplemented,
	unimplemented,
	stc_gbr_rn_N_0100,
	unimplemented,
	store_rm_r0_rn_indexed_b_M_0001_N_0100,
	store_rm_r0_rn_indexed_w_M_0001_N_0100,
	store_rm_r0_rn_indexed_l_M_0001_N_0100,
	mul_l_M_0001_N_0100,
	unimplemented,
	unimplemented,
	sts_macl_rn_N_0100,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_0001_N_0100,
	load_r0_rm_indexed_rn_w_M_0001_N_0100,
	load_r0_rm_indexed_rn_l_M_0001_N_0100,
	mac_l_M_0001_N_0100,
	unimplemented,
	unimplemented,
	stc_vbr_rn_N_0100,
	braf_M_0100,
	store_rm_r0_rn_indexed_b_M_0010_N_0100,
	store_rm_r0_rn_indexed_w_M_0010_N_0100,
	store_rm_r0_rn_indexed_l_M_0010_N_0100,
	mul_l_M_0010_N_0100,
	unimplemented,
	movt_N_0100,
	sts_pr_rn_N_0100,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_0010_N_0100,
	load_r0_rm_indexed_rn_w_M_0010_N_0100,
	load_r0_rm_indexed_rn_l_M_0010_N_0100,
	mac_l_M_0010_N_0100,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	store_rm_r0_rn_indexed_b_M_0011_N_0100,
	store_rm_r0_rn_indexed_w_M_0011_N_0100,
	store_rm_r0_rn_indexed_l_M_0011_N_0100,
	mul_l_M_0011_N_0100,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_0011_N_0100,
	load_r0_rm_indexed_rn_w_M_0011_N_0100,
	load_r0_rm_indexed_rn_l_M_0011_N_0100,
	mac_l_M_0011_N_0100,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	store_rm_r0_rn_indexed_b_M_0100_N_0100,
	store_rm_r0_rn_indexed_w_M_0100_N_0100,
	store_rm_r0_rn_indexed_l_M_0100_N_0100,
	mul_l_M_0100_N_0100,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_0100_N_0100,
	load_r0_rm_indexed_rn_w_M_0100_N_0100,
	load_r0_rm_indexed_rn_l_M_0100_N_0100,
	mac_l_M_0100_N_0100,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	store_rm_r0_rn_indexed_b_M_0101_N_0100,
	store_rm_r0_rn_indexed_w_M_0101_N_0100,
	store_rm_r0_rn_indexed_l_M_0101_N_0100,
	mul_l_M_0101_N_0100,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_0101_N_0100,
	load_r0_rm_indexed_rn_w_M_0101_N_0100,
	load_r0_rm_indexed_rn_l_M_0101_N_0100,
	mac_l_M_0101_N_0100,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	store_rm_r0_rn_indexed_b_M_0110_N_0100,
	store_rm_r0_rn_indexed_w_M_0110_N_0100,
	store_rm_r0_rn_indexed_l_M_0110_N_0100,
	mul_l_M_0110_N_0100,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_0110_N_0100,
	load_r0_rm_indexed_rn_w_M_0110_N_0100,
	load_r0_rm_indexed_rn_l_M_0110_N_0100,
	mac_l_M_0110_N_0100,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	store_rm_r0_rn_indexed_b_M_0111_N_0100,
	store_rm_r0_rn_indexed_w_M_0111_N_0100,
	store_rm_r0_rn_indexed_l_M_0111_N_0100,
	mul_l_M_0111_N_0100,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_0111_N_0100,
	load_r0_rm_indexed_rn_w_M_0111_N_0100,
	load_r0_rm_indexed_rn_l_M_0111_N_0100,
	mac_l_M_0111_N_0100,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	store_rm_r0_rn_indexed_b_M_1000_N_0100,
	store_rm_r0_rn_indexed_w_M_1000_N_0100,
	store_rm_r0_rn_indexed_l_M_1000_N_0100,
	mul_l_M_1000_N_0100,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_1000_N_0100,
	load_r0_rm_indexed_rn_w_M_1000_N_0100,
	load_r0_rm_indexed_rn_l_M_1000_N_0100,
	mac_l_M_1000_N_0100,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	store_rm_r0_rn_indexed_b_M_1001_N_0100,
	store_rm_r0_rn_indexed_w_M_1001_N_0100,
	store_rm_r0_rn_indexed_l_M_1001_N_0100,
	mul_l_M_1001_N_0100,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_1001_N_0100,
	load_r0_rm_indexed_rn_w_M_1001_N_0100,
	load_r0_rm_indexed_rn_l_M_1001_N_0100,
	mac_l_M_1001_N_0100,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	store_rm_r0_rn_indexed_b_M_1010_N_0100,
	store_rm_r0_rn_indexed_w_M_1010_N_0100,
	store_rm_r0_rn_indexed_l_M_1010_N_0100,
	mul_l_M_1010_N_0100,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_1010_N_0100,
	load_r0_rm_indexed_rn_w_M_1010_N_0100,
	load_r0_rm_indexed_rn_l_M_1010_N_0100,
	mac_l_M_1010_N_0100,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	store_rm_r0_rn_indexed_b_M_1011_N_0100,
	store_rm_r0_rn_indexed_w_M_1011_N_0100,
	store_rm_r0_rn_indexed_l_M_1011_N_0100,
	mul_l_M_1011_N_0100,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_1011_N_0100,
	load_r0_rm_indexed_rn_w_M_1011_N_0100,
	load_r0_rm_indexed_rn_l_M_1011_N_0100,
	mac_l_M_1011_N_0100,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	store_rm_r0_rn_indexed_b_M_1100_N_0100,
	store_rm_r0_rn_indexed_w_M_1100_N_0100,
	store_rm_r0_rn_indexed_l_M_1100_N_0100,
	mul_l_M_1100_N_0100,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_1100_N_0100,
	load_r0_rm_indexed_rn_w_M_1100_N_0100,
	load_r0_rm_indexed_rn_l_M_1100_N_0100,
	mac_l_M_1100_N_0100,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	store_rm_r0_rn_indexed_b_M_1101_N_0100,
	store_rm_r0_rn_indexed_w_M_1101_N_0100,
	store_rm_r0_rn_indexed_l_M_1101_N_0100,
	mul_l_M_1101_N_0100,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_1101_N_0100,
	load_r0_rm_indexed_rn_w_M_1101_N_0100,
	load_r0_rm_indexed_rn_l_M_1101_N_0100,
	mac_l_M_1101_N_0100,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	store_rm_r0_rn_indexed_b_M_1110_N_0100,
	store_rm_r0_rn_indexed_w_M_1110_N_0100,
	store_rm_r0_rn_indexed_l_M_1110_N_0100,
	mul_l_M_1110_N_0100,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_1110_N_0100,
	load_r0_rm_indexed_rn_w_M_1110_N_0100,
	load_r0_rm_indexed_rn_l_M_1110_N_0100,
	mac_l_M_1110_N_0100,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	store_rm_r0_rn_indexed_b_M_1111_N_0100,
	store_rm_r0_rn_indexed_w_M_1111_N_0100,
	store_rm_r0_rn_indexed_l_M_1111_N_0100,
	mul_l_M_1111_N_0100,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_1111_N_0100,
	load_r0_rm_indexed_rn_w_M_1111_N_0100,
	load_r0_rm_indexed_rn_l_M_1111_N_0100,
	mac_l_M_1111_N_0100,
	unimplemented,
	unimplemented,
	stc_sr_rn_N_0101,
	bsrf_M_0101,
	store_rm_r0_rn_indexed_b_M_0000_N_0101,
	store_rm_r0_rn_indexed_w_M_0000_N_0101,
	store_rm_r0_rn_indexed_l_M_0000_N_0101,
	mul_l_M_0000_N_0101,
	unimplemented,
	unimplemented,
	sts_mach_rn_N_0101,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_0000_N_0101,
	load_r0_rm_indexed_rn_w_M_0000_N_0101,
	load_r0_rm_indexed_rn_l_M_0000_N_0101,
	mac_l_M_0000_N_0101,
	unimplemented,
	unimplemented,
	stc_gbr_rn_N_0101,
	unimplemented,
	store_rm_r0_rn_indexed_b_M_0001_N_0101,
	store_rm_r0_rn_indexed_w_M_0001_N_0101,
	store_rm_r0_rn_indexed_l_M_0001_N_0101,
	mul_l_M_0001_N_0101,
	unimplemented,
	unimplemented,
	sts_macl_rn_N_0101,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_0001_N_0101,
	load_r0_rm_indexed_rn_w_M_0001_N_0101,
	load_r0_rm_indexed_rn_l_M_0001_N_0101,
	mac_l_M_0001_N_0101,
	unimplemented,
	unimplemented,
	stc_vbr_rn_N_0101,
	braf_M_0101,
	store_rm_r0_rn_indexed_b_M_0010_N_0101,
	store_rm_r0_rn_indexed_w_M_0010_N_0101,
	store_rm_r0_rn_indexed_l_M_0010_N_0101,
	mul_l_M_0010_N_0101,
	unimplemented,
	movt_N_0101,
	sts_pr_rn_N_0101,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_0010_N_0101,
	load_r0_rm_indexed_rn_w_M_0010_N_0101,
	load_r0_rm_indexed_rn_l_M_0010_N_0101,
	mac_l_M_0010_N_0101,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	store_rm_r0_rn_indexed_b_M_0011_N_0101,
	store_rm_r0_rn_indexed_w_M_0011_N_0101,
	store_rm_r0_rn_indexed_l_M_0011_N_0101,
	mul_l_M_0011_N_0101,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_0011_N_0101,
	load_r0_rm_indexed_rn_w_M_0011_N_0101,
	load_r0_rm_indexed_rn_l_M_0011_N_0101,
	mac_l_M_0011_N_0101,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	store_rm_r0_rn_indexed_b_M_0100_N_0101,
	store_rm_r0_rn_indexed_w_M_0100_N_0101,
	store_rm_r0_rn_indexed_l_M_0100_N_0101,
	mul_l_M_0100_N_0101,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_0100_N_0101,
	load_r0_rm_indexed_rn_w_M_0100_N_0101,
	load_r0_rm_indexed_rn_l_M_0100_N_0101,
	mac_l_M_0100_N_0101,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	store_rm_r0_rn_indexed_b_M_0101_N_0101,
	store_rm_r0_rn_indexed_w_M_0101_N_0101,
	store_rm_r0_rn_indexed_l_M_0101_N_0101,
	mul_l_M_0101_N_0101,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_0101_N_0101,
	load_r0_rm_indexed_rn_w_M_0101_N_0101,
	load_r0_rm_indexed_rn_l_M_0101_N_0101,
	mac_l_M_0101_N_0101,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	store_rm_r0_rn_indexed_b_M_0110_N_0101,
	store_rm_r0_rn_indexed_w_M_0110_N_0101,
	store_rm_r0_rn_indexed_l_M_0110_N_0101,
	mul_l_M_0110_N_0101,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_0110_N_0101,
	load_r0_rm_indexed_rn_w_M_0110_N_0101,
	load_r0_rm_indexed_rn_l_M_0110_N_0101,
	mac_l_M_0110_N_0101,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	store_rm_r0_rn_indexed_b_M_0111_N_0101,
	store_rm_r0_rn_indexed_w_M_0111_N_0101,
	store_rm_r0_rn_indexed_l_M_0111_N_0101,
	mul_l_M_0111_N_0101,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_0111_N_0101,
	load_r0_rm_indexed_rn_w_M_0111_N_0101,
	load_r0_rm_indexed_rn_l_M_0111_N_0101,
	mac_l_M_0111_N_0101,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	store_rm_r0_rn_indexed_b_M_1000_N_0101,
	store_rm_r0_rn_indexed_w_M_1000_N_0101,
	store_rm_r0_rn_indexed_l_M_1000_N_0101,
	mul_l_M_1000_N_0101,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_1000_N_0101,
	load_r0_rm_indexed_rn_w_M_1000_N_0101,
	load_r0_rm_indexed_rn_l_M_1000_N_0101,
	mac_l_M_1000_N_0101,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	store_rm_r0_rn_indexed_b_M_1001_N_0101,
	store_rm_r0_rn_indexed_w_M_1001_N_0101,
	store_rm_r0_rn_indexed_l_M_1001_N_0101,
	mul_l_M_1001_N_0101,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_1001_N_0101,
	load_r0_rm_indexed_rn_w_M_1001_N_0101,
	load_r0_rm_indexed_rn_l_M_1001_N_0101,
	mac_l_M_1001_N_0101,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	store_rm_r0_rn_indexed_b_M_1010_N_0101,
	store_rm_r0_rn_indexed_w_M_1010_N_0101,
	store_rm_r0_rn_indexed_l_M_1010_N_0101,
	mul_l_M_1010_N_0101,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_1010_N_0101,
	load_r0_rm_indexed_rn_w_M_1010_N_0101,
	load_r0_rm_indexed_rn_l_M_1010_N_0101,
	mac_l_M_1010_N_0101,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	store_rm_r0_rn_indexed_b_M_1011_N_0101,
	store_rm_r0_rn_indexed_w_M_1011_N_0101,
	store_rm_r0_rn_indexed_l_M_1011_N_0101,
	mul_l_M_1011_N_0101,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_1011_N_0101,
	load_r0_rm_indexed_rn_w_M_1011_N_0101,
	load_r0_rm_indexed_rn_l_M_1011_N_0101,
	mac_l_M_1011_N_0101,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	store_rm_r0_rn_indexed_b_M_1100_N_0101,
	store_rm_r0_rn_indexed_w_M_1100_N_0101,
	store_rm_r0_rn_indexed_l_M_1100_N_0101,
	mul_l_M_1100_N_0101,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_1100_N_0101,
	load_r0_rm_indexed_rn_w_M_1100_N_0101,
	load_r0_rm_indexed_rn_l_M_1100_N_0101,
	mac_l_M_1100_N_0101,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	store_rm_r0_rn_indexed_b_M_1101_N_0101,
	store_rm_r0_rn_indexed_w_M_1101_N_0101,
	store_rm_r0_rn_indexed_l_M_1101_N_0101,
	mul_l_M_1101_N_0101,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_1101_N_0101,
	load_r0_rm_indexed_rn_w_M_1101_N_0101,
	load_r0_rm_indexed_rn_l_M_1101_N_0101,
	mac_l_M_1101_N_0101,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	store_rm_r0_rn_indexed_b_M_1110_N_0101,
	store_rm_r0_rn_indexed_w_M_1110_N_0101,
	store_rm_r0_rn_indexed_l_M_1110_N_0101,
	mul_l_M_1110_N_0101,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_1110_N_0101,
	load_r0_rm_indexed_rn_w_M_1110_N_0101,
	load_r0_rm_indexed_rn_l_M_1110_N_0101,
	mac_l_M_1110_N_0101,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	store_rm_r0_rn_indexed_b_M_1111_N_0101,
	store_rm_r0_rn_indexed_w_M_1111_N_0101,
	store_rm_r0_rn_indexed_l_M_1111_N_0101,
	mul_l_M_1111_N_0101,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_1111_N_0101,
	load_r0_rm_indexed_rn_w_M_1111_N_0101,
	load_r0_rm_indexed_rn_l_M_1111_N_0101,
	mac_l_M_1111_N_0101,
	unimplemented,
	unimplemented,
	stc_sr_rn_N_0110,
	bsrf_M_0110,
	store_rm_r0_rn_indexed_b_M_0000_N_0110,
	store_rm_r0_rn_indexed_w_M_0000_N_0110,
	store_rm_r0_rn_indexed_l_M_0000_N_0110,
	mul_l_M_0000_N_0110,
	unimplemented,
	unimplemented,
	sts_mach_rn_N_0110,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_0000_N_0110,
	load_r0_rm_indexed_rn_w_M_0000_N_0110,
	load_r0_rm_indexed_rn_l_M_0000_N_0110,
	mac_l_M_0000_N_0110,
	unimplemented,
	unimplemented,
	stc_gbr_rn_N_0110,
	unimplemented,
	store_rm_r0_rn_indexed_b_M_0001_N_0110,
	store_rm_r0_rn_indexed_w_M_0001_N_0110,
	store_rm_r0_rn_indexed_l_M_0001_N_0110,
	mul_l_M_0001_N_0110,
	unimplemented,
	unimplemented,
	sts_macl_rn_N_0110,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_0001_N_0110,
	load_r0_rm_indexed_rn_w_M_0001_N_0110,
	load_r0_rm_indexed_rn_l_M_0001_N_0110,
	mac_l_M_0001_N_0110,
	unimplemented,
	unimplemented,
	stc_vbr_rn_N_0110,
	braf_M_0110,
	store_rm_r0_rn_indexed_b_M_0010_N_0110,
	store_rm_r0_rn_indexed_w_M_0010_N_0110,
	store_rm_r0_rn_indexed_l_M_0010_N_0110,
	mul_l_M_0010_N_0110,
	unimplemented,
	movt_N_0110,
	sts_pr_rn_N_0110,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_0010_N_0110,
	load_r0_rm_indexed_rn_w_M_0010_N_0110,
	load_r0_rm_indexed_rn_l_M_0010_N_0110,
	mac_l_M_0010_N_0110,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	store_rm_r0_rn_indexed_b_M_0011_N_0110,
	store_rm_r0_rn_indexed_w_M_0011_N_0110,
	store_rm_r0_rn_indexed_l_M_0011_N_0110,
	mul_l_M_0011_N_0110,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_0011_N_0110,
	load_r0_rm_indexed_rn_w_M_0011_N_0110,
	load_r0_rm_indexed_rn_l_M_0011_N_0110,
	mac_l_M_0011_N_0110,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	store_rm_r0_rn_indexed_b_M_0100_N_0110,
	store_rm_r0_rn_indexed_w_M_0100_N_0110,
	store_rm_r0_rn_indexed_l_M_0100_N_0110,
	mul_l_M_0100_N_0110,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_0100_N_0110,
	load_r0_rm_indexed_rn_w_M_0100_N_0110,
	load_r0_rm_indexed_rn_l_M_0100_N_0110,
	mac_l_M_0100_N_0110,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	store_rm_r0_rn_indexed_b_M_0101_N_0110,
	store_rm_r0_rn_indexed_w_M_0101_N_0110,
	store_rm_r0_rn_indexed_l_M_0101_N_0110,
	mul_l_M_0101_N_0110,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_0101_N_0110,
	load_r0_rm_indexed_rn_w_M_0101_N_0110,
	load_r0_rm_indexed_rn_l_M_0101_N_0110,
	mac_l_M_0101_N_0110,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	store_rm_r0_rn_indexed_b_M_0110_N_0110,
	store_rm_r0_rn_indexed_w_M_0110_N_0110,
	store_rm_r0_rn_indexed_l_M_0110_N_0110,
	mul_l_M_0110_N_0110,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_0110_N_0110,
	load_r0_rm_indexed_rn_w_M_0110_N_0110,
	load_r0_rm_indexed_rn_l_M_0110_N_0110,
	mac_l_M_0110_N_0110,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	store_rm_r0_rn_indexed_b_M_0111_N_0110,
	store_rm_r0_rn_indexed_w_M_0111_N_0110,
	store_rm_r0_rn_indexed_l_M_0111_N_0110,
	mul_l_M_0111_N_0110,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_0111_N_0110,
	load_r0_rm_indexed_rn_w_M_0111_N_0110,
	load_r0_rm_indexed_rn_l_M_0111_N_0110,
	mac_l_M_0111_N_0110,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	store_rm_r0_rn_indexed_b_M_1000_N_0110,
	store_rm_r0_rn_indexed_w_M_1000_N_0110,
	store_rm_r0_rn_indexed_l_M_1000_N_0110,
	mul_l_M_1000_N_0110,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_1000_N_0110,
	load_r0_rm_indexed_rn_w_M_1000_N_0110,
	load_r0_rm_indexed_rn_l_M_1000_N_0110,
	mac_l_M_1000_N_0110,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	store_rm_r0_rn_indexed_b_M_1001_N_0110,
	store_rm_r0_rn_indexed_w_M_1001_N_0110,
	store_rm_r0_rn_indexed_l_M_1001_N_0110,
	mul_l_M_1001_N_0110,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_1001_N_0110,
	load_r0_rm_indexed_rn_w_M_1001_N_0110,
	load_r0_rm_indexed_rn_l_M_1001_N_0110,
	mac_l_M_1001_N_0110,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	store_rm_r0_rn_indexed_b_M_1010_N_0110,
	store_rm_r0_rn_indexed_w_M_1010_N_0110,
	store_rm_r0_rn_indexed_l_M_1010_N_0110,
	mul_l_M_1010_N_0110,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_1010_N_0110,
	load_r0_rm_indexed_rn_w_M_1010_N_0110,
	load_r0_rm_indexed_rn_l_M_1010_N_0110,
	mac_l_M_1010_N_0110,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	store_rm_r0_rn_indexed_b_M_1011_N_0110,
	store_rm_r0_rn_indexed_w_M_1011_N_0110,
	store_rm_r0_rn_indexed_l_M_1011_N_0110,
	mul_l_M_1011_N_0110,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_1011_N_0110,
	load_r0_rm_indexed_rn_w_M_1011_N_0110,
	load_r0_rm_indexed_rn_l_M_1011_N_0110,
	mac_l_M_1011_N_0110,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	store_rm_r0_rn_indexed_b_M_1100_N_0110,
	store_rm_r0_rn_indexed_w_M_1100_N_0110,
	store_rm_r0_rn_indexed_l_M_1100_N_0110,
	mul_l_M_1100_N_0110,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_1100_N_0110,
	load_r0_rm_indexed_rn_w_M_1100_N_0110,
	load_r0_rm_indexed_rn_l_M_1100_N_0110,
	mac_l_M_1100_N_0110,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	store_rm_r0_rn_indexed_b_M_1101_N_0110,
	store_rm_r0_rn_indexed_w_M_1101_N_0110,
	store_rm_r0_rn_indexed_l_M_1101_N_0110,
	mul_l_M_1101_N_0110,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_1101_N_0110,
	load_r0_rm_indexed_rn_w_M_1101_N_0110,
	load_r0_rm_indexed_rn_l_M_1101_N_0110,
	mac_l_M_1101_N_0110,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	store_rm_r0_rn_indexed_b_M_1110_N_0110,
	store_rm_r0_rn_indexed_w_M_1110_N_0110,
	store_rm_r0_rn_indexed_l_M_1110_N_0110,
	mul_l_M_1110_N_0110,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_1110_N_0110,
	load_r0_rm_indexed_rn_w_M_1110_N_0110,
	load_r0_rm_indexed_rn_l_M_1110_N_0110,
	mac_l_M_1110_N_0110,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	store_rm_r0_rn_indexed_b_M_1111_N_0110,
	store_rm_r0_rn_indexed_w_M_1111_N_0110,
	store_rm_r0_rn_indexed_l_M_1111_N_0110,
	mul_l_M_1111_N_0110,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_1111_N_0110,
	load_r0_rm_indexed_rn_w_M_1111_N_0110,
	load_r0_rm_indexed_rn_l_M_1111_N_0110,
	mac_l_M_1111_N_0110,
	unimplemented,
	unimplemented,
	stc_sr_rn_N_0111,
	bsrf_M_0111,
	store_rm_r0_rn_indexed_b_M_0000_N_0111,
	store_rm_r0_rn_indexed_w_M_0000_N_0111,
	store_rm_r0_rn_indexed_l_M_0000_N_0111,
	mul_l_M_0000_N_0111,
	unimplemented,
	unimplemented,
	sts_mach_rn_N_0111,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_0000_N_0111,
	load_r0_rm_indexed_rn_w_M_0000_N_0111,
	load_r0_rm_indexed_rn_l_M_0000_N_0111,
	mac_l_M_0000_N_0111,
	unimplemented,
	unimplemented,
	stc_gbr_rn_N_0111,
	unimplemented,
	store_rm_r0_rn_indexed_b_M_0001_N_0111,
	store_rm_r0_rn_indexed_w_M_0001_N_0111,
	store_rm_r0_rn_indexed_l_M_0001_N_0111,
	mul_l_M_0001_N_0111,
	unimplemented,
	unimplemented,
	sts_macl_rn_N_0111,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_0001_N_0111,
	load_r0_rm_indexed_rn_w_M_0001_N_0111,
	load_r0_rm_indexed_rn_l_M_0001_N_0111,
	mac_l_M_0001_N_0111,
	unimplemented,
	unimplemented,
	stc_vbr_rn_N_0111,
	braf_M_0111,
	store_rm_r0_rn_indexed_b_M_0010_N_0111,
	store_rm_r0_rn_indexed_w_M_0010_N_0111,
	store_rm_r0_rn_indexed_l_M_0010_N_0111,
	mul_l_M_0010_N_0111,
	unimplemented,
	movt_N_0111,
	sts_pr_rn_N_0111,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_0010_N_0111,
	load_r0_rm_indexed_rn_w_M_0010_N_0111,
	load_r0_rm_indexed_rn_l_M_0010_N_0111,
	mac_l_M_0010_N_0111,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	store_rm_r0_rn_indexed_b_M_0011_N_0111,
	store_rm_r0_rn_indexed_w_M_0011_N_0111,
	store_rm_r0_rn_indexed_l_M_0011_N_0111,
	mul_l_M_0011_N_0111,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_0011_N_0111,
	load_r0_rm_indexed_rn_w_M_0011_N_0111,
	load_r0_rm_indexed_rn_l_M_0011_N_0111,
	mac_l_M_0011_N_0111,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	store_rm_r0_rn_indexed_b_M_0100_N_0111,
	store_rm_r0_rn_indexed_w_M_0100_N_0111,
	store_rm_r0_rn_indexed_l_M_0100_N_0111,
	mul_l_M_0100_N_0111,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_0100_N_0111,
	load_r0_rm_indexed_rn_w_M_0100_N_0111,
	load_r0_rm_indexed_rn_l_M_0100_N_0111,
	mac_l_M_0100_N_0111,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	store_rm_r0_rn_indexed_b_M_0101_N_0111,
	store_rm_r0_rn_indexed_w_M_0101_N_0111,
	store_rm_r0_rn_indexed_l_M_0101_N_0111,
	mul_l_M_0101_N_0111,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_0101_N_0111,
	load_r0_rm_indexed_rn_w_M_0101_N_0111,
	load_r0_rm_indexed_rn_l_M_0101_N_0111,
	mac_l_M_0101_N_0111,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	store_rm_r0_rn_indexed_b_M_0110_N_0111,
	store_rm_r0_rn_indexed_w_M_0110_N_0111,
	store_rm_r0_rn_indexed_l_M_0110_N_0111,
	mul_l_M_0110_N_0111,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_0110_N_0111,
	load_r0_rm_indexed_rn_w_M_0110_N_0111,
	load_r0_rm_indexed_rn_l_M_0110_N_0111,
	mac_l_M_0110_N_0111,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	store_rm_r0_rn_indexed_b_M_0111_N_0111,
	store_rm_r0_rn_indexed_w_M_0111_N_0111,
	store_rm_r0_rn_indexed_l_M_0111_N_0111,
	mul_l_M_0111_N_0111,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_0111_N_0111,
	load_r0_rm_indexed_rn_w_M_0111_N_0111,
	load_r0_rm_indexed_rn_l_M_0111_N_0111,
	mac_l_M_0111_N_0111,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	store_rm_r0_rn_indexed_b_M_1000_N_0111,
	store_rm_r0_rn_indexed_w_M_1000_N_0111,
	store_rm_r0_rn_indexed_l_M_1000_N_0111,
	mul_l_M_1000_N_0111,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_1000_N_0111,
	load_r0_rm_indexed_rn_w_M_1000_N_0111,
	load_r0_rm_indexed_rn_l_M_1000_N_0111,
	mac_l_M_1000_N_0111,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	store_rm_r0_rn_indexed_b_M_1001_N_0111,
	store_rm_r0_rn_indexed_w_M_1001_N_0111,
	store_rm_r0_rn_indexed_l_M_1001_N_0111,
	mul_l_M_1001_N_0111,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_1001_N_0111,
	load_r0_rm_indexed_rn_w_M_1001_N_0111,
	load_r0_rm_indexed_rn_l_M_1001_N_0111,
	mac_l_M_1001_N_0111,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	store_rm_r0_rn_indexed_b_M_1010_N_0111,
	store_rm_r0_rn_indexed_w_M_1010_N_0111,
	store_rm_r0_rn_indexed_l_M_1010_N_0111,
	mul_l_M_1010_N_0111,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_1010_N_0111,
	load_r0_rm_indexed_rn_w_M_1010_N_0111,
	load_r0_rm_indexed_rn_l_M_1010_N_0111,
	mac_l_M_1010_N_0111,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	store_rm_r0_rn_indexed_b_M_1011_N_0111,
	store_rm_r0_rn_indexed_w_M_1011_N_0111,
	store_rm_r0_rn_indexed_l_M_1011_N_0111,
	mul_l_M_1011_N_0111,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_1011_N_0111,
	load_r0_rm_indexed_rn_w_M_1011_N_0111,
	load_r0_rm_indexed_rn_l_M_1011_N_0111,
	mac_l_M_1011_N_0111,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	store_rm_r0_rn_indexed_b_M_1100_N_0111,
	store_rm_r0_rn_indexed_w_M_1100_N_0111,
	store_rm_r0_rn_indexed_l_M_1100_N_0111,
	mul_l_M_1100_N_0111,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_1100_N_0111,
	load_r0_rm_indexed_rn_w_M_1100_N_0111,
	load_r0_rm_indexed_rn_l_M_1100_N_0111,
	mac_l_M_1100_N_0111,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	store_rm_r0_rn_indexed_b_M_1101_N_0111,
	store_rm_r0_rn_indexed_w_M_1101_N_0111,
	store_rm_r0_rn_indexed_l_M_1101_N_0111,
	mul_l_M_1101_N_0111,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_1101_N_0111,
	load_r0_rm_indexed_rn_w_M_1101_N_0111,
	load_r0_rm_indexed_rn_l_M_1101_N_0111,
	mac_l_M_1101_N_0111,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	store_rm_r0_rn_indexed_b_M_1110_N_0111,
	store_rm_r0_rn_indexed_w_M_1110_N_0111,
	store_rm_r0_rn_indexed_l_M_1110_N_0111,
	mul_l_M_1110_N_0111,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_1110_N_0111,
	load_r0_rm_indexed_rn_w_M_1110_N_0111,
	load_r0_rm_indexed_rn_l_M_1110_N_0111,
	mac_l_M_1110_N_0111,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	store_rm_r0_rn_indexed_b_M_1111_N_0111,
	store_rm_r0_rn_indexed_w_M_1111_N_0111,
	store_rm_r0_rn_indexed_l_M_1111_N_0111,
	mul_l_M_1111_N_0111,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_1111_N_0111,
	load_r0_rm_indexed_rn_w_M_1111_N_0111,
	load_r0_rm_indexed_rn_l_M_1111_N_0111,
	mac_l_M_1111_N_0111,
	unimplemented,
	unimplemented,
	stc_sr_rn_N_1000,
	bsrf_M_1000,
	store_rm_r0_rn_indexed_b_M_0000_N_1000,
	store_rm_r0_rn_indexed_w_M_0000_N_1000,
	store_rm_r0_rn_indexed_l_M_0000_N_1000,
	mul_l_M_0000_N_1000,
	unimplemented,
	unimplemented,
	sts_mach_rn_N_1000,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_0000_N_1000,
	load_r0_rm_indexed_rn_w_M_0000_N_1000,
	load_r0_rm_indexed_rn_l_M_0000_N_1000,
	mac_l_M_0000_N_1000,
	unimplemented,
	unimplemented,
	stc_gbr_rn_N_1000,
	unimplemented,
	store_rm_r0_rn_indexed_b_M_0001_N_1000,
	store_rm_r0_rn_indexed_w_M_0001_N_1000,
	store_rm_r0_rn_indexed_l_M_0001_N_1000,
	mul_l_M_0001_N_1000,
	unimplemented,
	unimplemented,
	sts_macl_rn_N_1000,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_0001_N_1000,
	load_r0_rm_indexed_rn_w_M_0001_N_1000,
	load_r0_rm_indexed_rn_l_M_0001_N_1000,
	mac_l_M_0001_N_1000,
	unimplemented,
	unimplemented,
	stc_vbr_rn_N_1000,
	braf_M_1000,
	store_rm_r0_rn_indexed_b_M_0010_N_1000,
	store_rm_r0_rn_indexed_w_M_0010_N_1000,
	store_rm_r0_rn_indexed_l_M_0010_N_1000,
	mul_l_M_0010_N_1000,
	unimplemented,
	movt_N_1000,
	sts_pr_rn_N_1000,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_0010_N_1000,
	load_r0_rm_indexed_rn_w_M_0010_N_1000,
	load_r0_rm_indexed_rn_l_M_0010_N_1000,
	mac_l_M_0010_N_1000,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	store_rm_r0_rn_indexed_b_M_0011_N_1000,
	store_rm_r0_rn_indexed_w_M_0011_N_1000,
	store_rm_r0_rn_indexed_l_M_0011_N_1000,
	mul_l_M_0011_N_1000,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_0011_N_1000,
	load_r0_rm_indexed_rn_w_M_0011_N_1000,
	load_r0_rm_indexed_rn_l_M_0011_N_1000,
	mac_l_M_0011_N_1000,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	store_rm_r0_rn_indexed_b_M_0100_N_1000,
	store_rm_r0_rn_indexed_w_M_0100_N_1000,
	store_rm_r0_rn_indexed_l_M_0100_N_1000,
	mul_l_M_0100_N_1000,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_0100_N_1000,
	load_r0_rm_indexed_rn_w_M_0100_N_1000,
	load_r0_rm_indexed_rn_l_M_0100_N_1000,
	mac_l_M_0100_N_1000,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	store_rm_r0_rn_indexed_b_M_0101_N_1000,
	store_rm_r0_rn_indexed_w_M_0101_N_1000,
	store_rm_r0_rn_indexed_l_M_0101_N_1000,
	mul_l_M_0101_N_1000,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_0101_N_1000,
	load_r0_rm_indexed_rn_w_M_0101_N_1000,
	load_r0_rm_indexed_rn_l_M_0101_N_1000,
	mac_l_M_0101_N_1000,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	store_rm_r0_rn_indexed_b_M_0110_N_1000,
	store_rm_r0_rn_indexed_w_M_0110_N_1000,
	store_rm_r0_rn_indexed_l_M_0110_N_1000,
	mul_l_M_0110_N_1000,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_0110_N_1000,
	load_r0_rm_indexed_rn_w_M_0110_N_1000,
	load_r0_rm_indexed_rn_l_M_0110_N_1000,
	mac_l_M_0110_N_1000,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	store_rm_r0_rn_indexed_b_M_0111_N_1000,
	store_rm_r0_rn_indexed_w_M_0111_N_1000,
	store_rm_r0_rn_indexed_l_M_0111_N_1000,
	mul_l_M_0111_N_1000,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_0111_N_1000,
	load_r0_rm_indexed_rn_w_M_0111_N_1000,
	load_r0_rm_indexed_rn_l_M_0111_N_1000,
	mac_l_M_0111_N_1000,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	store_rm_r0_rn_indexed_b_M_1000_N_1000,
	store_rm_r0_rn_indexed_w_M_1000_N_1000,
	store_rm_r0_rn_indexed_l_M_1000_N_1000,
	mul_l_M_1000_N_1000,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_1000_N_1000,
	load_r0_rm_indexed_rn_w_M_1000_N_1000,
	load_r0_rm_indexed_rn_l_M_1000_N_1000,
	mac_l_M_1000_N_1000,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	store_rm_r0_rn_indexed_b_M_1001_N_1000,
	store_rm_r0_rn_indexed_w_M_1001_N_1000,
	store_rm_r0_rn_indexed_l_M_1001_N_1000,
	mul_l_M_1001_N_1000,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_1001_N_1000,
	load_r0_rm_indexed_rn_w_M_1001_N_1000,
	load_r0_rm_indexed_rn_l_M_1001_N_1000,
	mac_l_M_1001_N_1000,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	store_rm_r0_rn_indexed_b_M_1010_N_1000,
	store_rm_r0_rn_indexed_w_M_1010_N_1000,
	store_rm_r0_rn_indexed_l_M_1010_N_1000,
	mul_l_M_1010_N_1000,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_1010_N_1000,
	load_r0_rm_indexed_rn_w_M_1010_N_1000,
	load_r0_rm_indexed_rn_l_M_1010_N_1000,
	mac_l_M_1010_N_1000,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	store_rm_r0_rn_indexed_b_M_1011_N_1000,
	store_rm_r0_rn_indexed_w_M_1011_N_1000,
	store_rm_r0_rn_indexed_l_M_1011_N_1000,
	mul_l_M_1011_N_1000,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_1011_N_1000,
	load_r0_rm_indexed_rn_w_M_1011_N_1000,
	load_r0_rm_indexed_rn_l_M_1011_N_1000,
	mac_l_M_1011_N_1000,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	store_rm_r0_rn_indexed_b_M_1100_N_1000,
	store_rm_r0_rn_indexed_w_M_1100_N_1000,
	store_rm_r0_rn_indexed_l_M_1100_N_1000,
	mul_l_M_1100_N_1000,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_1100_N_1000,
	load_r0_rm_indexed_rn_w_M_1100_N_1000,
	load_r0_rm_indexed_rn_l_M_1100_N_1000,
	mac_l_M_1100_N_1000,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	store_rm_r0_rn_indexed_b_M_1101_N_1000,
	store_rm_r0_rn_indexed_w_M_1101_N_1000,
	store_rm_r0_rn_indexed_l_M_1101_N_1000,
	mul_l_M_1101_N_1000,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_1101_N_1000,
	load_r0_rm_indexed_rn_w_M_1101_N_1000,
	load_r0_rm_indexed_rn_l_M_1101_N_1000,
	mac_l_M_1101_N_1000,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	store_rm_r0_rn_indexed_b_M_1110_N_1000,
	store_rm_r0_rn_indexed_w_M_1110_N_1000,
	store_rm_r0_rn_indexed_l_M_1110_N_1000,
	mul_l_M_1110_N_1000,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_1110_N_1000,
	load_r0_rm_indexed_rn_w_M_1110_N_1000,
	load_r0_rm_indexed_rn_l_M_1110_N_1000,
	mac_l_M_1110_N_1000,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	store_rm_r0_rn_indexed_b_M_1111_N_1000,
	store_rm_r0_rn_indexed_w_M_1111_N_1000,
	store_rm_r0_rn_indexed_l_M_1111_N_1000,
	mul_l_M_1111_N_1000,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_1111_N_1000,
	load_r0_rm_indexed_rn_w_M_1111_N_1000,
	load_r0_rm_indexed_rn_l_M_1111_N_1000,
	mac_l_M_1111_N_1000,
	unimplemented,
	unimplemented,
	stc_sr_rn_N_1001,
	bsrf_M_1001,
	store_rm_r0_rn_indexed_b_M_0000_N_1001,
	store_rm_r0_rn_indexed_w_M_0000_N_1001,
	store_rm_r0_rn_indexed_l_M_0000_N_1001,
	mul_l_M_0000_N_1001,
	unimplemented,
	unimplemented,
	sts_mach_rn_N_1001,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_0000_N_1001,
	load_r0_rm_indexed_rn_w_M_0000_N_1001,
	load_r0_rm_indexed_rn_l_M_0000_N_1001,
	mac_l_M_0000_N_1001,
	unimplemented,
	unimplemented,
	stc_gbr_rn_N_1001,
	unimplemented,
	store_rm_r0_rn_indexed_b_M_0001_N_1001,
	store_rm_r0_rn_indexed_w_M_0001_N_1001,
	store_rm_r0_rn_indexed_l_M_0001_N_1001,
	mul_l_M_0001_N_1001,
	unimplemented,
	unimplemented,
	sts_macl_rn_N_1001,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_0001_N_1001,
	load_r0_rm_indexed_rn_w_M_0001_N_1001,
	load_r0_rm_indexed_rn_l_M_0001_N_1001,
	mac_l_M_0001_N_1001,
	unimplemented,
	unimplemented,
	stc_vbr_rn_N_1001,
	braf_M_1001,
	store_rm_r0_rn_indexed_b_M_0010_N_1001,
	store_rm_r0_rn_indexed_w_M_0010_N_1001,
	store_rm_r0_rn_indexed_l_M_0010_N_1001,
	mul_l_M_0010_N_1001,
	unimplemented,
	movt_N_1001,
	sts_pr_rn_N_1001,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_0010_N_1001,
	load_r0_rm_indexed_rn_w_M_0010_N_1001,
	load_r0_rm_indexed_rn_l_M_0010_N_1001,
	mac_l_M_0010_N_1001,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	store_rm_r0_rn_indexed_b_M_0011_N_1001,
	store_rm_r0_rn_indexed_w_M_0011_N_1001,
	store_rm_r0_rn_indexed_l_M_0011_N_1001,
	mul_l_M_0011_N_1001,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_0011_N_1001,
	load_r0_rm_indexed_rn_w_M_0011_N_1001,
	load_r0_rm_indexed_rn_l_M_0011_N_1001,
	mac_l_M_0011_N_1001,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	store_rm_r0_rn_indexed_b_M_0100_N_1001,
	store_rm_r0_rn_indexed_w_M_0100_N_1001,
	store_rm_r0_rn_indexed_l_M_0100_N_1001,
	mul_l_M_0100_N_1001,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_0100_N_1001,
	load_r0_rm_indexed_rn_w_M_0100_N_1001,
	load_r0_rm_indexed_rn_l_M_0100_N_1001,
	mac_l_M_0100_N_1001,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	store_rm_r0_rn_indexed_b_M_0101_N_1001,
	store_rm_r0_rn_indexed_w_M_0101_N_1001,
	store_rm_r0_rn_indexed_l_M_0101_N_1001,
	mul_l_M_0101_N_1001,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_0101_N_1001,
	load_r0_rm_indexed_rn_w_M_0101_N_1001,
	load_r0_rm_indexed_rn_l_M_0101_N_1001,
	mac_l_M_0101_N_1001,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	store_rm_r0_rn_indexed_b_M_0110_N_1001,
	store_rm_r0_rn_indexed_w_M_0110_N_1001,
	store_rm_r0_rn_indexed_l_M_0110_N_1001,
	mul_l_M_0110_N_1001,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_0110_N_1001,
	load_r0_rm_indexed_rn_w_M_0110_N_1001,
	load_r0_rm_indexed_rn_l_M_0110_N_1001,
	mac_l_M_0110_N_1001,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	store_rm_r0_rn_indexed_b_M_0111_N_1001,
	store_rm_r0_rn_indexed_w_M_0111_N_1001,
	store_rm_r0_rn_indexed_l_M_0111_N_1001,
	mul_l_M_0111_N_1001,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_0111_N_1001,
	load_r0_rm_indexed_rn_w_M_0111_N_1001,
	load_r0_rm_indexed_rn_l_M_0111_N_1001,
	mac_l_M_0111_N_1001,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	store_rm_r0_rn_indexed_b_M_1000_N_1001,
	store_rm_r0_rn_indexed_w_M_1000_N_1001,
	store_rm_r0_rn_indexed_l_M_1000_N_1001,
	mul_l_M_1000_N_1001,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_1000_N_1001,
	load_r0_rm_indexed_rn_w_M_1000_N_1001,
	load_r0_rm_indexed_rn_l_M_1000_N_1001,
	mac_l_M_1000_N_1001,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	store_rm_r0_rn_indexed_b_M_1001_N_1001,
	store_rm_r0_rn_indexed_w_M_1001_N_1001,
	store_rm_r0_rn_indexed_l_M_1001_N_1001,
	mul_l_M_1001_N_1001,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_1001_N_1001,
	load_r0_rm_indexed_rn_w_M_1001_N_1001,
	load_r0_rm_indexed_rn_l_M_1001_N_1001,
	mac_l_M_1001_N_1001,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	store_rm_r0_rn_indexed_b_M_1010_N_1001,
	store_rm_r0_rn_indexed_w_M_1010_N_1001,
	store_rm_r0_rn_indexed_l_M_1010_N_1001,
	mul_l_M_1010_N_1001,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_1010_N_1001,
	load_r0_rm_indexed_rn_w_M_1010_N_1001,
	load_r0_rm_indexed_rn_l_M_1010_N_1001,
	mac_l_M_1010_N_1001,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	store_rm_r0_rn_indexed_b_M_1011_N_1001,
	store_rm_r0_rn_indexed_w_M_1011_N_1001,
	store_rm_r0_rn_indexed_l_M_1011_N_1001,
	mul_l_M_1011_N_1001,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_1011_N_1001,
	load_r0_rm_indexed_rn_w_M_1011_N_1001,
	load_r0_rm_indexed_rn_l_M_1011_N_1001,
	mac_l_M_1011_N_1001,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	store_rm_r0_rn_indexed_b_M_1100_N_1001,
	store_rm_r0_rn_indexed_w_M_1100_N_1001,
	store_rm_r0_rn_indexed_l_M_1100_N_1001,
	mul_l_M_1100_N_1001,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_1100_N_1001,
	load_r0_rm_indexed_rn_w_M_1100_N_1001,
	load_r0_rm_indexed_rn_l_M_1100_N_1001,
	mac_l_M_1100_N_1001,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	store_rm_r0_rn_indexed_b_M_1101_N_1001,
	store_rm_r0_rn_indexed_w_M_1101_N_1001,
	store_rm_r0_rn_indexed_l_M_1101_N_1001,
	mul_l_M_1101_N_1001,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_1101_N_1001,
	load_r0_rm_indexed_rn_w_M_1101_N_1001,
	load_r0_rm_indexed_rn_l_M_1101_N_1001,
	mac_l_M_1101_N_1001,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	store_rm_r0_rn_indexed_b_M_1110_N_1001,
	store_rm_r0_rn_indexed_w_M_1110_N_1001,
	store_rm_r0_rn_indexed_l_M_1110_N_1001,
	mul_l_M_1110_N_1001,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_1110_N_1001,
	load_r0_rm_indexed_rn_w_M_1110_N_1001,
	load_r0_rm_indexed_rn_l_M_1110_N_1001,
	mac_l_M_1110_N_1001,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	store_rm_r0_rn_indexed_b_M_1111_N_1001,
	store_rm_r0_rn_indexed_w_M_1111_N_1001,
	store_rm_r0_rn_indexed_l_M_1111_N_1001,
	mul_l_M_1111_N_1001,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_1111_N_1001,
	load_r0_rm_indexed_rn_w_M_1111_N_1001,
	load_r0_rm_indexed_rn_l_M_1111_N_1001,
	mac_l_M_1111_N_1001,
	unimplemented,
	unimplemented,
	stc_sr_rn_N_1010,
	bsrf_M_1010,
	store_rm_r0_rn_indexed_b_M_0000_N_1010,
	store_rm_r0_rn_indexed_w_M_0000_N_1010,
	store_rm_r0_rn_indexed_l_M_0000_N_1010,
	mul_l_M_0000_N_1010,
	unimplemented,
	unimplemented,
	sts_mach_rn_N_1010,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_0000_N_1010,
	load_r0_rm_indexed_rn_w_M_0000_N_1010,
	load_r0_rm_indexed_rn_l_M_0000_N_1010,
	mac_l_M_0000_N_1010,
	unimplemented,
	unimplemented,
	stc_gbr_rn_N_1010,
	unimplemented,
	store_rm_r0_rn_indexed_b_M_0001_N_1010,
	store_rm_r0_rn_indexed_w_M_0001_N_1010,
	store_rm_r0_rn_indexed_l_M_0001_N_1010,
	mul_l_M_0001_N_1010,
	unimplemented,
	unimplemented,
	sts_macl_rn_N_1010,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_0001_N_1010,
	load_r0_rm_indexed_rn_w_M_0001_N_1010,
	load_r0_rm_indexed_rn_l_M_0001_N_1010,
	mac_l_M_0001_N_1010,
	unimplemented,
	unimplemented,
	stc_vbr_rn_N_1010,
	braf_M_1010,
	store_rm_r0_rn_indexed_b_M_0010_N_1010,
	store_rm_r0_rn_indexed_w_M_0010_N_1010,
	store_rm_r0_rn_indexed_l_M_0010_N_1010,
	mul_l_M_0010_N_1010,
	unimplemented,
	movt_N_1010,
	sts_pr_rn_N_1010,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_0010_N_1010,
	load_r0_rm_indexed_rn_w_M_0010_N_1010,
	load_r0_rm_indexed_rn_l_M_0010_N_1010,
	mac_l_M_0010_N_1010,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	store_rm_r0_rn_indexed_b_M_0011_N_1010,
	store_rm_r0_rn_indexed_w_M_0011_N_1010,
	store_rm_r0_rn_indexed_l_M_0011_N_1010,
	mul_l_M_0011_N_1010,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_0011_N_1010,
	load_r0_rm_indexed_rn_w_M_0011_N_1010,
	load_r0_rm_indexed_rn_l_M_0011_N_1010,
	mac_l_M_0011_N_1010,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	store_rm_r0_rn_indexed_b_M_0100_N_1010,
	store_rm_r0_rn_indexed_w_M_0100_N_1010,
	store_rm_r0_rn_indexed_l_M_0100_N_1010,
	mul_l_M_0100_N_1010,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_0100_N_1010,
	load_r0_rm_indexed_rn_w_M_0100_N_1010,
	load_r0_rm_indexed_rn_l_M_0100_N_1010,
	mac_l_M_0100_N_1010,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	store_rm_r0_rn_indexed_b_M_0101_N_1010,
	store_rm_r0_rn_indexed_w_M_0101_N_1010,
	store_rm_r0_rn_indexed_l_M_0101_N_1010,
	mul_l_M_0101_N_1010,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_0101_N_1010,
	load_r0_rm_indexed_rn_w_M_0101_N_1010,
	load_r0_rm_indexed_rn_l_M_0101_N_1010,
	mac_l_M_0101_N_1010,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	store_rm_r0_rn_indexed_b_M_0110_N_1010,
	store_rm_r0_rn_indexed_w_M_0110_N_1010,
	store_rm_r0_rn_indexed_l_M_0110_N_1010,
	mul_l_M_0110_N_1010,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_0110_N_1010,
	load_r0_rm_indexed_rn_w_M_0110_N_1010,
	load_r0_rm_indexed_rn_l_M_0110_N_1010,
	mac_l_M_0110_N_1010,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	store_rm_r0_rn_indexed_b_M_0111_N_1010,
	store_rm_r0_rn_indexed_w_M_0111_N_1010,
	store_rm_r0_rn_indexed_l_M_0111_N_1010,
	mul_l_M_0111_N_1010,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_0111_N_1010,
	load_r0_rm_indexed_rn_w_M_0111_N_1010,
	load_r0_rm_indexed_rn_l_M_0111_N_1010,
	mac_l_M_0111_N_1010,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	store_rm_r0_rn_indexed_b_M_1000_N_1010,
	store_rm_r0_rn_indexed_w_M_1000_N_1010,
	store_rm_r0_rn_indexed_l_M_1000_N_1010,
	mul_l_M_1000_N_1010,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_1000_N_1010,
	load_r0_rm_indexed_rn_w_M_1000_N_1010,
	load_r0_rm_indexed_rn_l_M_1000_N_1010,
	mac_l_M_1000_N_1010,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	store_rm_r0_rn_indexed_b_M_1001_N_1010,
	store_rm_r0_rn_indexed_w_M_1001_N_1010,
	store_rm_r0_rn_indexed_l_M_1001_N_1010,
	mul_l_M_1001_N_1010,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_1001_N_1010,
	load_r0_rm_indexed_rn_w_M_1001_N_1010,
	load_r0_rm_indexed_rn_l_M_1001_N_1010,
	mac_l_M_1001_N_1010,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	store_rm_r0_rn_indexed_b_M_1010_N_1010,
	store_rm_r0_rn_indexed_w_M_1010_N_1010,
	store_rm_r0_rn_indexed_l_M_1010_N_1010,
	mul_l_M_1010_N_1010,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_1010_N_1010,
	load_r0_rm_indexed_rn_w_M_1010_N_1010,
	load_r0_rm_indexed_rn_l_M_1010_N_1010,
	mac_l_M_1010_N_1010,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	store_rm_r0_rn_indexed_b_M_1011_N_1010,
	store_rm_r0_rn_indexed_w_M_1011_N_1010,
	store_rm_r0_rn_indexed_l_M_1011_N_1010,
	mul_l_M_1011_N_1010,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_1011_N_1010,
	load_r0_rm_indexed_rn_w_M_1011_N_1010,
	load_r0_rm_indexed_rn_l_M_1011_N_1010,
	mac_l_M_1011_N_1010,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	store_rm_r0_rn_indexed_b_M_1100_N_1010,
	store_rm_r0_rn_indexed_w_M_1100_N_1010,
	store_rm_r0_rn_indexed_l_M_1100_N_1010,
	mul_l_M_1100_N_1010,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_1100_N_1010,
	load_r0_rm_indexed_rn_w_M_1100_N_1010,
	load_r0_rm_indexed_rn_l_M_1100_N_1010,
	mac_l_M_1100_N_1010,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	store_rm_r0_rn_indexed_b_M_1101_N_1010,
	store_rm_r0_rn_indexed_w_M_1101_N_1010,
	store_rm_r0_rn_indexed_l_M_1101_N_1010,
	mul_l_M_1101_N_1010,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_1101_N_1010,
	load_r0_rm_indexed_rn_w_M_1101_N_1010,
	load_r0_rm_indexed_rn_l_M_1101_N_1010,
	mac_l_M_1101_N_1010,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	store_rm_r0_rn_indexed_b_M_1110_N_1010,
	store_rm_r0_rn_indexed_w_M_1110_N_1010,
	store_rm_r0_rn_indexed_l_M_1110_N_1010,
	mul_l_M_1110_N_1010,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_1110_N_1010,
	load_r0_rm_indexed_rn_w_M_1110_N_1010,
	load_r0_rm_indexed_rn_l_M_1110_N_1010,
	mac_l_M_1110_N_1010,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	store_rm_r0_rn_indexed_b_M_1111_N_1010,
	store_rm_r0_rn_indexed_w_M_1111_N_1010,
	store_rm_r0_rn_indexed_l_M_1111_N_1010,
	mul_l_M_1111_N_1010,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_1111_N_1010,
	load_r0_rm_indexed_rn_w_M_1111_N_1010,
	load_r0_rm_indexed_rn_l_M_1111_N_1010,
	mac_l_M_1111_N_1010,
	unimplemented,
	unimplemented,
	stc_sr_rn_N_1011,
	bsrf_M_1011,
	store_rm_r0_rn_indexed_b_M_0000_N_1011,
	store_rm_r0_rn_indexed_w_M_0000_N_1011,
	store_rm_r0_rn_indexed_l_M_0000_N_1011,
	mul_l_M_0000_N_1011,
	unimplemented,
	unimplemented,
	sts_mach_rn_N_1011,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_0000_N_1011,
	load_r0_rm_indexed_rn_w_M_0000_N_1011,
	load_r0_rm_indexed_rn_l_M_0000_N_1011,
	mac_l_M_0000_N_1011,
	unimplemented,
	unimplemented,
	stc_gbr_rn_N_1011,
	unimplemented,
	store_rm_r0_rn_indexed_b_M_0001_N_1011,
	store_rm_r0_rn_indexed_w_M_0001_N_1011,
	store_rm_r0_rn_indexed_l_M_0001_N_1011,
	mul_l_M_0001_N_1011,
	unimplemented,
	unimplemented,
	sts_macl_rn_N_1011,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_0001_N_1011,
	load_r0_rm_indexed_rn_w_M_0001_N_1011,
	load_r0_rm_indexed_rn_l_M_0001_N_1011,
	mac_l_M_0001_N_1011,
	unimplemented,
	unimplemented,
	stc_vbr_rn_N_1011,
	braf_M_1011,
	store_rm_r0_rn_indexed_b_M_0010_N_1011,
	store_rm_r0_rn_indexed_w_M_0010_N_1011,
	store_rm_r0_rn_indexed_l_M_0010_N_1011,
	mul_l_M_0010_N_1011,
	unimplemented,
	movt_N_1011,
	sts_pr_rn_N_1011,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_0010_N_1011,
	load_r0_rm_indexed_rn_w_M_0010_N_1011,
	load_r0_rm_indexed_rn_l_M_0010_N_1011,
	mac_l_M_0010_N_1011,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	store_rm_r0_rn_indexed_b_M_0011_N_1011,
	store_rm_r0_rn_indexed_w_M_0011_N_1011,
	store_rm_r0_rn_indexed_l_M_0011_N_1011,
	mul_l_M_0011_N_1011,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_0011_N_1011,
	load_r0_rm_indexed_rn_w_M_0011_N_1011,
	load_r0_rm_indexed_rn_l_M_0011_N_1011,
	mac_l_M_0011_N_1011,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	store_rm_r0_rn_indexed_b_M_0100_N_1011,
	store_rm_r0_rn_indexed_w_M_0100_N_1011,
	store_rm_r0_rn_indexed_l_M_0100_N_1011,
	mul_l_M_0100_N_1011,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_0100_N_1011,
	load_r0_rm_indexed_rn_w_M_0100_N_1011,
	load_r0_rm_indexed_rn_l_M_0100_N_1011,
	mac_l_M_0100_N_1011,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	store_rm_r0_rn_indexed_b_M_0101_N_1011,
	store_rm_r0_rn_indexed_w_M_0101_N_1011,
	store_rm_r0_rn_indexed_l_M_0101_N_1011,
	mul_l_M_0101_N_1011,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_0101_N_1011,
	load_r0_rm_indexed_rn_w_M_0101_N_1011,
	load_r0_rm_indexed_rn_l_M_0101_N_1011,
	mac_l_M_0101_N_1011,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	store_rm_r0_rn_indexed_b_M_0110_N_1011,
	store_rm_r0_rn_indexed_w_M_0110_N_1011,
	store_rm_r0_rn_indexed_l_M_0110_N_1011,
	mul_l_M_0110_N_1011,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_0110_N_1011,
	load_r0_rm_indexed_rn_w_M_0110_N_1011,
	load_r0_rm_indexed_rn_l_M_0110_N_1011,
	mac_l_M_0110_N_1011,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	store_rm_r0_rn_indexed_b_M_0111_N_1011,
	store_rm_r0_rn_indexed_w_M_0111_N_1011,
	store_rm_r0_rn_indexed_l_M_0111_N_1011,
	mul_l_M_0111_N_1011,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_0111_N_1011,
	load_r0_rm_indexed_rn_w_M_0111_N_1011,
	load_r0_rm_indexed_rn_l_M_0111_N_1011,
	mac_l_M_0111_N_1011,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	store_rm_r0_rn_indexed_b_M_1000_N_1011,
	store_rm_r0_rn_indexed_w_M_1000_N_1011,
	store_rm_r0_rn_indexed_l_M_1000_N_1011,
	mul_l_M_1000_N_1011,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_1000_N_1011,
	load_r0_rm_indexed_rn_w_M_1000_N_1011,
	load_r0_rm_indexed_rn_l_M_1000_N_1011,
	mac_l_M_1000_N_1011,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	store_rm_r0_rn_indexed_b_M_1001_N_1011,
	store_rm_r0_rn_indexed_w_M_1001_N_1011,
	store_rm_r0_rn_indexed_l_M_1001_N_1011,
	mul_l_M_1001_N_1011,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_1001_N_1011,
	load_r0_rm_indexed_rn_w_M_1001_N_1011,
	load_r0_rm_indexed_rn_l_M_1001_N_1011,
	mac_l_M_1001_N_1011,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	store_rm_r0_rn_indexed_b_M_1010_N_1011,
	store_rm_r0_rn_indexed_w_M_1010_N_1011,
	store_rm_r0_rn_indexed_l_M_1010_N_1011,
	mul_l_M_1010_N_1011,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_1010_N_1011,
	load_r0_rm_indexed_rn_w_M_1010_N_1011,
	load_r0_rm_indexed_rn_l_M_1010_N_1011,
	mac_l_M_1010_N_1011,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	store_rm_r0_rn_indexed_b_M_1011_N_1011,
	store_rm_r0_rn_indexed_w_M_1011_N_1011,
	store_rm_r0_rn_indexed_l_M_1011_N_1011,
	mul_l_M_1011_N_1011,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_1011_N_1011,
	load_r0_rm_indexed_rn_w_M_1011_N_1011,
	load_r0_rm_indexed_rn_l_M_1011_N_1011,
	mac_l_M_1011_N_1011,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	store_rm_r0_rn_indexed_b_M_1100_N_1011,
	store_rm_r0_rn_indexed_w_M_1100_N_1011,
	store_rm_r0_rn_indexed_l_M_1100_N_1011,
	mul_l_M_1100_N_1011,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_1100_N_1011,
	load_r0_rm_indexed_rn_w_M_1100_N_1011,
	load_r0_rm_indexed_rn_l_M_1100_N_1011,
	mac_l_M_1100_N_1011,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	store_rm_r0_rn_indexed_b_M_1101_N_1011,
	store_rm_r0_rn_indexed_w_M_1101_N_1011,
	store_rm_r0_rn_indexed_l_M_1101_N_1011,
	mul_l_M_1101_N_1011,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_1101_N_1011,
	load_r0_rm_indexed_rn_w_M_1101_N_1011,
	load_r0_rm_indexed_rn_l_M_1101_N_1011,
	mac_l_M_1101_N_1011,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	store_rm_r0_rn_indexed_b_M_1110_N_1011,
	store_rm_r0_rn_indexed_w_M_1110_N_1011,
	store_rm_r0_rn_indexed_l_M_1110_N_1011,
	mul_l_M_1110_N_1011,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_1110_N_1011,
	load_r0_rm_indexed_rn_w_M_1110_N_1011,
	load_r0_rm_indexed_rn_l_M_1110_N_1011,
	mac_l_M_1110_N_1011,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	store_rm_r0_rn_indexed_b_M_1111_N_1011,
	store_rm_r0_rn_indexed_w_M_1111_N_1011,
	store_rm_r0_rn_indexed_l_M_1111_N_1011,
	mul_l_M_1111_N_1011,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_1111_N_1011,
	load_r0_rm_indexed_rn_w_M_1111_N_1011,
	load_r0_rm_indexed_rn_l_M_1111_N_1011,
	mac_l_M_1111_N_1011,
	unimplemented,
	unimplemented,
	stc_sr_rn_N_1100,
	bsrf_M_1100,
	store_rm_r0_rn_indexed_b_M_0000_N_1100,
	store_rm_r0_rn_indexed_w_M_0000_N_1100,
	store_rm_r0_rn_indexed_l_M_0000_N_1100,
	mul_l_M_0000_N_1100,
	unimplemented,
	unimplemented,
	sts_mach_rn_N_1100,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_0000_N_1100,
	load_r0_rm_indexed_rn_w_M_0000_N_1100,
	load_r0_rm_indexed_rn_l_M_0000_N_1100,
	mac_l_M_0000_N_1100,
	unimplemented,
	unimplemented,
	stc_gbr_rn_N_1100,
	unimplemented,
	store_rm_r0_rn_indexed_b_M_0001_N_1100,
	store_rm_r0_rn_indexed_w_M_0001_N_1100,
	store_rm_r0_rn_indexed_l_M_0001_N_1100,
	mul_l_M_0001_N_1100,
	unimplemented,
	unimplemented,
	sts_macl_rn_N_1100,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_0001_N_1100,
	load_r0_rm_indexed_rn_w_M_0001_N_1100,
	load_r0_rm_indexed_rn_l_M_0001_N_1100,
	mac_l_M_0001_N_1100,
	unimplemented,
	unimplemented,
	stc_vbr_rn_N_1100,
	braf_M_1100,
	store_rm_r0_rn_indexed_b_M_0010_N_1100,
	store_rm_r0_rn_indexed_w_M_0010_N_1100,
	store_rm_r0_rn_indexed_l_M_0010_N_1100,
	mul_l_M_0010_N_1100,
	unimplemented,
	movt_N_1100,
	sts_pr_rn_N_1100,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_0010_N_1100,
	load_r0_rm_indexed_rn_w_M_0010_N_1100,
	load_r0_rm_indexed_rn_l_M_0010_N_1100,
	mac_l_M_0010_N_1100,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	store_rm_r0_rn_indexed_b_M_0011_N_1100,
	store_rm_r0_rn_indexed_w_M_0011_N_1100,
	store_rm_r0_rn_indexed_l_M_0011_N_1100,
	mul_l_M_0011_N_1100,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_0011_N_1100,
	load_r0_rm_indexed_rn_w_M_0011_N_1100,
	load_r0_rm_indexed_rn_l_M_0011_N_1100,
	mac_l_M_0011_N_1100,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	store_rm_r0_rn_indexed_b_M_0100_N_1100,
	store_rm_r0_rn_indexed_w_M_0100_N_1100,
	store_rm_r0_rn_indexed_l_M_0100_N_1100,
	mul_l_M_0100_N_1100,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_0100_N_1100,
	load_r0_rm_indexed_rn_w_M_0100_N_1100,
	load_r0_rm_indexed_rn_l_M_0100_N_1100,
	mac_l_M_0100_N_1100,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	store_rm_r0_rn_indexed_b_M_0101_N_1100,
	store_rm_r0_rn_indexed_w_M_0101_N_1100,
	store_rm_r0_rn_indexed_l_M_0101_N_1100,
	mul_l_M_0101_N_1100,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_0101_N_1100,
	load_r0_rm_indexed_rn_w_M_0101_N_1100,
	load_r0_rm_indexed_rn_l_M_0101_N_1100,
	mac_l_M_0101_N_1100,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	store_rm_r0_rn_indexed_b_M_0110_N_1100,
	store_rm_r0_rn_indexed_w_M_0110_N_1100,
	store_rm_r0_rn_indexed_l_M_0110_N_1100,
	mul_l_M_0110_N_1100,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_0110_N_1100,
	load_r0_rm_indexed_rn_w_M_0110_N_1100,
	load_r0_rm_indexed_rn_l_M_0110_N_1100,
	mac_l_M_0110_N_1100,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	store_rm_r0_rn_indexed_b_M_0111_N_1100,
	store_rm_r0_rn_indexed_w_M_0111_N_1100,
	store_rm_r0_rn_indexed_l_M_0111_N_1100,
	mul_l_M_0111_N_1100,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_0111_N_1100,
	load_r0_rm_indexed_rn_w_M_0111_N_1100,
	load_r0_rm_indexed_rn_l_M_0111_N_1100,
	mac_l_M_0111_N_1100,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	store_rm_r0_rn_indexed_b_M_1000_N_1100,
	store_rm_r0_rn_indexed_w_M_1000_N_1100,
	store_rm_r0_rn_indexed_l_M_1000_N_1100,
	mul_l_M_1000_N_1100,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_1000_N_1100,
	load_r0_rm_indexed_rn_w_M_1000_N_1100,
	load_r0_rm_indexed_rn_l_M_1000_N_1100,
	mac_l_M_1000_N_1100,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	store_rm_r0_rn_indexed_b_M_1001_N_1100,
	store_rm_r0_rn_indexed_w_M_1001_N_1100,
	store_rm_r0_rn_indexed_l_M_1001_N_1100,
	mul_l_M_1001_N_1100,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_1001_N_1100,
	load_r0_rm_indexed_rn_w_M_1001_N_1100,
	load_r0_rm_indexed_rn_l_M_1001_N_1100,
	mac_l_M_1001_N_1100,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	store_rm_r0_rn_indexed_b_M_1010_N_1100,
	store_rm_r0_rn_indexed_w_M_1010_N_1100,
	store_rm_r0_rn_indexed_l_M_1010_N_1100,
	mul_l_M_1010_N_1100,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_1010_N_1100,
	load_r0_rm_indexed_rn_w_M_1010_N_1100,
	load_r0_rm_indexed_rn_l_M_1010_N_1100,
	mac_l_M_1010_N_1100,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	store_rm_r0_rn_indexed_b_M_1011_N_1100,
	store_rm_r0_rn_indexed_w_M_1011_N_1100,
	store_rm_r0_rn_indexed_l_M_1011_N_1100,
	mul_l_M_1011_N_1100,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_1011_N_1100,
	load_r0_rm_indexed_rn_w_M_1011_N_1100,
	load_r0_rm_indexed_rn_l_M_1011_N_1100,
	mac_l_M_1011_N_1100,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	store_rm_r0_rn_indexed_b_M_1100_N_1100,
	store_rm_r0_rn_indexed_w_M_1100_N_1100,
	store_rm_r0_rn_indexed_l_M_1100_N_1100,
	mul_l_M_1100_N_1100,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_1100_N_1100,
	load_r0_rm_indexed_rn_w_M_1100_N_1100,
	load_r0_rm_indexed_rn_l_M_1100_N_1100,
	mac_l_M_1100_N_1100,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	store_rm_r0_rn_indexed_b_M_1101_N_1100,
	store_rm_r0_rn_indexed_w_M_1101_N_1100,
	store_rm_r0_rn_indexed_l_M_1101_N_1100,
	mul_l_M_1101_N_1100,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_1101_N_1100,
	load_r0_rm_indexed_rn_w_M_1101_N_1100,
	load_r0_rm_indexed_rn_l_M_1101_N_1100,
	mac_l_M_1101_N_1100,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	store_rm_r0_rn_indexed_b_M_1110_N_1100,
	store_rm_r0_rn_indexed_w_M_1110_N_1100,
	store_rm_r0_rn_indexed_l_M_1110_N_1100,
	mul_l_M_1110_N_1100,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_1110_N_1100,
	load_r0_rm_indexed_rn_w_M_1110_N_1100,
	load_r0_rm_indexed_rn_l_M_1110_N_1100,
	mac_l_M_1110_N_1100,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	store_rm_r0_rn_indexed_b_M_1111_N_1100,
	store_rm_r0_rn_indexed_w_M_1111_N_1100,
	store_rm_r0_rn_indexed_l_M_1111_N_1100,
	mul_l_M_1111_N_1100,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_1111_N_1100,
	load_r0_rm_indexed_rn_w_M_1111_N_1100,
	load_r0_rm_indexed_rn_l_M_1111_N_1100,
	mac_l_M_1111_N_1100,
	unimplemented,
	unimplemented,
	stc_sr_rn_N_1101,
	bsrf_M_1101,
	store_rm_r0_rn_indexed_b_M_0000_N_1101,
	store_rm_r0_rn_indexed_w_M_0000_N_1101,
	store_rm_r0_rn_indexed_l_M_0000_N_1101,
	mul_l_M_0000_N_1101,
	unimplemented,
	unimplemented,
	sts_mach_rn_N_1101,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_0000_N_1101,
	load_r0_rm_indexed_rn_w_M_0000_N_1101,
	load_r0_rm_indexed_rn_l_M_0000_N_1101,
	mac_l_M_0000_N_1101,
	unimplemented,
	unimplemented,
	stc_gbr_rn_N_1101,
	unimplemented,
	store_rm_r0_rn_indexed_b_M_0001_N_1101,
	store_rm_r0_rn_indexed_w_M_0001_N_1101,
	store_rm_r0_rn_indexed_l_M_0001_N_1101,
	mul_l_M_0001_N_1101,
	unimplemented,
	unimplemented,
	sts_macl_rn_N_1101,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_0001_N_1101,
	load_r0_rm_indexed_rn_w_M_0001_N_1101,
	load_r0_rm_indexed_rn_l_M_0001_N_1101,
	mac_l_M_0001_N_1101,
	unimplemented,
	unimplemented,
	stc_vbr_rn_N_1101,
	braf_M_1101,
	store_rm_r0_rn_indexed_b_M_0010_N_1101,
	store_rm_r0_rn_indexed_w_M_0010_N_1101,
	store_rm_r0_rn_indexed_l_M_0010_N_1101,
	mul_l_M_0010_N_1101,
	unimplemented,
	movt_N_1101,
	sts_pr_rn_N_1101,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_0010_N_1101,
	load_r0_rm_indexed_rn_w_M_0010_N_1101,
	load_r0_rm_indexed_rn_l_M_0010_N_1101,
	mac_l_M_0010_N_1101,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	store_rm_r0_rn_indexed_b_M_0011_N_1101,
	store_rm_r0_rn_indexed_w_M_0011_N_1101,
	store_rm_r0_rn_indexed_l_M_0011_N_1101,
	mul_l_M_0011_N_1101,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_0011_N_1101,
	load_r0_rm_indexed_rn_w_M_0011_N_1101,
	load_r0_rm_indexed_rn_l_M_0011_N_1101,
	mac_l_M_0011_N_1101,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	store_rm_r0_rn_indexed_b_M_0100_N_1101,
	store_rm_r0_rn_indexed_w_M_0100_N_1101,
	store_rm_r0_rn_indexed_l_M_0100_N_1101,
	mul_l_M_0100_N_1101,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_0100_N_1101,
	load_r0_rm_indexed_rn_w_M_0100_N_1101,
	load_r0_rm_indexed_rn_l_M_0100_N_1101,
	mac_l_M_0100_N_1101,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	store_rm_r0_rn_indexed_b_M_0101_N_1101,
	store_rm_r0_rn_indexed_w_M_0101_N_1101,
	store_rm_r0_rn_indexed_l_M_0101_N_1101,
	mul_l_M_0101_N_1101,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_0101_N_1101,
	load_r0_rm_indexed_rn_w_M_0101_N_1101,
	load_r0_rm_indexed_rn_l_M_0101_N_1101,
	mac_l_M_0101_N_1101,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	store_rm_r0_rn_indexed_b_M_0110_N_1101,
	store_rm_r0_rn_indexed_w_M_0110_N_1101,
	store_rm_r0_rn_indexed_l_M_0110_N_1101,
	mul_l_M_0110_N_1101,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_0110_N_1101,
	load_r0_rm_indexed_rn_w_M_0110_N_1101,
	load_r0_rm_indexed_rn_l_M_0110_N_1101,
	mac_l_M_0110_N_1101,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	store_rm_r0_rn_indexed_b_M_0111_N_1101,
	store_rm_r0_rn_indexed_w_M_0111_N_1101,
	store_rm_r0_rn_indexed_l_M_0111_N_1101,
	mul_l_M_0111_N_1101,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_0111_N_1101,
	load_r0_rm_indexed_rn_w_M_0111_N_1101,
	load_r0_rm_indexed_rn_l_M_0111_N_1101,
	mac_l_M_0111_N_1101,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	store_rm_r0_rn_indexed_b_M_1000_N_1101,
	store_rm_r0_rn_indexed_w_M_1000_N_1101,
	store_rm_r0_rn_indexed_l_M_1000_N_1101,
	mul_l_M_1000_N_1101,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_1000_N_1101,
	load_r0_rm_indexed_rn_w_M_1000_N_1101,
	load_r0_rm_indexed_rn_l_M_1000_N_1101,
	mac_l_M_1000_N_1101,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	store_rm_r0_rn_indexed_b_M_1001_N_1101,
	store_rm_r0_rn_indexed_w_M_1001_N_1101,
	store_rm_r0_rn_indexed_l_M_1001_N_1101,
	mul_l_M_1001_N_1101,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_1001_N_1101,
	load_r0_rm_indexed_rn_w_M_1001_N_1101,
	load_r0_rm_indexed_rn_l_M_1001_N_1101,
	mac_l_M_1001_N_1101,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	store_rm_r0_rn_indexed_b_M_1010_N_1101,
	store_rm_r0_rn_indexed_w_M_1010_N_1101,
	store_rm_r0_rn_indexed_l_M_1010_N_1101,
	mul_l_M_1010_N_1101,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_1010_N_1101,
	load_r0_rm_indexed_rn_w_M_1010_N_1101,
	load_r0_rm_indexed_rn_l_M_1010_N_1101,
	mac_l_M_1010_N_1101,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	store_rm_r0_rn_indexed_b_M_1011_N_1101,
	store_rm_r0_rn_indexed_w_M_1011_N_1101,
	store_rm_r0_rn_indexed_l_M_1011_N_1101,
	mul_l_M_1011_N_1101,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_1011_N_1101,
	load_r0_rm_indexed_rn_w_M_1011_N_1101,
	load_r0_rm_indexed_rn_l_M_1011_N_1101,
	mac_l_M_1011_N_1101,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	store_rm_r0_rn_indexed_b_M_1100_N_1101,
	store_rm_r0_rn_indexed_w_M_1100_N_1101,
	store_rm_r0_rn_indexed_l_M_1100_N_1101,
	mul_l_M_1100_N_1101,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_1100_N_1101,
	load_r0_rm_indexed_rn_w_M_1100_N_1101,
	load_r0_rm_indexed_rn_l_M_1100_N_1101,
	mac_l_M_1100_N_1101,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	store_rm_r0_rn_indexed_b_M_1101_N_1101,
	store_rm_r0_rn_indexed_w_M_1101_N_1101,
	store_rm_r0_rn_indexed_l_M_1101_N_1101,
	mul_l_M_1101_N_1101,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_1101_N_1101,
	load_r0_rm_indexed_rn_w_M_1101_N_1101,
	load_r0_rm_indexed_rn_l_M_1101_N_1101,
	mac_l_M_1101_N_1101,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	store_rm_r0_rn_indexed_b_M_1110_N_1101,
	store_rm_r0_rn_indexed_w_M_1110_N_1101,
	store_rm_r0_rn_indexed_l_M_1110_N_1101,
	mul_l_M_1110_N_1101,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_1110_N_1101,
	load_r0_rm_indexed_rn_w_M_1110_N_1101,
	load_r0_rm_indexed_rn_l_M_1110_N_1101,
	mac_l_M_1110_N_1101,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	store_rm_r0_rn_indexed_b_M_1111_N_1101,
	store_rm_r0_rn_indexed_w_M_1111_N_1101,
	store_rm_r0_rn_indexed_l_M_1111_N_1101,
	mul_l_M_1111_N_1101,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_1111_N_1101,
	load_r0_rm_indexed_rn_w_M_1111_N_1101,
	load_r0_rm_indexed_rn_l_M_1111_N_1101,
	mac_l_M_1111_N_1101,
	unimplemented,
	unimplemented,
	stc_sr_rn_N_1110,
	bsrf_M_1110,
	store_rm_r0_rn_indexed_b_M_0000_N_1110,
	store_rm_r0_rn_indexed_w_M_0000_N_1110,
	store_rm_r0_rn_indexed_l_M_0000_N_1110,
	mul_l_M_0000_N_1110,
	unimplemented,
	unimplemented,
	sts_mach_rn_N_1110,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_0000_N_1110,
	load_r0_rm_indexed_rn_w_M_0000_N_1110,
	load_r0_rm_indexed_rn_l_M_0000_N_1110,
	mac_l_M_0000_N_1110,
	unimplemented,
	unimplemented,
	stc_gbr_rn_N_1110,
	unimplemented,
	store_rm_r0_rn_indexed_b_M_0001_N_1110,
	store_rm_r0_rn_indexed_w_M_0001_N_1110,
	store_rm_r0_rn_indexed_l_M_0001_N_1110,
	mul_l_M_0001_N_1110,
	unimplemented,
	unimplemented,
	sts_macl_rn_N_1110,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_0001_N_1110,
	load_r0_rm_indexed_rn_w_M_0001_N_1110,
	load_r0_rm_indexed_rn_l_M_0001_N_1110,
	mac_l_M_0001_N_1110,
	unimplemented,
	unimplemented,
	stc_vbr_rn_N_1110,
	braf_M_1110,
	store_rm_r0_rn_indexed_b_M_0010_N_1110,
	store_rm_r0_rn_indexed_w_M_0010_N_1110,
	store_rm_r0_rn_indexed_l_M_0010_N_1110,
	mul_l_M_0010_N_1110,
	unimplemented,
	movt_N_1110,
	sts_pr_rn_N_1110,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_0010_N_1110,
	load_r0_rm_indexed_rn_w_M_0010_N_1110,
	load_r0_rm_indexed_rn_l_M_0010_N_1110,
	mac_l_M_0010_N_1110,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	store_rm_r0_rn_indexed_b_M_0011_N_1110,
	store_rm_r0_rn_indexed_w_M_0011_N_1110,
	store_rm_r0_rn_indexed_l_M_0011_N_1110,
	mul_l_M_0011_N_1110,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_0011_N_1110,
	load_r0_rm_indexed_rn_w_M_0011_N_1110,
	load_r0_rm_indexed_rn_l_M_0011_N_1110,
	mac_l_M_0011_N_1110,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	store_rm_r0_rn_indexed_b_M_0100_N_1110,
	store_rm_r0_rn_indexed_w_M_0100_N_1110,
	store_rm_r0_rn_indexed_l_M_0100_N_1110,
	mul_l_M_0100_N_1110,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_0100_N_1110,
	load_r0_rm_indexed_rn_w_M_0100_N_1110,
	load_r0_rm_indexed_rn_l_M_0100_N_1110,
	mac_l_M_0100_N_1110,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	store_rm_r0_rn_indexed_b_M_0101_N_1110,
	store_rm_r0_rn_indexed_w_M_0101_N_1110,
	store_rm_r0_rn_indexed_l_M_0101_N_1110,
	mul_l_M_0101_N_1110,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_0101_N_1110,
	load_r0_rm_indexed_rn_w_M_0101_N_1110,
	load_r0_rm_indexed_rn_l_M_0101_N_1110,
	mac_l_M_0101_N_1110,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	store_rm_r0_rn_indexed_b_M_0110_N_1110,
	store_rm_r0_rn_indexed_w_M_0110_N_1110,
	store_rm_r0_rn_indexed_l_M_0110_N_1110,
	mul_l_M_0110_N_1110,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_0110_N_1110,
	load_r0_rm_indexed_rn_w_M_0110_N_1110,
	load_r0_rm_indexed_rn_l_M_0110_N_1110,
	mac_l_M_0110_N_1110,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	store_rm_r0_rn_indexed_b_M_0111_N_1110,
	store_rm_r0_rn_indexed_w_M_0111_N_1110,
	store_rm_r0_rn_indexed_l_M_0111_N_1110,
	mul_l_M_0111_N_1110,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_0111_N_1110,
	load_r0_rm_indexed_rn_w_M_0111_N_1110,
	load_r0_rm_indexed_rn_l_M_0111_N_1110,
	mac_l_M_0111_N_1110,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	store_rm_r0_rn_indexed_b_M_1000_N_1110,
	store_rm_r0_rn_indexed_w_M_1000_N_1110,
	store_rm_r0_rn_indexed_l_M_1000_N_1110,
	mul_l_M_1000_N_1110,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_1000_N_1110,
	load_r0_rm_indexed_rn_w_M_1000_N_1110,
	load_r0_rm_indexed_rn_l_M_1000_N_1110,
	mac_l_M_1000_N_1110,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	store_rm_r0_rn_indexed_b_M_1001_N_1110,
	store_rm_r0_rn_indexed_w_M_1001_N_1110,
	store_rm_r0_rn_indexed_l_M_1001_N_1110,
	mul_l_M_1001_N_1110,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_1001_N_1110,
	load_r0_rm_indexed_rn_w_M_1001_N_1110,
	load_r0_rm_indexed_rn_l_M_1001_N_1110,
	mac_l_M_1001_N_1110,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	store_rm_r0_rn_indexed_b_M_1010_N_1110,
	store_rm_r0_rn_indexed_w_M_1010_N_1110,
	store_rm_r0_rn_indexed_l_M_1010_N_1110,
	mul_l_M_1010_N_1110,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_1010_N_1110,
	load_r0_rm_indexed_rn_w_M_1010_N_1110,
	load_r0_rm_indexed_rn_l_M_1010_N_1110,
	mac_l_M_1010_N_1110,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	store_rm_r0_rn_indexed_b_M_1011_N_1110,
	store_rm_r0_rn_indexed_w_M_1011_N_1110,
	store_rm_r0_rn_indexed_l_M_1011_N_1110,
	mul_l_M_1011_N_1110,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_1011_N_1110,
	load_r0_rm_indexed_rn_w_M_1011_N_1110,
	load_r0_rm_indexed_rn_l_M_1011_N_1110,
	mac_l_M_1011_N_1110,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	store_rm_r0_rn_indexed_b_M_1100_N_1110,
	store_rm_r0_rn_indexed_w_M_1100_N_1110,
	store_rm_r0_rn_indexed_l_M_1100_N_1110,
	mul_l_M_1100_N_1110,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_1100_N_1110,
	load_r0_rm_indexed_rn_w_M_1100_N_1110,
	load_r0_rm_indexed_rn_l_M_1100_N_1110,
	mac_l_M_1100_N_1110,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	store_rm_r0_rn_indexed_b_M_1101_N_1110,
	store_rm_r0_rn_indexed_w_M_1101_N_1110,
	store_rm_r0_rn_indexed_l_M_1101_N_1110,
	mul_l_M_1101_N_1110,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_1101_N_1110,
	load_r0_rm_indexed_rn_w_M_1101_N_1110,
	load_r0_rm_indexed_rn_l_M_1101_N_1110,
	mac_l_M_1101_N_1110,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	store_rm_r0_rn_indexed_b_M_1110_N_1110,
	store_rm_r0_rn_indexed_w_M_1110_N_1110,
	store_rm_r0_rn_indexed_l_M_1110_N_1110,
	mul_l_M_1110_N_1110,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_1110_N_1110,
	load_r0_rm_indexed_rn_w_M_1110_N_1110,
	load_r0_rm_indexed_rn_l_M_1110_N_1110,
	mac_l_M_1110_N_1110,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	store_rm_r0_rn_indexed_b_M_1111_N_1110,
	store_rm_r0_rn_indexed_w_M_1111_N_1110,
	store_rm_r0_rn_indexed_l_M_1111_N_1110,
	mul_l_M_1111_N_1110,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_1111_N_1110,
	load_r0_rm_indexed_rn_w_M_1111_N_1110,
	load_r0_rm_indexed_rn_l_M_1111_N_1110,
	mac_l_M_1111_N_1110,
	unimplemented,
	unimplemented,
	stc_sr_rn_N_1111,
	bsrf_M_1111,
	store_rm_r0_rn_indexed_b_M_0000_N_1111,
	store_rm_r0_rn_indexed_w_M_0000_N_1111,
	store_rm_r0_rn_indexed_l_M_0000_N_1111,
	mul_l_M_0000_N_1111,
	unimplemented,
	unimplemented,
	sts_mach_rn_N_1111,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_0000_N_1111,
	load_r0_rm_indexed_rn_w_M_0000_N_1111,
	load_r0_rm_indexed_rn_l_M_0000_N_1111,
	mac_l_M_0000_N_1111,
	unimplemented,
	unimplemented,
	stc_gbr_rn_N_1111,
	unimplemented,
	store_rm_r0_rn_indexed_b_M_0001_N_1111,
	store_rm_r0_rn_indexed_w_M_0001_N_1111,
	store_rm_r0_rn_indexed_l_M_0001_N_1111,
	mul_l_M_0001_N_1111,
	unimplemented,
	unimplemented,
	sts_macl_rn_N_1111,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_0001_N_1111,
	load_r0_rm_indexed_rn_w_M_0001_N_1111,
	load_r0_rm_indexed_rn_l_M_0001_N_1111,
	mac_l_M_0001_N_1111,
	unimplemented,
	unimplemented,
	stc_vbr_rn_N_1111,
	braf_M_1111,
	store_rm_r0_rn_indexed_b_M_0010_N_1111,
	store_rm_r0_rn_indexed_w_M_0010_N_1111,
	store_rm_r0_rn_indexed_l_M_0010_N_1111,
	mul_l_M_0010_N_1111,
	unimplemented,
	movt_N_1111,
	sts_pr_rn_N_1111,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_0010_N_1111,
	load_r0_rm_indexed_rn_w_M_0010_N_1111,
	load_r0_rm_indexed_rn_l_M_0010_N_1111,
	mac_l_M_0010_N_1111,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	store_rm_r0_rn_indexed_b_M_0011_N_1111,
	store_rm_r0_rn_indexed_w_M_0011_N_1111,
	store_rm_r0_rn_indexed_l_M_0011_N_1111,
	mul_l_M_0011_N_1111,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_0011_N_1111,
	load_r0_rm_indexed_rn_w_M_0011_N_1111,
	load_r0_rm_indexed_rn_l_M_0011_N_1111,
	mac_l_M_0011_N_1111,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	store_rm_r0_rn_indexed_b_M_0100_N_1111,
	store_rm_r0_rn_indexed_w_M_0100_N_1111,
	store_rm_r0_rn_indexed_l_M_0100_N_1111,
	mul_l_M_0100_N_1111,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_0100_N_1111,
	load_r0_rm_indexed_rn_w_M_0100_N_1111,
	load_r0_rm_indexed_rn_l_M_0100_N_1111,
	mac_l_M_0100_N_1111,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	store_rm_r0_rn_indexed_b_M_0101_N_1111,
	store_rm_r0_rn_indexed_w_M_0101_N_1111,
	store_rm_r0_rn_indexed_l_M_0101_N_1111,
	mul_l_M_0101_N_1111,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_0101_N_1111,
	load_r0_rm_indexed_rn_w_M_0101_N_1111,
	load_r0_rm_indexed_rn_l_M_0101_N_1111,
	mac_l_M_0101_N_1111,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	store_rm_r0_rn_indexed_b_M_0110_N_1111,
	store_rm_r0_rn_indexed_w_M_0110_N_1111,
	store_rm_r0_rn_indexed_l_M_0110_N_1111,
	mul_l_M_0110_N_1111,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_0110_N_1111,
	load_r0_rm_indexed_rn_w_M_0110_N_1111,
	load_r0_rm_indexed_rn_l_M_0110_N_1111,
	mac_l_M_0110_N_1111,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	store_rm_r0_rn_indexed_b_M_0111_N_1111,
	store_rm_r0_rn_indexed_w_M_0111_N_1111,
	store_rm_r0_rn_indexed_l_M_0111_N_1111,
	mul_l_M_0111_N_1111,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_0111_N_1111,
	load_r0_rm_indexed_rn_w_M_0111_N_1111,
	load_r0_rm_indexed_rn_l_M_0111_N_1111,
	mac_l_M_0111_N_1111,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	store_rm_r0_rn_indexed_b_M_1000_N_1111,
	store_rm_r0_rn_indexed_w_M_1000_N_1111,
	store_rm_r0_rn_indexed_l_M_1000_N_1111,
	mul_l_M_1000_N_1111,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_1000_N_1111,
	load_r0_rm_indexed_rn_w_M_1000_N_1111,
	load_r0_rm_indexed_rn_l_M_1000_N_1111,
	mac_l_M_1000_N_1111,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	store_rm_r0_rn_indexed_b_M_1001_N_1111,
	store_rm_r0_rn_indexed_w_M_1001_N_1111,
	store_rm_r0_rn_indexed_l_M_1001_N_1111,
	mul_l_M_1001_N_1111,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_1001_N_1111,
	load_r0_rm_indexed_rn_w_M_1001_N_1111,
	load_r0_rm_indexed_rn_l_M_1001_N_1111,
	mac_l_M_1001_N_1111,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	store_rm_r0_rn_indexed_b_M_1010_N_1111,
	store_rm_r0_rn_indexed_w_M_1010_N_1111,
	store_rm_r0_rn_indexed_l_M_1010_N_1111,
	mul_l_M_1010_N_1111,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_1010_N_1111,
	load_r0_rm_indexed_rn_w_M_1010_N_1111,
	load_r0_rm_indexed_rn_l_M_1010_N_1111,
	mac_l_M_1010_N_1111,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	store_rm_r0_rn_indexed_b_M_1011_N_1111,
	store_rm_r0_rn_indexed_w_M_1011_N_1111,
	store_rm_r0_rn_indexed_l_M_1011_N_1111,
	mul_l_M_1011_N_1111,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_1011_N_1111,
	load_r0_rm_indexed_rn_w_M_1011_N_1111,
	load_r0_rm_indexed_rn_l_M_1011_N_1111,
	mac_l_M_1011_N_1111,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	store_rm_r0_rn_indexed_b_M_1100_N_1111,
	store_rm_r0_rn_indexed_w_M_1100_N_1111,
	store_rm_r0_rn_indexed_l_M_1100_N_1111,
	mul_l_M_1100_N_1111,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_1100_N_1111,
	load_r0_rm_indexed_rn_w_M_1100_N_1111,
	load_r0_rm_indexed_rn_l_M_1100_N_1111,
	mac_l_M_1100_N_1111,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	store_rm_r0_rn_indexed_b_M_1101_N_1111,
	store_rm_r0_rn_indexed_w_M_1101_N_1111,
	store_rm_r0_rn_indexed_l_M_1101_N_1111,
	mul_l_M_1101_N_1111,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_1101_N_1111,
	load_r0_rm_indexed_rn_w_M_1101_N_1111,
	load_r0_rm_indexed_rn_l_M_1101_N_1111,
	mac_l_M_1101_N_1111,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	store_rm_r0_rn_indexed_b_M_1110_N_1111,
	store_rm_r0_rn_indexed_w_M_1110_N_1111,
	store_rm_r0_rn_indexed_l_M_1110_N_1111,
	mul_l_M_1110_N_1111,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_1110_N_1111,
	load_r0_rm_indexed_rn_w_M_1110_N_1111,
	load_r0_rm_indexed_rn_l_M_1110_N_1111,
	mac_l_M_1110_N_1111,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	store_rm_r0_rn_indexed_b_M_1111_N_1111,
	store_rm_r0_rn_indexed_w_M_1111_N_1111,
	store_rm_r0_rn_indexed_l_M_1111_N_1111,
	mul_l_M_1111_N_1111,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	load_r0_rm_indexed_rn_b_M_1111_N_1111,
	load_r0_rm_indexed_rn_w_M_1111_N_1111,
	load_r0_rm_indexed_rn_l_M_1111_N_1111,
	mac_l_M_1111_N_1111,
	store_rm_disp_rn_l_D_0000_M_0000_N_0000,
	store_rm_disp_rn_l_D_0001_M_0000_N_0000,
	store_rm_disp_rn_l_D_0010_M_0000_N_0000,
	store_rm_disp_rn_l_D_0011_M_0000_N_0000,
	store_rm_disp_rn_l_D_0100_M_0000_N_0000,
	store_rm_disp_rn_l_D_0101_M_0000_N_0000,
	store_rm_disp_rn_l_D_0110_M_0000_N_0000,
	store_rm_disp_rn_l_D_0111_M_0000_N_0000,
	store_rm_disp_rn_l_D_1000_M_0000_N_0000,
	store_rm_disp_rn_l_D_1001_M_0000_N_0000,
	store_rm_disp_rn_l_D_1010_M_0000_N_0000,
	store_rm_disp_rn_l_D_1011_M_0000_N_0000,
	store_rm_disp_rn_l_D_1100_M_0000_N_0000,
	store_rm_disp_rn_l_D_1101_M_0000_N_0000,
	store_rm_disp_rn_l_D_1110_M_0000_N_0000,
	store_rm_disp_rn_l_D_1111_M_0000_N_0000,
	store_rm_disp_rn_l_D_0000_M_0001_N_0000,
	store_rm_disp_rn_l_D_0001_M_0001_N_0000,
	store_rm_disp_rn_l_D_0010_M_0001_N_0000,
	store_rm_disp_rn_l_D_0011_M_0001_N_0000,
	store_rm_disp_rn_l_D_0100_M_0001_N_0000,
	store_rm_disp_rn_l_D_0101_M_0001_N_0000,
	store_rm_disp_rn_l_D_0110_M_0001_N_0000,
	store_rm_disp_rn_l_D_0111_M_0001_N_0000,
	store_rm_disp_rn_l_D_1000_M_0001_N_0000,
	store_rm_disp_rn_l_D_1001_M_0001_N_0000,
	store_rm_disp_rn_l_D_1010_M_0001_N_0000,
	store_rm_disp_rn_l_D_1011_M_0001_N_0000,
	store_rm_disp_rn_l_D_1100_M_0001_N_0000,
	store_rm_disp_rn_l_D_1101_M_0001_N_0000,
	store_rm_disp_rn_l_D_1110_M_0001_N_0000,
	store_rm_disp_rn_l_D_1111_M_0001_N_0000,
	store_rm_disp_rn_l_D_0000_M_0010_N_0000,
	store_rm_disp_rn_l_D_0001_M_0010_N_0000,
	store_rm_disp_rn_l_D_0010_M_0010_N_0000,
	store_rm_disp_rn_l_D_0011_M_0010_N_0000,
	store_rm_disp_rn_l_D_0100_M_0010_N_0000,
	store_rm_disp_rn_l_D_0101_M_0010_N_0000,
	store_rm_disp_rn_l_D_0110_M_0010_N_0000,
	store_rm_disp_rn_l_D_0111_M_0010_N_0000,
	store_rm_disp_rn_l_D_1000_M_0010_N_0000,
	store_rm_disp_rn_l_D_1001_M_0010_N_0000,
	store_rm_disp_rn_l_D_1010_M_0010_N_0000,
	store_rm_disp_rn_l_D_1011_M_0010_N_0000,
	store_rm_disp_rn_l_D_1100_M_0010_N_0000,
	store_rm_disp_rn_l_D_1101_M_0010_N_0000,
	store_rm_disp_rn_l_D_1110_M_0010_N_0000,
	store_rm_disp_rn_l_D_1111_M_0010_N_0000,
	store_rm_disp_rn_l_D_0000_M_0011_N_0000,
	store_rm_disp_rn_l_D_0001_M_0011_N_0000,
	store_rm_disp_rn_l_D_0010_M_0011_N_0000,
	store_rm_disp_rn_l_D_0011_M_0011_N_0000,
	store_rm_disp_rn_l_D_0100_M_0011_N_0000,
	store_rm_disp_rn_l_D_0101_M_0011_N_0000,
	store_rm_disp_rn_l_D_0110_M_0011_N_0000,
	store_rm_disp_rn_l_D_0111_M_0011_N_0000,
	store_rm_disp_rn_l_D_1000_M_0011_N_0000,
	store_rm_disp_rn_l_D_1001_M_0011_N_0000,
	store_rm_disp_rn_l_D_1010_M_0011_N_0000,
	store_rm_disp_rn_l_D_1011_M_0011_N_0000,
	store_rm_disp_rn_l_D_1100_M_0011_N_0000,
	store_rm_disp_rn_l_D_1101_M_0011_N_0000,
	store_rm_disp_rn_l_D_1110_M_0011_N_0000,
	store_rm_disp_rn_l_D_1111_M_0011_N_0000,
	store_rm_disp_rn_l_D_0000_M_0100_N_0000,
	store_rm_disp_rn_l_D_0001_M_0100_N_0000,
	store_rm_disp_rn_l_D_0010_M_0100_N_0000,
	store_rm_disp_rn_l_D_0011_M_0100_N_0000,
	store_rm_disp_rn_l_D_0100_M_0100_N_0000,
	store_rm_disp_rn_l_D_0101_M_0100_N_0000,
	store_rm_disp_rn_l_D_0110_M_0100_N_0000,
	store_rm_disp_rn_l_D_0111_M_0100_N_0000,
	store_rm_disp_rn_l_D_1000_M_0100_N_0000,
	store_rm_disp_rn_l_D_1001_M_0100_N_0000,
	store_rm_disp_rn_l_D_1010_M_0100_N_0000,
	store_rm_disp_rn_l_D_1011_M_0100_N_0000,
	store_rm_disp_rn_l_D_1100_M_0100_N_0000,
	store_rm_disp_rn_l_D_1101_M_0100_N_0000,
	store_rm_disp_rn_l_D_1110_M_0100_N_0000,
	store_rm_disp_rn_l_D_1111_M_0100_N_0000,
	store_rm_disp_rn_l_D_0000_M_0101_N_0000,
	store_rm_disp_rn_l_D_0001_M_0101_N_0000,
	store_rm_disp_rn_l_D_0010_M_0101_N_0000,
	store_rm_disp_rn_l_D_0011_M_0101_N_0000,
	store_rm_disp_rn_l_D_0100_M_0101_N_0000,
	store_rm_disp_rn_l_D_0101_M_0101_N_0000,
	store_rm_disp_rn_l_D_0110_M_0101_N_0000,
	store_rm_disp_rn_l_D_0111_M_0101_N_0000,
	store_rm_disp_rn_l_D_1000_M_0101_N_0000,
	store_rm_disp_rn_l_D_1001_M_0101_N_0000,
	store_rm_disp_rn_l_D_1010_M_0101_N_0000,
	store_rm_disp_rn_l_D_1011_M_0101_N_0000,
	store_rm_disp_rn_l_D_1100_M_0101_N_0000,
	store_rm_disp_rn_l_D_1101_M_0101_N_0000,
	store_rm_disp_rn_l_D_1110_M_0101_N_0000,
	store_rm_disp_rn_l_D_1111_M_0101_N_0000,
	store_rm_disp_rn_l_D_0000_M_0110_N_0000,
	store_rm_disp_rn_l_D_0001_M_0110_N_0000,
	store_rm_disp_rn_l_D_0010_M_0110_N_0000,
	store_rm_disp_rn_l_D_0011_M_0110_N_0000,
	store_rm_disp_rn_l_D_0100_M_0110_N_0000,
	store_rm_disp_rn_l_D_0101_M_0110_N_0000,
	store_rm_disp_rn_l_D_0110_M_0110_N_0000,
	store_rm_disp_rn_l_D_0111_M_0110_N_0000,
	store_rm_disp_rn_l_D_1000_M_0110_N_0000,
	store_rm_disp_rn_l_D_1001_M_0110_N_0000,
	store_rm_disp_rn_l_D_1010_M_0110_N_0000,
	store_rm_disp_rn_l_D_1011_M_0110_N_0000,
	store_rm_disp_rn_l_D_1100_M_0110_N_0000,
	store_rm_disp_rn_l_D_1101_M_0110_N_0000,
	store_rm_disp_rn_l_D_1110_M_0110_N_0000,
	store_rm_disp_rn_l_D_1111_M_0110_N_0000,
	store_rm_disp_rn_l_D_0000_M_0111_N_0000,
	store_rm_disp_rn_l_D_0001_M_0111_N_0000,
	store_rm_disp_rn_l_D_0010_M_0111_N_0000,
	store_rm_disp_rn_l_D_0011_M_0111_N_0000,
	store_rm_disp_rn_l_D_0100_M_0111_N_0000,
	store_rm_disp_rn_l_D_0101_M_0111_N_0000,
	store_rm_disp_rn_l_D_0110_M_0111_N_0000,
	store_rm_disp_rn_l_D_0111_M_0111_N_0000,
	store_rm_disp_rn_l_D_1000_M_0111_N_0000,
	store_rm_disp_rn_l_D_1001_M_0111_N_0000,
	store_rm_disp_rn_l_D_1010_M_0111_N_0000,
	store_rm_disp_rn_l_D_1011_M_0111_N_0000,
	store_rm_disp_rn_l_D_1100_M_0111_N_0000,
	store_rm_disp_rn_l_D_1101_M_0111_N_0000,
	store_rm_disp_rn_l_D_1110_M_0111_N_0000,
	store_rm_disp_rn_l_D_1111_M_0111_N_0000,
	store_rm_disp_rn_l_D_0000_M_1000_N_0000,
	store_rm_disp_rn_l_D_0001_M_1000_N_0000,
	store_rm_disp_rn_l_D_0010_M_1000_N_0000,
	store_rm_disp_rn_l_D_0011_M_1000_N_0000,
	store_rm_disp_rn_l_D_0100_M_1000_N_0000,
	store_rm_disp_rn_l_D_0101_M_1000_N_0000,
	store_rm_disp_rn_l_D_0110_M_1000_N_0000,
	store_rm_disp_rn_l_D_0111_M_1000_N_0000,
	store_rm_disp_rn_l_D_1000_M_1000_N_0000,
	store_rm_disp_rn_l_D_1001_M_1000_N_0000,
	store_rm_disp_rn_l_D_1010_M_1000_N_0000,
	store_rm_disp_rn_l_D_1011_M_1000_N_0000,
	store_rm_disp_rn_l_D_1100_M_1000_N_0000,
	store_rm_disp_rn_l_D_1101_M_1000_N_0000,
	store_rm_disp_rn_l_D_1110_M_1000_N_0000,
	store_rm_disp_rn_l_D_1111_M_1000_N_0000,
	store_rm_disp_rn_l_D_0000_M_1001_N_0000,
	store_rm_disp_rn_l_D_0001_M_1001_N_0000,
	store_rm_disp_rn_l_D_0010_M_1001_N_0000,
	store_rm_disp_rn_l_D_0011_M_1001_N_0000,
	store_rm_disp_rn_l_D_0100_M_1001_N_0000,
	store_rm_disp_rn_l_D_0101_M_1001_N_0000,
	store_rm_disp_rn_l_D_0110_M_1001_N_0000,
	store_rm_disp_rn_l_D_0111_M_1001_N_0000,
	store_rm_disp_rn_l_D_1000_M_1001_N_0000,
	store_rm_disp_rn_l_D_1001_M_1001_N_0000,
	store_rm_disp_rn_l_D_1010_M_1001_N_0000,
	store_rm_disp_rn_l_D_1011_M_1001_N_0000,
	store_rm_disp_rn_l_D_1100_M_1001_N_0000,
	store_rm_disp_rn_l_D_1101_M_1001_N_0000,
	store_rm_disp_rn_l_D_1110_M_1001_N_0000,
	store_rm_disp_rn_l_D_1111_M_1001_N_0000,
	store_rm_disp_rn_l_D_0000_M_1010_N_0000,
	store_rm_disp_rn_l_D_0001_M_1010_N_0000,
	store_rm_disp_rn_l_D_0010_M_1010_N_0000,
	store_rm_disp_rn_l_D_0011_M_1010_N_0000,
	store_rm_disp_rn_l_D_0100_M_1010_N_0000,
	store_rm_disp_rn_l_D_0101_M_1010_N_0000,
	store_rm_disp_rn_l_D_0110_M_1010_N_0000,
	store_rm_disp_rn_l_D_0111_M_1010_N_0000,
	store_rm_disp_rn_l_D_1000_M_1010_N_0000,
	store_rm_disp_rn_l_D_1001_M_1010_N_0000,
	store_rm_disp_rn_l_D_1010_M_1010_N_0000,
	store_rm_disp_rn_l_D_1011_M_1010_N_0000,
	store_rm_disp_rn_l_D_1100_M_1010_N_0000,
	store_rm_disp_rn_l_D_1101_M_1010_N_0000,
	store_rm_disp_rn_l_D_1110_M_1010_N_0000,
	store_rm_disp_rn_l_D_1111_M_1010_N_0000,
	store_rm_disp_rn_l_D_0000_M_1011_N_0000,
	store_rm_disp_rn_l_D_0001_M_1011_N_0000,
	store_rm_disp_rn_l_D_0010_M_1011_N_0000,
	store_rm_disp_rn_l_D_0011_M_1011_N_0000,
	store_rm_disp_rn_l_D_0100_M_1011_N_0000,
	store_rm_disp_rn_l_D_0101_M_1011_N_0000,
	store_rm_disp_rn_l_D_0110_M_1011_N_0000,
	store_rm_disp_rn_l_D_0111_M_1011_N_0000,
	store_rm_disp_rn_l_D_1000_M_1011_N_0000,
	store_rm_disp_rn_l_D_1001_M_1011_N_0000,
	store_rm_disp_rn_l_D_1010_M_1011_N_0000,
	store_rm_disp_rn_l_D_1011_M_1011_N_0000,
	store_rm_disp_rn_l_D_1100_M_1011_N_0000,
	store_rm_disp_rn_l_D_1101_M_1011_N_0000,
	store_rm_disp_rn_l_D_1110_M_1011_N_0000,
	store_rm_disp_rn_l_D_1111_M_1011_N_0000,
	store_rm_disp_rn_l_D_0000_M_1100_N_0000,
	store_rm_disp_rn_l_D_0001_M_1100_N_0000,
	store_rm_disp_rn_l_D_0010_M_1100_N_0000,
	store_rm_disp_rn_l_D_0011_M_1100_N_0000,
	store_rm_disp_rn_l_D_0100_M_1100_N_0000,
	store_rm_disp_rn_l_D_0101_M_1100_N_0000,
	store_rm_disp_rn_l_D_0110_M_1100_N_0000,
	store_rm_disp_rn_l_D_0111_M_1100_N_0000,
	store_rm_disp_rn_l_D_1000_M_1100_N_0000,
	store_rm_disp_rn_l_D_1001_M_1100_N_0000,
	store_rm_disp_rn_l_D_1010_M_1100_N_0000,
	store_rm_disp_rn_l_D_1011_M_1100_N_0000,
	store_rm_disp_rn_l_D_1100_M_1100_N_0000,
	store_rm_disp_rn_l_D_1101_M_1100_N_0000,
	store_rm_disp_rn_l_D_1110_M_1100_N_0000,
	store_rm_disp_rn_l_D_1111_M_1100_N_0000,
	store_rm_disp_rn_l_D_0000_M_1101_N_0000,
	store_rm_disp_rn_l_D_0001_M_1101_N_0000,
	store_rm_disp_rn_l_D_0010_M_1101_N_0000,
	store_rm_disp_rn_l_D_0011_M_1101_N_0000,
	store_rm_disp_rn_l_D_0100_M_1101_N_0000,
	store_rm_disp_rn_l_D_0101_M_1101_N_0000,
	store_rm_disp_rn_l_D_0110_M_1101_N_0000,
	store_rm_disp_rn_l_D_0111_M_1101_N_0000,
	store_rm_disp_rn_l_D_1000_M_1101_N_0000,
	store_rm_disp_rn_l_D_1001_M_1101_N_0000,
	store_rm_disp_rn_l_D_1010_M_1101_N_0000,
	store_rm_disp_rn_l_D_1011_M_1101_N_0000,
	store_rm_disp_rn_l_D_1100_M_1101_N_0000,
	store_rm_disp_rn_l_D_1101_M_1101_N_0000,
	store_rm_disp_rn_l_D_1110_M_1101_N_0000,
	store_rm_disp_rn_l_D_1111_M_1101_N_0000,
	store_rm_disp_rn_l_D_0000_M_1110_N_0000,
	store_rm_disp_rn_l_D_0001_M_1110_N_0000,
	store_rm_disp_rn_l_D_0010_M_1110_N_0000,
	store_rm_disp_rn_l_D_0011_M_1110_N_0000,
	store_rm_disp_rn_l_D_0100_M_1110_N_0000,
	store_rm_disp_rn_l_D_0101_M_1110_N_0000,
	store_rm_disp_rn_l_D_0110_M_1110_N_0000,
	store_rm_disp_rn_l_D_0111_M_1110_N_0000,
	store_rm_disp_rn_l_D_1000_M_1110_N_0000,
	store_rm_disp_rn_l_D_1001_M_1110_N_0000,
	store_rm_disp_rn_l_D_1010_M_1110_N_0000,
	store_rm_disp_rn_l_D_1011_M_1110_N_0000,
	store_rm_disp_rn_l_D_1100_M_1110_N_0000,
	store_rm_disp_rn_l_D_1101_M_1110_N_0000,
	store_rm_disp_rn_l_D_1110_M_1110_N_0000,
	store_rm_disp_rn_l_D_1111_M_1110_N_0000,
	store_rm_disp_rn_l_D_0000_M_1111_N_0000,
	store_rm_disp_rn_l_D_0001_M_1111_N_0000,
	store_rm_disp_rn_l_D_0010_M_1111_N_0000,
	store_rm_disp_rn_l_D_0011_M_1111_N_0000,
	store_rm_disp_rn_l_D_0100_M_1111_N_0000,
	store_rm_disp_rn_l_D_0101_M_1111_N_0000,
	store_rm_disp_rn_l_D_0110_M_1111_N_0000,
	store_rm_disp_rn_l_D_0111_M_1111_N_0000,
	store_rm_disp_rn_l_D_1000_M_1111_N_0000,
	store_rm_disp_rn_l_D_1001_M_1111_N_0000,
	store_rm_disp_rn_l_D_1010_M_1111_N_0000,
	store_rm_disp_rn_l_D_1011_M_1111_N_0000,
	store_rm_disp_rn_l_D_1100_M_1111_N_0000,
	store_rm_disp_rn_l_D_1101_M_1111_N_0000,
	store_rm_disp_rn_l_D_1110_M_1111_N_0000,
	store_rm_disp_rn_l_D_1111_M_1111_N_0000,
	store_rm_disp_rn_l_D_0000_M_0000_N_0001,
	store_rm_disp_rn_l_D_0001_M_0000_N_0001,
	store_rm_disp_rn_l_D_0010_M_0000_N_0001,
	store_rm_disp_rn_l_D_0011_M_0000_N_0001,
	store_rm_disp_rn_l_D_0100_M_0000_N_0001,
	store_rm_disp_rn_l_D_0101_M_0000_N_0001,
	store_rm_disp_rn_l_D_0110_M_0000_N_0001,
	store_rm_disp_rn_l_D_0111_M_0000_N_0001,
	store_rm_disp_rn_l_D_1000_M_0000_N_0001,
	store_rm_disp_rn_l_D_1001_M_0000_N_0001,
	store_rm_disp_rn_l_D_1010_M_0000_N_0001,
	store_rm_disp_rn_l_D_1011_M_0000_N_0001,
	store_rm_disp_rn_l_D_1100_M_0000_N_0001,
	store_rm_disp_rn_l_D_1101_M_0000_N_0001,
	store_rm_disp_rn_l_D_1110_M_0000_N_0001,
	store_rm_disp_rn_l_D_1111_M_0000_N_0001,
	store_rm_disp_rn_l_D_0000_M_0001_N_0001,
	store_rm_disp_rn_l_D_0001_M_0001_N_0001,
	store_rm_disp_rn_l_D_0010_M_0001_N_0001,
	store_rm_disp_rn_l_D_0011_M_0001_N_0001,
	store_rm_disp_rn_l_D_0100_M_0001_N_0001,
	store_rm_disp_rn_l_D_0101_M_0001_N_0001,
	store_rm_disp_rn_l_D_0110_M_0001_N_0001,
	store_rm_disp_rn_l_D_0111_M_0001_N_0001,
	store_rm_disp_rn_l_D_1000_M_0001_N_0001,
	store_rm_disp_rn_l_D_1001_M_0001_N_0001,
	store_rm_disp_rn_l_D_1010_M_0001_N_0001,
	store_rm_disp_rn_l_D_1011_M_0001_N_0001,
	store_rm_disp_rn_l_D_1100_M_0001_N_0001,
	store_rm_disp_rn_l_D_1101_M_0001_N_0001,
	store_rm_disp_rn_l_D_1110_M_0001_N_0001,
	store_rm_disp_rn_l_D_1111_M_0001_N_0001,
	store_rm_disp_rn_l_D_0000_M_0010_N_0001,
	store_rm_disp_rn_l_D_0001_M_0010_N_0001,
	store_rm_disp_rn_l_D_0010_M_0010_N_0001,
	store_rm_disp_rn_l_D_0011_M_0010_N_0001,
	store_rm_disp_rn_l_D_0100_M_0010_N_0001,
	store_rm_disp_rn_l_D_0101_M_0010_N_0001,
	store_rm_disp_rn_l_D_0110_M_0010_N_0001,
	store_rm_disp_rn_l_D_0111_M_0010_N_0001,
	store_rm_disp_rn_l_D_1000_M_0010_N_0001,
	store_rm_disp_rn_l_D_1001_M_0010_N_0001,
	store_rm_disp_rn_l_D_1010_M_0010_N_0001,
	store_rm_disp_rn_l_D_1011_M_0010_N_0001,
	store_rm_disp_rn_l_D_1100_M_0010_N_0001,
	store_rm_disp_rn_l_D_1101_M_0010_N_0001,
	store_rm_disp_rn_l_D_1110_M_0010_N_0001,
	store_rm_disp_rn_l_D_1111_M_0010_N_0001,
	store_rm_disp_rn_l_D_0000_M_0011_N_0001,
	store_rm_disp_rn_l_D_0001_M_0011_N_0001,
	store_rm_disp_rn_l_D_0010_M_0011_N_0001,
	store_rm_disp_rn_l_D_0011_M_0011_N_0001,
	store_rm_disp_rn_l_D_0100_M_0011_N_0001,
	store_rm_disp_rn_l_D_0101_M_0011_N_0001,
	store_rm_disp_rn_l_D_0110_M_0011_N_0001,
	store_rm_disp_rn_l_D_0111_M_0011_N_0001,
	store_rm_disp_rn_l_D_1000_M_0011_N_0001,
	store_rm_disp_rn_l_D_1001_M_0011_N_0001,
	store_rm_disp_rn_l_D_1010_M_0011_N_0001,
	store_rm_disp_rn_l_D_1011_M_0011_N_0001,
	store_rm_disp_rn_l_D_1100_M_0011_N_0001,
	store_rm_disp_rn_l_D_1101_M_0011_N_0001,
	store_rm_disp_rn_l_D_1110_M_0011_N_0001,
	store_rm_disp_rn_l_D_1111_M_0011_N_0001,
	store_rm_disp_rn_l_D_0000_M_0100_N_0001,
	store_rm_disp_rn_l_D_0001_M_0100_N_0001,
	store_rm_disp_rn_l_D_0010_M_0100_N_0001,
	store_rm_disp_rn_l_D_0011_M_0100_N_0001,
	store_rm_disp_rn_l_D_0100_M_0100_N_0001,
	store_rm_disp_rn_l_D_0101_M_0100_N_0001,
	store_rm_disp_rn_l_D_0110_M_0100_N_0001,
	store_rm_disp_rn_l_D_0111_M_0100_N_0001,
	store_rm_disp_rn_l_D_1000_M_0100_N_0001,
	store_rm_disp_rn_l_D_1001_M_0100_N_0001,
	store_rm_disp_rn_l_D_1010_M_0100_N_0001,
	store_rm_disp_rn_l_D_1011_M_0100_N_0001,
	store_rm_disp_rn_l_D_1100_M_0100_N_0001,
	store_rm_disp_rn_l_D_1101_M_0100_N_0001,
	store_rm_disp_rn_l_D_1110_M_0100_N_0001,
	store_rm_disp_rn_l_D_1111_M_0100_N_0001,
	store_rm_disp_rn_l_D_0000_M_0101_N_0001,
	store_rm_disp_rn_l_D_0001_M_0101_N_0001,
	store_rm_disp_rn_l_D_0010_M_0101_N_0001,
	store_rm_disp_rn_l_D_0011_M_0101_N_0001,
	store_rm_disp_rn_l_D_0100_M_0101_N_0001,
	store_rm_disp_rn_l_D_0101_M_0101_N_0001,
	store_rm_disp_rn_l_D_0110_M_0101_N_0001,
	store_rm_disp_rn_l_D_0111_M_0101_N_0001,
	store_rm_disp_rn_l_D_1000_M_0101_N_0001,
	store_rm_disp_rn_l_D_1001_M_0101_N_0001,
	store_rm_disp_rn_l_D_1010_M_0101_N_0001,
	store_rm_disp_rn_l_D_1011_M_0101_N_0001,
	store_rm_disp_rn_l_D_1100_M_0101_N_0001,
	store_rm_disp_rn_l_D_1101_M_0101_N_0001,
	store_rm_disp_rn_l_D_1110_M_0101_N_0001,
	store_rm_disp_rn_l_D_1111_M_0101_N_0001,
	store_rm_disp_rn_l_D_0000_M_0110_N_0001,
	store_rm_disp_rn_l_D_0001_M_0110_N_0001,
	store_rm_disp_rn_l_D_0010_M_0110_N_0001,
	store_rm_disp_rn_l_D_0011_M_0110_N_0001,
	store_rm_disp_rn_l_D_0100_M_0110_N_0001,
	store_rm_disp_rn_l_D_0101_M_0110_N_0001,
	store_rm_disp_rn_l_D_0110_M_0110_N_0001,
	store_rm_disp_rn_l_D_0111_M_0110_N_0001,
	store_rm_disp_rn_l_D_1000_M_0110_N_0001,
	store_rm_disp_rn_l_D_1001_M_0110_N_0001,
	store_rm_disp_rn_l_D_1010_M_0110_N_0001,
	store_rm_disp_rn_l_D_1011_M_0110_N_0001,
	store_rm_disp_rn_l_D_1100_M_0110_N_0001,
	store_rm_disp_rn_l_D_1101_M_0110_N_0001,
	store_rm_disp_rn_l_D_1110_M_0110_N_0001,
	store_rm_disp_rn_l_D_1111_M_0110_N_0001,
	store_rm_disp_rn_l_D_0000_M_0111_N_0001,
	store_rm_disp_rn_l_D_0001_M_0111_N_0001,
	store_rm_disp_rn_l_D_0010_M_0111_N_0001,
	store_rm_disp_rn_l_D_0011_M_0111_N_0001,
	store_rm_disp_rn_l_D_0100_M_0111_N_0001,
	store_rm_disp_rn_l_D_0101_M_0111_N_0001,
	store_rm_disp_rn_l_D_0110_M_0111_N_0001,
	store_rm_disp_rn_l_D_0111_M_0111_N_0001,
	store_rm_disp_rn_l_D_1000_M_0111_N_0001,
	store_rm_disp_rn_l_D_1001_M_0111_N_0001,
	store_rm_disp_rn_l_D_1010_M_0111_N_0001,
	store_rm_disp_rn_l_D_1011_M_0111_N_0001,
	store_rm_disp_rn_l_D_1100_M_0111_N_0001,
	store_rm_disp_rn_l_D_1101_M_0111_N_0001,
	store_rm_disp_rn_l_D_1110_M_0111_N_0001,
	store_rm_disp_rn_l_D_1111_M_0111_N_0001,
	store_rm_disp_rn_l_D_0000_M_1000_N_0001,
	store_rm_disp_rn_l_D_0001_M_1000_N_0001,
	store_rm_disp_rn_l_D_0010_M_1000_N_0001,
	store_rm_disp_rn_l_D_0011_M_1000_N_0001,
	store_rm_disp_rn_l_D_0100_M_1000_N_0001,
	store_rm_disp_rn_l_D_0101_M_1000_N_0001,
	store_rm_disp_rn_l_D_0110_M_1000_N_0001,
	store_rm_disp_rn_l_D_0111_M_1000_N_0001,
	store_rm_disp_rn_l_D_1000_M_1000_N_0001,
	store_rm_disp_rn_l_D_1001_M_1000_N_0001,
	store_rm_disp_rn_l_D_1010_M_1000_N_0001,
	store_rm_disp_rn_l_D_1011_M_1000_N_0001,
	store_rm_disp_rn_l_D_1100_M_1000_N_0001,
	store_rm_disp_rn_l_D_1101_M_1000_N_0001,
	store_rm_disp_rn_l_D_1110_M_1000_N_0001,
	store_rm_disp_rn_l_D_1111_M_1000_N_0001,
	store_rm_disp_rn_l_D_0000_M_1001_N_0001,
	store_rm_disp_rn_l_D_0001_M_1001_N_0001,
	store_rm_disp_rn_l_D_0010_M_1001_N_0001,
	store_rm_disp_rn_l_D_0011_M_1001_N_0001,
	store_rm_disp_rn_l_D_0100_M_1001_N_0001,
	store_rm_disp_rn_l_D_0101_M_1001_N_0001,
	store_rm_disp_rn_l_D_0110_M_1001_N_0001,
	store_rm_disp_rn_l_D_0111_M_1001_N_0001,
	store_rm_disp_rn_l_D_1000_M_1001_N_0001,
	store_rm_disp_rn_l_D_1001_M_1001_N_0001,
	store_rm_disp_rn_l_D_1010_M_1001_N_0001,
	store_rm_disp_rn_l_D_1011_M_1001_N_0001,
	store_rm_disp_rn_l_D_1100_M_1001_N_0001,
	store_rm_disp_rn_l_D_1101_M_1001_N_0001,
	store_rm_disp_rn_l_D_1110_M_1001_N_0001,
	store_rm_disp_rn_l_D_1111_M_1001_N_0001,
	store_rm_disp_rn_l_D_0000_M_1010_N_0001,
	store_rm_disp_rn_l_D_0001_M_1010_N_0001,
	store_rm_disp_rn_l_D_0010_M_1010_N_0001,
	store_rm_disp_rn_l_D_0011_M_1010_N_0001,
	store_rm_disp_rn_l_D_0100_M_1010_N_0001,
	store_rm_disp_rn_l_D_0101_M_1010_N_0001,
	store_rm_disp_rn_l_D_0110_M_1010_N_0001,
	store_rm_disp_rn_l_D_0111_M_1010_N_0001,
	store_rm_disp_rn_l_D_1000_M_1010_N_0001,
	store_rm_disp_rn_l_D_1001_M_1010_N_0001,
	store_rm_disp_rn_l_D_1010_M_1010_N_0001,
	store_rm_disp_rn_l_D_1011_M_1010_N_0001,
	store_rm_disp_rn_l_D_1100_M_1010_N_0001,
	store_rm_disp_rn_l_D_1101_M_1010_N_0001,
	store_rm_disp_rn_l_D_1110_M_1010_N_0001,
	store_rm_disp_rn_l_D_1111_M_1010_N_0001,
	store_rm_disp_rn_l_D_0000_M_1011_N_0001,
	store_rm_disp_rn_l_D_0001_M_1011_N_0001,
	store_rm_disp_rn_l_D_0010_M_1011_N_0001,
	store_rm_disp_rn_l_D_0011_M_1011_N_0001,
	store_rm_disp_rn_l_D_0100_M_1011_N_0001,
	store_rm_disp_rn_l_D_0101_M_1011_N_0001,
	store_rm_disp_rn_l_D_0110_M_1011_N_0001,
	store_rm_disp_rn_l_D_0111_M_1011_N_0001,
	store_rm_disp_rn_l_D_1000_M_1011_N_0001,
	store_rm_disp_rn_l_D_1001_M_1011_N_0001,
	store_rm_disp_rn_l_D_1010_M_1011_N_0001,
	store_rm_disp_rn_l_D_1011_M_1011_N_0001,
	store_rm_disp_rn_l_D_1100_M_1011_N_0001,
	store_rm_disp_rn_l_D_1101_M_1011_N_0001,
	store_rm_disp_rn_l_D_1110_M_1011_N_0001,
	store_rm_disp_rn_l_D_1111_M_1011_N_0001,
	store_rm_disp_rn_l_D_0000_M_1100_N_0001,
	store_rm_disp_rn_l_D_0001_M_1100_N_0001,
	store_rm_disp_rn_l_D_0010_M_1100_N_0001,
	store_rm_disp_rn_l_D_0011_M_1100_N_0001,
	store_rm_disp_rn_l_D_0100_M_1100_N_0001,
	store_rm_disp_rn_l_D_0101_M_1100_N_0001,
	store_rm_disp_rn_l_D_0110_M_1100_N_0001,
	store_rm_disp_rn_l_D_0111_M_1100_N_0001,
	store_rm_disp_rn_l_D_1000_M_1100_N_0001,
	store_rm_disp_rn_l_D_1001_M_1100_N_0001,
	store_rm_disp_rn_l_D_1010_M_1100_N_0001,
	store_rm_disp_rn_l_D_1011_M_1100_N_0001,
	store_rm_disp_rn_l_D_1100_M_1100_N_0001,
	store_rm_disp_rn_l_D_1101_M_1100_N_0001,
	store_rm_disp_rn_l_D_1110_M_1100_N_0001,
	store_rm_disp_rn_l_D_1111_M_1100_N_0001,
	store_rm_disp_rn_l_D_0000_M_1101_N_0001,
	store_rm_disp_rn_l_D_0001_M_1101_N_0001,
	store_rm_disp_rn_l_D_0010_M_1101_N_0001,
	store_rm_disp_rn_l_D_0011_M_1101_N_0001,
	store_rm_disp_rn_l_D_0100_M_1101_N_0001,
	store_rm_disp_rn_l_D_0101_M_1101_N_0001,
	store_rm_disp_rn_l_D_0110_M_1101_N_0001,
	store_rm_disp_rn_l_D_0111_M_1101_N_0001,
	store_rm_disp_rn_l_D_1000_M_1101_N_0001,
	store_rm_disp_rn_l_D_1001_M_1101_N_0001,
	store_rm_disp_rn_l_D_1010_M_1101_N_0001,
	store_rm_disp_rn_l_D_1011_M_1101_N_0001,
	store_rm_disp_rn_l_D_1100_M_1101_N_0001,
	store_rm_disp_rn_l_D_1101_M_1101_N_0001,
	store_rm_disp_rn_l_D_1110_M_1101_N_0001,
	store_rm_disp_rn_l_D_1111_M_1101_N_0001,
	store_rm_disp_rn_l_D_0000_M_1110_N_0001,
	store_rm_disp_rn_l_D_0001_M_1110_N_0001,
	store_rm_disp_rn_l_D_0010_M_1110_N_0001,
	store_rm_disp_rn_l_D_0011_M_1110_N_0001,
	store_rm_disp_rn_l_D_0100_M_1110_N_0001,
	store_rm_disp_rn_l_D_0101_M_1110_N_0001,
	store_rm_disp_rn_l_D_0110_M_1110_N_0001,
	store_rm_disp_rn_l_D_0111_M_1110_N_0001,
	store_rm_disp_rn_l_D_1000_M_1110_N_0001,
	store_rm_disp_rn_l_D_1001_M_1110_N_0001,
	store_rm_disp_rn_l_D_1010_M_1110_N_0001,
	store_rm_disp_rn_l_D_1011_M_1110_N_0001,
	store_rm_disp_rn_l_D_1100_M_1110_N_0001,
	store_rm_disp_rn_l_D_1101_M_1110_N_0001,
	store_rm_disp_rn_l_D_1110_M_1110_N_0001,
	store_rm_disp_rn_l_D_1111_M_1110_N_0001,
	store_rm_disp_rn_l_D_0000_M_1111_N_0001,
	store_rm_disp_rn_l_D_0001_M_1111_N_0001,
	store_rm_disp_rn_l_D_0010_M_1111_N_0001,
	store_rm_disp_rn_l_D_0011_M_1111_N_0001,
	store_rm_disp_rn_l_D_0100_M_1111_N_0001,
	store_rm_disp_rn_l_D_0101_M_1111_N_0001,
	store_rm_disp_rn_l_D_0110_M_1111_N_0001,
	store_rm_disp_rn_l_D_0111_M_1111_N_0001,
	store_rm_disp_rn_l_D_1000_M_1111_N_0001,
	store_rm_disp_rn_l_D_1001_M_1111_N_0001,
	store_rm_disp_rn_l_D_1010_M_1111_N_0001,
	store_rm_disp_rn_l_D_1011_M_1111_N_0001,
	store_rm_disp_rn_l_D_1100_M_1111_N_0001,
	store_rm_disp_rn_l_D_1101_M_1111_N_0001,
	store_rm_disp_rn_l_D_1110_M_1111_N_0001,
	store_rm_disp_rn_l_D_1111_M_1111_N_0001,
	store_rm_disp_rn_l_D_0000_M_0000_N_0010,
	store_rm_disp_rn_l_D_0001_M_0000_N_0010,
	store_rm_disp_rn_l_D_0010_M_0000_N_0010,
	store_rm_disp_rn_l_D_0011_M_0000_N_0010,
	store_rm_disp_rn_l_D_0100_M_0000_N_0010,
	store_rm_disp_rn_l_D_0101_M_0000_N_0010,
	store_rm_disp_rn_l_D_0110_M_0000_N_0010,
	store_rm_disp_rn_l_D_0111_M_0000_N_0010,
	store_rm_disp_rn_l_D_1000_M_0000_N_0010,
	store_rm_disp_rn_l_D_1001_M_0000_N_0010,
	store_rm_disp_rn_l_D_1010_M_0000_N_0010,
	store_rm_disp_rn_l_D_1011_M_0000_N_0010,
	store_rm_disp_rn_l_D_1100_M_0000_N_0010,
	store_rm_disp_rn_l_D_1101_M_0000_N_0010,
	store_rm_disp_rn_l_D_1110_M_0000_N_0010,
	store_rm_disp_rn_l_D_1111_M_0000_N_0010,
	store_rm_disp_rn_l_D_0000_M_0001_N_0010,
	store_rm_disp_rn_l_D_0001_M_0001_N_0010,
	store_rm_disp_rn_l_D_0010_M_0001_N_0010,
	store_rm_disp_rn_l_D_0011_M_0001_N_0010,
	store_rm_disp_rn_l_D_0100_M_0001_N_0010,
	store_rm_disp_rn_l_D_0101_M_0001_N_0010,
	store_rm_disp_rn_l_D_0110_M_0001_N_0010,
	store_rm_disp_rn_l_D_0111_M_0001_N_0010,
	store_rm_disp_rn_l_D_1000_M_0001_N_0010,
	store_rm_disp_rn_l_D_1001_M_0001_N_0010,
	store_rm_disp_rn_l_D_1010_M_0001_N_0010,
	store_rm_disp_rn_l_D_1011_M_0001_N_0010,
	store_rm_disp_rn_l_D_1100_M_0001_N_0010,
	store_rm_disp_rn_l_D_1101_M_0001_N_0010,
	store_rm_disp_rn_l_D_1110_M_0001_N_0010,
	store_rm_disp_rn_l_D_1111_M_0001_N_0010,
	store_rm_disp_rn_l_D_0000_M_0010_N_0010,
	store_rm_disp_rn_l_D_0001_M_0010_N_0010,
	store_rm_disp_rn_l_D_0010_M_0010_N_0010,
	store_rm_disp_rn_l_D_0011_M_0010_N_0010,
	store_rm_disp_rn_l_D_0100_M_0010_N_0010,
	store_rm_disp_rn_l_D_0101_M_0010_N_0010,
	store_rm_disp_rn_l_D_0110_M_0010_N_0010,
	store_rm_disp_rn_l_D_0111_M_0010_N_0010,
	store_rm_disp_rn_l_D_1000_M_0010_N_0010,
	store_rm_disp_rn_l_D_1001_M_0010_N_0010,
	store_rm_disp_rn_l_D_1010_M_0010_N_0010,
	store_rm_disp_rn_l_D_1011_M_0010_N_0010,
	store_rm_disp_rn_l_D_1100_M_0010_N_0010,
	store_rm_disp_rn_l_D_1101_M_0010_N_0010,
	store_rm_disp_rn_l_D_1110_M_0010_N_0010,
	store_rm_disp_rn_l_D_1111_M_0010_N_0010,
	store_rm_disp_rn_l_D_0000_M_0011_N_0010,
	store_rm_disp_rn_l_D_0001_M_0011_N_0010,
	store_rm_disp_rn_l_D_0010_M_0011_N_0010,
	store_rm_disp_rn_l_D_0011_M_0011_N_0010,
	store_rm_disp_rn_l_D_0100_M_0011_N_0010,
	store_rm_disp_rn_l_D_0101_M_0011_N_0010,
	store_rm_disp_rn_l_D_0110_M_0011_N_0010,
	store_rm_disp_rn_l_D_0111_M_0011_N_0010,
	store_rm_disp_rn_l_D_1000_M_0011_N_0010,
	store_rm_disp_rn_l_D_1001_M_0011_N_0010,
	store_rm_disp_rn_l_D_1010_M_0011_N_0010,
	store_rm_disp_rn_l_D_1011_M_0011_N_0010,
	store_rm_disp_rn_l_D_1100_M_0011_N_0010,
	store_rm_disp_rn_l_D_1101_M_0011_N_0010,
	store_rm_disp_rn_l_D_1110_M_0011_N_0010,
	store_rm_disp_rn_l_D_1111_M_0011_N_0010,
	store_rm_disp_rn_l_D_0000_M_0100_N_0010,
	store_rm_disp_rn_l_D_0001_M_0100_N_0010,
	store_rm_disp_rn_l_D_0010_M_0100_N_0010,
	store_rm_disp_rn_l_D_0011_M_0100_N_0010,
	store_rm_disp_rn_l_D_0100_M_0100_N_0010,
	store_rm_disp_rn_l_D_0101_M_0100_N_0010,
	store_rm_disp_rn_l_D_0110_M_0100_N_0010,
	store_rm_disp_rn_l_D_0111_M_0100_N_0010,
	store_rm_disp_rn_l_D_1000_M_0100_N_0010,
	store_rm_disp_rn_l_D_1001_M_0100_N_0010,
	store_rm_disp_rn_l_D_1010_M_0100_N_0010,
	store_rm_disp_rn_l_D_1011_M_0100_N_0010,
	store_rm_disp_rn_l_D_1100_M_0100_N_0010,
	store_rm_disp_rn_l_D_1101_M_0100_N_0010,
	store_rm_disp_rn_l_D_1110_M_0100_N_0010,
	store_rm_disp_rn_l_D_1111_M_0100_N_0010,
	store_rm_disp_rn_l_D_0000_M_0101_N_0010,
	store_rm_disp_rn_l_D_0001_M_0101_N_0010,
	store_rm_disp_rn_l_D_0010_M_0101_N_0010,
	store_rm_disp_rn_l_D_0011_M_0101_N_0010,
	store_rm_disp_rn_l_D_0100_M_0101_N_0010,
	store_rm_disp_rn_l_D_0101_M_0101_N_0010,
	store_rm_disp_rn_l_D_0110_M_0101_N_0010,
	store_rm_disp_rn_l_D_0111_M_0101_N_0010,
	store_rm_disp_rn_l_D_1000_M_0101_N_0010,
	store_rm_disp_rn_l_D_1001_M_0101_N_0010,
	store_rm_disp_rn_l_D_1010_M_0101_N_0010,
	store_rm_disp_rn_l_D_1011_M_0101_N_0010,
	store_rm_disp_rn_l_D_1100_M_0101_N_0010,
	store_rm_disp_rn_l_D_1101_M_0101_N_0010,
	store_rm_disp_rn_l_D_1110_M_0101_N_0010,
	store_rm_disp_rn_l_D_1111_M_0101_N_0010,
	store_rm_disp_rn_l_D_0000_M_0110_N_0010,
	store_rm_disp_rn_l_D_0001_M_0110_N_0010,
	store_rm_disp_rn_l_D_0010_M_0110_N_0010,
	store_rm_disp_rn_l_D_0011_M_0110_N_0010,
	store_rm_disp_rn_l_D_0100_M_0110_N_0010,
	store_rm_disp_rn_l_D_0101_M_0110_N_0010,
	store_rm_disp_rn_l_D_0110_M_0110_N_0010,
	store_rm_disp_rn_l_D_0111_M_0110_N_0010,
	store_rm_disp_rn_l_D_1000_M_0110_N_0010,
	store_rm_disp_rn_l_D_1001_M_0110_N_0010,
	store_rm_disp_rn_l_D_1010_M_0110_N_0010,
	store_rm_disp_rn_l_D_1011_M_0110_N_0010,
	store_rm_disp_rn_l_D_1100_M_0110_N_0010,
	store_rm_disp_rn_l_D_1101_M_0110_N_0010,
	store_rm_disp_rn_l_D_1110_M_0110_N_0010,
	store_rm_disp_rn_l_D_1111_M_0110_N_0010,
	store_rm_disp_rn_l_D_0000_M_0111_N_0010,
	store_rm_disp_rn_l_D_0001_M_0111_N_0010,
	store_rm_disp_rn_l_D_0010_M_0111_N_0010,
	store_rm_disp_rn_l_D_0011_M_0111_N_0010,
	store_rm_disp_rn_l_D_0100_M_0111_N_0010,
	store_rm_disp_rn_l_D_0101_M_0111_N_0010,
	store_rm_disp_rn_l_D_0110_M_0111_N_0010,
	store_rm_disp_rn_l_D_0111_M_0111_N_0010,
	store_rm_disp_rn_l_D_1000_M_0111_N_0010,
	store_rm_disp_rn_l_D_1001_M_0111_N_0010,
	store_rm_disp_rn_l_D_1010_M_0111_N_0010,
	store_rm_disp_rn_l_D_1011_M_0111_N_0010,
	store_rm_disp_rn_l_D_1100_M_0111_N_0010,
	store_rm_disp_rn_l_D_1101_M_0111_N_0010,
	store_rm_disp_rn_l_D_1110_M_0111_N_0010,
	store_rm_disp_rn_l_D_1111_M_0111_N_0010,
	store_rm_disp_rn_l_D_0000_M_1000_N_0010,
	store_rm_disp_rn_l_D_0001_M_1000_N_0010,
	store_rm_disp_rn_l_D_0010_M_1000_N_0010,
	store_rm_disp_rn_l_D_0011_M_1000_N_0010,
	store_rm_disp_rn_l_D_0100_M_1000_N_0010,
	store_rm_disp_rn_l_D_0101_M_1000_N_0010,
	store_rm_disp_rn_l_D_0110_M_1000_N_0010,
	store_rm_disp_rn_l_D_0111_M_1000_N_0010,
	store_rm_disp_rn_l_D_1000_M_1000_N_0010,
	store_rm_disp_rn_l_D_1001_M_1000_N_0010,
	store_rm_disp_rn_l_D_1010_M_1000_N_0010,
	store_rm_disp_rn_l_D_1011_M_1000_N_0010,
	store_rm_disp_rn_l_D_1100_M_1000_N_0010,
	store_rm_disp_rn_l_D_1101_M_1000_N_0010,
	store_rm_disp_rn_l_D_1110_M_1000_N_0010,
	store_rm_disp_rn_l_D_1111_M_1000_N_0010,
	store_rm_disp_rn_l_D_0000_M_1001_N_0010,
	store_rm_disp_rn_l_D_0001_M_1001_N_0010,
	store_rm_disp_rn_l_D_0010_M_1001_N_0010,
	store_rm_disp_rn_l_D_0011_M_1001_N_0010,
	store_rm_disp_rn_l_D_0100_M_1001_N_0010,
	store_rm_disp_rn_l_D_0101_M_1001_N_0010,
	store_rm_disp_rn_l_D_0110_M_1001_N_0010,
	store_rm_disp_rn_l_D_0111_M_1001_N_0010,
	store_rm_disp_rn_l_D_1000_M_1001_N_0010,
	store_rm_disp_rn_l_D_1001_M_1001_N_0010,
	store_rm_disp_rn_l_D_1010_M_1001_N_0010,
	store_rm_disp_rn_l_D_1011_M_1001_N_0010,
	store_rm_disp_rn_l_D_1100_M_1001_N_0010,
	store_rm_disp_rn_l_D_1101_M_1001_N_0010,
	store_rm_disp_rn_l_D_1110_M_1001_N_0010,
	store_rm_disp_rn_l_D_1111_M_1001_N_0010,
	store_rm_disp_rn_l_D_0000_M_1010_N_0010,
	store_rm_disp_rn_l_D_0001_M_1010_N_0010,
	store_rm_disp_rn_l_D_0010_M_1010_N_0010,
	store_rm_disp_rn_l_D_0011_M_1010_N_0010,
	store_rm_disp_rn_l_D_0100_M_1010_N_0010,
	store_rm_disp_rn_l_D_0101_M_1010_N_0010,
	store_rm_disp_rn_l_D_0110_M_1010_N_0010,
	store_rm_disp_rn_l_D_0111_M_1010_N_0010,
	store_rm_disp_rn_l_D_1000_M_1010_N_0010,
	store_rm_disp_rn_l_D_1001_M_1010_N_0010,
	store_rm_disp_rn_l_D_1010_M_1010_N_0010,
	store_rm_disp_rn_l_D_1011_M_1010_N_0010,
	store_rm_disp_rn_l_D_1100_M_1010_N_0010,
	store_rm_disp_rn_l_D_1101_M_1010_N_0010,
	store_rm_disp_rn_l_D_1110_M_1010_N_0010,
	store_rm_disp_rn_l_D_1111_M_1010_N_0010,
	store_rm_disp_rn_l_D_0000_M_1011_N_0010,
	store_rm_disp_rn_l_D_0001_M_1011_N_0010,
	store_rm_disp_rn_l_D_0010_M_1011_N_0010,
	store_rm_disp_rn_l_D_0011_M_1011_N_0010,
	store_rm_disp_rn_l_D_0100_M_1011_N_0010,
	store_rm_disp_rn_l_D_0101_M_1011_N_0010,
	store_rm_disp_rn_l_D_0110_M_1011_N_0010,
	store_rm_disp_rn_l_D_0111_M_1011_N_0010,
	store_rm_disp_rn_l_D_1000_M_1011_N_0010,
	store_rm_disp_rn_l_D_1001_M_1011_N_0010,
	store_rm_disp_rn_l_D_1010_M_1011_N_0010,
	store_rm_disp_rn_l_D_1011_M_1011_N_0010,
	store_rm_disp_rn_l_D_1100_M_1011_N_0010,
	store_rm_disp_rn_l_D_1101_M_1011_N_0010,
	store_rm_disp_rn_l_D_1110_M_1011_N_0010,
	store_rm_disp_rn_l_D_1111_M_1011_N_0010,
	store_rm_disp_rn_l_D_0000_M_1100_N_0010,
	store_rm_disp_rn_l_D_0001_M_1100_N_0010,
	store_rm_disp_rn_l_D_0010_M_1100_N_0010,
	store_rm_disp_rn_l_D_0011_M_1100_N_0010,
	store_rm_disp_rn_l_D_0100_M_1100_N_0010,
	store_rm_disp_rn_l_D_0101_M_1100_N_0010,
	store_rm_disp_rn_l_D_0110_M_1100_N_0010,
	store_rm_disp_rn_l_D_0111_M_1100_N_0010,
	store_rm_disp_rn_l_D_1000_M_1100_N_0010,
	store_rm_disp_rn_l_D_1001_M_1100_N_0010,
	store_rm_disp_rn_l_D_1010_M_1100_N_0010,
	store_rm_disp_rn_l_D_1011_M_1100_N_0010,
	store_rm_disp_rn_l_D_1100_M_1100_N_0010,
	store_rm_disp_rn_l_D_1101_M_1100_N_0010,
	store_rm_disp_rn_l_D_1110_M_1100_N_0010,
	store_rm_disp_rn_l_D_1111_M_1100_N_0010,
	store_rm_disp_rn_l_D_0000_M_1101_N_0010,
	store_rm_disp_rn_l_D_0001_M_1101_N_0010,
	store_rm_disp_rn_l_D_0010_M_1101_N_0010,
	store_rm_disp_rn_l_D_0011_M_1101_N_0010,
	store_rm_disp_rn_l_D_0100_M_1101_N_0010,
	store_rm_disp_rn_l_D_0101_M_1101_N_0010,
	store_rm_disp_rn_l_D_0110_M_1101_N_0010,
	store_rm_disp_rn_l_D_0111_M_1101_N_0010,
	store_rm_disp_rn_l_D_1000_M_1101_N_0010,
	store_rm_disp_rn_l_D_1001_M_1101_N_0010,
	store_rm_disp_rn_l_D_1010_M_1101_N_0010,
	store_rm_disp_rn_l_D_1011_M_1101_N_0010,
	store_rm_disp_rn_l_D_1100_M_1101_N_0010,
	store_rm_disp_rn_l_D_1101_M_1101_N_0010,
	store_rm_disp_rn_l_D_1110_M_1101_N_0010,
	store_rm_disp_rn_l_D_1111_M_1101_N_0010,
	store_rm_disp_rn_l_D_0000_M_1110_N_0010,
	store_rm_disp_rn_l_D_0001_M_1110_N_0010,
	store_rm_disp_rn_l_D_0010_M_1110_N_0010,
	store_rm_disp_rn_l_D_0011_M_1110_N_0010,
	store_rm_disp_rn_l_D_0100_M_1110_N_0010,
	store_rm_disp_rn_l_D_0101_M_1110_N_0010,
	store_rm_disp_rn_l_D_0110_M_1110_N_0010,
	store_rm_disp_rn_l_D_0111_M_1110_N_0010,
	store_rm_disp_rn_l_D_1000_M_1110_N_0010,
	store_rm_disp_rn_l_D_1001_M_1110_N_0010,
	store_rm_disp_rn_l_D_1010_M_1110_N_0010,
	store_rm_disp_rn_l_D_1011_M_1110_N_0010,
	store_rm_disp_rn_l_D_1100_M_1110_N_0010,
	store_rm_disp_rn_l_D_1101_M_1110_N_0010,
	store_rm_disp_rn_l_D_1110_M_1110_N_0010,
	store_rm_disp_rn_l_D_1111_M_1110_N_0010,
	store_rm_disp_rn_l_D_0000_M_1111_N_0010,
	store_rm_disp_rn_l_D_0001_M_1111_N_0010,
	store_rm_disp_rn_l_D_0010_M_1111_N_0010,
	store_rm_disp_rn_l_D_0011_M_1111_N_0010,
	store_rm_disp_rn_l_D_0100_M_1111_N_0010,
	store_rm_disp_rn_l_D_0101_M_1111_N_0010,
	store_rm_disp_rn_l_D_0110_M_1111_N_0010,
	store_rm_disp_rn_l_D_0111_M_1111_N_0010,
	store_rm_disp_rn_l_D_1000_M_1111_N_0010,
	store_rm_disp_rn_l_D_1001_M_1111_N_0010,
	store_rm_disp_rn_l_D_1010_M_1111_N_0010,
	store_rm_disp_rn_l_D_1011_M_1111_N_0010,
	store_rm_disp_rn_l_D_1100_M_1111_N_0010,
	store_rm_disp_rn_l_D_1101_M_1111_N_0010,
	store_rm_disp_rn_l_D_1110_M_1111_N_0010,
	store_rm_disp_rn_l_D_1111_M_1111_N_0010,
	store_rm_disp_rn_l_D_0000_M_0000_N_0011,
	store_rm_disp_rn_l_D_0001_M_0000_N_0011,
	store_rm_disp_rn_l_D_0010_M_0000_N_0011,
	store_rm_disp_rn_l_D_0011_M_0000_N_0011,
	store_rm_disp_rn_l_D_0100_M_0000_N_0011,
	store_rm_disp_rn_l_D_0101_M_0000_N_0011,
	store_rm_disp_rn_l_D_0110_M_0000_N_0011,
	store_rm_disp_rn_l_D_0111_M_0000_N_0011,
	store_rm_disp_rn_l_D_1000_M_0000_N_0011,
	store_rm_disp_rn_l_D_1001_M_0000_N_0011,
	store_rm_disp_rn_l_D_1010_M_0000_N_0011,
	store_rm_disp_rn_l_D_1011_M_0000_N_0011,
	store_rm_disp_rn_l_D_1100_M_0000_N_0011,
	store_rm_disp_rn_l_D_1101_M_0000_N_0011,
	store_rm_disp_rn_l_D_1110_M_0000_N_0011,
	store_rm_disp_rn_l_D_1111_M_0000_N_0011,
	store_rm_disp_rn_l_D_0000_M_0001_N_0011,
	store_rm_disp_rn_l_D_0001_M_0001_N_0011,
	store_rm_disp_rn_l_D_0010_M_0001_N_0011,
	store_rm_disp_rn_l_D_0011_M_0001_N_0011,
	store_rm_disp_rn_l_D_0100_M_0001_N_0011,
	store_rm_disp_rn_l_D_0101_M_0001_N_0011,
	store_rm_disp_rn_l_D_0110_M_0001_N_0011,
	store_rm_disp_rn_l_D_0111_M_0001_N_0011,
	store_rm_disp_rn_l_D_1000_M_0001_N_0011,
	store_rm_disp_rn_l_D_1001_M_0001_N_0011,
	store_rm_disp_rn_l_D_1010_M_0001_N_0011,
	store_rm_disp_rn_l_D_1011_M_0001_N_0011,
	store_rm_disp_rn_l_D_1100_M_0001_N_0011,
	store_rm_disp_rn_l_D_1101_M_0001_N_0011,
	store_rm_disp_rn_l_D_1110_M_0001_N_0011,
	store_rm_disp_rn_l_D_1111_M_0001_N_0011,
	store_rm_disp_rn_l_D_0000_M_0010_N_0011,
	store_rm_disp_rn_l_D_0001_M_0010_N_0011,
	store_rm_disp_rn_l_D_0010_M_0010_N_0011,
	store_rm_disp_rn_l_D_0011_M_0010_N_0011,
	store_rm_disp_rn_l_D_0100_M_0010_N_0011,
	store_rm_disp_rn_l_D_0101_M_0010_N_0011,
	store_rm_disp_rn_l_D_0110_M_0010_N_0011,
	store_rm_disp_rn_l_D_0111_M_0010_N_0011,
	store_rm_disp_rn_l_D_1000_M_0010_N_0011,
	store_rm_disp_rn_l_D_1001_M_0010_N_0011,
	store_rm_disp_rn_l_D_1010_M_0010_N_0011,
	store_rm_disp_rn_l_D_1011_M_0010_N_0011,
	store_rm_disp_rn_l_D_1100_M_0010_N_0011,
	store_rm_disp_rn_l_D_1101_M_0010_N_0011,
	store_rm_disp_rn_l_D_1110_M_0010_N_0011,
	store_rm_disp_rn_l_D_1111_M_0010_N_0011,
	store_rm_disp_rn_l_D_0000_M_0011_N_0011,
	store_rm_disp_rn_l_D_0001_M_0011_N_0011,
	store_rm_disp_rn_l_D_0010_M_0011_N_0011,
	store_rm_disp_rn_l_D_0011_M_0011_N_0011,
	store_rm_disp_rn_l_D_0100_M_0011_N_0011,
	store_rm_disp_rn_l_D_0101_M_0011_N_0011,
	store_rm_disp_rn_l_D_0110_M_0011_N_0011,
	store_rm_disp_rn_l_D_0111_M_0011_N_0011,
	store_rm_disp_rn_l_D_1000_M_0011_N_0011,
	store_rm_disp_rn_l_D_1001_M_0011_N_0011,
	store_rm_disp_rn_l_D_1010_M_0011_N_0011,
	store_rm_disp_rn_l_D_1011_M_0011_N_0011,
	store_rm_disp_rn_l_D_1100_M_0011_N_0011,
	store_rm_disp_rn_l_D_1101_M_0011_N_0011,
	store_rm_disp_rn_l_D_1110_M_0011_N_0011,
	store_rm_disp_rn_l_D_1111_M_0011_N_0011,
	store_rm_disp_rn_l_D_0000_M_0100_N_0011,
	store_rm_disp_rn_l_D_0001_M_0100_N_0011,
	store_rm_disp_rn_l_D_0010_M_0100_N_0011,
	store_rm_disp_rn_l_D_0011_M_0100_N_0011,
	store_rm_disp_rn_l_D_0100_M_0100_N_0011,
	store_rm_disp_rn_l_D_0101_M_0100_N_0011,
	store_rm_disp_rn_l_D_0110_M_0100_N_0011,
	store_rm_disp_rn_l_D_0111_M_0100_N_0011,
	store_rm_disp_rn_l_D_1000_M_0100_N_0011,
	store_rm_disp_rn_l_D_1001_M_0100_N_0011,
	store_rm_disp_rn_l_D_1010_M_0100_N_0011,
	store_rm_disp_rn_l_D_1011_M_0100_N_0011,
	store_rm_disp_rn_l_D_1100_M_0100_N_0011,
	store_rm_disp_rn_l_D_1101_M_0100_N_0011,
	store_rm_disp_rn_l_D_1110_M_0100_N_0011,
	store_rm_disp_rn_l_D_1111_M_0100_N_0011,
	store_rm_disp_rn_l_D_0000_M_0101_N_0011,
	store_rm_disp_rn_l_D_0001_M_0101_N_0011,
	store_rm_disp_rn_l_D_0010_M_0101_N_0011,
	store_rm_disp_rn_l_D_0011_M_0101_N_0011,
	store_rm_disp_rn_l_D_0100_M_0101_N_0011,
	store_rm_disp_rn_l_D_0101_M_0101_N_0011,
	store_rm_disp_rn_l_D_0110_M_0101_N_0011,
	store_rm_disp_rn_l_D_0111_M_0101_N_0011,
	store_rm_disp_rn_l_D_1000_M_0101_N_0011,
	store_rm_disp_rn_l_D_1001_M_0101_N_0011,
	store_rm_disp_rn_l_D_1010_M_0101_N_0011,
	store_rm_disp_rn_l_D_1011_M_0101_N_0011,
	store_rm_disp_rn_l_D_1100_M_0101_N_0011,
	store_rm_disp_rn_l_D_1101_M_0101_N_0011,
	store_rm_disp_rn_l_D_1110_M_0101_N_0011,
	store_rm_disp_rn_l_D_1111_M_0101_N_0011,
	store_rm_disp_rn_l_D_0000_M_0110_N_0011,
	store_rm_disp_rn_l_D_0001_M_0110_N_0011,
	store_rm_disp_rn_l_D_0010_M_0110_N_0011,
	store_rm_disp_rn_l_D_0011_M_0110_N_0011,
	store_rm_disp_rn_l_D_0100_M_0110_N_0011,
	store_rm_disp_rn_l_D_0101_M_0110_N_0011,
	store_rm_disp_rn_l_D_0110_M_0110_N_0011,
	store_rm_disp_rn_l_D_0111_M_0110_N_0011,
	store_rm_disp_rn_l_D_1000_M_0110_N_0011,
	store_rm_disp_rn_l_D_1001_M_0110_N_0011,
	store_rm_disp_rn_l_D_1010_M_0110_N_0011,
	store_rm_disp_rn_l_D_1011_M_0110_N_0011,
	store_rm_disp_rn_l_D_1100_M_0110_N_0011,
	store_rm_disp_rn_l_D_1101_M_0110_N_0011,
	store_rm_disp_rn_l_D_1110_M_0110_N_0011,
	store_rm_disp_rn_l_D_1111_M_0110_N_0011,
	store_rm_disp_rn_l_D_0000_M_0111_N_0011,
	store_rm_disp_rn_l_D_0001_M_0111_N_0011,
	store_rm_disp_rn_l_D_0010_M_0111_N_0011,
	store_rm_disp_rn_l_D_0011_M_0111_N_0011,
	store_rm_disp_rn_l_D_0100_M_0111_N_0011,
	store_rm_disp_rn_l_D_0101_M_0111_N_0011,
	store_rm_disp_rn_l_D_0110_M_0111_N_0011,
	store_rm_disp_rn_l_D_0111_M_0111_N_0011,
	store_rm_disp_rn_l_D_1000_M_0111_N_0011,
	store_rm_disp_rn_l_D_1001_M_0111_N_0011,
	store_rm_disp_rn_l_D_1010_M_0111_N_0011,
	store_rm_disp_rn_l_D_1011_M_0111_N_0011,
	store_rm_disp_rn_l_D_1100_M_0111_N_0011,
	store_rm_disp_rn_l_D_1101_M_0111_N_0011,
	store_rm_disp_rn_l_D_1110_M_0111_N_0011,
	store_rm_disp_rn_l_D_1111_M_0111_N_0011,
	store_rm_disp_rn_l_D_0000_M_1000_N_0011,
	store_rm_disp_rn_l_D_0001_M_1000_N_0011,
	store_rm_disp_rn_l_D_0010_M_1000_N_0011,
	store_rm_disp_rn_l_D_0011_M_1000_N_0011,
	store_rm_disp_rn_l_D_0100_M_1000_N_0011,
	store_rm_disp_rn_l_D_0101_M_1000_N_0011,
	store_rm_disp_rn_l_D_0110_M_1000_N_0011,
	store_rm_disp_rn_l_D_0111_M_1000_N_0011,
	store_rm_disp_rn_l_D_1000_M_1000_N_0011,
	store_rm_disp_rn_l_D_1001_M_1000_N_0011,
	store_rm_disp_rn_l_D_1010_M_1000_N_0011,
	store_rm_disp_rn_l_D_1011_M_1000_N_0011,
	store_rm_disp_rn_l_D_1100_M_1000_N_0011,
	store_rm_disp_rn_l_D_1101_M_1000_N_0011,
	store_rm_disp_rn_l_D_1110_M_1000_N_0011,
	store_rm_disp_rn_l_D_1111_M_1000_N_0011,
	store_rm_disp_rn_l_D_0000_M_1001_N_0011,
	store_rm_disp_rn_l_D_0001_M_1001_N_0011,
	store_rm_disp_rn_l_D_0010_M_1001_N_0011,
	store_rm_disp_rn_l_D_0011_M_1001_N_0011,
	store_rm_disp_rn_l_D_0100_M_1001_N_0011,
	store_rm_disp_rn_l_D_0101_M_1001_N_0011,
	store_rm_disp_rn_l_D_0110_M_1001_N_0011,
	store_rm_disp_rn_l_D_0111_M_1001_N_0011,
	store_rm_disp_rn_l_D_1000_M_1001_N_0011,
	store_rm_disp_rn_l_D_1001_M_1001_N_0011,
	store_rm_disp_rn_l_D_1010_M_1001_N_0011,
	store_rm_disp_rn_l_D_1011_M_1001_N_0011,
	store_rm_disp_rn_l_D_1100_M_1001_N_0011,
	store_rm_disp_rn_l_D_1101_M_1001_N_0011,
	store_rm_disp_rn_l_D_1110_M_1001_N_0011,
	store_rm_disp_rn_l_D_1111_M_1001_N_0011,
	store_rm_disp_rn_l_D_0000_M_1010_N_0011,
	store_rm_disp_rn_l_D_0001_M_1010_N_0011,
	store_rm_disp_rn_l_D_0010_M_1010_N_0011,
	store_rm_disp_rn_l_D_0011_M_1010_N_0011,
	store_rm_disp_rn_l_D_0100_M_1010_N_0011,
	store_rm_disp_rn_l_D_0101_M_1010_N_0011,
	store_rm_disp_rn_l_D_0110_M_1010_N_0011,
	store_rm_disp_rn_l_D_0111_M_1010_N_0011,
	store_rm_disp_rn_l_D_1000_M_1010_N_0011,
	store_rm_disp_rn_l_D_1001_M_1010_N_0011,
	store_rm_disp_rn_l_D_1010_M_1010_N_0011,
	store_rm_disp_rn_l_D_1011_M_1010_N_0011,
	store_rm_disp_rn_l_D_1100_M_1010_N_0011,
	store_rm_disp_rn_l_D_1101_M_1010_N_0011,
	store_rm_disp_rn_l_D_1110_M_1010_N_0011,
	store_rm_disp_rn_l_D_1111_M_1010_N_0011,
	store_rm_disp_rn_l_D_0000_M_1011_N_0011,
	store_rm_disp_rn_l_D_0001_M_1011_N_0011,
	store_rm_disp_rn_l_D_0010_M_1011_N_0011,
	store_rm_disp_rn_l_D_0011_M_1011_N_0011,
	store_rm_disp_rn_l_D_0100_M_1011_N_0011,
	store_rm_disp_rn_l_D_0101_M_1011_N_0011,
	store_rm_disp_rn_l_D_0110_M_1011_N_0011,
	store_rm_disp_rn_l_D_0111_M_1011_N_0011,
	store_rm_disp_rn_l_D_1000_M_1011_N_0011,
	store_rm_disp_rn_l_D_1001_M_1011_N_0011,
	store_rm_disp_rn_l_D_1010_M_1011_N_0011,
	store_rm_disp_rn_l_D_1011_M_1011_N_0011,
	store_rm_disp_rn_l_D_1100_M_1011_N_0011,
	store_rm_disp_rn_l_D_1101_M_1011_N_0011,
	store_rm_disp_rn_l_D_1110_M_1011_N_0011,
	store_rm_disp_rn_l_D_1111_M_1011_N_0011,
	store_rm_disp_rn_l_D_0000_M_1100_N_0011,
	store_rm_disp_rn_l_D_0001_M_1100_N_0011,
	store_rm_disp_rn_l_D_0010_M_1100_N_0011,
	store_rm_disp_rn_l_D_0011_M_1100_N_0011,
	store_rm_disp_rn_l_D_0100_M_1100_N_0011,
	store_rm_disp_rn_l_D_0101_M_1100_N_0011,
	store_rm_disp_rn_l_D_0110_M_1100_N_0011,
	store_rm_disp_rn_l_D_0111_M_1100_N_0011,
	store_rm_disp_rn_l_D_1000_M_1100_N_0011,
	store_rm_disp_rn_l_D_1001_M_1100_N_0011,
	store_rm_disp_rn_l_D_1010_M_1100_N_0011,
	store_rm_disp_rn_l_D_1011_M_1100_N_0011,
	store_rm_disp_rn_l_D_1100_M_1100_N_0011,
	store_rm_disp_rn_l_D_1101_M_1100_N_0011,
	store_rm_disp_rn_l_D_1110_M_1100_N_0011,
	store_rm_disp_rn_l_D_1111_M_1100_N_0011,
	store_rm_disp_rn_l_D_0000_M_1101_N_0011,
	store_rm_disp_rn_l_D_0001_M_1101_N_0011,
	store_rm_disp_rn_l_D_0010_M_1101_N_0011,
	store_rm_disp_rn_l_D_0011_M_1101_N_0011,
	store_rm_disp_rn_l_D_0100_M_1101_N_0011,
	store_rm_disp_rn_l_D_0101_M_1101_N_0011,
	store_rm_disp_rn_l_D_0110_M_1101_N_0011,
	store_rm_disp_rn_l_D_0111_M_1101_N_0011,
	store_rm_disp_rn_l_D_1000_M_1101_N_0011,
	store_rm_disp_rn_l_D_1001_M_1101_N_0011,
	store_rm_disp_rn_l_D_1010_M_1101_N_0011,
	store_rm_disp_rn_l_D_1011_M_1101_N_0011,
	store_rm_disp_rn_l_D_1100_M_1101_N_0011,
	store_rm_disp_rn_l_D_1101_M_1101_N_0011,
	store_rm_disp_rn_l_D_1110_M_1101_N_0011,
	store_rm_disp_rn_l_D_1111_M_1101_N_0011,
	store_rm_disp_rn_l_D_0000_M_1110_N_0011,
	store_rm_disp_rn_l_D_0001_M_1110_N_0011,
	store_rm_disp_rn_l_D_0010_M_1110_N_0011,
	store_rm_disp_rn_l_D_0011_M_1110_N_0011,
	store_rm_disp_rn_l_D_0100_M_1110_N_0011,
	store_rm_disp_rn_l_D_0101_M_1110_N_0011,
	store_rm_disp_rn_l_D_0110_M_1110_N_0011,
	store_rm_disp_rn_l_D_0111_M_1110_N_0011,
	store_rm_disp_rn_l_D_1000_M_1110_N_0011,
	store_rm_disp_rn_l_D_1001_M_1110_N_0011,
	store_rm_disp_rn_l_D_1010_M_1110_N_0011,
	store_rm_disp_rn_l_D_1011_M_1110_N_0011,
	store_rm_disp_rn_l_D_1100_M_1110_N_0011,
	store_rm_disp_rn_l_D_1101_M_1110_N_0011,
	store_rm_disp_rn_l_D_1110_M_1110_N_0011,
	store_rm_disp_rn_l_D_1111_M_1110_N_0011,
	store_rm_disp_rn_l_D_0000_M_1111_N_0011,
	store_rm_disp_rn_l_D_0001_M_1111_N_0011,
	store_rm_disp_rn_l_D_0010_M_1111_N_0011,
	store_rm_disp_rn_l_D_0011_M_1111_N_0011,
	store_rm_disp_rn_l_D_0100_M_1111_N_0011,
	store_rm_disp_rn_l_D_0101_M_1111_N_0011,
	store_rm_disp_rn_l_D_0110_M_1111_N_0011,
	store_rm_disp_rn_l_D_0111_M_1111_N_0011,
	store_rm_disp_rn_l_D_1000_M_1111_N_0011,
	store_rm_disp_rn_l_D_1001_M_1111_N_0011,
	store_rm_disp_rn_l_D_1010_M_1111_N_0011,
	store_rm_disp_rn_l_D_1011_M_1111_N_0011,
	store_rm_disp_rn_l_D_1100_M_1111_N_0011,
	store_rm_disp_rn_l_D_1101_M_1111_N_0011,
	store_rm_disp_rn_l_D_1110_M_1111_N_0011,
	store_rm_disp_rn_l_D_1111_M_1111_N_0011,
	store_rm_disp_rn_l_D_0000_M_0000_N_0100,
	store_rm_disp_rn_l_D_0001_M_0000_N_0100,
	store_rm_disp_rn_l_D_0010_M_0000_N_0100,
	store_rm_disp_rn_l_D_0011_M_0000_N_0100,
	store_rm_disp_rn_l_D_0100_M_0000_N_0100,
	store_rm_disp_rn_l_D_0101_M_0000_N_0100,
	store_rm_disp_rn_l_D_0110_M_0000_N_0100,
	store_rm_disp_rn_l_D_0111_M_0000_N_0100,
	store_rm_disp_rn_l_D_1000_M_0000_N_0100,
	store_rm_disp_rn_l_D_1001_M_0000_N_0100,
	store_rm_disp_rn_l_D_1010_M_0000_N_0100,
	store_rm_disp_rn_l_D_1011_M_0000_N_0100,
	store_rm_disp_rn_l_D_1100_M_0000_N_0100,
	store_rm_disp_rn_l_D_1101_M_0000_N_0100,
	store_rm_disp_rn_l_D_1110_M_0000_N_0100,
	store_rm_disp_rn_l_D_1111_M_0000_N_0100,
	store_rm_disp_rn_l_D_0000_M_0001_N_0100,
	store_rm_disp_rn_l_D_0001_M_0001_N_0100,
	store_rm_disp_rn_l_D_0010_M_0001_N_0100,
	store_rm_disp_rn_l_D_0011_M_0001_N_0100,
	store_rm_disp_rn_l_D_0100_M_0001_N_0100,
	store_rm_disp_rn_l_D_0101_M_0001_N_0100,
	store_rm_disp_rn_l_D_0110_M_0001_N_0100,
	store_rm_disp_rn_l_D_0111_M_0001_N_0100,
	store_rm_disp_rn_l_D_1000_M_0001_N_0100,
	store_rm_disp_rn_l_D_1001_M_0001_N_0100,
	store_rm_disp_rn_l_D_1010_M_0001_N_0100,
	store_rm_disp_rn_l_D_1011_M_0001_N_0100,
	store_rm_disp_rn_l_D_1100_M_0001_N_0100,
	store_rm_disp_rn_l_D_1101_M_0001_N_0100,
	store_rm_disp_rn_l_D_1110_M_0001_N_0100,
	store_rm_disp_rn_l_D_1111_M_0001_N_0100,
	store_rm_disp_rn_l_D_0000_M_0010_N_0100,
	store_rm_disp_rn_l_D_0001_M_0010_N_0100,
	store_rm_disp_rn_l_D_0010_M_0010_N_0100,
	store_rm_disp_rn_l_D_0011_M_0010_N_0100,
	store_rm_disp_rn_l_D_0100_M_0010_N_0100,
	store_rm_disp_rn_l_D_0101_M_0010_N_0100,
	store_rm_disp_rn_l_D_0110_M_0010_N_0100,
	store_rm_disp_rn_l_D_0111_M_0010_N_0100,
	store_rm_disp_rn_l_D_1000_M_0010_N_0100,
	store_rm_disp_rn_l_D_1001_M_0010_N_0100,
	store_rm_disp_rn_l_D_1010_M_0010_N_0100,
	store_rm_disp_rn_l_D_1011_M_0010_N_0100,
	store_rm_disp_rn_l_D_1100_M_0010_N_0100,
	store_rm_disp_rn_l_D_1101_M_0010_N_0100,
	store_rm_disp_rn_l_D_1110_M_0010_N_0100,
	store_rm_disp_rn_l_D_1111_M_0010_N_0100,
	store_rm_disp_rn_l_D_0000_M_0011_N_0100,
	store_rm_disp_rn_l_D_0001_M_0011_N_0100,
	store_rm_disp_rn_l_D_0010_M_0011_N_0100,
	store_rm_disp_rn_l_D_0011_M_0011_N_0100,
	store_rm_disp_rn_l_D_0100_M_0011_N_0100,
	store_rm_disp_rn_l_D_0101_M_0011_N_0100,
	store_rm_disp_rn_l_D_0110_M_0011_N_0100,
	store_rm_disp_rn_l_D_0111_M_0011_N_0100,
	store_rm_disp_rn_l_D_1000_M_0011_N_0100,
	store_rm_disp_rn_l_D_1001_M_0011_N_0100,
	store_rm_disp_rn_l_D_1010_M_0011_N_0100,
	store_rm_disp_rn_l_D_1011_M_0011_N_0100,
	store_rm_disp_rn_l_D_1100_M_0011_N_0100,
	store_rm_disp_rn_l_D_1101_M_0011_N_0100,
	store_rm_disp_rn_l_D_1110_M_0011_N_0100,
	store_rm_disp_rn_l_D_1111_M_0011_N_0100,
	store_rm_disp_rn_l_D_0000_M_0100_N_0100,
	store_rm_disp_rn_l_D_0001_M_0100_N_0100,
	store_rm_disp_rn_l_D_0010_M_0100_N_0100,
	store_rm_disp_rn_l_D_0011_M_0100_N_0100,
	store_rm_disp_rn_l_D_0100_M_0100_N_0100,
	store_rm_disp_rn_l_D_0101_M_0100_N_0100,
	store_rm_disp_rn_l_D_0110_M_0100_N_0100,
	store_rm_disp_rn_l_D_0111_M_0100_N_0100,
	store_rm_disp_rn_l_D_1000_M_0100_N_0100,
	store_rm_disp_rn_l_D_1001_M_0100_N_0100,
	store_rm_disp_rn_l_D_1010_M_0100_N_0100,
	store_rm_disp_rn_l_D_1011_M_0100_N_0100,
	store_rm_disp_rn_l_D_1100_M_0100_N_0100,
	store_rm_disp_rn_l_D_1101_M_0100_N_0100,
	store_rm_disp_rn_l_D_1110_M_0100_N_0100,
	store_rm_disp_rn_l_D_1111_M_0100_N_0100,
	store_rm_disp_rn_l_D_0000_M_0101_N_0100,
	store_rm_disp_rn_l_D_0001_M_0101_N_0100,
	store_rm_disp_rn_l_D_0010_M_0101_N_0100,
	store_rm_disp_rn_l_D_0011_M_0101_N_0100,
	store_rm_disp_rn_l_D_0100_M_0101_N_0100,
	store_rm_disp_rn_l_D_0101_M_0101_N_0100,
	store_rm_disp_rn_l_D_0110_M_0101_N_0100,
	store_rm_disp_rn_l_D_0111_M_0101_N_0100,
	store_rm_disp_rn_l_D_1000_M_0101_N_0100,
	store_rm_disp_rn_l_D_1001_M_0101_N_0100,
	store_rm_disp_rn_l_D_1010_M_0101_N_0100,
	store_rm_disp_rn_l_D_1011_M_0101_N_0100,
	store_rm_disp_rn_l_D_1100_M_0101_N_0100,
	store_rm_disp_rn_l_D_1101_M_0101_N_0100,
	store_rm_disp_rn_l_D_1110_M_0101_N_0100,
	store_rm_disp_rn_l_D_1111_M_0101_N_0100,
	store_rm_disp_rn_l_D_0000_M_0110_N_0100,
	store_rm_disp_rn_l_D_0001_M_0110_N_0100,
	store_rm_disp_rn_l_D_0010_M_0110_N_0100,
	store_rm_disp_rn_l_D_0011_M_0110_N_0100,
	store_rm_disp_rn_l_D_0100_M_0110_N_0100,
	store_rm_disp_rn_l_D_0101_M_0110_N_0100,
	store_rm_disp_rn_l_D_0110_M_0110_N_0100,
	store_rm_disp_rn_l_D_0111_M_0110_N_0100,
	store_rm_disp_rn_l_D_1000_M_0110_N_0100,
	store_rm_disp_rn_l_D_1001_M_0110_N_0100,
	store_rm_disp_rn_l_D_1010_M_0110_N_0100,
	store_rm_disp_rn_l_D_1011_M_0110_N_0100,
	store_rm_disp_rn_l_D_1100_M_0110_N_0100,
	store_rm_disp_rn_l_D_1101_M_0110_N_0100,
	store_rm_disp_rn_l_D_1110_M_0110_N_0100,
	store_rm_disp_rn_l_D_1111_M_0110_N_0100,
	store_rm_disp_rn_l_D_0000_M_0111_N_0100,
	store_rm_disp_rn_l_D_0001_M_0111_N_0100,
	store_rm_disp_rn_l_D_0010_M_0111_N_0100,
	store_rm_disp_rn_l_D_0011_M_0111_N_0100,
	store_rm_disp_rn_l_D_0100_M_0111_N_0100,
	store_rm_disp_rn_l_D_0101_M_0111_N_0100,
	store_rm_disp_rn_l_D_0110_M_0111_N_0100,
	store_rm_disp_rn_l_D_0111_M_0111_N_0100,
	store_rm_disp_rn_l_D_1000_M_0111_N_0100,
	store_rm_disp_rn_l_D_1001_M_0111_N_0100,
	store_rm_disp_rn_l_D_1010_M_0111_N_0100,
	store_rm_disp_rn_l_D_1011_M_0111_N_0100,
	store_rm_disp_rn_l_D_1100_M_0111_N_0100,
	store_rm_disp_rn_l_D_1101_M_0111_N_0100,
	store_rm_disp_rn_l_D_1110_M_0111_N_0100,
	store_rm_disp_rn_l_D_1111_M_0111_N_0100,
	store_rm_disp_rn_l_D_0000_M_1000_N_0100,
	store_rm_disp_rn_l_D_0001_M_1000_N_0100,
	store_rm_disp_rn_l_D_0010_M_1000_N_0100,
	store_rm_disp_rn_l_D_0011_M_1000_N_0100,
	store_rm_disp_rn_l_D_0100_M_1000_N_0100,
	store_rm_disp_rn_l_D_0101_M_1000_N_0100,
	store_rm_disp_rn_l_D_0110_M_1000_N_0100,
	store_rm_disp_rn_l_D_0111_M_1000_N_0100,
	store_rm_disp_rn_l_D_1000_M_1000_N_0100,
	store_rm_disp_rn_l_D_1001_M_1000_N_0100,
	store_rm_disp_rn_l_D_1010_M_1000_N_0100,
	store_rm_disp_rn_l_D_1011_M_1000_N_0100,
	store_rm_disp_rn_l_D_1100_M_1000_N_0100,
	store_rm_disp_rn_l_D_1101_M_1000_N_0100,
	store_rm_disp_rn_l_D_1110_M_1000_N_0100,
	store_rm_disp_rn_l_D_1111_M_1000_N_0100,
	store_rm_disp_rn_l_D_0000_M_1001_N_0100,
	store_rm_disp_rn_l_D_0001_M_1001_N_0100,
	store_rm_disp_rn_l_D_0010_M_1001_N_0100,
	store_rm_disp_rn_l_D_0011_M_1001_N_0100,
	store_rm_disp_rn_l_D_0100_M_1001_N_0100,
	store_rm_disp_rn_l_D_0101_M_1001_N_0100,
	store_rm_disp_rn_l_D_0110_M_1001_N_0100,
	store_rm_disp_rn_l_D_0111_M_1001_N_0100,
	store_rm_disp_rn_l_D_1000_M_1001_N_0100,
	store_rm_disp_rn_l_D_1001_M_1001_N_0100,
	store_rm_disp_rn_l_D_1010_M_1001_N_0100,
	store_rm_disp_rn_l_D_1011_M_1001_N_0100,
	store_rm_disp_rn_l_D_1100_M_1001_N_0100,
	store_rm_disp_rn_l_D_1101_M_1001_N_0100,
	store_rm_disp_rn_l_D_1110_M_1001_N_0100,
	store_rm_disp_rn_l_D_1111_M_1001_N_0100,
	store_rm_disp_rn_l_D_0000_M_1010_N_0100,
	store_rm_disp_rn_l_D_0001_M_1010_N_0100,
	store_rm_disp_rn_l_D_0010_M_1010_N_0100,
	store_rm_disp_rn_l_D_0011_M_1010_N_0100,
	store_rm_disp_rn_l_D_0100_M_1010_N_0100,
	store_rm_disp_rn_l_D_0101_M_1010_N_0100,
	store_rm_disp_rn_l_D_0110_M_1010_N_0100,
	store_rm_disp_rn_l_D_0111_M_1010_N_0100,
	store_rm_disp_rn_l_D_1000_M_1010_N_0100,
	store_rm_disp_rn_l_D_1001_M_1010_N_0100,
	store_rm_disp_rn_l_D_1010_M_1010_N_0100,
	store_rm_disp_rn_l_D_1011_M_1010_N_0100,
	store_rm_disp_rn_l_D_1100_M_1010_N_0100,
	store_rm_disp_rn_l_D_1101_M_1010_N_0100,
	store_rm_disp_rn_l_D_1110_M_1010_N_0100,
	store_rm_disp_rn_l_D_1111_M_1010_N_0100,
	store_rm_disp_rn_l_D_0000_M_1011_N_0100,
	store_rm_disp_rn_l_D_0001_M_1011_N_0100,
	store_rm_disp_rn_l_D_0010_M_1011_N_0100,
	store_rm_disp_rn_l_D_0011_M_1011_N_0100,
	store_rm_disp_rn_l_D_0100_M_1011_N_0100,
	store_rm_disp_rn_l_D_0101_M_1011_N_0100,
	store_rm_disp_rn_l_D_0110_M_1011_N_0100,
	store_rm_disp_rn_l_D_0111_M_1011_N_0100,
	store_rm_disp_rn_l_D_1000_M_1011_N_0100,
	store_rm_disp_rn_l_D_1001_M_1011_N_0100,
	store_rm_disp_rn_l_D_1010_M_1011_N_0100,
	store_rm_disp_rn_l_D_1011_M_1011_N_0100,
	store_rm_disp_rn_l_D_1100_M_1011_N_0100,
	store_rm_disp_rn_l_D_1101_M_1011_N_0100,
	store_rm_disp_rn_l_D_1110_M_1011_N_0100,
	store_rm_disp_rn_l_D_1111_M_1011_N_0100,
	store_rm_disp_rn_l_D_0000_M_1100_N_0100,
	store_rm_disp_rn_l_D_0001_M_1100_N_0100,
	store_rm_disp_rn_l_D_0010_M_1100_N_0100,
	store_rm_disp_rn_l_D_0011_M_1100_N_0100,
	store_rm_disp_rn_l_D_0100_M_1100_N_0100,
	store_rm_disp_rn_l_D_0101_M_1100_N_0100,
	store_rm_disp_rn_l_D_0110_M_1100_N_0100,
	store_rm_disp_rn_l_D_0111_M_1100_N_0100,
	store_rm_disp_rn_l_D_1000_M_1100_N_0100,
	store_rm_disp_rn_l_D_1001_M_1100_N_0100,
	store_rm_disp_rn_l_D_1010_M_1100_N_0100,
	store_rm_disp_rn_l_D_1011_M_1100_N_0100,
	store_rm_disp_rn_l_D_1100_M_1100_N_0100,
	store_rm_disp_rn_l_D_1101_M_1100_N_0100,
	store_rm_disp_rn_l_D_1110_M_1100_N_0100,
	store_rm_disp_rn_l_D_1111_M_1100_N_0100,
	store_rm_disp_rn_l_D_0000_M_1101_N_0100,
	store_rm_disp_rn_l_D_0001_M_1101_N_0100,
	store_rm_disp_rn_l_D_0010_M_1101_N_0100,
	store_rm_disp_rn_l_D_0011_M_1101_N_0100,
	store_rm_disp_rn_l_D_0100_M_1101_N_0100,
	store_rm_disp_rn_l_D_0101_M_1101_N_0100,
	store_rm_disp_rn_l_D_0110_M_1101_N_0100,
	store_rm_disp_rn_l_D_0111_M_1101_N_0100,
	store_rm_disp_rn_l_D_1000_M_1101_N_0100,
	store_rm_disp_rn_l_D_1001_M_1101_N_0100,
	store_rm_disp_rn_l_D_1010_M_1101_N_0100,
	store_rm_disp_rn_l_D_1011_M_1101_N_0100,
	store_rm_disp_rn_l_D_1100_M_1101_N_0100,
	store_rm_disp_rn_l_D_1101_M_1101_N_0100,
	store_rm_disp_rn_l_D_1110_M_1101_N_0100,
	store_rm_disp_rn_l_D_1111_M_1101_N_0100,
	store_rm_disp_rn_l_D_0000_M_1110_N_0100,
	store_rm_disp_rn_l_D_0001_M_1110_N_0100,
	store_rm_disp_rn_l_D_0010_M_1110_N_0100,
	store_rm_disp_rn_l_D_0011_M_1110_N_0100,
	store_rm_disp_rn_l_D_0100_M_1110_N_0100,
	store_rm_disp_rn_l_D_0101_M_1110_N_0100,
	store_rm_disp_rn_l_D_0110_M_1110_N_0100,
	store_rm_disp_rn_l_D_0111_M_1110_N_0100,
	store_rm_disp_rn_l_D_1000_M_1110_N_0100,
	store_rm_disp_rn_l_D_1001_M_1110_N_0100,
	store_rm_disp_rn_l_D_1010_M_1110_N_0100,
	store_rm_disp_rn_l_D_1011_M_1110_N_0100,
	store_rm_disp_rn_l_D_1100_M_1110_N_0100,
	store_rm_disp_rn_l_D_1101_M_1110_N_0100,
	store_rm_disp_rn_l_D_1110_M_1110_N_0100,
	store_rm_disp_rn_l_D_1111_M_1110_N_0100,
	store_rm_disp_rn_l_D_0000_M_1111_N_0100,
	store_rm_disp_rn_l_D_0001_M_1111_N_0100,
	store_rm_disp_rn_l_D_0010_M_1111_N_0100,
	store_rm_disp_rn_l_D_0011_M_1111_N_0100,
	store_rm_disp_rn_l_D_0100_M_1111_N_0100,
	store_rm_disp_rn_l_D_0101_M_1111_N_0100,
	store_rm_disp_rn_l_D_0110_M_1111_N_0100,
	store_rm_disp_rn_l_D_0111_M_1111_N_0100,
	store_rm_disp_rn_l_D_1000_M_1111_N_0100,
	store_rm_disp_rn_l_D_1001_M_1111_N_0100,
	store_rm_disp_rn_l_D_1010_M_1111_N_0100,
	store_rm_disp_rn_l_D_1011_M_1111_N_0100,
	store_rm_disp_rn_l_D_1100_M_1111_N_0100,
	store_rm_disp_rn_l_D_1101_M_1111_N_0100,
	store_rm_disp_rn_l_D_1110_M_1111_N_0100,
	store_rm_disp_rn_l_D_1111_M_1111_N_0100,
	store_rm_disp_rn_l_D_0000_M_0000_N_0101,
	store_rm_disp_rn_l_D_0001_M_0000_N_0101,
	store_rm_disp_rn_l_D_0010_M_0000_N_0101,
	store_rm_disp_rn_l_D_0011_M_0000_N_0101,
	store_rm_disp_rn_l_D_0100_M_0000_N_0101,
	store_rm_disp_rn_l_D_0101_M_0000_N_0101,
	store_rm_disp_rn_l_D_0110_M_0000_N_0101,
	store_rm_disp_rn_l_D_0111_M_0000_N_0101,
	store_rm_disp_rn_l_D_1000_M_0000_N_0101,
	store_rm_disp_rn_l_D_1001_M_0000_N_0101,
	store_rm_disp_rn_l_D_1010_M_0000_N_0101,
	store_rm_disp_rn_l_D_1011_M_0000_N_0101,
	store_rm_disp_rn_l_D_1100_M_0000_N_0101,
	store_rm_disp_rn_l_D_1101_M_0000_N_0101,
	store_rm_disp_rn_l_D_1110_M_0000_N_0101,
	store_rm_disp_rn_l_D_1111_M_0000_N_0101,
	store_rm_disp_rn_l_D_0000_M_0001_N_0101,
	store_rm_disp_rn_l_D_0001_M_0001_N_0101,
	store_rm_disp_rn_l_D_0010_M_0001_N_0101,
	store_rm_disp_rn_l_D_0011_M_0001_N_0101,
	store_rm_disp_rn_l_D_0100_M_0001_N_0101,
	store_rm_disp_rn_l_D_0101_M_0001_N_0101,
	store_rm_disp_rn_l_D_0110_M_0001_N_0101,
	store_rm_disp_rn_l_D_0111_M_0001_N_0101,
	store_rm_disp_rn_l_D_1000_M_0001_N_0101,
	store_rm_disp_rn_l_D_1001_M_0001_N_0101,
	store_rm_disp_rn_l_D_1010_M_0001_N_0101,
	store_rm_disp_rn_l_D_1011_M_0001_N_0101,
	store_rm_disp_rn_l_D_1100_M_0001_N_0101,
	store_rm_disp_rn_l_D_1101_M_0001_N_0101,
	store_rm_disp_rn_l_D_1110_M_0001_N_0101,
	store_rm_disp_rn_l_D_1111_M_0001_N_0101,
	store_rm_disp_rn_l_D_0000_M_0010_N_0101,
	store_rm_disp_rn_l_D_0001_M_0010_N_0101,
	store_rm_disp_rn_l_D_0010_M_0010_N_0101,
	store_rm_disp_rn_l_D_0011_M_0010_N_0101,
	store_rm_disp_rn_l_D_0100_M_0010_N_0101,
	store_rm_disp_rn_l_D_0101_M_0010_N_0101,
	store_rm_disp_rn_l_D_0110_M_0010_N_0101,
	store_rm_disp_rn_l_D_0111_M_0010_N_0101,
	store_rm_disp_rn_l_D_1000_M_0010_N_0101,
	store_rm_disp_rn_l_D_1001_M_0010_N_0101,
	store_rm_disp_rn_l_D_1010_M_0010_N_0101,
	store_rm_disp_rn_l_D_1011_M_0010_N_0101,
	store_rm_disp_rn_l_D_1100_M_0010_N_0101,
	store_rm_disp_rn_l_D_1101_M_0010_N_0101,
	store_rm_disp_rn_l_D_1110_M_0010_N_0101,
	store_rm_disp_rn_l_D_1111_M_0010_N_0101,
	store_rm_disp_rn_l_D_0000_M_0011_N_0101,
	store_rm_disp_rn_l_D_0001_M_0011_N_0101,
	store_rm_disp_rn_l_D_0010_M_0011_N_0101,
	store_rm_disp_rn_l_D_0011_M_0011_N_0101,
	store_rm_disp_rn_l_D_0100_M_0011_N_0101,
	store_rm_disp_rn_l_D_0101_M_0011_N_0101,
	store_rm_disp_rn_l_D_0110_M_0011_N_0101,
	store_rm_disp_rn_l_D_0111_M_0011_N_0101,
	store_rm_disp_rn_l_D_1000_M_0011_N_0101,
	store_rm_disp_rn_l_D_1001_M_0011_N_0101,
	store_rm_disp_rn_l_D_1010_M_0011_N_0101,
	store_rm_disp_rn_l_D_1011_M_0011_N_0101,
	store_rm_disp_rn_l_D_1100_M_0011_N_0101,
	store_rm_disp_rn_l_D_1101_M_0011_N_0101,
	store_rm_disp_rn_l_D_1110_M_0011_N_0101,
	store_rm_disp_rn_l_D_1111_M_0011_N_0101,
	store_rm_disp_rn_l_D_0000_M_0100_N_0101,
	store_rm_disp_rn_l_D_0001_M_0100_N_0101,
	store_rm_disp_rn_l_D_0010_M_0100_N_0101,
	store_rm_disp_rn_l_D_0011_M_0100_N_0101,
	store_rm_disp_rn_l_D_0100_M_0100_N_0101,
	store_rm_disp_rn_l_D_0101_M_0100_N_0101,
	store_rm_disp_rn_l_D_0110_M_0100_N_0101,
	store_rm_disp_rn_l_D_0111_M_0100_N_0101,
	store_rm_disp_rn_l_D_1000_M_0100_N_0101,
	store_rm_disp_rn_l_D_1001_M_0100_N_0101,
	store_rm_disp_rn_l_D_1010_M_0100_N_0101,
	store_rm_disp_rn_l_D_1011_M_0100_N_0101,
	store_rm_disp_rn_l_D_1100_M_0100_N_0101,
	store_rm_disp_rn_l_D_1101_M_0100_N_0101,
	store_rm_disp_rn_l_D_1110_M_0100_N_0101,
	store_rm_disp_rn_l_D_1111_M_0100_N_0101,
	store_rm_disp_rn_l_D_0000_M_0101_N_0101,
	store_rm_disp_rn_l_D_0001_M_0101_N_0101,
	store_rm_disp_rn_l_D_0010_M_0101_N_0101,
	store_rm_disp_rn_l_D_0011_M_0101_N_0101,
	store_rm_disp_rn_l_D_0100_M_0101_N_0101,
	store_rm_disp_rn_l_D_0101_M_0101_N_0101,
	store_rm_disp_rn_l_D_0110_M_0101_N_0101,
	store_rm_disp_rn_l_D_0111_M_0101_N_0101,
	store_rm_disp_rn_l_D_1000_M_0101_N_0101,
	store_rm_disp_rn_l_D_1001_M_0101_N_0101,
	store_rm_disp_rn_l_D_1010_M_0101_N_0101,
	store_rm_disp_rn_l_D_1011_M_0101_N_0101,
	store_rm_disp_rn_l_D_1100_M_0101_N_0101,
	store_rm_disp_rn_l_D_1101_M_0101_N_0101,
	store_rm_disp_rn_l_D_1110_M_0101_N_0101,
	store_rm_disp_rn_l_D_1111_M_0101_N_0101,
	store_rm_disp_rn_l_D_0000_M_0110_N_0101,
	store_rm_disp_rn_l_D_0001_M_0110_N_0101,
	store_rm_disp_rn_l_D_0010_M_0110_N_0101,
	store_rm_disp_rn_l_D_0011_M_0110_N_0101,
	store_rm_disp_rn_l_D_0100_M_0110_N_0101,
	store_rm_disp_rn_l_D_0101_M_0110_N_0101,
	store_rm_disp_rn_l_D_0110_M_0110_N_0101,
	store_rm_disp_rn_l_D_0111_M_0110_N_0101,
	store_rm_disp_rn_l_D_1000_M_0110_N_0101,
	store_rm_disp_rn_l_D_1001_M_0110_N_0101,
	store_rm_disp_rn_l_D_1010_M_0110_N_0101,
	store_rm_disp_rn_l_D_1011_M_0110_N_0101,
	store_rm_disp_rn_l_D_1100_M_0110_N_0101,
	store_rm_disp_rn_l_D_1101_M_0110_N_0101,
	store_rm_disp_rn_l_D_1110_M_0110_N_0101,
	store_rm_disp_rn_l_D_1111_M_0110_N_0101,
	store_rm_disp_rn_l_D_0000_M_0111_N_0101,
	store_rm_disp_rn_l_D_0001_M_0111_N_0101,
	store_rm_disp_rn_l_D_0010_M_0111_N_0101,
	store_rm_disp_rn_l_D_0011_M_0111_N_0101,
	store_rm_disp_rn_l_D_0100_M_0111_N_0101,
	store_rm_disp_rn_l_D_0101_M_0111_N_0101,
	store_rm_disp_rn_l_D_0110_M_0111_N_0101,
	store_rm_disp_rn_l_D_0111_M_0111_N_0101,
	store_rm_disp_rn_l_D_1000_M_0111_N_0101,
	store_rm_disp_rn_l_D_1001_M_0111_N_0101,
	store_rm_disp_rn_l_D_1010_M_0111_N_0101,
	store_rm_disp_rn_l_D_1011_M_0111_N_0101,
	store_rm_disp_rn_l_D_1100_M_0111_N_0101,
	store_rm_disp_rn_l_D_1101_M_0111_N_0101,
	store_rm_disp_rn_l_D_1110_M_0111_N_0101,
	store_rm_disp_rn_l_D_1111_M_0111_N_0101,
	store_rm_disp_rn_l_D_0000_M_1000_N_0101,
	store_rm_disp_rn_l_D_0001_M_1000_N_0101,
	store_rm_disp_rn_l_D_0010_M_1000_N_0101,
	store_rm_disp_rn_l_D_0011_M_1000_N_0101,
	store_rm_disp_rn_l_D_0100_M_1000_N_0101,
	store_rm_disp_rn_l_D_0101_M_1000_N_0101,
	store_rm_disp_rn_l_D_0110_M_1000_N_0101,
	store_rm_disp_rn_l_D_0111_M_1000_N_0101,
	store_rm_disp_rn_l_D_1000_M_1000_N_0101,
	store_rm_disp_rn_l_D_1001_M_1000_N_0101,
	store_rm_disp_rn_l_D_1010_M_1000_N_0101,
	store_rm_disp_rn_l_D_1011_M_1000_N_0101,
	store_rm_disp_rn_l_D_1100_M_1000_N_0101,
	store_rm_disp_rn_l_D_1101_M_1000_N_0101,
	store_rm_disp_rn_l_D_1110_M_1000_N_0101,
	store_rm_disp_rn_l_D_1111_M_1000_N_0101,
	store_rm_disp_rn_l_D_0000_M_1001_N_0101,
	store_rm_disp_rn_l_D_0001_M_1001_N_0101,
	store_rm_disp_rn_l_D_0010_M_1001_N_0101,
	store_rm_disp_rn_l_D_0011_M_1001_N_0101,
	store_rm_disp_rn_l_D_0100_M_1001_N_0101,
	store_rm_disp_rn_l_D_0101_M_1001_N_0101,
	store_rm_disp_rn_l_D_0110_M_1001_N_0101,
	store_rm_disp_rn_l_D_0111_M_1001_N_0101,
	store_rm_disp_rn_l_D_1000_M_1001_N_0101,
	store_rm_disp_rn_l_D_1001_M_1001_N_0101,
	store_rm_disp_rn_l_D_1010_M_1001_N_0101,
	store_rm_disp_rn_l_D_1011_M_1001_N_0101,
	store_rm_disp_rn_l_D_1100_M_1001_N_0101,
	store_rm_disp_rn_l_D_1101_M_1001_N_0101,
	store_rm_disp_rn_l_D_1110_M_1001_N_0101,
	store_rm_disp_rn_l_D_1111_M_1001_N_0101,
	store_rm_disp_rn_l_D_0000_M_1010_N_0101,
	store_rm_disp_rn_l_D_0001_M_1010_N_0101,
	store_rm_disp_rn_l_D_0010_M_1010_N_0101,
	store_rm_disp_rn_l_D_0011_M_1010_N_0101,
	store_rm_disp_rn_l_D_0100_M_1010_N_0101,
	store_rm_disp_rn_l_D_0101_M_1010_N_0101,
	store_rm_disp_rn_l_D_0110_M_1010_N_0101,
	store_rm_disp_rn_l_D_0111_M_1010_N_0101,
	store_rm_disp_rn_l_D_1000_M_1010_N_0101,
	store_rm_disp_rn_l_D_1001_M_1010_N_0101,
	store_rm_disp_rn_l_D_1010_M_1010_N_0101,
	store_rm_disp_rn_l_D_1011_M_1010_N_0101,
	store_rm_disp_rn_l_D_1100_M_1010_N_0101,
	store_rm_disp_rn_l_D_1101_M_1010_N_0101,
	store_rm_disp_rn_l_D_1110_M_1010_N_0101,
	store_rm_disp_rn_l_D_1111_M_1010_N_0101,
	store_rm_disp_rn_l_D_0000_M_1011_N_0101,
	store_rm_disp_rn_l_D_0001_M_1011_N_0101,
	store_rm_disp_rn_l_D_0010_M_1011_N_0101,
	store_rm_disp_rn_l_D_0011_M_1011_N_0101,
	store_rm_disp_rn_l_D_0100_M_1011_N_0101,
	store_rm_disp_rn_l_D_0101_M_1011_N_0101,
	store_rm_disp_rn_l_D_0110_M_1011_N_0101,
	store_rm_disp_rn_l_D_0111_M_1011_N_0101,
	store_rm_disp_rn_l_D_1000_M_1011_N_0101,
	store_rm_disp_rn_l_D_1001_M_1011_N_0101,
	store_rm_disp_rn_l_D_1010_M_1011_N_0101,
	store_rm_disp_rn_l_D_1011_M_1011_N_0101,
	store_rm_disp_rn_l_D_1100_M_1011_N_0101,
	store_rm_disp_rn_l_D_1101_M_1011_N_0101,
	store_rm_disp_rn_l_D_1110_M_1011_N_0101,
	store_rm_disp_rn_l_D_1111_M_1011_N_0101,
	store_rm_disp_rn_l_D_0000_M_1100_N_0101,
	store_rm_disp_rn_l_D_0001_M_1100_N_0101,
	store_rm_disp_rn_l_D_0010_M_1100_N_0101,
	store_rm_disp_rn_l_D_0011_M_1100_N_0101,
	store_rm_disp_rn_l_D_0100_M_1100_N_0101,
	store_rm_disp_rn_l_D_0101_M_1100_N_0101,
	store_rm_disp_rn_l_D_0110_M_1100_N_0101,
	store_rm_disp_rn_l_D_0111_M_1100_N_0101,
	store_rm_disp_rn_l_D_1000_M_1100_N_0101,
	store_rm_disp_rn_l_D_1001_M_1100_N_0101,
	store_rm_disp_rn_l_D_1010_M_1100_N_0101,
	store_rm_disp_rn_l_D_1011_M_1100_N_0101,
	store_rm_disp_rn_l_D_1100_M_1100_N_0101,
	store_rm_disp_rn_l_D_1101_M_1100_N_0101,
	store_rm_disp_rn_l_D_1110_M_1100_N_0101,
	store_rm_disp_rn_l_D_1111_M_1100_N_0101,
	store_rm_disp_rn_l_D_0000_M_1101_N_0101,
	store_rm_disp_rn_l_D_0001_M_1101_N_0101,
	store_rm_disp_rn_l_D_0010_M_1101_N_0101,
	store_rm_disp_rn_l_D_0011_M_1101_N_0101,
	store_rm_disp_rn_l_D_0100_M_1101_N_0101,
	store_rm_disp_rn_l_D_0101_M_1101_N_0101,
	store_rm_disp_rn_l_D_0110_M_1101_N_0101,
	store_rm_disp_rn_l_D_0111_M_1101_N_0101,
	store_rm_disp_rn_l_D_1000_M_1101_N_0101,
	store_rm_disp_rn_l_D_1001_M_1101_N_0101,
	store_rm_disp_rn_l_D_1010_M_1101_N_0101,
	store_rm_disp_rn_l_D_1011_M_1101_N_0101,
	store_rm_disp_rn_l_D_1100_M_1101_N_0101,
	store_rm_disp_rn_l_D_1101_M_1101_N_0101,
	store_rm_disp_rn_l_D_1110_M_1101_N_0101,
	store_rm_disp_rn_l_D_1111_M_1101_N_0101,
	store_rm_disp_rn_l_D_0000_M_1110_N_0101,
	store_rm_disp_rn_l_D_0001_M_1110_N_0101,
	store_rm_disp_rn_l_D_0010_M_1110_N_0101,
	store_rm_disp_rn_l_D_0011_M_1110_N_0101,
	store_rm_disp_rn_l_D_0100_M_1110_N_0101,
	store_rm_disp_rn_l_D_0101_M_1110_N_0101,
	store_rm_disp_rn_l_D_0110_M_1110_N_0101,
	store_rm_disp_rn_l_D_0111_M_1110_N_0101,
	store_rm_disp_rn_l_D_1000_M_1110_N_0101,
	store_rm_disp_rn_l_D_1001_M_1110_N_0101,
	store_rm_disp_rn_l_D_1010_M_1110_N_0101,
	store_rm_disp_rn_l_D_1011_M_1110_N_0101,
	store_rm_disp_rn_l_D_1100_M_1110_N_0101,
	store_rm_disp_rn_l_D_1101_M_1110_N_0101,
	store_rm_disp_rn_l_D_1110_M_1110_N_0101,
	store_rm_disp_rn_l_D_1111_M_1110_N_0101,
	store_rm_disp_rn_l_D_0000_M_1111_N_0101,
	store_rm_disp_rn_l_D_0001_M_1111_N_0101,
	store_rm_disp_rn_l_D_0010_M_1111_N_0101,
	store_rm_disp_rn_l_D_0011_M_1111_N_0101,
	store_rm_disp_rn_l_D_0100_M_1111_N_0101,
	store_rm_disp_rn_l_D_0101_M_1111_N_0101,
	store_rm_disp_rn_l_D_0110_M_1111_N_0101,
	store_rm_disp_rn_l_D_0111_M_1111_N_0101,
	store_rm_disp_rn_l_D_1000_M_1111_N_0101,
	store_rm_disp_rn_l_D_1001_M_1111_N_0101,
	store_rm_disp_rn_l_D_1010_M_1111_N_0101,
	store_rm_disp_rn_l_D_1011_M_1111_N_0101,
	store_rm_disp_rn_l_D_1100_M_1111_N_0101,
	store_rm_disp_rn_l_D_1101_M_1111_N_0101,
	store_rm_disp_rn_l_D_1110_M_1111_N_0101,
	store_rm_disp_rn_l_D_1111_M_1111_N_0101,
	store_rm_disp_rn_l_D_0000_M_0000_N_0110,
	store_rm_disp_rn_l_D_0001_M_0000_N_0110,
	store_rm_disp_rn_l_D_0010_M_0000_N_0110,
	store_rm_disp_rn_l_D_0011_M_0000_N_0110,
	store_rm_disp_rn_l_D_0100_M_0000_N_0110,
	store_rm_disp_rn_l_D_0101_M_0000_N_0110,
	store_rm_disp_rn_l_D_0110_M_0000_N_0110,
	store_rm_disp_rn_l_D_0111_M_0000_N_0110,
	store_rm_disp_rn_l_D_1000_M_0000_N_0110,
	store_rm_disp_rn_l_D_1001_M_0000_N_0110,
	store_rm_disp_rn_l_D_1010_M_0000_N_0110,
	store_rm_disp_rn_l_D_1011_M_0000_N_0110,
	store_rm_disp_rn_l_D_1100_M_0000_N_0110,
	store_rm_disp_rn_l_D_1101_M_0000_N_0110,
	store_rm_disp_rn_l_D_1110_M_0000_N_0110,
	store_rm_disp_rn_l_D_1111_M_0000_N_0110,
	store_rm_disp_rn_l_D_0000_M_0001_N_0110,
	store_rm_disp_rn_l_D_0001_M_0001_N_0110,
	store_rm_disp_rn_l_D_0010_M_0001_N_0110,
	store_rm_disp_rn_l_D_0011_M_0001_N_0110,
	store_rm_disp_rn_l_D_0100_M_0001_N_0110,
	store_rm_disp_rn_l_D_0101_M_0001_N_0110,
	store_rm_disp_rn_l_D_0110_M_0001_N_0110,
	store_rm_disp_rn_l_D_0111_M_0001_N_0110,
	store_rm_disp_rn_l_D_1000_M_0001_N_0110,
	store_rm_disp_rn_l_D_1001_M_0001_N_0110,
	store_rm_disp_rn_l_D_1010_M_0001_N_0110,
	store_rm_disp_rn_l_D_1011_M_0001_N_0110,
	store_rm_disp_rn_l_D_1100_M_0001_N_0110,
	store_rm_disp_rn_l_D_1101_M_0001_N_0110,
	store_rm_disp_rn_l_D_1110_M_0001_N_0110,
	store_rm_disp_rn_l_D_1111_M_0001_N_0110,
	store_rm_disp_rn_l_D_0000_M_0010_N_0110,
	store_rm_disp_rn_l_D_0001_M_0010_N_0110,
	store_rm_disp_rn_l_D_0010_M_0010_N_0110,
	store_rm_disp_rn_l_D_0011_M_0010_N_0110,
	store_rm_disp_rn_l_D_0100_M_0010_N_0110,
	store_rm_disp_rn_l_D_0101_M_0010_N_0110,
	store_rm_disp_rn_l_D_0110_M_0010_N_0110,
	store_rm_disp_rn_l_D_0111_M_0010_N_0110,
	store_rm_disp_rn_l_D_1000_M_0010_N_0110,
	store_rm_disp_rn_l_D_1001_M_0010_N_0110,
	store_rm_disp_rn_l_D_1010_M_0010_N_0110,
	store_rm_disp_rn_l_D_1011_M_0010_N_0110,
	store_rm_disp_rn_l_D_1100_M_0010_N_0110,
	store_rm_disp_rn_l_D_1101_M_0010_N_0110,
	store_rm_disp_rn_l_D_1110_M_0010_N_0110,
	store_rm_disp_rn_l_D_1111_M_0010_N_0110,
	store_rm_disp_rn_l_D_0000_M_0011_N_0110,
	store_rm_disp_rn_l_D_0001_M_0011_N_0110,
	store_rm_disp_rn_l_D_0010_M_0011_N_0110,
	store_rm_disp_rn_l_D_0011_M_0011_N_0110,
	store_rm_disp_rn_l_D_0100_M_0011_N_0110,
	store_rm_disp_rn_l_D_0101_M_0011_N_0110,
	store_rm_disp_rn_l_D_0110_M_0011_N_0110,
	store_rm_disp_rn_l_D_0111_M_0011_N_0110,
	store_rm_disp_rn_l_D_1000_M_0011_N_0110,
	store_rm_disp_rn_l_D_1001_M_0011_N_0110,
	store_rm_disp_rn_l_D_1010_M_0011_N_0110,
	store_rm_disp_rn_l_D_1011_M_0011_N_0110,
	store_rm_disp_rn_l_D_1100_M_0011_N_0110,
	store_rm_disp_rn_l_D_1101_M_0011_N_0110,
	store_rm_disp_rn_l_D_1110_M_0011_N_0110,
	store_rm_disp_rn_l_D_1111_M_0011_N_0110,
	store_rm_disp_rn_l_D_0000_M_0100_N_0110,
	store_rm_disp_rn_l_D_0001_M_0100_N_0110,
	store_rm_disp_rn_l_D_0010_M_0100_N_0110,
	store_rm_disp_rn_l_D_0011_M_0100_N_0110,
	store_rm_disp_rn_l_D_0100_M_0100_N_0110,
	store_rm_disp_rn_l_D_0101_M_0100_N_0110,
	store_rm_disp_rn_l_D_0110_M_0100_N_0110,
	store_rm_disp_rn_l_D_0111_M_0100_N_0110,
	store_rm_disp_rn_l_D_1000_M_0100_N_0110,
	store_rm_disp_rn_l_D_1001_M_0100_N_0110,
	store_rm_disp_rn_l_D_1010_M_0100_N_0110,
	store_rm_disp_rn_l_D_1011_M_0100_N_0110,
	store_rm_disp_rn_l_D_1100_M_0100_N_0110,
	store_rm_disp_rn_l_D_1101_M_0100_N_0110,
	store_rm_disp_rn_l_D_1110_M_0100_N_0110,
	store_rm_disp_rn_l_D_1111_M_0100_N_0110,
	store_rm_disp_rn_l_D_0000_M_0101_N_0110,
	store_rm_disp_rn_l_D_0001_M_0101_N_0110,
	store_rm_disp_rn_l_D_0010_M_0101_N_0110,
	store_rm_disp_rn_l_D_0011_M_0101_N_0110,
	store_rm_disp_rn_l_D_0100_M_0101_N_0110,
	store_rm_disp_rn_l_D_0101_M_0101_N_0110,
	store_rm_disp_rn_l_D_0110_M_0101_N_0110,
	store_rm_disp_rn_l_D_0111_M_0101_N_0110,
	store_rm_disp_rn_l_D_1000_M_0101_N_0110,
	store_rm_disp_rn_l_D_1001_M_0101_N_0110,
	store_rm_disp_rn_l_D_1010_M_0101_N_0110,
	store_rm_disp_rn_l_D_1011_M_0101_N_0110,
	store_rm_disp_rn_l_D_1100_M_0101_N_0110,
	store_rm_disp_rn_l_D_1101_M_0101_N_0110,
	store_rm_disp_rn_l_D_1110_M_0101_N_0110,
	store_rm_disp_rn_l_D_1111_M_0101_N_0110,
	store_rm_disp_rn_l_D_0000_M_0110_N_0110,
	store_rm_disp_rn_l_D_0001_M_0110_N_0110,
	store_rm_disp_rn_l_D_0010_M_0110_N_0110,
	store_rm_disp_rn_l_D_0011_M_0110_N_0110,
	store_rm_disp_rn_l_D_0100_M_0110_N_0110,
	store_rm_disp_rn_l_D_0101_M_0110_N_0110,
	store_rm_disp_rn_l_D_0110_M_0110_N_0110,
	store_rm_disp_rn_l_D_0111_M_0110_N_0110,
	store_rm_disp_rn_l_D_1000_M_0110_N_0110,
	store_rm_disp_rn_l_D_1001_M_0110_N_0110,
	store_rm_disp_rn_l_D_1010_M_0110_N_0110,
	store_rm_disp_rn_l_D_1011_M_0110_N_0110,
	store_rm_disp_rn_l_D_1100_M_0110_N_0110,
	store_rm_disp_rn_l_D_1101_M_0110_N_0110,
	store_rm_disp_rn_l_D_1110_M_0110_N_0110,
	store_rm_disp_rn_l_D_1111_M_0110_N_0110,
	store_rm_disp_rn_l_D_0000_M_0111_N_0110,
	store_rm_disp_rn_l_D_0001_M_0111_N_0110,
	store_rm_disp_rn_l_D_0010_M_0111_N_0110,
	store_rm_disp_rn_l_D_0011_M_0111_N_0110,
	store_rm_disp_rn_l_D_0100_M_0111_N_0110,
	store_rm_disp_rn_l_D_0101_M_0111_N_0110,
	store_rm_disp_rn_l_D_0110_M_0111_N_0110,
	store_rm_disp_rn_l_D_0111_M_0111_N_0110,
	store_rm_disp_rn_l_D_1000_M_0111_N_0110,
	store_rm_disp_rn_l_D_1001_M_0111_N_0110,
	store_rm_disp_rn_l_D_1010_M_0111_N_0110,
	store_rm_disp_rn_l_D_1011_M_0111_N_0110,
	store_rm_disp_rn_l_D_1100_M_0111_N_0110,
	store_rm_disp_rn_l_D_1101_M_0111_N_0110,
	store_rm_disp_rn_l_D_1110_M_0111_N_0110,
	store_rm_disp_rn_l_D_1111_M_0111_N_0110,
	store_rm_disp_rn_l_D_0000_M_1000_N_0110,
	store_rm_disp_rn_l_D_0001_M_1000_N_0110,
	store_rm_disp_rn_l_D_0010_M_1000_N_0110,
	store_rm_disp_rn_l_D_0011_M_1000_N_0110,
	store_rm_disp_rn_l_D_0100_M_1000_N_0110,
	store_rm_disp_rn_l_D_0101_M_1000_N_0110,
	store_rm_disp_rn_l_D_0110_M_1000_N_0110,
	store_rm_disp_rn_l_D_0111_M_1000_N_0110,
	store_rm_disp_rn_l_D_1000_M_1000_N_0110,
	store_rm_disp_rn_l_D_1001_M_1000_N_0110,
	store_rm_disp_rn_l_D_1010_M_1000_N_0110,
	store_rm_disp_rn_l_D_1011_M_1000_N_0110,
	store_rm_disp_rn_l_D_1100_M_1000_N_0110,
	store_rm_disp_rn_l_D_1101_M_1000_N_0110,
	store_rm_disp_rn_l_D_1110_M_1000_N_0110,
	store_rm_disp_rn_l_D_1111_M_1000_N_0110,
	store_rm_disp_rn_l_D_0000_M_1001_N_0110,
	store_rm_disp_rn_l_D_0001_M_1001_N_0110,
	store_rm_disp_rn_l_D_0010_M_1001_N_0110,
	store_rm_disp_rn_l_D_0011_M_1001_N_0110,
	store_rm_disp_rn_l_D_0100_M_1001_N_0110,
	store_rm_disp_rn_l_D_0101_M_1001_N_0110,
	store_rm_disp_rn_l_D_0110_M_1001_N_0110,
	store_rm_disp_rn_l_D_0111_M_1001_N_0110,
	store_rm_disp_rn_l_D_1000_M_1001_N_0110,
	store_rm_disp_rn_l_D_1001_M_1001_N_0110,
	store_rm_disp_rn_l_D_1010_M_1001_N_0110,
	store_rm_disp_rn_l_D_1011_M_1001_N_0110,
	store_rm_disp_rn_l_D_1100_M_1001_N_0110,
	store_rm_disp_rn_l_D_1101_M_1001_N_0110,
	store_rm_disp_rn_l_D_1110_M_1001_N_0110,
	store_rm_disp_rn_l_D_1111_M_1001_N_0110,
	store_rm_disp_rn_l_D_0000_M_1010_N_0110,
	store_rm_disp_rn_l_D_0001_M_1010_N_0110,
	store_rm_disp_rn_l_D_0010_M_1010_N_0110,
	store_rm_disp_rn_l_D_0011_M_1010_N_0110,
	store_rm_disp_rn_l_D_0100_M_1010_N_0110,
	store_rm_disp_rn_l_D_0101_M_1010_N_0110,
	store_rm_disp_rn_l_D_0110_M_1010_N_0110,
	store_rm_disp_rn_l_D_0111_M_1010_N_0110,
	store_rm_disp_rn_l_D_1000_M_1010_N_0110,
	store_rm_disp_rn_l_D_1001_M_1010_N_0110,
	store_rm_disp_rn_l_D_1010_M_1010_N_0110,
	store_rm_disp_rn_l_D_1011_M_1010_N_0110,
	store_rm_disp_rn_l_D_1100_M_1010_N_0110,
	store_rm_disp_rn_l_D_1101_M_1010_N_0110,
	store_rm_disp_rn_l_D_1110_M_1010_N_0110,
	store_rm_disp_rn_l_D_1111_M_1010_N_0110,
	store_rm_disp_rn_l_D_0000_M_1011_N_0110,
	store_rm_disp_rn_l_D_0001_M_1011_N_0110,
	store_rm_disp_rn_l_D_0010_M_1011_N_0110,
	store_rm_disp_rn_l_D_0011_M_1011_N_0110,
	store_rm_disp_rn_l_D_0100_M_1011_N_0110,
	store_rm_disp_rn_l_D_0101_M_1011_N_0110,
	store_rm_disp_rn_l_D_0110_M_1011_N_0110,
	store_rm_disp_rn_l_D_0111_M_1011_N_0110,
	store_rm_disp_rn_l_D_1000_M_1011_N_0110,
	store_rm_disp_rn_l_D_1001_M_1011_N_0110,
	store_rm_disp_rn_l_D_1010_M_1011_N_0110,
	store_rm_disp_rn_l_D_1011_M_1011_N_0110,
	store_rm_disp_rn_l_D_1100_M_1011_N_0110,
	store_rm_disp_rn_l_D_1101_M_1011_N_0110,
	store_rm_disp_rn_l_D_1110_M_1011_N_0110,
	store_rm_disp_rn_l_D_1111_M_1011_N_0110,
	store_rm_disp_rn_l_D_0000_M_1100_N_0110,
	store_rm_disp_rn_l_D_0001_M_1100_N_0110,
	store_rm_disp_rn_l_D_0010_M_1100_N_0110,
	store_rm_disp_rn_l_D_0011_M_1100_N_0110,
	store_rm_disp_rn_l_D_0100_M_1100_N_0110,
	store_rm_disp_rn_l_D_0101_M_1100_N_0110,
	store_rm_disp_rn_l_D_0110_M_1100_N_0110,
	store_rm_disp_rn_l_D_0111_M_1100_N_0110,
	store_rm_disp_rn_l_D_1000_M_1100_N_0110,
	store_rm_disp_rn_l_D_1001_M_1100_N_0110,
	store_rm_disp_rn_l_D_1010_M_1100_N_0110,
	store_rm_disp_rn_l_D_1011_M_1100_N_0110,
	store_rm_disp_rn_l_D_1100_M_1100_N_0110,
	store_rm_disp_rn_l_D_1101_M_1100_N_0110,
	store_rm_disp_rn_l_D_1110_M_1100_N_0110,
	store_rm_disp_rn_l_D_1111_M_1100_N_0110,
	store_rm_disp_rn_l_D_0000_M_1101_N_0110,
	store_rm_disp_rn_l_D_0001_M_1101_N_0110,
	store_rm_disp_rn_l_D_0010_M_1101_N_0110,
	store_rm_disp_rn_l_D_0011_M_1101_N_0110,
	store_rm_disp_rn_l_D_0100_M_1101_N_0110,
	store_rm_disp_rn_l_D_0101_M_1101_N_0110,
	store_rm_disp_rn_l_D_0110_M_1101_N_0110,
	store_rm_disp_rn_l_D_0111_M_1101_N_0110,
	store_rm_disp_rn_l_D_1000_M_1101_N_0110,
	store_rm_disp_rn_l_D_1001_M_1101_N_0110,
	store_rm_disp_rn_l_D_1010_M_1101_N_0110,
	store_rm_disp_rn_l_D_1011_M_1101_N_0110,
	store_rm_disp_rn_l_D_1100_M_1101_N_0110,
	store_rm_disp_rn_l_D_1101_M_1101_N_0110,
	store_rm_disp_rn_l_D_1110_M_1101_N_0110,
	store_rm_disp_rn_l_D_1111_M_1101_N_0110,
	store_rm_disp_rn_l_D_0000_M_1110_N_0110,
	store_rm_disp_rn_l_D_0001_M_1110_N_0110,
	store_rm_disp_rn_l_D_0010_M_1110_N_0110,
	store_rm_disp_rn_l_D_0011_M_1110_N_0110,
	store_rm_disp_rn_l_D_0100_M_1110_N_0110,
	store_rm_disp_rn_l_D_0101_M_1110_N_0110,
	store_rm_disp_rn_l_D_0110_M_1110_N_0110,
	store_rm_disp_rn_l_D_0111_M_1110_N_0110,
	store_rm_disp_rn_l_D_1000_M_1110_N_0110,
	store_rm_disp_rn_l_D_1001_M_1110_N_0110,
	store_rm_disp_rn_l_D_1010_M_1110_N_0110,
	store_rm_disp_rn_l_D_1011_M_1110_N_0110,
	store_rm_disp_rn_l_D_1100_M_1110_N_0110,
	store_rm_disp_rn_l_D_1101_M_1110_N_0110,
	store_rm_disp_rn_l_D_1110_M_1110_N_0110,
	store_rm_disp_rn_l_D_1111_M_1110_N_0110,
	store_rm_disp_rn_l_D_0000_M_1111_N_0110,
	store_rm_disp_rn_l_D_0001_M_1111_N_0110,
	store_rm_disp_rn_l_D_0010_M_1111_N_0110,
	store_rm_disp_rn_l_D_0011_M_1111_N_0110,
	store_rm_disp_rn_l_D_0100_M_1111_N_0110,
	store_rm_disp_rn_l_D_0101_M_1111_N_0110,
	store_rm_disp_rn_l_D_0110_M_1111_N_0110,
	store_rm_disp_rn_l_D_0111_M_1111_N_0110,
	store_rm_disp_rn_l_D_1000_M_1111_N_0110,
	store_rm_disp_rn_l_D_1001_M_1111_N_0110,
	store_rm_disp_rn_l_D_1010_M_1111_N_0110,
	store_rm_disp_rn_l_D_1011_M_1111_N_0110,
	store_rm_disp_rn_l_D_1100_M_1111_N_0110,
	store_rm_disp_rn_l_D_1101_M_1111_N_0110,
	store_rm_disp_rn_l_D_1110_M_1111_N_0110,
	store_rm_disp_rn_l_D_1111_M_1111_N_0110,
	store_rm_disp_rn_l_D_0000_M_0000_N_0111,
	store_rm_disp_rn_l_D_0001_M_0000_N_0111,
	store_rm_disp_rn_l_D_0010_M_0000_N_0111,
	store_rm_disp_rn_l_D_0011_M_0000_N_0111,
	store_rm_disp_rn_l_D_0100_M_0000_N_0111,
	store_rm_disp_rn_l_D_0101_M_0000_N_0111,
	store_rm_disp_rn_l_D_0110_M_0000_N_0111,
	store_rm_disp_rn_l_D_0111_M_0000_N_0111,
	store_rm_disp_rn_l_D_1000_M_0000_N_0111,
	store_rm_disp_rn_l_D_1001_M_0000_N_0111,
	store_rm_disp_rn_l_D_1010_M_0000_N_0111,
	store_rm_disp_rn_l_D_1011_M_0000_N_0111,
	store_rm_disp_rn_l_D_1100_M_0000_N_0111,
	store_rm_disp_rn_l_D_1101_M_0000_N_0111,
	store_rm_disp_rn_l_D_1110_M_0000_N_0111,
	store_rm_disp_rn_l_D_1111_M_0000_N_0111,
	store_rm_disp_rn_l_D_0000_M_0001_N_0111,
	store_rm_disp_rn_l_D_0001_M_0001_N_0111,
	store_rm_disp_rn_l_D_0010_M_0001_N_0111,
	store_rm_disp_rn_l_D_0011_M_0001_N_0111,
	store_rm_disp_rn_l_D_0100_M_0001_N_0111,
	store_rm_disp_rn_l_D_0101_M_0001_N_0111,
	store_rm_disp_rn_l_D_0110_M_0001_N_0111,
	store_rm_disp_rn_l_D_0111_M_0001_N_0111,
	store_rm_disp_rn_l_D_1000_M_0001_N_0111,
	store_rm_disp_rn_l_D_1001_M_0001_N_0111,
	store_rm_disp_rn_l_D_1010_M_0001_N_0111,
	store_rm_disp_rn_l_D_1011_M_0001_N_0111,
	store_rm_disp_rn_l_D_1100_M_0001_N_0111,
	store_rm_disp_rn_l_D_1101_M_0001_N_0111,
	store_rm_disp_rn_l_D_1110_M_0001_N_0111,
	store_rm_disp_rn_l_D_1111_M_0001_N_0111,
	store_rm_disp_rn_l_D_0000_M_0010_N_0111,
	store_rm_disp_rn_l_D_0001_M_0010_N_0111,
	store_rm_disp_rn_l_D_0010_M_0010_N_0111,
	store_rm_disp_rn_l_D_0011_M_0010_N_0111,
	store_rm_disp_rn_l_D_0100_M_0010_N_0111,
	store_rm_disp_rn_l_D_0101_M_0010_N_0111,
	store_rm_disp_rn_l_D_0110_M_0010_N_0111,
	store_rm_disp_rn_l_D_0111_M_0010_N_0111,
	store_rm_disp_rn_l_D_1000_M_0010_N_0111,
	store_rm_disp_rn_l_D_1001_M_0010_N_0111,
	store_rm_disp_rn_l_D_1010_M_0010_N_0111,
	store_rm_disp_rn_l_D_1011_M_0010_N_0111,
	store_rm_disp_rn_l_D_1100_M_0010_N_0111,
	store_rm_disp_rn_l_D_1101_M_0010_N_0111,
	store_rm_disp_rn_l_D_1110_M_0010_N_0111,
	store_rm_disp_rn_l_D_1111_M_0010_N_0111,
	store_rm_disp_rn_l_D_0000_M_0011_N_0111,
	store_rm_disp_rn_l_D_0001_M_0011_N_0111,
	store_rm_disp_rn_l_D_0010_M_0011_N_0111,
	store_rm_disp_rn_l_D_0011_M_0011_N_0111,
	store_rm_disp_rn_l_D_0100_M_0011_N_0111,
	store_rm_disp_rn_l_D_0101_M_0011_N_0111,
	store_rm_disp_rn_l_D_0110_M_0011_N_0111,
	store_rm_disp_rn_l_D_0111_M_0011_N_0111,
	store_rm_disp_rn_l_D_1000_M_0011_N_0111,
	store_rm_disp_rn_l_D_1001_M_0011_N_0111,
	store_rm_disp_rn_l_D_1010_M_0011_N_0111,
	store_rm_disp_rn_l_D_1011_M_0011_N_0111,
	store_rm_disp_rn_l_D_1100_M_0011_N_0111,
	store_rm_disp_rn_l_D_1101_M_0011_N_0111,
	store_rm_disp_rn_l_D_1110_M_0011_N_0111,
	store_rm_disp_rn_l_D_1111_M_0011_N_0111,
	store_rm_disp_rn_l_D_0000_M_0100_N_0111,
	store_rm_disp_rn_l_D_0001_M_0100_N_0111,
	store_rm_disp_rn_l_D_0010_M_0100_N_0111,
	store_rm_disp_rn_l_D_0011_M_0100_N_0111,
	store_rm_disp_rn_l_D_0100_M_0100_N_0111,
	store_rm_disp_rn_l_D_0101_M_0100_N_0111,
	store_rm_disp_rn_l_D_0110_M_0100_N_0111,
	store_rm_disp_rn_l_D_0111_M_0100_N_0111,
	store_rm_disp_rn_l_D_1000_M_0100_N_0111,
	store_rm_disp_rn_l_D_1001_M_0100_N_0111,
	store_rm_disp_rn_l_D_1010_M_0100_N_0111,
	store_rm_disp_rn_l_D_1011_M_0100_N_0111,
	store_rm_disp_rn_l_D_1100_M_0100_N_0111,
	store_rm_disp_rn_l_D_1101_M_0100_N_0111,
	store_rm_disp_rn_l_D_1110_M_0100_N_0111,
	store_rm_disp_rn_l_D_1111_M_0100_N_0111,
	store_rm_disp_rn_l_D_0000_M_0101_N_0111,
	store_rm_disp_rn_l_D_0001_M_0101_N_0111,
	store_rm_disp_rn_l_D_0010_M_0101_N_0111,
	store_rm_disp_rn_l_D_0011_M_0101_N_0111,
	store_rm_disp_rn_l_D_0100_M_0101_N_0111,
	store_rm_disp_rn_l_D_0101_M_0101_N_0111,
	store_rm_disp_rn_l_D_0110_M_0101_N_0111,
	store_rm_disp_rn_l_D_0111_M_0101_N_0111,
	store_rm_disp_rn_l_D_1000_M_0101_N_0111,
	store_rm_disp_rn_l_D_1001_M_0101_N_0111,
	store_rm_disp_rn_l_D_1010_M_0101_N_0111,
	store_rm_disp_rn_l_D_1011_M_0101_N_0111,
	store_rm_disp_rn_l_D_1100_M_0101_N_0111,
	store_rm_disp_rn_l_D_1101_M_0101_N_0111,
	store_rm_disp_rn_l_D_1110_M_0101_N_0111,
	store_rm_disp_rn_l_D_1111_M_0101_N_0111,
	store_rm_disp_rn_l_D_0000_M_0110_N_0111,
	store_rm_disp_rn_l_D_0001_M_0110_N_0111,
	store_rm_disp_rn_l_D_0010_M_0110_N_0111,
	store_rm_disp_rn_l_D_0011_M_0110_N_0111,
	store_rm_disp_rn_l_D_0100_M_0110_N_0111,
	store_rm_disp_rn_l_D_0101_M_0110_N_0111,
	store_rm_disp_rn_l_D_0110_M_0110_N_0111,
	store_rm_disp_rn_l_D_0111_M_0110_N_0111,
	store_rm_disp_rn_l_D_1000_M_0110_N_0111,
	store_rm_disp_rn_l_D_1001_M_0110_N_0111,
	store_rm_disp_rn_l_D_1010_M_0110_N_0111,
	store_rm_disp_rn_l_D_1011_M_0110_N_0111,
	store_rm_disp_rn_l_D_1100_M_0110_N_0111,
	store_rm_disp_rn_l_D_1101_M_0110_N_0111,
	store_rm_disp_rn_l_D_1110_M_0110_N_0111,
	store_rm_disp_rn_l_D_1111_M_0110_N_0111,
	store_rm_disp_rn_l_D_0000_M_0111_N_0111,
	store_rm_disp_rn_l_D_0001_M_0111_N_0111,
	store_rm_disp_rn_l_D_0010_M_0111_N_0111,
	store_rm_disp_rn_l_D_0011_M_0111_N_0111,
	store_rm_disp_rn_l_D_0100_M_0111_N_0111,
	store_rm_disp_rn_l_D_0101_M_0111_N_0111,
	store_rm_disp_rn_l_D_0110_M_0111_N_0111,
	store_rm_disp_rn_l_D_0111_M_0111_N_0111,
	store_rm_disp_rn_l_D_1000_M_0111_N_0111,
	store_rm_disp_rn_l_D_1001_M_0111_N_0111,
	store_rm_disp_rn_l_D_1010_M_0111_N_0111,
	store_rm_disp_rn_l_D_1011_M_0111_N_0111,
	store_rm_disp_rn_l_D_1100_M_0111_N_0111,
	store_rm_disp_rn_l_D_1101_M_0111_N_0111,
	store_rm_disp_rn_l_D_1110_M_0111_N_0111,
	store_rm_disp_rn_l_D_1111_M_0111_N_0111,
	store_rm_disp_rn_l_D_0000_M_1000_N_0111,
	store_rm_disp_rn_l_D_0001_M_1000_N_0111,
	store_rm_disp_rn_l_D_0010_M_1000_N_0111,
	store_rm_disp_rn_l_D_0011_M_1000_N_0111,
	store_rm_disp_rn_l_D_0100_M_1000_N_0111,
	store_rm_disp_rn_l_D_0101_M_1000_N_0111,
	store_rm_disp_rn_l_D_0110_M_1000_N_0111,
	store_rm_disp_rn_l_D_0111_M_1000_N_0111,
	store_rm_disp_rn_l_D_1000_M_1000_N_0111,
	store_rm_disp_rn_l_D_1001_M_1000_N_0111,
	store_rm_disp_rn_l_D_1010_M_1000_N_0111,
	store_rm_disp_rn_l_D_1011_M_1000_N_0111,
	store_rm_disp_rn_l_D_1100_M_1000_N_0111,
	store_rm_disp_rn_l_D_1101_M_1000_N_0111,
	store_rm_disp_rn_l_D_1110_M_1000_N_0111,
	store_rm_disp_rn_l_D_1111_M_1000_N_0111,
	store_rm_disp_rn_l_D_0000_M_1001_N_0111,
	store_rm_disp_rn_l_D_0001_M_1001_N_0111,
	store_rm_disp_rn_l_D_0010_M_1001_N_0111,
	store_rm_disp_rn_l_D_0011_M_1001_N_0111,
	store_rm_disp_rn_l_D_0100_M_1001_N_0111,
	store_rm_disp_rn_l_D_0101_M_1001_N_0111,
	store_rm_disp_rn_l_D_0110_M_1001_N_0111,
	store_rm_disp_rn_l_D_0111_M_1001_N_0111,
	store_rm_disp_rn_l_D_1000_M_1001_N_0111,
	store_rm_disp_rn_l_D_1001_M_1001_N_0111,
	store_rm_disp_rn_l_D_1010_M_1001_N_0111,
	store_rm_disp_rn_l_D_1011_M_1001_N_0111,
	store_rm_disp_rn_l_D_1100_M_1001_N_0111,
	store_rm_disp_rn_l_D_1101_M_1001_N_0111,
	store_rm_disp_rn_l_D_1110_M_1001_N_0111,
	store_rm_disp_rn_l_D_1111_M_1001_N_0111,
	store_rm_disp_rn_l_D_0000_M_1010_N_0111,
	store_rm_disp_rn_l_D_0001_M_1010_N_0111,
	store_rm_disp_rn_l_D_0010_M_1010_N_0111,
	store_rm_disp_rn_l_D_0011_M_1010_N_0111,
	store_rm_disp_rn_l_D_0100_M_1010_N_0111,
	store_rm_disp_rn_l_D_0101_M_1010_N_0111,
	store_rm_disp_rn_l_D_0110_M_1010_N_0111,
	store_rm_disp_rn_l_D_0111_M_1010_N_0111,
	store_rm_disp_rn_l_D_1000_M_1010_N_0111,
	store_rm_disp_rn_l_D_1001_M_1010_N_0111,
	store_rm_disp_rn_l_D_1010_M_1010_N_0111,
	store_rm_disp_rn_l_D_1011_M_1010_N_0111,
	store_rm_disp_rn_l_D_1100_M_1010_N_0111,
	store_rm_disp_rn_l_D_1101_M_1010_N_0111,
	store_rm_disp_rn_l_D_1110_M_1010_N_0111,
	store_rm_disp_rn_l_D_1111_M_1010_N_0111,
	store_rm_disp_rn_l_D_0000_M_1011_N_0111,
	store_rm_disp_rn_l_D_0001_M_1011_N_0111,
	store_rm_disp_rn_l_D_0010_M_1011_N_0111,
	store_rm_disp_rn_l_D_0011_M_1011_N_0111,
	store_rm_disp_rn_l_D_0100_M_1011_N_0111,
	store_rm_disp_rn_l_D_0101_M_1011_N_0111,
	store_rm_disp_rn_l_D_0110_M_1011_N_0111,
	store_rm_disp_rn_l_D_0111_M_1011_N_0111,
	store_rm_disp_rn_l_D_1000_M_1011_N_0111,
	store_rm_disp_rn_l_D_1001_M_1011_N_0111,
	store_rm_disp_rn_l_D_1010_M_1011_N_0111,
	store_rm_disp_rn_l_D_1011_M_1011_N_0111,
	store_rm_disp_rn_l_D_1100_M_1011_N_0111,
	store_rm_disp_rn_l_D_1101_M_1011_N_0111,
	store_rm_disp_rn_l_D_1110_M_1011_N_0111,
	store_rm_disp_rn_l_D_1111_M_1011_N_0111,
	store_rm_disp_rn_l_D_0000_M_1100_N_0111,
	store_rm_disp_rn_l_D_0001_M_1100_N_0111,
	store_rm_disp_rn_l_D_0010_M_1100_N_0111,
	store_rm_disp_rn_l_D_0011_M_1100_N_0111,
	store_rm_disp_rn_l_D_0100_M_1100_N_0111,
	store_rm_disp_rn_l_D_0101_M_1100_N_0111,
	store_rm_disp_rn_l_D_0110_M_1100_N_0111,
	store_rm_disp_rn_l_D_0111_M_1100_N_0111,
	store_rm_disp_rn_l_D_1000_M_1100_N_0111,
	store_rm_disp_rn_l_D_1001_M_1100_N_0111,
	store_rm_disp_rn_l_D_1010_M_1100_N_0111,
	store_rm_disp_rn_l_D_1011_M_1100_N_0111,
	store_rm_disp_rn_l_D_1100_M_1100_N_0111,
	store_rm_disp_rn_l_D_1101_M_1100_N_0111,
	store_rm_disp_rn_l_D_1110_M_1100_N_0111,
	store_rm_disp_rn_l_D_1111_M_1100_N_0111,
	store_rm_disp_rn_l_D_0000_M_1101_N_0111,
	store_rm_disp_rn_l_D_0001_M_1101_N_0111,
	store_rm_disp_rn_l_D_0010_M_1101_N_0111,
	store_rm_disp_rn_l_D_0011_M_1101_N_0111,
	store_rm_disp_rn_l_D_0100_M_1101_N_0111,
	store_rm_disp_rn_l_D_0101_M_1101_N_0111,
	store_rm_disp_rn_l_D_0110_M_1101_N_0111,
	store_rm_disp_rn_l_D_0111_M_1101_N_0111,
	store_rm_disp_rn_l_D_1000_M_1101_N_0111,
	store_rm_disp_rn_l_D_1001_M_1101_N_0111,
	store_rm_disp_rn_l_D_1010_M_1101_N_0111,
	store_rm_disp_rn_l_D_1011_M_1101_N_0111,
	store_rm_disp_rn_l_D_1100_M_1101_N_0111,
	store_rm_disp_rn_l_D_1101_M_1101_N_0111,
	store_rm_disp_rn_l_D_1110_M_1101_N_0111,
	store_rm_disp_rn_l_D_1111_M_1101_N_0111,
	store_rm_disp_rn_l_D_0000_M_1110_N_0111,
	store_rm_disp_rn_l_D_0001_M_1110_N_0111,
	store_rm_disp_rn_l_D_0010_M_1110_N_0111,
	store_rm_disp_rn_l_D_0011_M_1110_N_0111,
	store_rm_disp_rn_l_D_0100_M_1110_N_0111,
	store_rm_disp_rn_l_D_0101_M_1110_N_0111,
	store_rm_disp_rn_l_D_0110_M_1110_N_0111,
	store_rm_disp_rn_l_D_0111_M_1110_N_0111,
	store_rm_disp_rn_l_D_1000_M_1110_N_0111,
	store_rm_disp_rn_l_D_1001_M_1110_N_0111,
	store_rm_disp_rn_l_D_1010_M_1110_N_0111,
	store_rm_disp_rn_l_D_1011_M_1110_N_0111,
	store_rm_disp_rn_l_D_1100_M_1110_N_0111,
	store_rm_disp_rn_l_D_1101_M_1110_N_0111,
	store_rm_disp_rn_l_D_1110_M_1110_N_0111,
	store_rm_disp_rn_l_D_1111_M_1110_N_0111,
	store_rm_disp_rn_l_D_0000_M_1111_N_0111,
	store_rm_disp_rn_l_D_0001_M_1111_N_0111,
	store_rm_disp_rn_l_D_0010_M_1111_N_0111,
	store_rm_disp_rn_l_D_0011_M_1111_N_0111,
	store_rm_disp_rn_l_D_0100_M_1111_N_0111,
	store_rm_disp_rn_l_D_0101_M_1111_N_0111,
	store_rm_disp_rn_l_D_0110_M_1111_N_0111,
	store_rm_disp_rn_l_D_0111_M_1111_N_0111,
	store_rm_disp_rn_l_D_1000_M_1111_N_0111,
	store_rm_disp_rn_l_D_1001_M_1111_N_0111,
	store_rm_disp_rn_l_D_1010_M_1111_N_0111,
	store_rm_disp_rn_l_D_1011_M_1111_N_0111,
	store_rm_disp_rn_l_D_1100_M_1111_N_0111,
	store_rm_disp_rn_l_D_1101_M_1111_N_0111,
	store_rm_disp_rn_l_D_1110_M_1111_N_0111,
	store_rm_disp_rn_l_D_1111_M_1111_N_0111,
	store_rm_disp_rn_l_D_0000_M_0000_N_1000,
	store_rm_disp_rn_l_D_0001_M_0000_N_1000,
	store_rm_disp_rn_l_D_0010_M_0000_N_1000,
	store_rm_disp_rn_l_D_0011_M_0000_N_1000,
	store_rm_disp_rn_l_D_0100_M_0000_N_1000,
	store_rm_disp_rn_l_D_0101_M_0000_N_1000,
	store_rm_disp_rn_l_D_0110_M_0000_N_1000,
	store_rm_disp_rn_l_D_0111_M_0000_N_1000,
	store_rm_disp_rn_l_D_1000_M_0000_N_1000,
	store_rm_disp_rn_l_D_1001_M_0000_N_1000,
	store_rm_disp_rn_l_D_1010_M_0000_N_1000,
	store_rm_disp_rn_l_D_1011_M_0000_N_1000,
	store_rm_disp_rn_l_D_1100_M_0000_N_1000,
	store_rm_disp_rn_l_D_1101_M_0000_N_1000,
	store_rm_disp_rn_l_D_1110_M_0000_N_1000,
	store_rm_disp_rn_l_D_1111_M_0000_N_1000,
	store_rm_disp_rn_l_D_0000_M_0001_N_1000,
	store_rm_disp_rn_l_D_0001_M_0001_N_1000,
	store_rm_disp_rn_l_D_0010_M_0001_N_1000,
	store_rm_disp_rn_l_D_0011_M_0001_N_1000,
	store_rm_disp_rn_l_D_0100_M_0001_N_1000,
	store_rm_disp_rn_l_D_0101_M_0001_N_1000,
	store_rm_disp_rn_l_D_0110_M_0001_N_1000,
	store_rm_disp_rn_l_D_0111_M_0001_N_1000,
	store_rm_disp_rn_l_D_1000_M_0001_N_1000,
	store_rm_disp_rn_l_D_1001_M_0001_N_1000,
	store_rm_disp_rn_l_D_1010_M_0001_N_1000,
	store_rm_disp_rn_l_D_1011_M_0001_N_1000,
	store_rm_disp_rn_l_D_1100_M_0001_N_1000,
	store_rm_disp_rn_l_D_1101_M_0001_N_1000,
	store_rm_disp_rn_l_D_1110_M_0001_N_1000,
	store_rm_disp_rn_l_D_1111_M_0001_N_1000,
	store_rm_disp_rn_l_D_0000_M_0010_N_1000,
	store_rm_disp_rn_l_D_0001_M_0010_N_1000,
	store_rm_disp_rn_l_D_0010_M_0010_N_1000,
	store_rm_disp_rn_l_D_0011_M_0010_N_1000,
	store_rm_disp_rn_l_D_0100_M_0010_N_1000,
	store_rm_disp_rn_l_D_0101_M_0010_N_1000,
	store_rm_disp_rn_l_D_0110_M_0010_N_1000,
	store_rm_disp_rn_l_D_0111_M_0010_N_1000,
	store_rm_disp_rn_l_D_1000_M_0010_N_1000,
	store_rm_disp_rn_l_D_1001_M_0010_N_1000,
	store_rm_disp_rn_l_D_1010_M_0010_N_1000,
	store_rm_disp_rn_l_D_1011_M_0010_N_1000,
	store_rm_disp_rn_l_D_1100_M_0010_N_1000,
	store_rm_disp_rn_l_D_1101_M_0010_N_1000,
	store_rm_disp_rn_l_D_1110_M_0010_N_1000,
	store_rm_disp_rn_l_D_1111_M_0010_N_1000,
	store_rm_disp_rn_l_D_0000_M_0011_N_1000,
	store_rm_disp_rn_l_D_0001_M_0011_N_1000,
	store_rm_disp_rn_l_D_0010_M_0011_N_1000,
	store_rm_disp_rn_l_D_0011_M_0011_N_1000,
	store_rm_disp_rn_l_D_0100_M_0011_N_1000,
	store_rm_disp_rn_l_D_0101_M_0011_N_1000,
	store_rm_disp_rn_l_D_0110_M_0011_N_1000,
	store_rm_disp_rn_l_D_0111_M_0011_N_1000,
	store_rm_disp_rn_l_D_1000_M_0011_N_1000,
	store_rm_disp_rn_l_D_1001_M_0011_N_1000,
	store_rm_disp_rn_l_D_1010_M_0011_N_1000,
	store_rm_disp_rn_l_D_1011_M_0011_N_1000,
	store_rm_disp_rn_l_D_1100_M_0011_N_1000,
	store_rm_disp_rn_l_D_1101_M_0011_N_1000,
	store_rm_disp_rn_l_D_1110_M_0011_N_1000,
	store_rm_disp_rn_l_D_1111_M_0011_N_1000,
	store_rm_disp_rn_l_D_0000_M_0100_N_1000,
	store_rm_disp_rn_l_D_0001_M_0100_N_1000,
	store_rm_disp_rn_l_D_0010_M_0100_N_1000,
	store_rm_disp_rn_l_D_0011_M_0100_N_1000,
	store_rm_disp_rn_l_D_0100_M_0100_N_1000,
	store_rm_disp_rn_l_D_0101_M_0100_N_1000,
	store_rm_disp_rn_l_D_0110_M_0100_N_1000,
	store_rm_disp_rn_l_D_0111_M_0100_N_1000,
	store_rm_disp_rn_l_D_1000_M_0100_N_1000,
	store_rm_disp_rn_l_D_1001_M_0100_N_1000,
	store_rm_disp_rn_l_D_1010_M_0100_N_1000,
	store_rm_disp_rn_l_D_1011_M_0100_N_1000,
	store_rm_disp_rn_l_D_1100_M_0100_N_1000,
	store_rm_disp_rn_l_D_1101_M_0100_N_1000,
	store_rm_disp_rn_l_D_1110_M_0100_N_1000,
	store_rm_disp_rn_l_D_1111_M_0100_N_1000,
	store_rm_disp_rn_l_D_0000_M_0101_N_1000,
	store_rm_disp_rn_l_D_0001_M_0101_N_1000,
	store_rm_disp_rn_l_D_0010_M_0101_N_1000,
	store_rm_disp_rn_l_D_0011_M_0101_N_1000,
	store_rm_disp_rn_l_D_0100_M_0101_N_1000,
	store_rm_disp_rn_l_D_0101_M_0101_N_1000,
	store_rm_disp_rn_l_D_0110_M_0101_N_1000,
	store_rm_disp_rn_l_D_0111_M_0101_N_1000,
	store_rm_disp_rn_l_D_1000_M_0101_N_1000,
	store_rm_disp_rn_l_D_1001_M_0101_N_1000,
	store_rm_disp_rn_l_D_1010_M_0101_N_1000,
	store_rm_disp_rn_l_D_1011_M_0101_N_1000,
	store_rm_disp_rn_l_D_1100_M_0101_N_1000,
	store_rm_disp_rn_l_D_1101_M_0101_N_1000,
	store_rm_disp_rn_l_D_1110_M_0101_N_1000,
	store_rm_disp_rn_l_D_1111_M_0101_N_1000,
	store_rm_disp_rn_l_D_0000_M_0110_N_1000,
	store_rm_disp_rn_l_D_0001_M_0110_N_1000,
	store_rm_disp_rn_l_D_0010_M_0110_N_1000,
	store_rm_disp_rn_l_D_0011_M_0110_N_1000,
	store_rm_disp_rn_l_D_0100_M_0110_N_1000,
	store_rm_disp_rn_l_D_0101_M_0110_N_1000,
	store_rm_disp_rn_l_D_0110_M_0110_N_1000,
	store_rm_disp_rn_l_D_0111_M_0110_N_1000,
	store_rm_disp_rn_l_D_1000_M_0110_N_1000,
	store_rm_disp_rn_l_D_1001_M_0110_N_1000,
	store_rm_disp_rn_l_D_1010_M_0110_N_1000,
	store_rm_disp_rn_l_D_1011_M_0110_N_1000,
	store_rm_disp_rn_l_D_1100_M_0110_N_1000,
	store_rm_disp_rn_l_D_1101_M_0110_N_1000,
	store_rm_disp_rn_l_D_1110_M_0110_N_1000,
	store_rm_disp_rn_l_D_1111_M_0110_N_1000,
	store_rm_disp_rn_l_D_0000_M_0111_N_1000,
	store_rm_disp_rn_l_D_0001_M_0111_N_1000,
	store_rm_disp_rn_l_D_0010_M_0111_N_1000,
	store_rm_disp_rn_l_D_0011_M_0111_N_1000,
	store_rm_disp_rn_l_D_0100_M_0111_N_1000,
	store_rm_disp_rn_l_D_0101_M_0111_N_1000,
	store_rm_disp_rn_l_D_0110_M_0111_N_1000,
	store_rm_disp_rn_l_D_0111_M_0111_N_1000,
	store_rm_disp_rn_l_D_1000_M_0111_N_1000,
	store_rm_disp_rn_l_D_1001_M_0111_N_1000,
	store_rm_disp_rn_l_D_1010_M_0111_N_1000,
	store_rm_disp_rn_l_D_1011_M_0111_N_1000,
	store_rm_disp_rn_l_D_1100_M_0111_N_1000,
	store_rm_disp_rn_l_D_1101_M_0111_N_1000,
	store_rm_disp_rn_l_D_1110_M_0111_N_1000,
	store_rm_disp_rn_l_D_1111_M_0111_N_1000,
	store_rm_disp_rn_l_D_0000_M_1000_N_1000,
	store_rm_disp_rn_l_D_0001_M_1000_N_1000,
	store_rm_disp_rn_l_D_0010_M_1000_N_1000,
	store_rm_disp_rn_l_D_0011_M_1000_N_1000,
	store_rm_disp_rn_l_D_0100_M_1000_N_1000,
	store_rm_disp_rn_l_D_0101_M_1000_N_1000,
	store_rm_disp_rn_l_D_0110_M_1000_N_1000,
	store_rm_disp_rn_l_D_0111_M_1000_N_1000,
	store_rm_disp_rn_l_D_1000_M_1000_N_1000,
	store_rm_disp_rn_l_D_1001_M_1000_N_1000,
	store_rm_disp_rn_l_D_1010_M_1000_N_1000,
	store_rm_disp_rn_l_D_1011_M_1000_N_1000,
	store_rm_disp_rn_l_D_1100_M_1000_N_1000,
	store_rm_disp_rn_l_D_1101_M_1000_N_1000,
	store_rm_disp_rn_l_D_1110_M_1000_N_1000,
	store_rm_disp_rn_l_D_1111_M_1000_N_1000,
	store_rm_disp_rn_l_D_0000_M_1001_N_1000,
	store_rm_disp_rn_l_D_0001_M_1001_N_1000,
	store_rm_disp_rn_l_D_0010_M_1001_N_1000,
	store_rm_disp_rn_l_D_0011_M_1001_N_1000,
	store_rm_disp_rn_l_D_0100_M_1001_N_1000,
	store_rm_disp_rn_l_D_0101_M_1001_N_1000,
	store_rm_disp_rn_l_D_0110_M_1001_N_1000,
	store_rm_disp_rn_l_D_0111_M_1001_N_1000,
	store_rm_disp_rn_l_D_1000_M_1001_N_1000,
	store_rm_disp_rn_l_D_1001_M_1001_N_1000,
	store_rm_disp_rn_l_D_1010_M_1001_N_1000,
	store_rm_disp_rn_l_D_1011_M_1001_N_1000,
	store_rm_disp_rn_l_D_1100_M_1001_N_1000,
	store_rm_disp_rn_l_D_1101_M_1001_N_1000,
	store_rm_disp_rn_l_D_1110_M_1001_N_1000,
	store_rm_disp_rn_l_D_1111_M_1001_N_1000,
	store_rm_disp_rn_l_D_0000_M_1010_N_1000,
	store_rm_disp_rn_l_D_0001_M_1010_N_1000,
	store_rm_disp_rn_l_D_0010_M_1010_N_1000,
	store_rm_disp_rn_l_D_0011_M_1010_N_1000,
	store_rm_disp_rn_l_D_0100_M_1010_N_1000,
	store_rm_disp_rn_l_D_0101_M_1010_N_1000,
	store_rm_disp_rn_l_D_0110_M_1010_N_1000,
	store_rm_disp_rn_l_D_0111_M_1010_N_1000,
	store_rm_disp_rn_l_D_1000_M_1010_N_1000,
	store_rm_disp_rn_l_D_1001_M_1010_N_1000,
	store_rm_disp_rn_l_D_1010_M_1010_N_1000,
	store_rm_disp_rn_l_D_1011_M_1010_N_1000,
	store_rm_disp_rn_l_D_1100_M_1010_N_1000,
	store_rm_disp_rn_l_D_1101_M_1010_N_1000,
	store_rm_disp_rn_l_D_1110_M_1010_N_1000,
	store_rm_disp_rn_l_D_1111_M_1010_N_1000,
	store_rm_disp_rn_l_D_0000_M_1011_N_1000,
	store_rm_disp_rn_l_D_0001_M_1011_N_1000,
	store_rm_disp_rn_l_D_0010_M_1011_N_1000,
	store_rm_disp_rn_l_D_0011_M_1011_N_1000,
	store_rm_disp_rn_l_D_0100_M_1011_N_1000,
	store_rm_disp_rn_l_D_0101_M_1011_N_1000,
	store_rm_disp_rn_l_D_0110_M_1011_N_1000,
	store_rm_disp_rn_l_D_0111_M_1011_N_1000,
	store_rm_disp_rn_l_D_1000_M_1011_N_1000,
	store_rm_disp_rn_l_D_1001_M_1011_N_1000,
	store_rm_disp_rn_l_D_1010_M_1011_N_1000,
	store_rm_disp_rn_l_D_1011_M_1011_N_1000,
	store_rm_disp_rn_l_D_1100_M_1011_N_1000,
	store_rm_disp_rn_l_D_1101_M_1011_N_1000,
	store_rm_disp_rn_l_D_1110_M_1011_N_1000,
	store_rm_disp_rn_l_D_1111_M_1011_N_1000,
	store_rm_disp_rn_l_D_0000_M_1100_N_1000,
	store_rm_disp_rn_l_D_0001_M_1100_N_1000,
	store_rm_disp_rn_l_D_0010_M_1100_N_1000,
	store_rm_disp_rn_l_D_0011_M_1100_N_1000,
	store_rm_disp_rn_l_D_0100_M_1100_N_1000,
	store_rm_disp_rn_l_D_0101_M_1100_N_1000,
	store_rm_disp_rn_l_D_0110_M_1100_N_1000,
	store_rm_disp_rn_l_D_0111_M_1100_N_1000,
	store_rm_disp_rn_l_D_1000_M_1100_N_1000,
	store_rm_disp_rn_l_D_1001_M_1100_N_1000,
	store_rm_disp_rn_l_D_1010_M_1100_N_1000,
	store_rm_disp_rn_l_D_1011_M_1100_N_1000,
	store_rm_disp_rn_l_D_1100_M_1100_N_1000,
	store_rm_disp_rn_l_D_1101_M_1100_N_1000,
	store_rm_disp_rn_l_D_1110_M_1100_N_1000,
	store_rm_disp_rn_l_D_1111_M_1100_N_1000,
	store_rm_disp_rn_l_D_0000_M_1101_N_1000,
	store_rm_disp_rn_l_D_0001_M_1101_N_1000,
	store_rm_disp_rn_l_D_0010_M_1101_N_1000,
	store_rm_disp_rn_l_D_0011_M_1101_N_1000,
	store_rm_disp_rn_l_D_0100_M_1101_N_1000,
	store_rm_disp_rn_l_D_0101_M_1101_N_1000,
	store_rm_disp_rn_l_D_0110_M_1101_N_1000,
	store_rm_disp_rn_l_D_0111_M_1101_N_1000,
	store_rm_disp_rn_l_D_1000_M_1101_N_1000,
	store_rm_disp_rn_l_D_1001_M_1101_N_1000,
	store_rm_disp_rn_l_D_1010_M_1101_N_1000,
	store_rm_disp_rn_l_D_1011_M_1101_N_1000,
	store_rm_disp_rn_l_D_1100_M_1101_N_1000,
	store_rm_disp_rn_l_D_1101_M_1101_N_1000,
	store_rm_disp_rn_l_D_1110_M_1101_N_1000,
	store_rm_disp_rn_l_D_1111_M_1101_N_1000,
	store_rm_disp_rn_l_D_0000_M_1110_N_1000,
	store_rm_disp_rn_l_D_0001_M_1110_N_1000,
	store_rm_disp_rn_l_D_0010_M_1110_N_1000,
	store_rm_disp_rn_l_D_0011_M_1110_N_1000,
	store_rm_disp_rn_l_D_0100_M_1110_N_1000,
	store_rm_disp_rn_l_D_0101_M_1110_N_1000,
	store_rm_disp_rn_l_D_0110_M_1110_N_1000,
	store_rm_disp_rn_l_D_0111_M_1110_N_1000,
	store_rm_disp_rn_l_D_1000_M_1110_N_1000,
	store_rm_disp_rn_l_D_1001_M_1110_N_1000,
	store_rm_disp_rn_l_D_1010_M_1110_N_1000,
	store_rm_disp_rn_l_D_1011_M_1110_N_1000,
	store_rm_disp_rn_l_D_1100_M_1110_N_1000,
	store_rm_disp_rn_l_D_1101_M_1110_N_1000,
	store_rm_disp_rn_l_D_1110_M_1110_N_1000,
	store_rm_disp_rn_l_D_1111_M_1110_N_1000,
	store_rm_disp_rn_l_D_0000_M_1111_N_1000,
	store_rm_disp_rn_l_D_0001_M_1111_N_1000,
	store_rm_disp_rn_l_D_0010_M_1111_N_1000,
	store_rm_disp_rn_l_D_0011_M_1111_N_1000,
	store_rm_disp_rn_l_D_0100_M_1111_N_1000,
	store_rm_disp_rn_l_D_0101_M_1111_N_1000,
	store_rm_disp_rn_l_D_0110_M_1111_N_1000,
	store_rm_disp_rn_l_D_0111_M_1111_N_1000,
	store_rm_disp_rn_l_D_1000_M_1111_N_1000,
	store_rm_disp_rn_l_D_1001_M_1111_N_1000,
	store_rm_disp_rn_l_D_1010_M_1111_N_1000,
	store_rm_disp_rn_l_D_1011_M_1111_N_1000,
	store_rm_disp_rn_l_D_1100_M_1111_N_1000,
	store_rm_disp_rn_l_D_1101_M_1111_N_1000,
	store_rm_disp_rn_l_D_1110_M_1111_N_1000,
	store_rm_disp_rn_l_D_1111_M_1111_N_1000,
	store_rm_disp_rn_l_D_0000_M_0000_N_1001,
	store_rm_disp_rn_l_D_0001_M_0000_N_1001,
	store_rm_disp_rn_l_D_0010_M_0000_N_1001,
	store_rm_disp_rn_l_D_0011_M_0000_N_1001,
	store_rm_disp_rn_l_D_0100_M_0000_N_1001,
	store_rm_disp_rn_l_D_0101_M_0000_N_1001,
	store_rm_disp_rn_l_D_0110_M_0000_N_1001,
	store_rm_disp_rn_l_D_0111_M_0000_N_1001,
	store_rm_disp_rn_l_D_1000_M_0000_N_1001,
	store_rm_disp_rn_l_D_1001_M_0000_N_1001,
	store_rm_disp_rn_l_D_1010_M_0000_N_1001,
	store_rm_disp_rn_l_D_1011_M_0000_N_1001,
	store_rm_disp_rn_l_D_1100_M_0000_N_1001,
	store_rm_disp_rn_l_D_1101_M_0000_N_1001,
	store_rm_disp_rn_l_D_1110_M_0000_N_1001,
	store_rm_disp_rn_l_D_1111_M_0000_N_1001,
	store_rm_disp_rn_l_D_0000_M_0001_N_1001,
	store_rm_disp_rn_l_D_0001_M_0001_N_1001,
	store_rm_disp_rn_l_D_0010_M_0001_N_1001,
	store_rm_disp_rn_l_D_0011_M_0001_N_1001,
	store_rm_disp_rn_l_D_0100_M_0001_N_1001,
	store_rm_disp_rn_l_D_0101_M_0001_N_1001,
	store_rm_disp_rn_l_D_0110_M_0001_N_1001,
	store_rm_disp_rn_l_D_0111_M_0001_N_1001,
	store_rm_disp_rn_l_D_1000_M_0001_N_1001,
	store_rm_disp_rn_l_D_1001_M_0001_N_1001,
	store_rm_disp_rn_l_D_1010_M_0001_N_1001,
	store_rm_disp_rn_l_D_1011_M_0001_N_1001,
	store_rm_disp_rn_l_D_1100_M_0001_N_1001,
	store_rm_disp_rn_l_D_1101_M_0001_N_1001,
	store_rm_disp_rn_l_D_1110_M_0001_N_1001,
	store_rm_disp_rn_l_D_1111_M_0001_N_1001,
	store_rm_disp_rn_l_D_0000_M_0010_N_1001,
	store_rm_disp_rn_l_D_0001_M_0010_N_1001,
	store_rm_disp_rn_l_D_0010_M_0010_N_1001,
	store_rm_disp_rn_l_D_0011_M_0010_N_1001,
	store_rm_disp_rn_l_D_0100_M_0010_N_1001,
	store_rm_disp_rn_l_D_0101_M_0010_N_1001,
	store_rm_disp_rn_l_D_0110_M_0010_N_1001,
	store_rm_disp_rn_l_D_0111_M_0010_N_1001,
	store_rm_disp_rn_l_D_1000_M_0010_N_1001,
	store_rm_disp_rn_l_D_1001_M_0010_N_1001,
	store_rm_disp_rn_l_D_1010_M_0010_N_1001,
	store_rm_disp_rn_l_D_1011_M_0010_N_1001,
	store_rm_disp_rn_l_D_1100_M_0010_N_1001,
	store_rm_disp_rn_l_D_1101_M_0010_N_1001,
	store_rm_disp_rn_l_D_1110_M_0010_N_1001,
	store_rm_disp_rn_l_D_1111_M_0010_N_1001,
	store_rm_disp_rn_l_D_0000_M_0011_N_1001,
	store_rm_disp_rn_l_D_0001_M_0011_N_1001,
	store_rm_disp_rn_l_D_0010_M_0011_N_1001,
	store_rm_disp_rn_l_D_0011_M_0011_N_1001,
	store_rm_disp_rn_l_D_0100_M_0011_N_1001,
	store_rm_disp_rn_l_D_0101_M_0011_N_1001,
	store_rm_disp_rn_l_D_0110_M_0011_N_1001,
	store_rm_disp_rn_l_D_0111_M_0011_N_1001,
	store_rm_disp_rn_l_D_1000_M_0011_N_1001,
	store_rm_disp_rn_l_D_1001_M_0011_N_1001,
	store_rm_disp_rn_l_D_1010_M_0011_N_1001,
	store_rm_disp_rn_l_D_1011_M_0011_N_1001,
	store_rm_disp_rn_l_D_1100_M_0011_N_1001,
	store_rm_disp_rn_l_D_1101_M_0011_N_1001,
	store_rm_disp_rn_l_D_1110_M_0011_N_1001,
	store_rm_disp_rn_l_D_1111_M_0011_N_1001,
	store_rm_disp_rn_l_D_0000_M_0100_N_1001,
	store_rm_disp_rn_l_D_0001_M_0100_N_1001,
	store_rm_disp_rn_l_D_0010_M_0100_N_1001,
	store_rm_disp_rn_l_D_0011_M_0100_N_1001,
	store_rm_disp_rn_l_D_0100_M_0100_N_1001,
	store_rm_disp_rn_l_D_0101_M_0100_N_1001,
	store_rm_disp_rn_l_D_0110_M_0100_N_1001,
	store_rm_disp_rn_l_D_0111_M_0100_N_1001,
	store_rm_disp_rn_l_D_1000_M_0100_N_1001,
	store_rm_disp_rn_l_D_1001_M_0100_N_1001,
	store_rm_disp_rn_l_D_1010_M_0100_N_1001,
	store_rm_disp_rn_l_D_1011_M_0100_N_1001,
	store_rm_disp_rn_l_D_1100_M_0100_N_1001,
	store_rm_disp_rn_l_D_1101_M_0100_N_1001,
	store_rm_disp_rn_l_D_1110_M_0100_N_1001,
	store_rm_disp_rn_l_D_1111_M_0100_N_1001,
	store_rm_disp_rn_l_D_0000_M_0101_N_1001,
	store_rm_disp_rn_l_D_0001_M_0101_N_1001,
	store_rm_disp_rn_l_D_0010_M_0101_N_1001,
	store_rm_disp_rn_l_D_0011_M_0101_N_1001,
	store_rm_disp_rn_l_D_0100_M_0101_N_1001,
	store_rm_disp_rn_l_D_0101_M_0101_N_1001,
	store_rm_disp_rn_l_D_0110_M_0101_N_1001,
	store_rm_disp_rn_l_D_0111_M_0101_N_1001,
	store_rm_disp_rn_l_D_1000_M_0101_N_1001,
	store_rm_disp_rn_l_D_1001_M_0101_N_1001,
	store_rm_disp_rn_l_D_1010_M_0101_N_1001,
	store_rm_disp_rn_l_D_1011_M_0101_N_1001,
	store_rm_disp_rn_l_D_1100_M_0101_N_1001,
	store_rm_disp_rn_l_D_1101_M_0101_N_1001,
	store_rm_disp_rn_l_D_1110_M_0101_N_1001,
	store_rm_disp_rn_l_D_1111_M_0101_N_1001,
	store_rm_disp_rn_l_D_0000_M_0110_N_1001,
	store_rm_disp_rn_l_D_0001_M_0110_N_1001,
	store_rm_disp_rn_l_D_0010_M_0110_N_1001,
	store_rm_disp_rn_l_D_0011_M_0110_N_1001,
	store_rm_disp_rn_l_D_0100_M_0110_N_1001,
	store_rm_disp_rn_l_D_0101_M_0110_N_1001,
	store_rm_disp_rn_l_D_0110_M_0110_N_1001,
	store_rm_disp_rn_l_D_0111_M_0110_N_1001,
	store_rm_disp_rn_l_D_1000_M_0110_N_1001,
	store_rm_disp_rn_l_D_1001_M_0110_N_1001,
	store_rm_disp_rn_l_D_1010_M_0110_N_1001,
	store_rm_disp_rn_l_D_1011_M_0110_N_1001,
	store_rm_disp_rn_l_D_1100_M_0110_N_1001,
	store_rm_disp_rn_l_D_1101_M_0110_N_1001,
	store_rm_disp_rn_l_D_1110_M_0110_N_1001,
	store_rm_disp_rn_l_D_1111_M_0110_N_1001,
	store_rm_disp_rn_l_D_0000_M_0111_N_1001,
	store_rm_disp_rn_l_D_0001_M_0111_N_1001,
	store_rm_disp_rn_l_D_0010_M_0111_N_1001,
	store_rm_disp_rn_l_D_0011_M_0111_N_1001,
	store_rm_disp_rn_l_D_0100_M_0111_N_1001,
	store_rm_disp_rn_l_D_0101_M_0111_N_1001,
	store_rm_disp_rn_l_D_0110_M_0111_N_1001,
	store_rm_disp_rn_l_D_0111_M_0111_N_1001,
	store_rm_disp_rn_l_D_1000_M_0111_N_1001,
	store_rm_disp_rn_l_D_1001_M_0111_N_1001,
	store_rm_disp_rn_l_D_1010_M_0111_N_1001,
	store_rm_disp_rn_l_D_1011_M_0111_N_1001,
	store_rm_disp_rn_l_D_1100_M_0111_N_1001,
	store_rm_disp_rn_l_D_1101_M_0111_N_1001,
	store_rm_disp_rn_l_D_1110_M_0111_N_1001,
	store_rm_disp_rn_l_D_1111_M_0111_N_1001,
	store_rm_disp_rn_l_D_0000_M_1000_N_1001,
	store_rm_disp_rn_l_D_0001_M_1000_N_1001,
	store_rm_disp_rn_l_D_0010_M_1000_N_1001,
	store_rm_disp_rn_l_D_0011_M_1000_N_1001,
	store_rm_disp_rn_l_D_0100_M_1000_N_1001,
	store_rm_disp_rn_l_D_0101_M_1000_N_1001,
	store_rm_disp_rn_l_D_0110_M_1000_N_1001,
	store_rm_disp_rn_l_D_0111_M_1000_N_1001,
	store_rm_disp_rn_l_D_1000_M_1000_N_1001,
	store_rm_disp_rn_l_D_1001_M_1000_N_1001,
	store_rm_disp_rn_l_D_1010_M_1000_N_1001,
	store_rm_disp_rn_l_D_1011_M_1000_N_1001,
	store_rm_disp_rn_l_D_1100_M_1000_N_1001,
	store_rm_disp_rn_l_D_1101_M_1000_N_1001,
	store_rm_disp_rn_l_D_1110_M_1000_N_1001,
	store_rm_disp_rn_l_D_1111_M_1000_N_1001,
	store_rm_disp_rn_l_D_0000_M_1001_N_1001,
	store_rm_disp_rn_l_D_0001_M_1001_N_1001,
	store_rm_disp_rn_l_D_0010_M_1001_N_1001,
	store_rm_disp_rn_l_D_0011_M_1001_N_1001,
	store_rm_disp_rn_l_D_0100_M_1001_N_1001,
	store_rm_disp_rn_l_D_0101_M_1001_N_1001,
	store_rm_disp_rn_l_D_0110_M_1001_N_1001,
	store_rm_disp_rn_l_D_0111_M_1001_N_1001,
	store_rm_disp_rn_l_D_1000_M_1001_N_1001,
	store_rm_disp_rn_l_D_1001_M_1001_N_1001,
	store_rm_disp_rn_l_D_1010_M_1001_N_1001,
	store_rm_disp_rn_l_D_1011_M_1001_N_1001,
	store_rm_disp_rn_l_D_1100_M_1001_N_1001,
	store_rm_disp_rn_l_D_1101_M_1001_N_1001,
	store_rm_disp_rn_l_D_1110_M_1001_N_1001,
	store_rm_disp_rn_l_D_1111_M_1001_N_1001,
	store_rm_disp_rn_l_D_0000_M_1010_N_1001,
	store_rm_disp_rn_l_D_0001_M_1010_N_1001,
	store_rm_disp_rn_l_D_0010_M_1010_N_1001,
	store_rm_disp_rn_l_D_0011_M_1010_N_1001,
	store_rm_disp_rn_l_D_0100_M_1010_N_1001,
	store_rm_disp_rn_l_D_0101_M_1010_N_1001,
	store_rm_disp_rn_l_D_0110_M_1010_N_1001,
	store_rm_disp_rn_l_D_0111_M_1010_N_1001,
	store_rm_disp_rn_l_D_1000_M_1010_N_1001,
	store_rm_disp_rn_l_D_1001_M_1010_N_1001,
	store_rm_disp_rn_l_D_1010_M_1010_N_1001,
	store_rm_disp_rn_l_D_1011_M_1010_N_1001,
	store_rm_disp_rn_l_D_1100_M_1010_N_1001,
	store_rm_disp_rn_l_D_1101_M_1010_N_1001,
	store_rm_disp_rn_l_D_1110_M_1010_N_1001,
	store_rm_disp_rn_l_D_1111_M_1010_N_1001,
	store_rm_disp_rn_l_D_0000_M_1011_N_1001,
	store_rm_disp_rn_l_D_0001_M_1011_N_1001,
	store_rm_disp_rn_l_D_0010_M_1011_N_1001,
	store_rm_disp_rn_l_D_0011_M_1011_N_1001,
	store_rm_disp_rn_l_D_0100_M_1011_N_1001,
	store_rm_disp_rn_l_D_0101_M_1011_N_1001,
	store_rm_disp_rn_l_D_0110_M_1011_N_1001,
	store_rm_disp_rn_l_D_0111_M_1011_N_1001,
	store_rm_disp_rn_l_D_1000_M_1011_N_1001,
	store_rm_disp_rn_l_D_1001_M_1011_N_1001,
	store_rm_disp_rn_l_D_1010_M_1011_N_1001,
	store_rm_disp_rn_l_D_1011_M_1011_N_1001,
	store_rm_disp_rn_l_D_1100_M_1011_N_1001,
	store_rm_disp_rn_l_D_1101_M_1011_N_1001,
	store_rm_disp_rn_l_D_1110_M_1011_N_1001,
	store_rm_disp_rn_l_D_1111_M_1011_N_1001,
	store_rm_disp_rn_l_D_0000_M_1100_N_1001,
	store_rm_disp_rn_l_D_0001_M_1100_N_1001,
	store_rm_disp_rn_l_D_0010_M_1100_N_1001,
	store_rm_disp_rn_l_D_0011_M_1100_N_1001,
	store_rm_disp_rn_l_D_0100_M_1100_N_1001,
	store_rm_disp_rn_l_D_0101_M_1100_N_1001,
	store_rm_disp_rn_l_D_0110_M_1100_N_1001,
	store_rm_disp_rn_l_D_0111_M_1100_N_1001,
	store_rm_disp_rn_l_D_1000_M_1100_N_1001,
	store_rm_disp_rn_l_D_1001_M_1100_N_1001,
	store_rm_disp_rn_l_D_1010_M_1100_N_1001,
	store_rm_disp_rn_l_D_1011_M_1100_N_1001,
	store_rm_disp_rn_l_D_1100_M_1100_N_1001,
	store_rm_disp_rn_l_D_1101_M_1100_N_1001,
	store_rm_disp_rn_l_D_1110_M_1100_N_1001,
	store_rm_disp_rn_l_D_1111_M_1100_N_1001,
	store_rm_disp_rn_l_D_0000_M_1101_N_1001,
	store_rm_disp_rn_l_D_0001_M_1101_N_1001,
	store_rm_disp_rn_l_D_0010_M_1101_N_1001,
	store_rm_disp_rn_l_D_0011_M_1101_N_1001,
	store_rm_disp_rn_l_D_0100_M_1101_N_1001,
	store_rm_disp_rn_l_D_0101_M_1101_N_1001,
	store_rm_disp_rn_l_D_0110_M_1101_N_1001,
	store_rm_disp_rn_l_D_0111_M_1101_N_1001,
	store_rm_disp_rn_l_D_1000_M_1101_N_1001,
	store_rm_disp_rn_l_D_1001_M_1101_N_1001,
	store_rm_disp_rn_l_D_1010_M_1101_N_1001,
	store_rm_disp_rn_l_D_1011_M_1101_N_1001,
	store_rm_disp_rn_l_D_1100_M_1101_N_1001,
	store_rm_disp_rn_l_D_1101_M_1101_N_1001,
	store_rm_disp_rn_l_D_1110_M_1101_N_1001,
	store_rm_disp_rn_l_D_1111_M_1101_N_1001,
	store_rm_disp_rn_l_D_0000_M_1110_N_1001,
	store_rm_disp_rn_l_D_0001_M_1110_N_1001,
	store_rm_disp_rn_l_D_0010_M_1110_N_1001,
	store_rm_disp_rn_l_D_0011_M_1110_N_1001,
	store_rm_disp_rn_l_D_0100_M_1110_N_1001,
	store_rm_disp_rn_l_D_0101_M_1110_N_1001,
	store_rm_disp_rn_l_D_0110_M_1110_N_1001,
	store_rm_disp_rn_l_D_0111_M_1110_N_1001,
	store_rm_disp_rn_l_D_1000_M_1110_N_1001,
	store_rm_disp_rn_l_D_1001_M_1110_N_1001,
	store_rm_disp_rn_l_D_1010_M_1110_N_1001,
	store_rm_disp_rn_l_D_1011_M_1110_N_1001,
	store_rm_disp_rn_l_D_1100_M_1110_N_1001,
	store_rm_disp_rn_l_D_1101_M_1110_N_1001,
	store_rm_disp_rn_l_D_1110_M_1110_N_1001,
	store_rm_disp_rn_l_D_1111_M_1110_N_1001,
	store_rm_disp_rn_l_D_0000_M_1111_N_1001,
	store_rm_disp_rn_l_D_0001_M_1111_N_1001,
	store_rm_disp_rn_l_D_0010_M_1111_N_1001,
	store_rm_disp_rn_l_D_0011_M_1111_N_1001,
	store_rm_disp_rn_l_D_0100_M_1111_N_1001,
	store_rm_disp_rn_l_D_0101_M_1111_N_1001,
	store_rm_disp_rn_l_D_0110_M_1111_N_1001,
	store_rm_disp_rn_l_D_0111_M_1111_N_1001,
	store_rm_disp_rn_l_D_1000_M_1111_N_1001,
	store_rm_disp_rn_l_D_1001_M_1111_N_1001,
	store_rm_disp_rn_l_D_1010_M_1111_N_1001,
	store_rm_disp_rn_l_D_1011_M_1111_N_1001,
	store_rm_disp_rn_l_D_1100_M_1111_N_1001,
	store_rm_disp_rn_l_D_1101_M_1111_N_1001,
	store_rm_disp_rn_l_D_1110_M_1111_N_1001,
	store_rm_disp_rn_l_D_1111_M_1111_N_1001,
	store_rm_disp_rn_l_D_0000_M_0000_N_1010,
	store_rm_disp_rn_l_D_0001_M_0000_N_1010,
	store_rm_disp_rn_l_D_0010_M_0000_N_1010,
	store_rm_disp_rn_l_D_0011_M_0000_N_1010,
	store_rm_disp_rn_l_D_0100_M_0000_N_1010,
	store_rm_disp_rn_l_D_0101_M_0000_N_1010,
	store_rm_disp_rn_l_D_0110_M_0000_N_1010,
	store_rm_disp_rn_l_D_0111_M_0000_N_1010,
	store_rm_disp_rn_l_D_1000_M_0000_N_1010,
	store_rm_disp_rn_l_D_1001_M_0000_N_1010,
	store_rm_disp_rn_l_D_1010_M_0000_N_1010,
	store_rm_disp_rn_l_D_1011_M_0000_N_1010,
	store_rm_disp_rn_l_D_1100_M_0000_N_1010,
	store_rm_disp_rn_l_D_1101_M_0000_N_1010,
	store_rm_disp_rn_l_D_1110_M_0000_N_1010,
	store_rm_disp_rn_l_D_1111_M_0000_N_1010,
	store_rm_disp_rn_l_D_0000_M_0001_N_1010,
	store_rm_disp_rn_l_D_0001_M_0001_N_1010,
	store_rm_disp_rn_l_D_0010_M_0001_N_1010,
	store_rm_disp_rn_l_D_0011_M_0001_N_1010,
	store_rm_disp_rn_l_D_0100_M_0001_N_1010,
	store_rm_disp_rn_l_D_0101_M_0001_N_1010,
	store_rm_disp_rn_l_D_0110_M_0001_N_1010,
	store_rm_disp_rn_l_D_0111_M_0001_N_1010,
	store_rm_disp_rn_l_D_1000_M_0001_N_1010,
	store_rm_disp_rn_l_D_1001_M_0001_N_1010,
	store_rm_disp_rn_l_D_1010_M_0001_N_1010,
	store_rm_disp_rn_l_D_1011_M_0001_N_1010,
	store_rm_disp_rn_l_D_1100_M_0001_N_1010,
	store_rm_disp_rn_l_D_1101_M_0001_N_1010,
	store_rm_disp_rn_l_D_1110_M_0001_N_1010,
	store_rm_disp_rn_l_D_1111_M_0001_N_1010,
	store_rm_disp_rn_l_D_0000_M_0010_N_1010,
	store_rm_disp_rn_l_D_0001_M_0010_N_1010,
	store_rm_disp_rn_l_D_0010_M_0010_N_1010,
	store_rm_disp_rn_l_D_0011_M_0010_N_1010,
	store_rm_disp_rn_l_D_0100_M_0010_N_1010,
	store_rm_disp_rn_l_D_0101_M_0010_N_1010,
	store_rm_disp_rn_l_D_0110_M_0010_N_1010,
	store_rm_disp_rn_l_D_0111_M_0010_N_1010,
	store_rm_disp_rn_l_D_1000_M_0010_N_1010,
	store_rm_disp_rn_l_D_1001_M_0010_N_1010,
	store_rm_disp_rn_l_D_1010_M_0010_N_1010,
	store_rm_disp_rn_l_D_1011_M_0010_N_1010,
	store_rm_disp_rn_l_D_1100_M_0010_N_1010,
	store_rm_disp_rn_l_D_1101_M_0010_N_1010,
	store_rm_disp_rn_l_D_1110_M_0010_N_1010,
	store_rm_disp_rn_l_D_1111_M_0010_N_1010,
	store_rm_disp_rn_l_D_0000_M_0011_N_1010,
	store_rm_disp_rn_l_D_0001_M_0011_N_1010,
	store_rm_disp_rn_l_D_0010_M_0011_N_1010,
	store_rm_disp_rn_l_D_0011_M_0011_N_1010,
	store_rm_disp_rn_l_D_0100_M_0011_N_1010,
	store_rm_disp_rn_l_D_0101_M_0011_N_1010,
	store_rm_disp_rn_l_D_0110_M_0011_N_1010,
	store_rm_disp_rn_l_D_0111_M_0011_N_1010,
	store_rm_disp_rn_l_D_1000_M_0011_N_1010,
	store_rm_disp_rn_l_D_1001_M_0011_N_1010,
	store_rm_disp_rn_l_D_1010_M_0011_N_1010,
	store_rm_disp_rn_l_D_1011_M_0011_N_1010,
	store_rm_disp_rn_l_D_1100_M_0011_N_1010,
	store_rm_disp_rn_l_D_1101_M_0011_N_1010,
	store_rm_disp_rn_l_D_1110_M_0011_N_1010,
	store_rm_disp_rn_l_D_1111_M_0011_N_1010,
	store_rm_disp_rn_l_D_0000_M_0100_N_1010,
	store_rm_disp_rn_l_D_0001_M_0100_N_1010,
	store_rm_disp_rn_l_D_0010_M_0100_N_1010,
	store_rm_disp_rn_l_D_0011_M_0100_N_1010,
	store_rm_disp_rn_l_D_0100_M_0100_N_1010,
	store_rm_disp_rn_l_D_0101_M_0100_N_1010,
	store_rm_disp_rn_l_D_0110_M_0100_N_1010,
	store_rm_disp_rn_l_D_0111_M_0100_N_1010,
	store_rm_disp_rn_l_D_1000_M_0100_N_1010,
	store_rm_disp_rn_l_D_1001_M_0100_N_1010,
	store_rm_disp_rn_l_D_1010_M_0100_N_1010,
	store_rm_disp_rn_l_D_1011_M_0100_N_1010,
	store_rm_disp_rn_l_D_1100_M_0100_N_1010,
	store_rm_disp_rn_l_D_1101_M_0100_N_1010,
	store_rm_disp_rn_l_D_1110_M_0100_N_1010,
	store_rm_disp_rn_l_D_1111_M_0100_N_1010,
	store_rm_disp_rn_l_D_0000_M_0101_N_1010,
	store_rm_disp_rn_l_D_0001_M_0101_N_1010,
	store_rm_disp_rn_l_D_0010_M_0101_N_1010,
	store_rm_disp_rn_l_D_0011_M_0101_N_1010,
	store_rm_disp_rn_l_D_0100_M_0101_N_1010,
	store_rm_disp_rn_l_D_0101_M_0101_N_1010,
	store_rm_disp_rn_l_D_0110_M_0101_N_1010,
	store_rm_disp_rn_l_D_0111_M_0101_N_1010,
	store_rm_disp_rn_l_D_1000_M_0101_N_1010,
	store_rm_disp_rn_l_D_1001_M_0101_N_1010,
	store_rm_disp_rn_l_D_1010_M_0101_N_1010,
	store_rm_disp_rn_l_D_1011_M_0101_N_1010,
	store_rm_disp_rn_l_D_1100_M_0101_N_1010,
	store_rm_disp_rn_l_D_1101_M_0101_N_1010,
	store_rm_disp_rn_l_D_1110_M_0101_N_1010,
	store_rm_disp_rn_l_D_1111_M_0101_N_1010,
	store_rm_disp_rn_l_D_0000_M_0110_N_1010,
	store_rm_disp_rn_l_D_0001_M_0110_N_1010,
	store_rm_disp_rn_l_D_0010_M_0110_N_1010,
	store_rm_disp_rn_l_D_0011_M_0110_N_1010,
	store_rm_disp_rn_l_D_0100_M_0110_N_1010,
	store_rm_disp_rn_l_D_0101_M_0110_N_1010,
	store_rm_disp_rn_l_D_0110_M_0110_N_1010,
	store_rm_disp_rn_l_D_0111_M_0110_N_1010,
	store_rm_disp_rn_l_D_1000_M_0110_N_1010,
	store_rm_disp_rn_l_D_1001_M_0110_N_1010,
	store_rm_disp_rn_l_D_1010_M_0110_N_1010,
	store_rm_disp_rn_l_D_1011_M_0110_N_1010,
	store_rm_disp_rn_l_D_1100_M_0110_N_1010,
	store_rm_disp_rn_l_D_1101_M_0110_N_1010,
	store_rm_disp_rn_l_D_1110_M_0110_N_1010,
	store_rm_disp_rn_l_D_1111_M_0110_N_1010,
	store_rm_disp_rn_l_D_0000_M_0111_N_1010,
	store_rm_disp_rn_l_D_0001_M_0111_N_1010,
	store_rm_disp_rn_l_D_0010_M_0111_N_1010,
	store_rm_disp_rn_l_D_0011_M_0111_N_1010,
	store_rm_disp_rn_l_D_0100_M_0111_N_1010,
	store_rm_disp_rn_l_D_0101_M_0111_N_1010,
	store_rm_disp_rn_l_D_0110_M_0111_N_1010,
	store_rm_disp_rn_l_D_0111_M_0111_N_1010,
	store_rm_disp_rn_l_D_1000_M_0111_N_1010,
	store_rm_disp_rn_l_D_1001_M_0111_N_1010,
	store_rm_disp_rn_l_D_1010_M_0111_N_1010,
	store_rm_disp_rn_l_D_1011_M_0111_N_1010,
	store_rm_disp_rn_l_D_1100_M_0111_N_1010,
	store_rm_disp_rn_l_D_1101_M_0111_N_1010,
	store_rm_disp_rn_l_D_1110_M_0111_N_1010,
	store_rm_disp_rn_l_D_1111_M_0111_N_1010,
	store_rm_disp_rn_l_D_0000_M_1000_N_1010,
	store_rm_disp_rn_l_D_0001_M_1000_N_1010,
	store_rm_disp_rn_l_D_0010_M_1000_N_1010,
	store_rm_disp_rn_l_D_0011_M_1000_N_1010,
	store_rm_disp_rn_l_D_0100_M_1000_N_1010,
	store_rm_disp_rn_l_D_0101_M_1000_N_1010,
	store_rm_disp_rn_l_D_0110_M_1000_N_1010,
	store_rm_disp_rn_l_D_0111_M_1000_N_1010,
	store_rm_disp_rn_l_D_1000_M_1000_N_1010,
	store_rm_disp_rn_l_D_1001_M_1000_N_1010,
	store_rm_disp_rn_l_D_1010_M_1000_N_1010,
	store_rm_disp_rn_l_D_1011_M_1000_N_1010,
	store_rm_disp_rn_l_D_1100_M_1000_N_1010,
	store_rm_disp_rn_l_D_1101_M_1000_N_1010,
	store_rm_disp_rn_l_D_1110_M_1000_N_1010,
	store_rm_disp_rn_l_D_1111_M_1000_N_1010,
	store_rm_disp_rn_l_D_0000_M_1001_N_1010,
	store_rm_disp_rn_l_D_0001_M_1001_N_1010,
	store_rm_disp_rn_l_D_0010_M_1001_N_1010,
	store_rm_disp_rn_l_D_0011_M_1001_N_1010,
	store_rm_disp_rn_l_D_0100_M_1001_N_1010,
	store_rm_disp_rn_l_D_0101_M_1001_N_1010,
	store_rm_disp_rn_l_D_0110_M_1001_N_1010,
	store_rm_disp_rn_l_D_0111_M_1001_N_1010,
	store_rm_disp_rn_l_D_1000_M_1001_N_1010,
	store_rm_disp_rn_l_D_1001_M_1001_N_1010,
	store_rm_disp_rn_l_D_1010_M_1001_N_1010,
	store_rm_disp_rn_l_D_1011_M_1001_N_1010,
	store_rm_disp_rn_l_D_1100_M_1001_N_1010,
	store_rm_disp_rn_l_D_1101_M_1001_N_1010,
	store_rm_disp_rn_l_D_1110_M_1001_N_1010,
	store_rm_disp_rn_l_D_1111_M_1001_N_1010,
	store_rm_disp_rn_l_D_0000_M_1010_N_1010,
	store_rm_disp_rn_l_D_0001_M_1010_N_1010,
	store_rm_disp_rn_l_D_0010_M_1010_N_1010,
	store_rm_disp_rn_l_D_0011_M_1010_N_1010,
	store_rm_disp_rn_l_D_0100_M_1010_N_1010,
	store_rm_disp_rn_l_D_0101_M_1010_N_1010,
	store_rm_disp_rn_l_D_0110_M_1010_N_1010,
	store_rm_disp_rn_l_D_0111_M_1010_N_1010,
	store_rm_disp_rn_l_D_1000_M_1010_N_1010,
	store_rm_disp_rn_l_D_1001_M_1010_N_1010,
	store_rm_disp_rn_l_D_1010_M_1010_N_1010,
	store_rm_disp_rn_l_D_1011_M_1010_N_1010,
	store_rm_disp_rn_l_D_1100_M_1010_N_1010,
	store_rm_disp_rn_l_D_1101_M_1010_N_1010,
	store_rm_disp_rn_l_D_1110_M_1010_N_1010,
	store_rm_disp_rn_l_D_1111_M_1010_N_1010,
	store_rm_disp_rn_l_D_0000_M_1011_N_1010,
	store_rm_disp_rn_l_D_0001_M_1011_N_1010,
	store_rm_disp_rn_l_D_0010_M_1011_N_1010,
	store_rm_disp_rn_l_D_0011_M_1011_N_1010,
	store_rm_disp_rn_l_D_0100_M_1011_N_1010,
	store_rm_disp_rn_l_D_0101_M_1011_N_1010,
	store_rm_disp_rn_l_D_0110_M_1011_N_1010,
	store_rm_disp_rn_l_D_0111_M_1011_N_1010,
	store_rm_disp_rn_l_D_1000_M_1011_N_1010,
	store_rm_disp_rn_l_D_1001_M_1011_N_1010,
	store_rm_disp_rn_l_D_1010_M_1011_N_1010,
	store_rm_disp_rn_l_D_1011_M_1011_N_1010,
	store_rm_disp_rn_l_D_1100_M_1011_N_1010,
	store_rm_disp_rn_l_D_1101_M_1011_N_1010,
	store_rm_disp_rn_l_D_1110_M_1011_N_1010,
	store_rm_disp_rn_l_D_1111_M_1011_N_1010,
	store_rm_disp_rn_l_D_0000_M_1100_N_1010,
	store_rm_disp_rn_l_D_0001_M_1100_N_1010,
	store_rm_disp_rn_l_D_0010_M_1100_N_1010,
	store_rm_disp_rn_l_D_0011_M_1100_N_1010,
	store_rm_disp_rn_l_D_0100_M_1100_N_1010,
	store_rm_disp_rn_l_D_0101_M_1100_N_1010,
	store_rm_disp_rn_l_D_0110_M_1100_N_1010,
	store_rm_disp_rn_l_D_0111_M_1100_N_1010,
	store_rm_disp_rn_l_D_1000_M_1100_N_1010,
	store_rm_disp_rn_l_D_1001_M_1100_N_1010,
	store_rm_disp_rn_l_D_1010_M_1100_N_1010,
	store_rm_disp_rn_l_D_1011_M_1100_N_1010,
	store_rm_disp_rn_l_D_1100_M_1100_N_1010,
	store_rm_disp_rn_l_D_1101_M_1100_N_1010,
	store_rm_disp_rn_l_D_1110_M_1100_N_1010,
	store_rm_disp_rn_l_D_1111_M_1100_N_1010,
	store_rm_disp_rn_l_D_0000_M_1101_N_1010,
	store_rm_disp_rn_l_D_0001_M_1101_N_1010,
	store_rm_disp_rn_l_D_0010_M_1101_N_1010,
	store_rm_disp_rn_l_D_0011_M_1101_N_1010,
	store_rm_disp_rn_l_D_0100_M_1101_N_1010,
	store_rm_disp_rn_l_D_0101_M_1101_N_1010,
	store_rm_disp_rn_l_D_0110_M_1101_N_1010,
	store_rm_disp_rn_l_D_0111_M_1101_N_1010,
	store_rm_disp_rn_l_D_1000_M_1101_N_1010,
	store_rm_disp_rn_l_D_1001_M_1101_N_1010,
	store_rm_disp_rn_l_D_1010_M_1101_N_1010,
	store_rm_disp_rn_l_D_1011_M_1101_N_1010,
	store_rm_disp_rn_l_D_1100_M_1101_N_1010,
	store_rm_disp_rn_l_D_1101_M_1101_N_1010,
	store_rm_disp_rn_l_D_1110_M_1101_N_1010,
	store_rm_disp_rn_l_D_1111_M_1101_N_1010,
	store_rm_disp_rn_l_D_0000_M_1110_N_1010,
	store_rm_disp_rn_l_D_0001_M_1110_N_1010,
	store_rm_disp_rn_l_D_0010_M_1110_N_1010,
	store_rm_disp_rn_l_D_0011_M_1110_N_1010,
	store_rm_disp_rn_l_D_0100_M_1110_N_1010,
	store_rm_disp_rn_l_D_0101_M_1110_N_1010,
	store_rm_disp_rn_l_D_0110_M_1110_N_1010,
	store_rm_disp_rn_l_D_0111_M_1110_N_1010,
	store_rm_disp_rn_l_D_1000_M_1110_N_1010,
	store_rm_disp_rn_l_D_1001_M_1110_N_1010,
	store_rm_disp_rn_l_D_1010_M_1110_N_1010,
	store_rm_disp_rn_l_D_1011_M_1110_N_1010,
	store_rm_disp_rn_l_D_1100_M_1110_N_1010,
	store_rm_disp_rn_l_D_1101_M_1110_N_1010,
	store_rm_disp_rn_l_D_1110_M_1110_N_1010,
	store_rm_disp_rn_l_D_1111_M_1110_N_1010,
	store_rm_disp_rn_l_D_0000_M_1111_N_1010,
	store_rm_disp_rn_l_D_0001_M_1111_N_1010,
	store_rm_disp_rn_l_D_0010_M_1111_N_1010,
	store_rm_disp_rn_l_D_0011_M_1111_N_1010,
	store_rm_disp_rn_l_D_0100_M_1111_N_1010,
	store_rm_disp_rn_l_D_0101_M_1111_N_1010,
	store_rm_disp_rn_l_D_0110_M_1111_N_1010,
	store_rm_disp_rn_l_D_0111_M_1111_N_1010,
	store_rm_disp_rn_l_D_1000_M_1111_N_1010,
	store_rm_disp_rn_l_D_1001_M_1111_N_1010,
	store_rm_disp_rn_l_D_1010_M_1111_N_1010,
	store_rm_disp_rn_l_D_1011_M_1111_N_1010,
	store_rm_disp_rn_l_D_1100_M_1111_N_1010,
	store_rm_disp_rn_l_D_1101_M_1111_N_1010,
	store_rm_disp_rn_l_D_1110_M_1111_N_1010,
	store_rm_disp_rn_l_D_1111_M_1111_N_1010,
	store_rm_disp_rn_l_D_0000_M_0000_N_1011,
	store_rm_disp_rn_l_D_0001_M_0000_N_1011,
	store_rm_disp_rn_l_D_0010_M_0000_N_1011,
	store_rm_disp_rn_l_D_0011_M_0000_N_1011,
	store_rm_disp_rn_l_D_0100_M_0000_N_1011,
	store_rm_disp_rn_l_D_0101_M_0000_N_1011,
	store_rm_disp_rn_l_D_0110_M_0000_N_1011,
	store_rm_disp_rn_l_D_0111_M_0000_N_1011,
	store_rm_disp_rn_l_D_1000_M_0000_N_1011,
	store_rm_disp_rn_l_D_1001_M_0000_N_1011,
	store_rm_disp_rn_l_D_1010_M_0000_N_1011,
	store_rm_disp_rn_l_D_1011_M_0000_N_1011,
	store_rm_disp_rn_l_D_1100_M_0000_N_1011,
	store_rm_disp_rn_l_D_1101_M_0000_N_1011,
	store_rm_disp_rn_l_D_1110_M_0000_N_1011,
	store_rm_disp_rn_l_D_1111_M_0000_N_1011,
	store_rm_disp_rn_l_D_0000_M_0001_N_1011,
	store_rm_disp_rn_l_D_0001_M_0001_N_1011,
	store_rm_disp_rn_l_D_0010_M_0001_N_1011,
	store_rm_disp_rn_l_D_0011_M_0001_N_1011,
	store_rm_disp_rn_l_D_0100_M_0001_N_1011,
	store_rm_disp_rn_l_D_0101_M_0001_N_1011,
	store_rm_disp_rn_l_D_0110_M_0001_N_1011,
	store_rm_disp_rn_l_D_0111_M_0001_N_1011,
	store_rm_disp_rn_l_D_1000_M_0001_N_1011,
	store_rm_disp_rn_l_D_1001_M_0001_N_1011,
	store_rm_disp_rn_l_D_1010_M_0001_N_1011,
	store_rm_disp_rn_l_D_1011_M_0001_N_1011,
	store_rm_disp_rn_l_D_1100_M_0001_N_1011,
	store_rm_disp_rn_l_D_1101_M_0001_N_1011,
	store_rm_disp_rn_l_D_1110_M_0001_N_1011,
	store_rm_disp_rn_l_D_1111_M_0001_N_1011,
	store_rm_disp_rn_l_D_0000_M_0010_N_1011,
	store_rm_disp_rn_l_D_0001_M_0010_N_1011,
	store_rm_disp_rn_l_D_0010_M_0010_N_1011,
	store_rm_disp_rn_l_D_0011_M_0010_N_1011,
	store_rm_disp_rn_l_D_0100_M_0010_N_1011,
	store_rm_disp_rn_l_D_0101_M_0010_N_1011,
	store_rm_disp_rn_l_D_0110_M_0010_N_1011,
	store_rm_disp_rn_l_D_0111_M_0010_N_1011,
	store_rm_disp_rn_l_D_1000_M_0010_N_1011,
	store_rm_disp_rn_l_D_1001_M_0010_N_1011,
	store_rm_disp_rn_l_D_1010_M_0010_N_1011,
	store_rm_disp_rn_l_D_1011_M_0010_N_1011,
	store_rm_disp_rn_l_D_1100_M_0010_N_1011,
	store_rm_disp_rn_l_D_1101_M_0010_N_1011,
	store_rm_disp_rn_l_D_1110_M_0010_N_1011,
	store_rm_disp_rn_l_D_1111_M_0010_N_1011,
	store_rm_disp_rn_l_D_0000_M_0011_N_1011,
	store_rm_disp_rn_l_D_0001_M_0011_N_1011,
	store_rm_disp_rn_l_D_0010_M_0011_N_1011,
	store_rm_disp_rn_l_D_0011_M_0011_N_1011,
	store_rm_disp_rn_l_D_0100_M_0011_N_1011,
	store_rm_disp_rn_l_D_0101_M_0011_N_1011,
	store_rm_disp_rn_l_D_0110_M_0011_N_1011,
	store_rm_disp_rn_l_D_0111_M_0011_N_1011,
	store_rm_disp_rn_l_D_1000_M_0011_N_1011,
	store_rm_disp_rn_l_D_1001_M_0011_N_1011,
	store_rm_disp_rn_l_D_1010_M_0011_N_1011,
	store_rm_disp_rn_l_D_1011_M_0011_N_1011,
	store_rm_disp_rn_l_D_1100_M_0011_N_1011,
	store_rm_disp_rn_l_D_1101_M_0011_N_1011,
	store_rm_disp_rn_l_D_1110_M_0011_N_1011,
	store_rm_disp_rn_l_D_1111_M_0011_N_1011,
	store_rm_disp_rn_l_D_0000_M_0100_N_1011,
	store_rm_disp_rn_l_D_0001_M_0100_N_1011,
	store_rm_disp_rn_l_D_0010_M_0100_N_1011,
	store_rm_disp_rn_l_D_0011_M_0100_N_1011,
	store_rm_disp_rn_l_D_0100_M_0100_N_1011,
	store_rm_disp_rn_l_D_0101_M_0100_N_1011,
	store_rm_disp_rn_l_D_0110_M_0100_N_1011,
	store_rm_disp_rn_l_D_0111_M_0100_N_1011,
	store_rm_disp_rn_l_D_1000_M_0100_N_1011,
	store_rm_disp_rn_l_D_1001_M_0100_N_1011,
	store_rm_disp_rn_l_D_1010_M_0100_N_1011,
	store_rm_disp_rn_l_D_1011_M_0100_N_1011,
	store_rm_disp_rn_l_D_1100_M_0100_N_1011,
	store_rm_disp_rn_l_D_1101_M_0100_N_1011,
	store_rm_disp_rn_l_D_1110_M_0100_N_1011,
	store_rm_disp_rn_l_D_1111_M_0100_N_1011,
	store_rm_disp_rn_l_D_0000_M_0101_N_1011,
	store_rm_disp_rn_l_D_0001_M_0101_N_1011,
	store_rm_disp_rn_l_D_0010_M_0101_N_1011,
	store_rm_disp_rn_l_D_0011_M_0101_N_1011,
	store_rm_disp_rn_l_D_0100_M_0101_N_1011,
	store_rm_disp_rn_l_D_0101_M_0101_N_1011,
	store_rm_disp_rn_l_D_0110_M_0101_N_1011,
	store_rm_disp_rn_l_D_0111_M_0101_N_1011,
	store_rm_disp_rn_l_D_1000_M_0101_N_1011,
	store_rm_disp_rn_l_D_1001_M_0101_N_1011,
	store_rm_disp_rn_l_D_1010_M_0101_N_1011,
	store_rm_disp_rn_l_D_1011_M_0101_N_1011,
	store_rm_disp_rn_l_D_1100_M_0101_N_1011,
	store_rm_disp_rn_l_D_1101_M_0101_N_1011,
	store_rm_disp_rn_l_D_1110_M_0101_N_1011,
	store_rm_disp_rn_l_D_1111_M_0101_N_1011,
	store_rm_disp_rn_l_D_0000_M_0110_N_1011,
	store_rm_disp_rn_l_D_0001_M_0110_N_1011,
	store_rm_disp_rn_l_D_0010_M_0110_N_1011,
	store_rm_disp_rn_l_D_0011_M_0110_N_1011,
	store_rm_disp_rn_l_D_0100_M_0110_N_1011,
	store_rm_disp_rn_l_D_0101_M_0110_N_1011,
	store_rm_disp_rn_l_D_0110_M_0110_N_1011,
	store_rm_disp_rn_l_D_0111_M_0110_N_1011,
	store_rm_disp_rn_l_D_1000_M_0110_N_1011,
	store_rm_disp_rn_l_D_1001_M_0110_N_1011,
	store_rm_disp_rn_l_D_1010_M_0110_N_1011,
	store_rm_disp_rn_l_D_1011_M_0110_N_1011,
	store_rm_disp_rn_l_D_1100_M_0110_N_1011,
	store_rm_disp_rn_l_D_1101_M_0110_N_1011,
	store_rm_disp_rn_l_D_1110_M_0110_N_1011,
	store_rm_disp_rn_l_D_1111_M_0110_N_1011,
	store_rm_disp_rn_l_D_0000_M_0111_N_1011,
	store_rm_disp_rn_l_D_0001_M_0111_N_1011,
	store_rm_disp_rn_l_D_0010_M_0111_N_1011,
	store_rm_disp_rn_l_D_0011_M_0111_N_1011,
	store_rm_disp_rn_l_D_0100_M_0111_N_1011,
	store_rm_disp_rn_l_D_0101_M_0111_N_1011,
	store_rm_disp_rn_l_D_0110_M_0111_N_1011,
	store_rm_disp_rn_l_D_0111_M_0111_N_1011,
	store_rm_disp_rn_l_D_1000_M_0111_N_1011,
	store_rm_disp_rn_l_D_1001_M_0111_N_1011,
	store_rm_disp_rn_l_D_1010_M_0111_N_1011,
	store_rm_disp_rn_l_D_1011_M_0111_N_1011,
	store_rm_disp_rn_l_D_1100_M_0111_N_1011,
	store_rm_disp_rn_l_D_1101_M_0111_N_1011,
	store_rm_disp_rn_l_D_1110_M_0111_N_1011,
	store_rm_disp_rn_l_D_1111_M_0111_N_1011,
	store_rm_disp_rn_l_D_0000_M_1000_N_1011,
	store_rm_disp_rn_l_D_0001_M_1000_N_1011,
	store_rm_disp_rn_l_D_0010_M_1000_N_1011,
	store_rm_disp_rn_l_D_0011_M_1000_N_1011,
	store_rm_disp_rn_l_D_0100_M_1000_N_1011,
	store_rm_disp_rn_l_D_0101_M_1000_N_1011,
	store_rm_disp_rn_l_D_0110_M_1000_N_1011,
	store_rm_disp_rn_l_D_0111_M_1000_N_1011,
	store_rm_disp_rn_l_D_1000_M_1000_N_1011,
	store_rm_disp_rn_l_D_1001_M_1000_N_1011,
	store_rm_disp_rn_l_D_1010_M_1000_N_1011,
	store_rm_disp_rn_l_D_1011_M_1000_N_1011,
	store_rm_disp_rn_l_D_1100_M_1000_N_1011,
	store_rm_disp_rn_l_D_1101_M_1000_N_1011,
	store_rm_disp_rn_l_D_1110_M_1000_N_1011,
	store_rm_disp_rn_l_D_1111_M_1000_N_1011,
	store_rm_disp_rn_l_D_0000_M_1001_N_1011,
	store_rm_disp_rn_l_D_0001_M_1001_N_1011,
	store_rm_disp_rn_l_D_0010_M_1001_N_1011,
	store_rm_disp_rn_l_D_0011_M_1001_N_1011,
	store_rm_disp_rn_l_D_0100_M_1001_N_1011,
	store_rm_disp_rn_l_D_0101_M_1001_N_1011,
	store_rm_disp_rn_l_D_0110_M_1001_N_1011,
	store_rm_disp_rn_l_D_0111_M_1001_N_1011,
	store_rm_disp_rn_l_D_1000_M_1001_N_1011,
	store_rm_disp_rn_l_D_1001_M_1001_N_1011,
	store_rm_disp_rn_l_D_1010_M_1001_N_1011,
	store_rm_disp_rn_l_D_1011_M_1001_N_1011,
	store_rm_disp_rn_l_D_1100_M_1001_N_1011,
	store_rm_disp_rn_l_D_1101_M_1001_N_1011,
	store_rm_disp_rn_l_D_1110_M_1001_N_1011,
	store_rm_disp_rn_l_D_1111_M_1001_N_1011,
	store_rm_disp_rn_l_D_0000_M_1010_N_1011,
	store_rm_disp_rn_l_D_0001_M_1010_N_1011,
	store_rm_disp_rn_l_D_0010_M_1010_N_1011,
	store_rm_disp_rn_l_D_0011_M_1010_N_1011,
	store_rm_disp_rn_l_D_0100_M_1010_N_1011,
	store_rm_disp_rn_l_D_0101_M_1010_N_1011,
	store_rm_disp_rn_l_D_0110_M_1010_N_1011,
	store_rm_disp_rn_l_D_0111_M_1010_N_1011,
	store_rm_disp_rn_l_D_1000_M_1010_N_1011,
	store_rm_disp_rn_l_D_1001_M_1010_N_1011,
	store_rm_disp_rn_l_D_1010_M_1010_N_1011,
	store_rm_disp_rn_l_D_1011_M_1010_N_1011,
	store_rm_disp_rn_l_D_1100_M_1010_N_1011,
	store_rm_disp_rn_l_D_1101_M_1010_N_1011,
	store_rm_disp_rn_l_D_1110_M_1010_N_1011,
	store_rm_disp_rn_l_D_1111_M_1010_N_1011,
	store_rm_disp_rn_l_D_0000_M_1011_N_1011,
	store_rm_disp_rn_l_D_0001_M_1011_N_1011,
	store_rm_disp_rn_l_D_0010_M_1011_N_1011,
	store_rm_disp_rn_l_D_0011_M_1011_N_1011,
	store_rm_disp_rn_l_D_0100_M_1011_N_1011,
	store_rm_disp_rn_l_D_0101_M_1011_N_1011,
	store_rm_disp_rn_l_D_0110_M_1011_N_1011,
	store_rm_disp_rn_l_D_0111_M_1011_N_1011,
	store_rm_disp_rn_l_D_1000_M_1011_N_1011,
	store_rm_disp_rn_l_D_1001_M_1011_N_1011,
	store_rm_disp_rn_l_D_1010_M_1011_N_1011,
	store_rm_disp_rn_l_D_1011_M_1011_N_1011,
	store_rm_disp_rn_l_D_1100_M_1011_N_1011,
	store_rm_disp_rn_l_D_1101_M_1011_N_1011,
	store_rm_disp_rn_l_D_1110_M_1011_N_1011,
	store_rm_disp_rn_l_D_1111_M_1011_N_1011,
	store_rm_disp_rn_l_D_0000_M_1100_N_1011,
	store_rm_disp_rn_l_D_0001_M_1100_N_1011,
	store_rm_disp_rn_l_D_0010_M_1100_N_1011,
	store_rm_disp_rn_l_D_0011_M_1100_N_1011,
	store_rm_disp_rn_l_D_0100_M_1100_N_1011,
	store_rm_disp_rn_l_D_0101_M_1100_N_1011,
	store_rm_disp_rn_l_D_0110_M_1100_N_1011,
	store_rm_disp_rn_l_D_0111_M_1100_N_1011,
	store_rm_disp_rn_l_D_1000_M_1100_N_1011,
	store_rm_disp_rn_l_D_1001_M_1100_N_1011,
	store_rm_disp_rn_l_D_1010_M_1100_N_1011,
	store_rm_disp_rn_l_D_1011_M_1100_N_1011,
	store_rm_disp_rn_l_D_1100_M_1100_N_1011,
	store_rm_disp_rn_l_D_1101_M_1100_N_1011,
	store_rm_disp_rn_l_D_1110_M_1100_N_1011,
	store_rm_disp_rn_l_D_1111_M_1100_N_1011,
	store_rm_disp_rn_l_D_0000_M_1101_N_1011,
	store_rm_disp_rn_l_D_0001_M_1101_N_1011,
	store_rm_disp_rn_l_D_0010_M_1101_N_1011,
	store_rm_disp_rn_l_D_0011_M_1101_N_1011,
	store_rm_disp_rn_l_D_0100_M_1101_N_1011,
	store_rm_disp_rn_l_D_0101_M_1101_N_1011,
	store_rm_disp_rn_l_D_0110_M_1101_N_1011,
	store_rm_disp_rn_l_D_0111_M_1101_N_1011,
	store_rm_disp_rn_l_D_1000_M_1101_N_1011,
	store_rm_disp_rn_l_D_1001_M_1101_N_1011,
	store_rm_disp_rn_l_D_1010_M_1101_N_1011,
	store_rm_disp_rn_l_D_1011_M_1101_N_1011,
	store_rm_disp_rn_l_D_1100_M_1101_N_1011,
	store_rm_disp_rn_l_D_1101_M_1101_N_1011,
	store_rm_disp_rn_l_D_1110_M_1101_N_1011,
	store_rm_disp_rn_l_D_1111_M_1101_N_1011,
	store_rm_disp_rn_l_D_0000_M_1110_N_1011,
	store_rm_disp_rn_l_D_0001_M_1110_N_1011,
	store_rm_disp_rn_l_D_0010_M_1110_N_1011,
	store_rm_disp_rn_l_D_0011_M_1110_N_1011,
	store_rm_disp_rn_l_D_0100_M_1110_N_1011,
	store_rm_disp_rn_l_D_0101_M_1110_N_1011,
	store_rm_disp_rn_l_D_0110_M_1110_N_1011,
	store_rm_disp_rn_l_D_0111_M_1110_N_1011,
	store_rm_disp_rn_l_D_1000_M_1110_N_1011,
	store_rm_disp_rn_l_D_1001_M_1110_N_1011,
	store_rm_disp_rn_l_D_1010_M_1110_N_1011,
	store_rm_disp_rn_l_D_1011_M_1110_N_1011,
	store_rm_disp_rn_l_D_1100_M_1110_N_1011,
	store_rm_disp_rn_l_D_1101_M_1110_N_1011,
	store_rm_disp_rn_l_D_1110_M_1110_N_1011,
	store_rm_disp_rn_l_D_1111_M_1110_N_1011,
	store_rm_disp_rn_l_D_0000_M_1111_N_1011,
	store_rm_disp_rn_l_D_0001_M_1111_N_1011,
	store_rm_disp_rn_l_D_0010_M_1111_N_1011,
	store_rm_disp_rn_l_D_0011_M_1111_N_1011,
	store_rm_disp_rn_l_D_0100_M_1111_N_1011,
	store_rm_disp_rn_l_D_0101_M_1111_N_1011,
	store_rm_disp_rn_l_D_0110_M_1111_N_1011,
	store_rm_disp_rn_l_D_0111_M_1111_N_1011,
	store_rm_disp_rn_l_D_1000_M_1111_N_1011,
	store_rm_disp_rn_l_D_1001_M_1111_N_1011,
	store_rm_disp_rn_l_D_1010_M_1111_N_1011,
	store_rm_disp_rn_l_D_1011_M_1111_N_1011,
	store_rm_disp_rn_l_D_1100_M_1111_N_1011,
	store_rm_disp_rn_l_D_1101_M_1111_N_1011,
	store_rm_disp_rn_l_D_1110_M_1111_N_1011,
	store_rm_disp_rn_l_D_1111_M_1111_N_1011,
	store_rm_disp_rn_l_D_0000_M_0000_N_1100,
	store_rm_disp_rn_l_D_0001_M_0000_N_1100,
	store_rm_disp_rn_l_D_0010_M_0000_N_1100,
	store_rm_disp_rn_l_D_0011_M_0000_N_1100,
	store_rm_disp_rn_l_D_0100_M_0000_N_1100,
	store_rm_disp_rn_l_D_0101_M_0000_N_1100,
	store_rm_disp_rn_l_D_0110_M_0000_N_1100,
	store_rm_disp_rn_l_D_0111_M_0000_N_1100,
	store_rm_disp_rn_l_D_1000_M_0000_N_1100,
	store_rm_disp_rn_l_D_1001_M_0000_N_1100,
	store_rm_disp_rn_l_D_1010_M_0000_N_1100,
	store_rm_disp_rn_l_D_1011_M_0000_N_1100,
	store_rm_disp_rn_l_D_1100_M_0000_N_1100,
	store_rm_disp_rn_l_D_1101_M_0000_N_1100,
	store_rm_disp_rn_l_D_1110_M_0000_N_1100,
	store_rm_disp_rn_l_D_1111_M_0000_N_1100,
	store_rm_disp_rn_l_D_0000_M_0001_N_1100,
	store_rm_disp_rn_l_D_0001_M_0001_N_1100,
	store_rm_disp_rn_l_D_0010_M_0001_N_1100,
	store_rm_disp_rn_l_D_0011_M_0001_N_1100,
	store_rm_disp_rn_l_D_0100_M_0001_N_1100,
	store_rm_disp_rn_l_D_0101_M_0001_N_1100,
	store_rm_disp_rn_l_D_0110_M_0001_N_1100,
	store_rm_disp_rn_l_D_0111_M_0001_N_1100,
	store_rm_disp_rn_l_D_1000_M_0001_N_1100,
	store_rm_disp_rn_l_D_1001_M_0001_N_1100,
	store_rm_disp_rn_l_D_1010_M_0001_N_1100,
	store_rm_disp_rn_l_D_1011_M_0001_N_1100,
	store_rm_disp_rn_l_D_1100_M_0001_N_1100,
	store_rm_disp_rn_l_D_1101_M_0001_N_1100,
	store_rm_disp_rn_l_D_1110_M_0001_N_1100,
	store_rm_disp_rn_l_D_1111_M_0001_N_1100,
	store_rm_disp_rn_l_D_0000_M_0010_N_1100,
	store_rm_disp_rn_l_D_0001_M_0010_N_1100,
	store_rm_disp_rn_l_D_0010_M_0010_N_1100,
	store_rm_disp_rn_l_D_0011_M_0010_N_1100,
	store_rm_disp_rn_l_D_0100_M_0010_N_1100,
	store_rm_disp_rn_l_D_0101_M_0010_N_1100,
	store_rm_disp_rn_l_D_0110_M_0010_N_1100,
	store_rm_disp_rn_l_D_0111_M_0010_N_1100,
	store_rm_disp_rn_l_D_1000_M_0010_N_1100,
	store_rm_disp_rn_l_D_1001_M_0010_N_1100,
	store_rm_disp_rn_l_D_1010_M_0010_N_1100,
	store_rm_disp_rn_l_D_1011_M_0010_N_1100,
	store_rm_disp_rn_l_D_1100_M_0010_N_1100,
	store_rm_disp_rn_l_D_1101_M_0010_N_1100,
	store_rm_disp_rn_l_D_1110_M_0010_N_1100,
	store_rm_disp_rn_l_D_1111_M_0010_N_1100,
	store_rm_disp_rn_l_D_0000_M_0011_N_1100,
	store_rm_disp_rn_l_D_0001_M_0011_N_1100,
	store_rm_disp_rn_l_D_0010_M_0011_N_1100,
	store_rm_disp_rn_l_D_0011_M_0011_N_1100,
	store_rm_disp_rn_l_D_0100_M_0011_N_1100,
	store_rm_disp_rn_l_D_0101_M_0011_N_1100,
	store_rm_disp_rn_l_D_0110_M_0011_N_1100,
	store_rm_disp_rn_l_D_0111_M_0011_N_1100,
	store_rm_disp_rn_l_D_1000_M_0011_N_1100,
	store_rm_disp_rn_l_D_1001_M_0011_N_1100,
	store_rm_disp_rn_l_D_1010_M_0011_N_1100,
	store_rm_disp_rn_l_D_1011_M_0011_N_1100,
	store_rm_disp_rn_l_D_1100_M_0011_N_1100,
	store_rm_disp_rn_l_D_1101_M_0011_N_1100,
	store_rm_disp_rn_l_D_1110_M_0011_N_1100,
	store_rm_disp_rn_l_D_1111_M_0011_N_1100,
	store_rm_disp_rn_l_D_0000_M_0100_N_1100,
	store_rm_disp_rn_l_D_0001_M_0100_N_1100,
	store_rm_disp_rn_l_D_0010_M_0100_N_1100,
	store_rm_disp_rn_l_D_0011_M_0100_N_1100,
	store_rm_disp_rn_l_D_0100_M_0100_N_1100,
	store_rm_disp_rn_l_D_0101_M_0100_N_1100,
	store_rm_disp_rn_l_D_0110_M_0100_N_1100,
	store_rm_disp_rn_l_D_0111_M_0100_N_1100,
	store_rm_disp_rn_l_D_1000_M_0100_N_1100,
	store_rm_disp_rn_l_D_1001_M_0100_N_1100,
	store_rm_disp_rn_l_D_1010_M_0100_N_1100,
	store_rm_disp_rn_l_D_1011_M_0100_N_1100,
	store_rm_disp_rn_l_D_1100_M_0100_N_1100,
	store_rm_disp_rn_l_D_1101_M_0100_N_1100,
	store_rm_disp_rn_l_D_1110_M_0100_N_1100,
	store_rm_disp_rn_l_D_1111_M_0100_N_1100,
	store_rm_disp_rn_l_D_0000_M_0101_N_1100,
	store_rm_disp_rn_l_D_0001_M_0101_N_1100,
	store_rm_disp_rn_l_D_0010_M_0101_N_1100,
	store_rm_disp_rn_l_D_0011_M_0101_N_1100,
	store_rm_disp_rn_l_D_0100_M_0101_N_1100,
	store_rm_disp_rn_l_D_0101_M_0101_N_1100,
	store_rm_disp_rn_l_D_0110_M_0101_N_1100,
	store_rm_disp_rn_l_D_0111_M_0101_N_1100,
	store_rm_disp_rn_l_D_1000_M_0101_N_1100,
	store_rm_disp_rn_l_D_1001_M_0101_N_1100,
	store_rm_disp_rn_l_D_1010_M_0101_N_1100,
	store_rm_disp_rn_l_D_1011_M_0101_N_1100,
	store_rm_disp_rn_l_D_1100_M_0101_N_1100,
	store_rm_disp_rn_l_D_1101_M_0101_N_1100,
	store_rm_disp_rn_l_D_1110_M_0101_N_1100,
	store_rm_disp_rn_l_D_1111_M_0101_N_1100,
	store_rm_disp_rn_l_D_0000_M_0110_N_1100,
	store_rm_disp_rn_l_D_0001_M_0110_N_1100,
	store_rm_disp_rn_l_D_0010_M_0110_N_1100,
	store_rm_disp_rn_l_D_0011_M_0110_N_1100,
	store_rm_disp_rn_l_D_0100_M_0110_N_1100,
	store_rm_disp_rn_l_D_0101_M_0110_N_1100,
	store_rm_disp_rn_l_D_0110_M_0110_N_1100,
	store_rm_disp_rn_l_D_0111_M_0110_N_1100,
	store_rm_disp_rn_l_D_1000_M_0110_N_1100,
	store_rm_disp_rn_l_D_1001_M_0110_N_1100,
	store_rm_disp_rn_l_D_1010_M_0110_N_1100,
	store_rm_disp_rn_l_D_1011_M_0110_N_1100,
	store_rm_disp_rn_l_D_1100_M_0110_N_1100,
	store_rm_disp_rn_l_D_1101_M_0110_N_1100,
	store_rm_disp_rn_l_D_1110_M_0110_N_1100,
	store_rm_disp_rn_l_D_1111_M_0110_N_1100,
	store_rm_disp_rn_l_D_0000_M_0111_N_1100,
	store_rm_disp_rn_l_D_0001_M_0111_N_1100,
	store_rm_disp_rn_l_D_0010_M_0111_N_1100,
	store_rm_disp_rn_l_D_0011_M_0111_N_1100,
	store_rm_disp_rn_l_D_0100_M_0111_N_1100,
	store_rm_disp_rn_l_D_0101_M_0111_N_1100,
	store_rm_disp_rn_l_D_0110_M_0111_N_1100,
	store_rm_disp_rn_l_D_0111_M_0111_N_1100,
	store_rm_disp_rn_l_D_1000_M_0111_N_1100,
	store_rm_disp_rn_l_D_1001_M_0111_N_1100,
	store_rm_disp_rn_l_D_1010_M_0111_N_1100,
	store_rm_disp_rn_l_D_1011_M_0111_N_1100,
	store_rm_disp_rn_l_D_1100_M_0111_N_1100,
	store_rm_disp_rn_l_D_1101_M_0111_N_1100,
	store_rm_disp_rn_l_D_1110_M_0111_N_1100,
	store_rm_disp_rn_l_D_1111_M_0111_N_1100,
	store_rm_disp_rn_l_D_0000_M_1000_N_1100,
	store_rm_disp_rn_l_D_0001_M_1000_N_1100,
	store_rm_disp_rn_l_D_0010_M_1000_N_1100,
	store_rm_disp_rn_l_D_0011_M_1000_N_1100,
	store_rm_disp_rn_l_D_0100_M_1000_N_1100,
	store_rm_disp_rn_l_D_0101_M_1000_N_1100,
	store_rm_disp_rn_l_D_0110_M_1000_N_1100,
	store_rm_disp_rn_l_D_0111_M_1000_N_1100,
	store_rm_disp_rn_l_D_1000_M_1000_N_1100,
	store_rm_disp_rn_l_D_1001_M_1000_N_1100,
	store_rm_disp_rn_l_D_1010_M_1000_N_1100,
	store_rm_disp_rn_l_D_1011_M_1000_N_1100,
	store_rm_disp_rn_l_D_1100_M_1000_N_1100,
	store_rm_disp_rn_l_D_1101_M_1000_N_1100,
	store_rm_disp_rn_l_D_1110_M_1000_N_1100,
	store_rm_disp_rn_l_D_1111_M_1000_N_1100,
	store_rm_disp_rn_l_D_0000_M_1001_N_1100,
	store_rm_disp_rn_l_D_0001_M_1001_N_1100,
	store_rm_disp_rn_l_D_0010_M_1001_N_1100,
	store_rm_disp_rn_l_D_0011_M_1001_N_1100,
	store_rm_disp_rn_l_D_0100_M_1001_N_1100,
	store_rm_disp_rn_l_D_0101_M_1001_N_1100,
	store_rm_disp_rn_l_D_0110_M_1001_N_1100,
	store_rm_disp_rn_l_D_0111_M_1001_N_1100,
	store_rm_disp_rn_l_D_1000_M_1001_N_1100,
	store_rm_disp_rn_l_D_1001_M_1001_N_1100,
	store_rm_disp_rn_l_D_1010_M_1001_N_1100,
	store_rm_disp_rn_l_D_1011_M_1001_N_1100,
	store_rm_disp_rn_l_D_1100_M_1001_N_1100,
	store_rm_disp_rn_l_D_1101_M_1001_N_1100,
	store_rm_disp_rn_l_D_1110_M_1001_N_1100,
	store_rm_disp_rn_l_D_1111_M_1001_N_1100,
	store_rm_disp_rn_l_D_0000_M_1010_N_1100,
	store_rm_disp_rn_l_D_0001_M_1010_N_1100,
	store_rm_disp_rn_l_D_0010_M_1010_N_1100,
	store_rm_disp_rn_l_D_0011_M_1010_N_1100,
	store_rm_disp_rn_l_D_0100_M_1010_N_1100,
	store_rm_disp_rn_l_D_0101_M_1010_N_1100,
	store_rm_disp_rn_l_D_0110_M_1010_N_1100,
	store_rm_disp_rn_l_D_0111_M_1010_N_1100,
	store_rm_disp_rn_l_D_1000_M_1010_N_1100,
	store_rm_disp_rn_l_D_1001_M_1010_N_1100,
	store_rm_disp_rn_l_D_1010_M_1010_N_1100,
	store_rm_disp_rn_l_D_1011_M_1010_N_1100,
	store_rm_disp_rn_l_D_1100_M_1010_N_1100,
	store_rm_disp_rn_l_D_1101_M_1010_N_1100,
	store_rm_disp_rn_l_D_1110_M_1010_N_1100,
	store_rm_disp_rn_l_D_1111_M_1010_N_1100,
	store_rm_disp_rn_l_D_0000_M_1011_N_1100,
	store_rm_disp_rn_l_D_0001_M_1011_N_1100,
	store_rm_disp_rn_l_D_0010_M_1011_N_1100,
	store_rm_disp_rn_l_D_0011_M_1011_N_1100,
	store_rm_disp_rn_l_D_0100_M_1011_N_1100,
	store_rm_disp_rn_l_D_0101_M_1011_N_1100,
	store_rm_disp_rn_l_D_0110_M_1011_N_1100,
	store_rm_disp_rn_l_D_0111_M_1011_N_1100,
	store_rm_disp_rn_l_D_1000_M_1011_N_1100,
	store_rm_disp_rn_l_D_1001_M_1011_N_1100,
	store_rm_disp_rn_l_D_1010_M_1011_N_1100,
	store_rm_disp_rn_l_D_1011_M_1011_N_1100,
	store_rm_disp_rn_l_D_1100_M_1011_N_1100,
	store_rm_disp_rn_l_D_1101_M_1011_N_1100,
	store_rm_disp_rn_l_D_1110_M_1011_N_1100,
	store_rm_disp_rn_l_D_1111_M_1011_N_1100,
	store_rm_disp_rn_l_D_0000_M_1100_N_1100,
	store_rm_disp_rn_l_D_0001_M_1100_N_1100,
	store_rm_disp_rn_l_D_0010_M_1100_N_1100,
	store_rm_disp_rn_l_D_0011_M_1100_N_1100,
	store_rm_disp_rn_l_D_0100_M_1100_N_1100,
	store_rm_disp_rn_l_D_0101_M_1100_N_1100,
	store_rm_disp_rn_l_D_0110_M_1100_N_1100,
	store_rm_disp_rn_l_D_0111_M_1100_N_1100,
	store_rm_disp_rn_l_D_1000_M_1100_N_1100,
	store_rm_disp_rn_l_D_1001_M_1100_N_1100,
	store_rm_disp_rn_l_D_1010_M_1100_N_1100,
	store_rm_disp_rn_l_D_1011_M_1100_N_1100,
	store_rm_disp_rn_l_D_1100_M_1100_N_1100,
	store_rm_disp_rn_l_D_1101_M_1100_N_1100,
	store_rm_disp_rn_l_D_1110_M_1100_N_1100,
	store_rm_disp_rn_l_D_1111_M_1100_N_1100,
	store_rm_disp_rn_l_D_0000_M_1101_N_1100,
	store_rm_disp_rn_l_D_0001_M_1101_N_1100,
	store_rm_disp_rn_l_D_0010_M_1101_N_1100,
	store_rm_disp_rn_l_D_0011_M_1101_N_1100,
	store_rm_disp_rn_l_D_0100_M_1101_N_1100,
	store_rm_disp_rn_l_D_0101_M_1101_N_1100,
	store_rm_disp_rn_l_D_0110_M_1101_N_1100,
	store_rm_disp_rn_l_D_0111_M_1101_N_1100,
	store_rm_disp_rn_l_D_1000_M_1101_N_1100,
	store_rm_disp_rn_l_D_1001_M_1101_N_1100,
	store_rm_disp_rn_l_D_1010_M_1101_N_1100,
	store_rm_disp_rn_l_D_1011_M_1101_N_1100,
	store_rm_disp_rn_l_D_1100_M_1101_N_1100,
	store_rm_disp_rn_l_D_1101_M_1101_N_1100,
	store_rm_disp_rn_l_D_1110_M_1101_N_1100,
	store_rm_disp_rn_l_D_1111_M_1101_N_1100,
	store_rm_disp_rn_l_D_0000_M_1110_N_1100,
	store_rm_disp_rn_l_D_0001_M_1110_N_1100,
	store_rm_disp_rn_l_D_0010_M_1110_N_1100,
	store_rm_disp_rn_l_D_0011_M_1110_N_1100,
	store_rm_disp_rn_l_D_0100_M_1110_N_1100,
	store_rm_disp_rn_l_D_0101_M_1110_N_1100,
	store_rm_disp_rn_l_D_0110_M_1110_N_1100,
	store_rm_disp_rn_l_D_0111_M_1110_N_1100,
	store_rm_disp_rn_l_D_1000_M_1110_N_1100,
	store_rm_disp_rn_l_D_1001_M_1110_N_1100,
	store_rm_disp_rn_l_D_1010_M_1110_N_1100,
	store_rm_disp_rn_l_D_1011_M_1110_N_1100,
	store_rm_disp_rn_l_D_1100_M_1110_N_1100,
	store_rm_disp_rn_l_D_1101_M_1110_N_1100,
	store_rm_disp_rn_l_D_1110_M_1110_N_1100,
	store_rm_disp_rn_l_D_1111_M_1110_N_1100,
	store_rm_disp_rn_l_D_0000_M_1111_N_1100,
	store_rm_disp_rn_l_D_0001_M_1111_N_1100,
	store_rm_disp_rn_l_D_0010_M_1111_N_1100,
	store_rm_disp_rn_l_D_0011_M_1111_N_1100,
	store_rm_disp_rn_l_D_0100_M_1111_N_1100,
	store_rm_disp_rn_l_D_0101_M_1111_N_1100,
	store_rm_disp_rn_l_D_0110_M_1111_N_1100,
	store_rm_disp_rn_l_D_0111_M_1111_N_1100,
	store_rm_disp_rn_l_D_1000_M_1111_N_1100,
	store_rm_disp_rn_l_D_1001_M_1111_N_1100,
	store_rm_disp_rn_l_D_1010_M_1111_N_1100,
	store_rm_disp_rn_l_D_1011_M_1111_N_1100,
	store_rm_disp_rn_l_D_1100_M_1111_N_1100,
	store_rm_disp_rn_l_D_1101_M_1111_N_1100,
	store_rm_disp_rn_l_D_1110_M_1111_N_1100,
	store_rm_disp_rn_l_D_1111_M_1111_N_1100,
	store_rm_disp_rn_l_D_0000_M_0000_N_1101,
	store_rm_disp_rn_l_D_0001_M_0000_N_1101,
	store_rm_disp_rn_l_D_0010_M_0000_N_1101,
	store_rm_disp_rn_l_D_0011_M_0000_N_1101,
	store_rm_disp_rn_l_D_0100_M_0000_N_1101,
	store_rm_disp_rn_l_D_0101_M_0000_N_1101,
	store_rm_disp_rn_l_D_0110_M_0000_N_1101,
	store_rm_disp_rn_l_D_0111_M_0000_N_1101,
	store_rm_disp_rn_l_D_1000_M_0000_N_1101,
	store_rm_disp_rn_l_D_1001_M_0000_N_1101,
	store_rm_disp_rn_l_D_1010_M_0000_N_1101,
	store_rm_disp_rn_l_D_1011_M_0000_N_1101,
	store_rm_disp_rn_l_D_1100_M_0000_N_1101,
	store_rm_disp_rn_l_D_1101_M_0000_N_1101,
	store_rm_disp_rn_l_D_1110_M_0000_N_1101,
	store_rm_disp_rn_l_D_1111_M_0000_N_1101,
	store_rm_disp_rn_l_D_0000_M_0001_N_1101,
	store_rm_disp_rn_l_D_0001_M_0001_N_1101,
	store_rm_disp_rn_l_D_0010_M_0001_N_1101,
	store_rm_disp_rn_l_D_0011_M_0001_N_1101,
	store_rm_disp_rn_l_D_0100_M_0001_N_1101,
	store_rm_disp_rn_l_D_0101_M_0001_N_1101,
	store_rm_disp_rn_l_D_0110_M_0001_N_1101,
	store_rm_disp_rn_l_D_0111_M_0001_N_1101,
	store_rm_disp_rn_l_D_1000_M_0001_N_1101,
	store_rm_disp_rn_l_D_1001_M_0001_N_1101,
	store_rm_disp_rn_l_D_1010_M_0001_N_1101,
	store_rm_disp_rn_l_D_1011_M_0001_N_1101,
	store_rm_disp_rn_l_D_1100_M_0001_N_1101,
	store_rm_disp_rn_l_D_1101_M_0001_N_1101,
	store_rm_disp_rn_l_D_1110_M_0001_N_1101,
	store_rm_disp_rn_l_D_1111_M_0001_N_1101,
	store_rm_disp_rn_l_D_0000_M_0010_N_1101,
	store_rm_disp_rn_l_D_0001_M_0010_N_1101,
	store_rm_disp_rn_l_D_0010_M_0010_N_1101,
	store_rm_disp_rn_l_D_0011_M_0010_N_1101,
	store_rm_disp_rn_l_D_0100_M_0010_N_1101,
	store_rm_disp_rn_l_D_0101_M_0010_N_1101,
	store_rm_disp_rn_l_D_0110_M_0010_N_1101,
	store_rm_disp_rn_l_D_0111_M_0010_N_1101,
	store_rm_disp_rn_l_D_1000_M_0010_N_1101,
	store_rm_disp_rn_l_D_1001_M_0010_N_1101,
	store_rm_disp_rn_l_D_1010_M_0010_N_1101,
	store_rm_disp_rn_l_D_1011_M_0010_N_1101,
	store_rm_disp_rn_l_D_1100_M_0010_N_1101,
	store_rm_disp_rn_l_D_1101_M_0010_N_1101,
	store_rm_disp_rn_l_D_1110_M_0010_N_1101,
	store_rm_disp_rn_l_D_1111_M_0010_N_1101,
	store_rm_disp_rn_l_D_0000_M_0011_N_1101,
	store_rm_disp_rn_l_D_0001_M_0011_N_1101,
	store_rm_disp_rn_l_D_0010_M_0011_N_1101,
	store_rm_disp_rn_l_D_0011_M_0011_N_1101,
	store_rm_disp_rn_l_D_0100_M_0011_N_1101,
	store_rm_disp_rn_l_D_0101_M_0011_N_1101,
	store_rm_disp_rn_l_D_0110_M_0011_N_1101,
	store_rm_disp_rn_l_D_0111_M_0011_N_1101,
	store_rm_disp_rn_l_D_1000_M_0011_N_1101,
	store_rm_disp_rn_l_D_1001_M_0011_N_1101,
	store_rm_disp_rn_l_D_1010_M_0011_N_1101,
	store_rm_disp_rn_l_D_1011_M_0011_N_1101,
	store_rm_disp_rn_l_D_1100_M_0011_N_1101,
	store_rm_disp_rn_l_D_1101_M_0011_N_1101,
	store_rm_disp_rn_l_D_1110_M_0011_N_1101,
	store_rm_disp_rn_l_D_1111_M_0011_N_1101,
	store_rm_disp_rn_l_D_0000_M_0100_N_1101,
	store_rm_disp_rn_l_D_0001_M_0100_N_1101,
	store_rm_disp_rn_l_D_0010_M_0100_N_1101,
	store_rm_disp_rn_l_D_0011_M_0100_N_1101,
	store_rm_disp_rn_l_D_0100_M_0100_N_1101,
	store_rm_disp_rn_l_D_0101_M_0100_N_1101,
	store_rm_disp_rn_l_D_0110_M_0100_N_1101,
	store_rm_disp_rn_l_D_0111_M_0100_N_1101,
	store_rm_disp_rn_l_D_1000_M_0100_N_1101,
	store_rm_disp_rn_l_D_1001_M_0100_N_1101,
	store_rm_disp_rn_l_D_1010_M_0100_N_1101,
	store_rm_disp_rn_l_D_1011_M_0100_N_1101,
	store_rm_disp_rn_l_D_1100_M_0100_N_1101,
	store_rm_disp_rn_l_D_1101_M_0100_N_1101,
	store_rm_disp_rn_l_D_1110_M_0100_N_1101,
	store_rm_disp_rn_l_D_1111_M_0100_N_1101,
	store_rm_disp_rn_l_D_0000_M_0101_N_1101,
	store_rm_disp_rn_l_D_0001_M_0101_N_1101,
	store_rm_disp_rn_l_D_0010_M_0101_N_1101,
	store_rm_disp_rn_l_D_0011_M_0101_N_1101,
	store_rm_disp_rn_l_D_0100_M_0101_N_1101,
	store_rm_disp_rn_l_D_0101_M_0101_N_1101,
	store_rm_disp_rn_l_D_0110_M_0101_N_1101,
	store_rm_disp_rn_l_D_0111_M_0101_N_1101,
	store_rm_disp_rn_l_D_1000_M_0101_N_1101,
	store_rm_disp_rn_l_D_1001_M_0101_N_1101,
	store_rm_disp_rn_l_D_1010_M_0101_N_1101,
	store_rm_disp_rn_l_D_1011_M_0101_N_1101,
	store_rm_disp_rn_l_D_1100_M_0101_N_1101,
	store_rm_disp_rn_l_D_1101_M_0101_N_1101,
	store_rm_disp_rn_l_D_1110_M_0101_N_1101,
	store_rm_disp_rn_l_D_1111_M_0101_N_1101,
	store_rm_disp_rn_l_D_0000_M_0110_N_1101,
	store_rm_disp_rn_l_D_0001_M_0110_N_1101,
	store_rm_disp_rn_l_D_0010_M_0110_N_1101,
	store_rm_disp_rn_l_D_0011_M_0110_N_1101,
	store_rm_disp_rn_l_D_0100_M_0110_N_1101,
	store_rm_disp_rn_l_D_0101_M_0110_N_1101,
	store_rm_disp_rn_l_D_0110_M_0110_N_1101,
	store_rm_disp_rn_l_D_0111_M_0110_N_1101,
	store_rm_disp_rn_l_D_1000_M_0110_N_1101,
	store_rm_disp_rn_l_D_1001_M_0110_N_1101,
	store_rm_disp_rn_l_D_1010_M_0110_N_1101,
	store_rm_disp_rn_l_D_1011_M_0110_N_1101,
	store_rm_disp_rn_l_D_1100_M_0110_N_1101,
	store_rm_disp_rn_l_D_1101_M_0110_N_1101,
	store_rm_disp_rn_l_D_1110_M_0110_N_1101,
	store_rm_disp_rn_l_D_1111_M_0110_N_1101,
	store_rm_disp_rn_l_D_0000_M_0111_N_1101,
	store_rm_disp_rn_l_D_0001_M_0111_N_1101,
	store_rm_disp_rn_l_D_0010_M_0111_N_1101,
	store_rm_disp_rn_l_D_0011_M_0111_N_1101,
	store_rm_disp_rn_l_D_0100_M_0111_N_1101,
	store_rm_disp_rn_l_D_0101_M_0111_N_1101,
	store_rm_disp_rn_l_D_0110_M_0111_N_1101,
	store_rm_disp_rn_l_D_0111_M_0111_N_1101,
	store_rm_disp_rn_l_D_1000_M_0111_N_1101,
	store_rm_disp_rn_l_D_1001_M_0111_N_1101,
	store_rm_disp_rn_l_D_1010_M_0111_N_1101,
	store_rm_disp_rn_l_D_1011_M_0111_N_1101,
	store_rm_disp_rn_l_D_1100_M_0111_N_1101,
	store_rm_disp_rn_l_D_1101_M_0111_N_1101,
	store_rm_disp_rn_l_D_1110_M_0111_N_1101,
	store_rm_disp_rn_l_D_1111_M_0111_N_1101,
	store_rm_disp_rn_l_D_0000_M_1000_N_1101,
	store_rm_disp_rn_l_D_0001_M_1000_N_1101,
	store_rm_disp_rn_l_D_0010_M_1000_N_1101,
	store_rm_disp_rn_l_D_0011_M_1000_N_1101,
	store_rm_disp_rn_l_D_0100_M_1000_N_1101,
	store_rm_disp_rn_l_D_0101_M_1000_N_1101,
	store_rm_disp_rn_l_D_0110_M_1000_N_1101,
	store_rm_disp_rn_l_D_0111_M_1000_N_1101,
	store_rm_disp_rn_l_D_1000_M_1000_N_1101,
	store_rm_disp_rn_l_D_1001_M_1000_N_1101,
	store_rm_disp_rn_l_D_1010_M_1000_N_1101,
	store_rm_disp_rn_l_D_1011_M_1000_N_1101,
	store_rm_disp_rn_l_D_1100_M_1000_N_1101,
	store_rm_disp_rn_l_D_1101_M_1000_N_1101,
	store_rm_disp_rn_l_D_1110_M_1000_N_1101,
	store_rm_disp_rn_l_D_1111_M_1000_N_1101,
	store_rm_disp_rn_l_D_0000_M_1001_N_1101,
	store_rm_disp_rn_l_D_0001_M_1001_N_1101,
	store_rm_disp_rn_l_D_0010_M_1001_N_1101,
	store_rm_disp_rn_l_D_0011_M_1001_N_1101,
	store_rm_disp_rn_l_D_0100_M_1001_N_1101,
	store_rm_disp_rn_l_D_0101_M_1001_N_1101,
	store_rm_disp_rn_l_D_0110_M_1001_N_1101,
	store_rm_disp_rn_l_D_0111_M_1001_N_1101,
	store_rm_disp_rn_l_D_1000_M_1001_N_1101,
	store_rm_disp_rn_l_D_1001_M_1001_N_1101,
	store_rm_disp_rn_l_D_1010_M_1001_N_1101,
	store_rm_disp_rn_l_D_1011_M_1001_N_1101,
	store_rm_disp_rn_l_D_1100_M_1001_N_1101,
	store_rm_disp_rn_l_D_1101_M_1001_N_1101,
	store_rm_disp_rn_l_D_1110_M_1001_N_1101,
	store_rm_disp_rn_l_D_1111_M_1001_N_1101,
	store_rm_disp_rn_l_D_0000_M_1010_N_1101,
	store_rm_disp_rn_l_D_0001_M_1010_N_1101,
	store_rm_disp_rn_l_D_0010_M_1010_N_1101,
	store_rm_disp_rn_l_D_0011_M_1010_N_1101,
	store_rm_disp_rn_l_D_0100_M_1010_N_1101,
	store_rm_disp_rn_l_D_0101_M_1010_N_1101,
	store_rm_disp_rn_l_D_0110_M_1010_N_1101,
	store_rm_disp_rn_l_D_0111_M_1010_N_1101,
	store_rm_disp_rn_l_D_1000_M_1010_N_1101,
	store_rm_disp_rn_l_D_1001_M_1010_N_1101,
	store_rm_disp_rn_l_D_1010_M_1010_N_1101,
	store_rm_disp_rn_l_D_1011_M_1010_N_1101,
	store_rm_disp_rn_l_D_1100_M_1010_N_1101,
	store_rm_disp_rn_l_D_1101_M_1010_N_1101,
	store_rm_disp_rn_l_D_1110_M_1010_N_1101,
	store_rm_disp_rn_l_D_1111_M_1010_N_1101,
	store_rm_disp_rn_l_D_0000_M_1011_N_1101,
	store_rm_disp_rn_l_D_0001_M_1011_N_1101,
	store_rm_disp_rn_l_D_0010_M_1011_N_1101,
	store_rm_disp_rn_l_D_0011_M_1011_N_1101,
	store_rm_disp_rn_l_D_0100_M_1011_N_1101,
	store_rm_disp_rn_l_D_0101_M_1011_N_1101,
	store_rm_disp_rn_l_D_0110_M_1011_N_1101,
	store_rm_disp_rn_l_D_0111_M_1011_N_1101,
	store_rm_disp_rn_l_D_1000_M_1011_N_1101,
	store_rm_disp_rn_l_D_1001_M_1011_N_1101,
	store_rm_disp_rn_l_D_1010_M_1011_N_1101,
	store_rm_disp_rn_l_D_1011_M_1011_N_1101,
	store_rm_disp_rn_l_D_1100_M_1011_N_1101,
	store_rm_disp_rn_l_D_1101_M_1011_N_1101,
	store_rm_disp_rn_l_D_1110_M_1011_N_1101,
	store_rm_disp_rn_l_D_1111_M_1011_N_1101,
	store_rm_disp_rn_l_D_0000_M_1100_N_1101,
	store_rm_disp_rn_l_D_0001_M_1100_N_1101,
	store_rm_disp_rn_l_D_0010_M_1100_N_1101,
	store_rm_disp_rn_l_D_0011_M_1100_N_1101,
	store_rm_disp_rn_l_D_0100_M_1100_N_1101,
	store_rm_disp_rn_l_D_0101_M_1100_N_1101,
	store_rm_disp_rn_l_D_0110_M_1100_N_1101,
	store_rm_disp_rn_l_D_0111_M_1100_N_1101,
	store_rm_disp_rn_l_D_1000_M_1100_N_1101,
	store_rm_disp_rn_l_D_1001_M_1100_N_1101,
	store_rm_disp_rn_l_D_1010_M_1100_N_1101,
	store_rm_disp_rn_l_D_1011_M_1100_N_1101,
	store_rm_disp_rn_l_D_1100_M_1100_N_1101,
	store_rm_disp_rn_l_D_1101_M_1100_N_1101,
	store_rm_disp_rn_l_D_1110_M_1100_N_1101,
	store_rm_disp_rn_l_D_1111_M_1100_N_1101,
	store_rm_disp_rn_l_D_0000_M_1101_N_1101,
	store_rm_disp_rn_l_D_0001_M_1101_N_1101,
	store_rm_disp_rn_l_D_0010_M_1101_N_1101,
	store_rm_disp_rn_l_D_0011_M_1101_N_1101,
	store_rm_disp_rn_l_D_0100_M_1101_N_1101,
	store_rm_disp_rn_l_D_0101_M_1101_N_1101,
	store_rm_disp_rn_l_D_0110_M_1101_N_1101,
	store_rm_disp_rn_l_D_0111_M_1101_N_1101,
	store_rm_disp_rn_l_D_1000_M_1101_N_1101,
	store_rm_disp_rn_l_D_1001_M_1101_N_1101,
	store_rm_disp_rn_l_D_1010_M_1101_N_1101,
	store_rm_disp_rn_l_D_1011_M_1101_N_1101,
	store_rm_disp_rn_l_D_1100_M_1101_N_1101,
	store_rm_disp_rn_l_D_1101_M_1101_N_1101,
	store_rm_disp_rn_l_D_1110_M_1101_N_1101,
	store_rm_disp_rn_l_D_1111_M_1101_N_1101,
	store_rm_disp_rn_l_D_0000_M_1110_N_1101,
	store_rm_disp_rn_l_D_0001_M_1110_N_1101,
	store_rm_disp_rn_l_D_0010_M_1110_N_1101,
	store_rm_disp_rn_l_D_0011_M_1110_N_1101,
	store_rm_disp_rn_l_D_0100_M_1110_N_1101,
	store_rm_disp_rn_l_D_0101_M_1110_N_1101,
	store_rm_disp_rn_l_D_0110_M_1110_N_1101,
	store_rm_disp_rn_l_D_0111_M_1110_N_1101,
	store_rm_disp_rn_l_D_1000_M_1110_N_1101,
	store_rm_disp_rn_l_D_1001_M_1110_N_1101,
	store_rm_disp_rn_l_D_1010_M_1110_N_1101,
	store_rm_disp_rn_l_D_1011_M_1110_N_1101,
	store_rm_disp_rn_l_D_1100_M_1110_N_1101,
	store_rm_disp_rn_l_D_1101_M_1110_N_1101,
	store_rm_disp_rn_l_D_1110_M_1110_N_1101,
	store_rm_disp_rn_l_D_1111_M_1110_N_1101,
	store_rm_disp_rn_l_D_0000_M_1111_N_1101,
	store_rm_disp_rn_l_D_0001_M_1111_N_1101,
	store_rm_disp_rn_l_D_0010_M_1111_N_1101,
	store_rm_disp_rn_l_D_0011_M_1111_N_1101,
	store_rm_disp_rn_l_D_0100_M_1111_N_1101,
	store_rm_disp_rn_l_D_0101_M_1111_N_1101,
	store_rm_disp_rn_l_D_0110_M_1111_N_1101,
	store_rm_disp_rn_l_D_0111_M_1111_N_1101,
	store_rm_disp_rn_l_D_1000_M_1111_N_1101,
	store_rm_disp_rn_l_D_1001_M_1111_N_1101,
	store_rm_disp_rn_l_D_1010_M_1111_N_1101,
	store_rm_disp_rn_l_D_1011_M_1111_N_1101,
	store_rm_disp_rn_l_D_1100_M_1111_N_1101,
	store_rm_disp_rn_l_D_1101_M_1111_N_1101,
	store_rm_disp_rn_l_D_1110_M_1111_N_1101,
	store_rm_disp_rn_l_D_1111_M_1111_N_1101,
	store_rm_disp_rn_l_D_0000_M_0000_N_1110,
	store_rm_disp_rn_l_D_0001_M_0000_N_1110,
	store_rm_disp_rn_l_D_0010_M_0000_N_1110,
	store_rm_disp_rn_l_D_0011_M_0000_N_1110,
	store_rm_disp_rn_l_D_0100_M_0000_N_1110,
	store_rm_disp_rn_l_D_0101_M_0000_N_1110,
	store_rm_disp_rn_l_D_0110_M_0000_N_1110,
	store_rm_disp_rn_l_D_0111_M_0000_N_1110,
	store_rm_disp_rn_l_D_1000_M_0000_N_1110,
	store_rm_disp_rn_l_D_1001_M_0000_N_1110,
	store_rm_disp_rn_l_D_1010_M_0000_N_1110,
	store_rm_disp_rn_l_D_1011_M_0000_N_1110,
	store_rm_disp_rn_l_D_1100_M_0000_N_1110,
	store_rm_disp_rn_l_D_1101_M_0000_N_1110,
	store_rm_disp_rn_l_D_1110_M_0000_N_1110,
	store_rm_disp_rn_l_D_1111_M_0000_N_1110,
	store_rm_disp_rn_l_D_0000_M_0001_N_1110,
	store_rm_disp_rn_l_D_0001_M_0001_N_1110,
	store_rm_disp_rn_l_D_0010_M_0001_N_1110,
	store_rm_disp_rn_l_D_0011_M_0001_N_1110,
	store_rm_disp_rn_l_D_0100_M_0001_N_1110,
	store_rm_disp_rn_l_D_0101_M_0001_N_1110,
	store_rm_disp_rn_l_D_0110_M_0001_N_1110,
	store_rm_disp_rn_l_D_0111_M_0001_N_1110,
	store_rm_disp_rn_l_D_1000_M_0001_N_1110,
	store_rm_disp_rn_l_D_1001_M_0001_N_1110,
	store_rm_disp_rn_l_D_1010_M_0001_N_1110,
	store_rm_disp_rn_l_D_1011_M_0001_N_1110,
	store_rm_disp_rn_l_D_1100_M_0001_N_1110,
	store_rm_disp_rn_l_D_1101_M_0001_N_1110,
	store_rm_disp_rn_l_D_1110_M_0001_N_1110,
	store_rm_disp_rn_l_D_1111_M_0001_N_1110,
	store_rm_disp_rn_l_D_0000_M_0010_N_1110,
	store_rm_disp_rn_l_D_0001_M_0010_N_1110,
	store_rm_disp_rn_l_D_0010_M_0010_N_1110,
	store_rm_disp_rn_l_D_0011_M_0010_N_1110,
	store_rm_disp_rn_l_D_0100_M_0010_N_1110,
	store_rm_disp_rn_l_D_0101_M_0010_N_1110,
	store_rm_disp_rn_l_D_0110_M_0010_N_1110,
	store_rm_disp_rn_l_D_0111_M_0010_N_1110,
	store_rm_disp_rn_l_D_1000_M_0010_N_1110,
	store_rm_disp_rn_l_D_1001_M_0010_N_1110,
	store_rm_disp_rn_l_D_1010_M_0010_N_1110,
	store_rm_disp_rn_l_D_1011_M_0010_N_1110,
	store_rm_disp_rn_l_D_1100_M_0010_N_1110,
	store_rm_disp_rn_l_D_1101_M_0010_N_1110,
	store_rm_disp_rn_l_D_1110_M_0010_N_1110,
	store_rm_disp_rn_l_D_1111_M_0010_N_1110,
	store_rm_disp_rn_l_D_0000_M_0011_N_1110,
	store_rm_disp_rn_l_D_0001_M_0011_N_1110,
	store_rm_disp_rn_l_D_0010_M_0011_N_1110,
	store_rm_disp_rn_l_D_0011_M_0011_N_1110,
	store_rm_disp_rn_l_D_0100_M_0011_N_1110,
	store_rm_disp_rn_l_D_0101_M_0011_N_1110,
	store_rm_disp_rn_l_D_0110_M_0011_N_1110,
	store_rm_disp_rn_l_D_0111_M_0011_N_1110,
	store_rm_disp_rn_l_D_1000_M_0011_N_1110,
	store_rm_disp_rn_l_D_1001_M_0011_N_1110,
	store_rm_disp_rn_l_D_1010_M_0011_N_1110,
	store_rm_disp_rn_l_D_1011_M_0011_N_1110,
	store_rm_disp_rn_l_D_1100_M_0011_N_1110,
	store_rm_disp_rn_l_D_1101_M_0011_N_1110,
	store_rm_disp_rn_l_D_1110_M_0011_N_1110,
	store_rm_disp_rn_l_D_1111_M_0011_N_1110,
	store_rm_disp_rn_l_D_0000_M_0100_N_1110,
	store_rm_disp_rn_l_D_0001_M_0100_N_1110,
	store_rm_disp_rn_l_D_0010_M_0100_N_1110,
	store_rm_disp_rn_l_D_0011_M_0100_N_1110,
	store_rm_disp_rn_l_D_0100_M_0100_N_1110,
	store_rm_disp_rn_l_D_0101_M_0100_N_1110,
	store_rm_disp_rn_l_D_0110_M_0100_N_1110,
	store_rm_disp_rn_l_D_0111_M_0100_N_1110,
	store_rm_disp_rn_l_D_1000_M_0100_N_1110,
	store_rm_disp_rn_l_D_1001_M_0100_N_1110,
	store_rm_disp_rn_l_D_1010_M_0100_N_1110,
	store_rm_disp_rn_l_D_1011_M_0100_N_1110,
	store_rm_disp_rn_l_D_1100_M_0100_N_1110,
	store_rm_disp_rn_l_D_1101_M_0100_N_1110,
	store_rm_disp_rn_l_D_1110_M_0100_N_1110,
	store_rm_disp_rn_l_D_1111_M_0100_N_1110,
	store_rm_disp_rn_l_D_0000_M_0101_N_1110,
	store_rm_disp_rn_l_D_0001_M_0101_N_1110,
	store_rm_disp_rn_l_D_0010_M_0101_N_1110,
	store_rm_disp_rn_l_D_0011_M_0101_N_1110,
	store_rm_disp_rn_l_D_0100_M_0101_N_1110,
	store_rm_disp_rn_l_D_0101_M_0101_N_1110,
	store_rm_disp_rn_l_D_0110_M_0101_N_1110,
	store_rm_disp_rn_l_D_0111_M_0101_N_1110,
	store_rm_disp_rn_l_D_1000_M_0101_N_1110,
	store_rm_disp_rn_l_D_1001_M_0101_N_1110,
	store_rm_disp_rn_l_D_1010_M_0101_N_1110,
	store_rm_disp_rn_l_D_1011_M_0101_N_1110,
	store_rm_disp_rn_l_D_1100_M_0101_N_1110,
	store_rm_disp_rn_l_D_1101_M_0101_N_1110,
	store_rm_disp_rn_l_D_1110_M_0101_N_1110,
	store_rm_disp_rn_l_D_1111_M_0101_N_1110,
	store_rm_disp_rn_l_D_0000_M_0110_N_1110,
	store_rm_disp_rn_l_D_0001_M_0110_N_1110,
	store_rm_disp_rn_l_D_0010_M_0110_N_1110,
	store_rm_disp_rn_l_D_0011_M_0110_N_1110,
	store_rm_disp_rn_l_D_0100_M_0110_N_1110,
	store_rm_disp_rn_l_D_0101_M_0110_N_1110,
	store_rm_disp_rn_l_D_0110_M_0110_N_1110,
	store_rm_disp_rn_l_D_0111_M_0110_N_1110,
	store_rm_disp_rn_l_D_1000_M_0110_N_1110,
	store_rm_disp_rn_l_D_1001_M_0110_N_1110,
	store_rm_disp_rn_l_D_1010_M_0110_N_1110,
	store_rm_disp_rn_l_D_1011_M_0110_N_1110,
	store_rm_disp_rn_l_D_1100_M_0110_N_1110,
	store_rm_disp_rn_l_D_1101_M_0110_N_1110,
	store_rm_disp_rn_l_D_1110_M_0110_N_1110,
	store_rm_disp_rn_l_D_1111_M_0110_N_1110,
	store_rm_disp_rn_l_D_0000_M_0111_N_1110,
	store_rm_disp_rn_l_D_0001_M_0111_N_1110,
	store_rm_disp_rn_l_D_0010_M_0111_N_1110,
	store_rm_disp_rn_l_D_0011_M_0111_N_1110,
	store_rm_disp_rn_l_D_0100_M_0111_N_1110,
	store_rm_disp_rn_l_D_0101_M_0111_N_1110,
	store_rm_disp_rn_l_D_0110_M_0111_N_1110,
	store_rm_disp_rn_l_D_0111_M_0111_N_1110,
	store_rm_disp_rn_l_D_1000_M_0111_N_1110,
	store_rm_disp_rn_l_D_1001_M_0111_N_1110,
	store_rm_disp_rn_l_D_1010_M_0111_N_1110,
	store_rm_disp_rn_l_D_1011_M_0111_N_1110,
	store_rm_disp_rn_l_D_1100_M_0111_N_1110,
	store_rm_disp_rn_l_D_1101_M_0111_N_1110,
	store_rm_disp_rn_l_D_1110_M_0111_N_1110,
	store_rm_disp_rn_l_D_1111_M_0111_N_1110,
	store_rm_disp_rn_l_D_0000_M_1000_N_1110,
	store_rm_disp_rn_l_D_0001_M_1000_N_1110,
	store_rm_disp_rn_l_D_0010_M_1000_N_1110,
	store_rm_disp_rn_l_D_0011_M_1000_N_1110,
	store_rm_disp_rn_l_D_0100_M_1000_N_1110,
	store_rm_disp_rn_l_D_0101_M_1000_N_1110,
	store_rm_disp_rn_l_D_0110_M_1000_N_1110,
	store_rm_disp_rn_l_D_0111_M_1000_N_1110,
	store_rm_disp_rn_l_D_1000_M_1000_N_1110,
	store_rm_disp_rn_l_D_1001_M_1000_N_1110,
	store_rm_disp_rn_l_D_1010_M_1000_N_1110,
	store_rm_disp_rn_l_D_1011_M_1000_N_1110,
	store_rm_disp_rn_l_D_1100_M_1000_N_1110,
	store_rm_disp_rn_l_D_1101_M_1000_N_1110,
	store_rm_disp_rn_l_D_1110_M_1000_N_1110,
	store_rm_disp_rn_l_D_1111_M_1000_N_1110,
	store_rm_disp_rn_l_D_0000_M_1001_N_1110,
	store_rm_disp_rn_l_D_0001_M_1001_N_1110,
	store_rm_disp_rn_l_D_0010_M_1001_N_1110,
	store_rm_disp_rn_l_D_0011_M_1001_N_1110,
	store_rm_disp_rn_l_D_0100_M_1001_N_1110,
	store_rm_disp_rn_l_D_0101_M_1001_N_1110,
	store_rm_disp_rn_l_D_0110_M_1001_N_1110,
	store_rm_disp_rn_l_D_0111_M_1001_N_1110,
	store_rm_disp_rn_l_D_1000_M_1001_N_1110,
	store_rm_disp_rn_l_D_1001_M_1001_N_1110,
	store_rm_disp_rn_l_D_1010_M_1001_N_1110,
	store_rm_disp_rn_l_D_1011_M_1001_N_1110,
	store_rm_disp_rn_l_D_1100_M_1001_N_1110,
	store_rm_disp_rn_l_D_1101_M_1001_N_1110,
	store_rm_disp_rn_l_D_1110_M_1001_N_1110,
	store_rm_disp_rn_l_D_1111_M_1001_N_1110,
	store_rm_disp_rn_l_D_0000_M_1010_N_1110,
	store_rm_disp_rn_l_D_0001_M_1010_N_1110,
	store_rm_disp_rn_l_D_0010_M_1010_N_1110,
	store_rm_disp_rn_l_D_0011_M_1010_N_1110,
	store_rm_disp_rn_l_D_0100_M_1010_N_1110,
	store_rm_disp_rn_l_D_0101_M_1010_N_1110,
	store_rm_disp_rn_l_D_0110_M_1010_N_1110,
	store_rm_disp_rn_l_D_0111_M_1010_N_1110,
	store_rm_disp_rn_l_D_1000_M_1010_N_1110,
	store_rm_disp_rn_l_D_1001_M_1010_N_1110,
	store_rm_disp_rn_l_D_1010_M_1010_N_1110,
	store_rm_disp_rn_l_D_1011_M_1010_N_1110,
	store_rm_disp_rn_l_D_1100_M_1010_N_1110,
	store_rm_disp_rn_l_D_1101_M_1010_N_1110,
	store_rm_disp_rn_l_D_1110_M_1010_N_1110,
	store_rm_disp_rn_l_D_1111_M_1010_N_1110,
	store_rm_disp_rn_l_D_0000_M_1011_N_1110,
	store_rm_disp_rn_l_D_0001_M_1011_N_1110,
	store_rm_disp_rn_l_D_0010_M_1011_N_1110,
	store_rm_disp_rn_l_D_0011_M_1011_N_1110,
	store_rm_disp_rn_l_D_0100_M_1011_N_1110,
	store_rm_disp_rn_l_D_0101_M_1011_N_1110,
	store_rm_disp_rn_l_D_0110_M_1011_N_1110,
	store_rm_disp_rn_l_D_0111_M_1011_N_1110,
	store_rm_disp_rn_l_D_1000_M_1011_N_1110,
	store_rm_disp_rn_l_D_1001_M_1011_N_1110,
	store_rm_disp_rn_l_D_1010_M_1011_N_1110,
	store_rm_disp_rn_l_D_1011_M_1011_N_1110,
	store_rm_disp_rn_l_D_1100_M_1011_N_1110,
	store_rm_disp_rn_l_D_1101_M_1011_N_1110,
	store_rm_disp_rn_l_D_1110_M_1011_N_1110,
	store_rm_disp_rn_l_D_1111_M_1011_N_1110,
	store_rm_disp_rn_l_D_0000_M_1100_N_1110,
	store_rm_disp_rn_l_D_0001_M_1100_N_1110,
	store_rm_disp_rn_l_D_0010_M_1100_N_1110,
	store_rm_disp_rn_l_D_0011_M_1100_N_1110,
	store_rm_disp_rn_l_D_0100_M_1100_N_1110,
	store_rm_disp_rn_l_D_0101_M_1100_N_1110,
	store_rm_disp_rn_l_D_0110_M_1100_N_1110,
	store_rm_disp_rn_l_D_0111_M_1100_N_1110,
	store_rm_disp_rn_l_D_1000_M_1100_N_1110,
	store_rm_disp_rn_l_D_1001_M_1100_N_1110,
	store_rm_disp_rn_l_D_1010_M_1100_N_1110,
	store_rm_disp_rn_l_D_1011_M_1100_N_1110,
	store_rm_disp_rn_l_D_1100_M_1100_N_1110,
	store_rm_disp_rn_l_D_1101_M_1100_N_1110,
	store_rm_disp_rn_l_D_1110_M_1100_N_1110,
	store_rm_disp_rn_l_D_1111_M_1100_N_1110,
	store_rm_disp_rn_l_D_0000_M_1101_N_1110,
	store_rm_disp_rn_l_D_0001_M_1101_N_1110,
	store_rm_disp_rn_l_D_0010_M_1101_N_1110,
	store_rm_disp_rn_l_D_0011_M_1101_N_1110,
	store_rm_disp_rn_l_D_0100_M_1101_N_1110,
	store_rm_disp_rn_l_D_0101_M_1101_N_1110,
	store_rm_disp_rn_l_D_0110_M_1101_N_1110,
	store_rm_disp_rn_l_D_0111_M_1101_N_1110,
	store_rm_disp_rn_l_D_1000_M_1101_N_1110,
	store_rm_disp_rn_l_D_1001_M_1101_N_1110,
	store_rm_disp_rn_l_D_1010_M_1101_N_1110,
	store_rm_disp_rn_l_D_1011_M_1101_N_1110,
	store_rm_disp_rn_l_D_1100_M_1101_N_1110,
	store_rm_disp_rn_l_D_1101_M_1101_N_1110,
	store_rm_disp_rn_l_D_1110_M_1101_N_1110,
	store_rm_disp_rn_l_D_1111_M_1101_N_1110,
	store_rm_disp_rn_l_D_0000_M_1110_N_1110,
	store_rm_disp_rn_l_D_0001_M_1110_N_1110,
	store_rm_disp_rn_l_D_0010_M_1110_N_1110,
	store_rm_disp_rn_l_D_0011_M_1110_N_1110,
	store_rm_disp_rn_l_D_0100_M_1110_N_1110,
	store_rm_disp_rn_l_D_0101_M_1110_N_1110,
	store_rm_disp_rn_l_D_0110_M_1110_N_1110,
	store_rm_disp_rn_l_D_0111_M_1110_N_1110,
	store_rm_disp_rn_l_D_1000_M_1110_N_1110,
	store_rm_disp_rn_l_D_1001_M_1110_N_1110,
	store_rm_disp_rn_l_D_1010_M_1110_N_1110,
	store_rm_disp_rn_l_D_1011_M_1110_N_1110,
	store_rm_disp_rn_l_D_1100_M_1110_N_1110,
	store_rm_disp_rn_l_D_1101_M_1110_N_1110,
	store_rm_disp_rn_l_D_1110_M_1110_N_1110,
	store_rm_disp_rn_l_D_1111_M_1110_N_1110,
	store_rm_disp_rn_l_D_0000_M_1111_N_1110,
	store_rm_disp_rn_l_D_0001_M_1111_N_1110,
	store_rm_disp_rn_l_D_0010_M_1111_N_1110,
	store_rm_disp_rn_l_D_0011_M_1111_N_1110,
	store_rm_disp_rn_l_D_0100_M_1111_N_1110,
	store_rm_disp_rn_l_D_0101_M_1111_N_1110,
	store_rm_disp_rn_l_D_0110_M_1111_N_1110,
	store_rm_disp_rn_l_D_0111_M_1111_N_1110,
	store_rm_disp_rn_l_D_1000_M_1111_N_1110,
	store_rm_disp_rn_l_D_1001_M_1111_N_1110,
	store_rm_disp_rn_l_D_1010_M_1111_N_1110,
	store_rm_disp_rn_l_D_1011_M_1111_N_1110,
	store_rm_disp_rn_l_D_1100_M_1111_N_1110,
	store_rm_disp_rn_l_D_1101_M_1111_N_1110,
	store_rm_disp_rn_l_D_1110_M_1111_N_1110,
	store_rm_disp_rn_l_D_1111_M_1111_N_1110,
	store_rm_disp_rn_l_D_0000_M_0000_N_1111,
	store_rm_disp_rn_l_D_0001_M_0000_N_1111,
	store_rm_disp_rn_l_D_0010_M_0000_N_1111,
	store_rm_disp_rn_l_D_0011_M_0000_N_1111,
	store_rm_disp_rn_l_D_0100_M_0000_N_1111,
	store_rm_disp_rn_l_D_0101_M_0000_N_1111,
	store_rm_disp_rn_l_D_0110_M_0000_N_1111,
	store_rm_disp_rn_l_D_0111_M_0000_N_1111,
	store_rm_disp_rn_l_D_1000_M_0000_N_1111,
	store_rm_disp_rn_l_D_1001_M_0000_N_1111,
	store_rm_disp_rn_l_D_1010_M_0000_N_1111,
	store_rm_disp_rn_l_D_1011_M_0000_N_1111,
	store_rm_disp_rn_l_D_1100_M_0000_N_1111,
	store_rm_disp_rn_l_D_1101_M_0000_N_1111,
	store_rm_disp_rn_l_D_1110_M_0000_N_1111,
	store_rm_disp_rn_l_D_1111_M_0000_N_1111,
	store_rm_disp_rn_l_D_0000_M_0001_N_1111,
	store_rm_disp_rn_l_D_0001_M_0001_N_1111,
	store_rm_disp_rn_l_D_0010_M_0001_N_1111,
	store_rm_disp_rn_l_D_0011_M_0001_N_1111,
	store_rm_disp_rn_l_D_0100_M_0001_N_1111,
	store_rm_disp_rn_l_D_0101_M_0001_N_1111,
	store_rm_disp_rn_l_D_0110_M_0001_N_1111,
	store_rm_disp_rn_l_D_0111_M_0001_N_1111,
	store_rm_disp_rn_l_D_1000_M_0001_N_1111,
	store_rm_disp_rn_l_D_1001_M_0001_N_1111,
	store_rm_disp_rn_l_D_1010_M_0001_N_1111,
	store_rm_disp_rn_l_D_1011_M_0001_N_1111,
	store_rm_disp_rn_l_D_1100_M_0001_N_1111,
	store_rm_disp_rn_l_D_1101_M_0001_N_1111,
	store_rm_disp_rn_l_D_1110_M_0001_N_1111,
	store_rm_disp_rn_l_D_1111_M_0001_N_1111,
	store_rm_disp_rn_l_D_0000_M_0010_N_1111,
	store_rm_disp_rn_l_D_0001_M_0010_N_1111,
	store_rm_disp_rn_l_D_0010_M_0010_N_1111,
	store_rm_disp_rn_l_D_0011_M_0010_N_1111,
	store_rm_disp_rn_l_D_0100_M_0010_N_1111,
	store_rm_disp_rn_l_D_0101_M_0010_N_1111,
	store_rm_disp_rn_l_D_0110_M_0010_N_1111,
	store_rm_disp_rn_l_D_0111_M_0010_N_1111,
	store_rm_disp_rn_l_D_1000_M_0010_N_1111,
	store_rm_disp_rn_l_D_1001_M_0010_N_1111,
	store_rm_disp_rn_l_D_1010_M_0010_N_1111,
	store_rm_disp_rn_l_D_1011_M_0010_N_1111,
	store_rm_disp_rn_l_D_1100_M_0010_N_1111,
	store_rm_disp_rn_l_D_1101_M_0010_N_1111,
	store_rm_disp_rn_l_D_1110_M_0010_N_1111,
	store_rm_disp_rn_l_D_1111_M_0010_N_1111,
	store_rm_disp_rn_l_D_0000_M_0011_N_1111,
	store_rm_disp_rn_l_D_0001_M_0011_N_1111,
	store_rm_disp_rn_l_D_0010_M_0011_N_1111,
	store_rm_disp_rn_l_D_0011_M_0011_N_1111,
	store_rm_disp_rn_l_D_0100_M_0011_N_1111,
	store_rm_disp_rn_l_D_0101_M_0011_N_1111,
	store_rm_disp_rn_l_D_0110_M_0011_N_1111,
	store_rm_disp_rn_l_D_0111_M_0011_N_1111,
	store_rm_disp_rn_l_D_1000_M_0011_N_1111,
	store_rm_disp_rn_l_D_1001_M_0011_N_1111,
	store_rm_disp_rn_l_D_1010_M_0011_N_1111,
	store_rm_disp_rn_l_D_1011_M_0011_N_1111,
	store_rm_disp_rn_l_D_1100_M_0011_N_1111,
	store_rm_disp_rn_l_D_1101_M_0011_N_1111,
	store_rm_disp_rn_l_D_1110_M_0011_N_1111,
	store_rm_disp_rn_l_D_1111_M_0011_N_1111,
	store_rm_disp_rn_l_D_0000_M_0100_N_1111,
	store_rm_disp_rn_l_D_0001_M_0100_N_1111,
	store_rm_disp_rn_l_D_0010_M_0100_N_1111,
	store_rm_disp_rn_l_D_0011_M_0100_N_1111,
	store_rm_disp_rn_l_D_0100_M_0100_N_1111,
	store_rm_disp_rn_l_D_0101_M_0100_N_1111,
	store_rm_disp_rn_l_D_0110_M_0100_N_1111,
	store_rm_disp_rn_l_D_0111_M_0100_N_1111,
	store_rm_disp_rn_l_D_1000_M_0100_N_1111,
	store_rm_disp_rn_l_D_1001_M_0100_N_1111,
	store_rm_disp_rn_l_D_1010_M_0100_N_1111,
	store_rm_disp_rn_l_D_1011_M_0100_N_1111,
	store_rm_disp_rn_l_D_1100_M_0100_N_1111,
	store_rm_disp_rn_l_D_1101_M_0100_N_1111,
	store_rm_disp_rn_l_D_1110_M_0100_N_1111,
	store_rm_disp_rn_l_D_1111_M_0100_N_1111,
	store_rm_disp_rn_l_D_0000_M_0101_N_1111,
	store_rm_disp_rn_l_D_0001_M_0101_N_1111,
	store_rm_disp_rn_l_D_0010_M_0101_N_1111,
	store_rm_disp_rn_l_D_0011_M_0101_N_1111,
	store_rm_disp_rn_l_D_0100_M_0101_N_1111,
	store_rm_disp_rn_l_D_0101_M_0101_N_1111,
	store_rm_disp_rn_l_D_0110_M_0101_N_1111,
	store_rm_disp_rn_l_D_0111_M_0101_N_1111,
	store_rm_disp_rn_l_D_1000_M_0101_N_1111,
	store_rm_disp_rn_l_D_1001_M_0101_N_1111,
	store_rm_disp_rn_l_D_1010_M_0101_N_1111,
	store_rm_disp_rn_l_D_1011_M_0101_N_1111,
	store_rm_disp_rn_l_D_1100_M_0101_N_1111,
	store_rm_disp_rn_l_D_1101_M_0101_N_1111,
	store_rm_disp_rn_l_D_1110_M_0101_N_1111,
	store_rm_disp_rn_l_D_1111_M_0101_N_1111,
	store_rm_disp_rn_l_D_0000_M_0110_N_1111,
	store_rm_disp_rn_l_D_0001_M_0110_N_1111,
	store_rm_disp_rn_l_D_0010_M_0110_N_1111,
	store_rm_disp_rn_l_D_0011_M_0110_N_1111,
	store_rm_disp_rn_l_D_0100_M_0110_N_1111,
	store_rm_disp_rn_l_D_0101_M_0110_N_1111,
	store_rm_disp_rn_l_D_0110_M_0110_N_1111,
	store_rm_disp_rn_l_D_0111_M_0110_N_1111,
	store_rm_disp_rn_l_D_1000_M_0110_N_1111,
	store_rm_disp_rn_l_D_1001_M_0110_N_1111,
	store_rm_disp_rn_l_D_1010_M_0110_N_1111,
	store_rm_disp_rn_l_D_1011_M_0110_N_1111,
	store_rm_disp_rn_l_D_1100_M_0110_N_1111,
	store_rm_disp_rn_l_D_1101_M_0110_N_1111,
	store_rm_disp_rn_l_D_1110_M_0110_N_1111,
	store_rm_disp_rn_l_D_1111_M_0110_N_1111,
	store_rm_disp_rn_l_D_0000_M_0111_N_1111,
	store_rm_disp_rn_l_D_0001_M_0111_N_1111,
	store_rm_disp_rn_l_D_0010_M_0111_N_1111,
	store_rm_disp_rn_l_D_0011_M_0111_N_1111,
	store_rm_disp_rn_l_D_0100_M_0111_N_1111,
	store_rm_disp_rn_l_D_0101_M_0111_N_1111,
	store_rm_disp_rn_l_D_0110_M_0111_N_1111,
	store_rm_disp_rn_l_D_0111_M_0111_N_1111,
	store_rm_disp_rn_l_D_1000_M_0111_N_1111,
	store_rm_disp_rn_l_D_1001_M_0111_N_1111,
	store_rm_disp_rn_l_D_1010_M_0111_N_1111,
	store_rm_disp_rn_l_D_1011_M_0111_N_1111,
	store_rm_disp_rn_l_D_1100_M_0111_N_1111,
	store_rm_disp_rn_l_D_1101_M_0111_N_1111,
	store_rm_disp_rn_l_D_1110_M_0111_N_1111,
	store_rm_disp_rn_l_D_1111_M_0111_N_1111,
	store_rm_disp_rn_l_D_0000_M_1000_N_1111,
	store_rm_disp_rn_l_D_0001_M_1000_N_1111,
	store_rm_disp_rn_l_D_0010_M_1000_N_1111,
	store_rm_disp_rn_l_D_0011_M_1000_N_1111,
	store_rm_disp_rn_l_D_0100_M_1000_N_1111,
	store_rm_disp_rn_l_D_0101_M_1000_N_1111,
	store_rm_disp_rn_l_D_0110_M_1000_N_1111,
	store_rm_disp_rn_l_D_0111_M_1000_N_1111,
	store_rm_disp_rn_l_D_1000_M_1000_N_1111,
	store_rm_disp_rn_l_D_1001_M_1000_N_1111,
	store_rm_disp_rn_l_D_1010_M_1000_N_1111,
	store_rm_disp_rn_l_D_1011_M_1000_N_1111,
	store_rm_disp_rn_l_D_1100_M_1000_N_1111,
	store_rm_disp_rn_l_D_1101_M_1000_N_1111,
	store_rm_disp_rn_l_D_1110_M_1000_N_1111,
	store_rm_disp_rn_l_D_1111_M_1000_N_1111,
	store_rm_disp_rn_l_D_0000_M_1001_N_1111,
	store_rm_disp_rn_l_D_0001_M_1001_N_1111,
	store_rm_disp_rn_l_D_0010_M_1001_N_1111,
	store_rm_disp_rn_l_D_0011_M_1001_N_1111,
	store_rm_disp_rn_l_D_0100_M_1001_N_1111,
	store_rm_disp_rn_l_D_0101_M_1001_N_1111,
	store_rm_disp_rn_l_D_0110_M_1001_N_1111,
	store_rm_disp_rn_l_D_0111_M_1001_N_1111,
	store_rm_disp_rn_l_D_1000_M_1001_N_1111,
	store_rm_disp_rn_l_D_1001_M_1001_N_1111,
	store_rm_disp_rn_l_D_1010_M_1001_N_1111,
	store_rm_disp_rn_l_D_1011_M_1001_N_1111,
	store_rm_disp_rn_l_D_1100_M_1001_N_1111,
	store_rm_disp_rn_l_D_1101_M_1001_N_1111,
	store_rm_disp_rn_l_D_1110_M_1001_N_1111,
	store_rm_disp_rn_l_D_1111_M_1001_N_1111,
	store_rm_disp_rn_l_D_0000_M_1010_N_1111,
	store_rm_disp_rn_l_D_0001_M_1010_N_1111,
	store_rm_disp_rn_l_D_0010_M_1010_N_1111,
	store_rm_disp_rn_l_D_0011_M_1010_N_1111,
	store_rm_disp_rn_l_D_0100_M_1010_N_1111,
	store_rm_disp_rn_l_D_0101_M_1010_N_1111,
	store_rm_disp_rn_l_D_0110_M_1010_N_1111,
	store_rm_disp_rn_l_D_0111_M_1010_N_1111,
	store_rm_disp_rn_l_D_1000_M_1010_N_1111,
	store_rm_disp_rn_l_D_1001_M_1010_N_1111,
	store_rm_disp_rn_l_D_1010_M_1010_N_1111,
	store_rm_disp_rn_l_D_1011_M_1010_N_1111,
	store_rm_disp_rn_l_D_1100_M_1010_N_1111,
	store_rm_disp_rn_l_D_1101_M_1010_N_1111,
	store_rm_disp_rn_l_D_1110_M_1010_N_1111,
	store_rm_disp_rn_l_D_1111_M_1010_N_1111,
	store_rm_disp_rn_l_D_0000_M_1011_N_1111,
	store_rm_disp_rn_l_D_0001_M_1011_N_1111,
	store_rm_disp_rn_l_D_0010_M_1011_N_1111,
	store_rm_disp_rn_l_D_0011_M_1011_N_1111,
	store_rm_disp_rn_l_D_0100_M_1011_N_1111,
	store_rm_disp_rn_l_D_0101_M_1011_N_1111,
	store_rm_disp_rn_l_D_0110_M_1011_N_1111,
	store_rm_disp_rn_l_D_0111_M_1011_N_1111,
	store_rm_disp_rn_l_D_1000_M_1011_N_1111,
	store_rm_disp_rn_l_D_1001_M_1011_N_1111,
	store_rm_disp_rn_l_D_1010_M_1011_N_1111,
	store_rm_disp_rn_l_D_1011_M_1011_N_1111,
	store_rm_disp_rn_l_D_1100_M_1011_N_1111,
	store_rm_disp_rn_l_D_1101_M_1011_N_1111,
	store_rm_disp_rn_l_D_1110_M_1011_N_1111,
	store_rm_disp_rn_l_D_1111_M_1011_N_1111,
	store_rm_disp_rn_l_D_0000_M_1100_N_1111,
	store_rm_disp_rn_l_D_0001_M_1100_N_1111,
	store_rm_disp_rn_l_D_0010_M_1100_N_1111,
	store_rm_disp_rn_l_D_0011_M_1100_N_1111,
	store_rm_disp_rn_l_D_0100_M_1100_N_1111,
	store_rm_disp_rn_l_D_0101_M_1100_N_1111,
	store_rm_disp_rn_l_D_0110_M_1100_N_1111,
	store_rm_disp_rn_l_D_0111_M_1100_N_1111,
	store_rm_disp_rn_l_D_1000_M_1100_N_1111,
	store_rm_disp_rn_l_D_1001_M_1100_N_1111,
	store_rm_disp_rn_l_D_1010_M_1100_N_1111,
	store_rm_disp_rn_l_D_1011_M_1100_N_1111,
	store_rm_disp_rn_l_D_1100_M_1100_N_1111,
	store_rm_disp_rn_l_D_1101_M_1100_N_1111,
	store_rm_disp_rn_l_D_1110_M_1100_N_1111,
	store_rm_disp_rn_l_D_1111_M_1100_N_1111,
	store_rm_disp_rn_l_D_0000_M_1101_N_1111,
	store_rm_disp_rn_l_D_0001_M_1101_N_1111,
	store_rm_disp_rn_l_D_0010_M_1101_N_1111,
	store_rm_disp_rn_l_D_0011_M_1101_N_1111,
	store_rm_disp_rn_l_D_0100_M_1101_N_1111,
	store_rm_disp_rn_l_D_0101_M_1101_N_1111,
	store_rm_disp_rn_l_D_0110_M_1101_N_1111,
	store_rm_disp_rn_l_D_0111_M_1101_N_1111,
	store_rm_disp_rn_l_D_1000_M_1101_N_1111,
	store_rm_disp_rn_l_D_1001_M_1101_N_1111,
	store_rm_disp_rn_l_D_1010_M_1101_N_1111,
	store_rm_disp_rn_l_D_1011_M_1101_N_1111,
	store_rm_disp_rn_l_D_1100_M_1101_N_1111,
	store_rm_disp_rn_l_D_1101_M_1101_N_1111,
	store_rm_disp_rn_l_D_1110_M_1101_N_1111,
	store_rm_disp_rn_l_D_1111_M_1101_N_1111,
	store_rm_disp_rn_l_D_0000_M_1110_N_1111,
	store_rm_disp_rn_l_D_0001_M_1110_N_1111,
	store_rm_disp_rn_l_D_0010_M_1110_N_1111,
	store_rm_disp_rn_l_D_0011_M_1110_N_1111,
	store_rm_disp_rn_l_D_0100_M_1110_N_1111,
	store_rm_disp_rn_l_D_0101_M_1110_N_1111,
	store_rm_disp_rn_l_D_0110_M_1110_N_1111,
	store_rm_disp_rn_l_D_0111_M_1110_N_1111,
	store_rm_disp_rn_l_D_1000_M_1110_N_1111,
	store_rm_disp_rn_l_D_1001_M_1110_N_1111,
	store_rm_disp_rn_l_D_1010_M_1110_N_1111,
	store_rm_disp_rn_l_D_1011_M_1110_N_1111,
	store_rm_disp_rn_l_D_1100_M_1110_N_1111,
	store_rm_disp_rn_l_D_1101_M_1110_N_1111,
	store_rm_disp_rn_l_D_1110_M_1110_N_1111,
	store_rm_disp_rn_l_D_1111_M_1110_N_1111,
	store_rm_disp_rn_l_D_0000_M_1111_N_1111,
	store_rm_disp_rn_l_D_0001_M_1111_N_1111,
	store_rm_disp_rn_l_D_0010_M_1111_N_1111,
	store_rm_disp_rn_l_D_0011_M_1111_N_1111,
	store_rm_disp_rn_l_D_0100_M_1111_N_1111,
	store_rm_disp_rn_l_D_0101_M_1111_N_1111,
	store_rm_disp_rn_l_D_0110_M_1111_N_1111,
	store_rm_disp_rn_l_D_0111_M_1111_N_1111,
	store_rm_disp_rn_l_D_1000_M_1111_N_1111,
	store_rm_disp_rn_l_D_1001_M_1111_N_1111,
	store_rm_disp_rn_l_D_1010_M_1111_N_1111,
	store_rm_disp_rn_l_D_1011_M_1111_N_1111,
	store_rm_disp_rn_l_D_1100_M_1111_N_1111,
	store_rm_disp_rn_l_D_1101_M_1111_N_1111,
	store_rm_disp_rn_l_D_1110_M_1111_N_1111,
	store_rm_disp_rn_l_D_1111_M_1111_N_1111,
	store_rm_rn_b_M_0000_N_0000,
	store_rm_rn_w_M_0000_N_0000,
	store_rm_rn_l_M_0000_N_0000,
	unimplemented,
	store_predec_rm_rn_b_M_0000_N_0000,
	store_predec_rm_rn_w_M_0000_N_0000,
	store_predec_rm_rn_l_M_0000_N_0000,
	div0s_M_0000_N_0000,
	tst_rm_rn_M_0000_N_0000,
	and_rm_rn_M_0000_N_0000,
	xor_rm_rn_M_0000_N_0000,
	or_rm_rn_M_0000_N_0000,
	cmpstr_rm_rn_M_0000_N_0000,
	xtrct_M_0000_N_0000,
	mulu_w_M_0000_N_0000,
	muls_w_M_0000_N_0000,
	store_rm_rn_b_M_0001_N_0000,
	store_rm_rn_w_M_0001_N_0000,
	store_rm_rn_l_M_0001_N_0000,
	unimplemented,
	store_predec_rm_rn_b_M_0001_N_0000,
	store_predec_rm_rn_w_M_0001_N_0000,
	store_predec_rm_rn_l_M_0001_N_0000,
	div0s_M_0001_N_0000,
	tst_rm_rn_M_0001_N_0000,
	and_rm_rn_M_0001_N_0000,
	xor_rm_rn_M_0001_N_0000,
	or_rm_rn_M_0001_N_0000,
	cmpstr_rm_rn_M_0001_N_0000,
	xtrct_M_0001_N_0000,
	mulu_w_M_0001_N_0000,
	muls_w_M_0001_N_0000,
	store_rm_rn_b_M_0010_N_0000,
	store_rm_rn_w_M_0010_N_0000,
	store_rm_rn_l_M_0010_N_0000,
	unimplemented,
	store_predec_rm_rn_b_M_0010_N_0000,
	store_predec_rm_rn_w_M_0010_N_0000,
	store_predec_rm_rn_l_M_0010_N_0000,
	div0s_M_0010_N_0000,
	tst_rm_rn_M_0010_N_0000,
	and_rm_rn_M_0010_N_0000,
	xor_rm_rn_M_0010_N_0000,
	or_rm_rn_M_0010_N_0000,
	cmpstr_rm_rn_M_0010_N_0000,
	xtrct_M_0010_N_0000,
	mulu_w_M_0010_N_0000,
	muls_w_M_0010_N_0000,
	store_rm_rn_b_M_0011_N_0000,
	store_rm_rn_w_M_0011_N_0000,
	store_rm_rn_l_M_0011_N_0000,
	unimplemented,
	store_predec_rm_rn_b_M_0011_N_0000,
	store_predec_rm_rn_w_M_0011_N_0000,
	store_predec_rm_rn_l_M_0011_N_0000,
	div0s_M_0011_N_0000,
	tst_rm_rn_M_0011_N_0000,
	and_rm_rn_M_0011_N_0000,
	xor_rm_rn_M_0011_N_0000,
	or_rm_rn_M_0011_N_0000,
	cmpstr_rm_rn_M_0011_N_0000,
	xtrct_M_0011_N_0000,
	mulu_w_M_0011_N_0000,
	muls_w_M_0011_N_0000,
	store_rm_rn_b_M_0100_N_0000,
	store_rm_rn_w_M_0100_N_0000,
	store_rm_rn_l_M_0100_N_0000,
	unimplemented,
	store_predec_rm_rn_b_M_0100_N_0000,
	store_predec_rm_rn_w_M_0100_N_0000,
	store_predec_rm_rn_l_M_0100_N_0000,
	div0s_M_0100_N_0000,
	tst_rm_rn_M_0100_N_0000,
	and_rm_rn_M_0100_N_0000,
	xor_rm_rn_M_0100_N_0000,
	or_rm_rn_M_0100_N_0000,
	cmpstr_rm_rn_M_0100_N_0000,
	xtrct_M_0100_N_0000,
	mulu_w_M_0100_N_0000,
	muls_w_M_0100_N_0000,
	store_rm_rn_b_M_0101_N_0000,
	store_rm_rn_w_M_0101_N_0000,
	store_rm_rn_l_M_0101_N_0000,
	unimplemented,
	store_predec_rm_rn_b_M_0101_N_0000,
	store_predec_rm_rn_w_M_0101_N_0000,
	store_predec_rm_rn_l_M_0101_N_0000,
	div0s_M_0101_N_0000,
	tst_rm_rn_M_0101_N_0000,
	and_rm_rn_M_0101_N_0000,
	xor_rm_rn_M_0101_N_0000,
	or_rm_rn_M_0101_N_0000,
	cmpstr_rm_rn_M_0101_N_0000,
	xtrct_M_0101_N_0000,
	mulu_w_M_0101_N_0000,
	muls_w_M_0101_N_0000,
	store_rm_rn_b_M_0110_N_0000,
	store_rm_rn_w_M_0110_N_0000,
	store_rm_rn_l_M_0110_N_0000,
	unimplemented,
	store_predec_rm_rn_b_M_0110_N_0000,
	store_predec_rm_rn_w_M_0110_N_0000,
	store_predec_rm_rn_l_M_0110_N_0000,
	div0s_M_0110_N_0000,
	tst_rm_rn_M_0110_N_0000,
	and_rm_rn_M_0110_N_0000,
	xor_rm_rn_M_0110_N_0000,
	or_rm_rn_M_0110_N_0000,
	cmpstr_rm_rn_M_0110_N_0000,
	xtrct_M_0110_N_0000,
	mulu_w_M_0110_N_0000,
	muls_w_M_0110_N_0000,
	store_rm_rn_b_M_0111_N_0000,
	store_rm_rn_w_M_0111_N_0000,
	store_rm_rn_l_M_0111_N_0000,
	unimplemented,
	store_predec_rm_rn_b_M_0111_N_0000,
	store_predec_rm_rn_w_M_0111_N_0000,
	store_predec_rm_rn_l_M_0111_N_0000,
	div0s_M_0111_N_0000,
	tst_rm_rn_M_0111_N_0000,
	and_rm_rn_M_0111_N_0000,
	xor_rm_rn_M_0111_N_0000,
	or_rm_rn_M_0111_N_0000,
	cmpstr_rm_rn_M_0111_N_0000,
	xtrct_M_0111_N_0000,
	mulu_w_M_0111_N_0000,
	muls_w_M_0111_N_0000,
	store_rm_rn_b_M_1000_N_0000,
	store_rm_rn_w_M_1000_N_0000,
	store_rm_rn_l_M_1000_N_0000,
	unimplemented,
	store_predec_rm_rn_b_M_1000_N_0000,
	store_predec_rm_rn_w_M_1000_N_0000,
	store_predec_rm_rn_l_M_1000_N_0000,
	div0s_M_1000_N_0000,
	tst_rm_rn_M_1000_N_0000,
	and_rm_rn_M_1000_N_0000,
	xor_rm_rn_M_1000_N_0000,
	or_rm_rn_M_1000_N_0000,
	cmpstr_rm_rn_M_1000_N_0000,
	xtrct_M_1000_N_0000,
	mulu_w_M_1000_N_0000,
	muls_w_M_1000_N_0000,
	store_rm_rn_b_M_1001_N_0000,
	store_rm_rn_w_M_1001_N_0000,
	store_rm_rn_l_M_1001_N_0000,
	unimplemented,
	store_predec_rm_rn_b_M_1001_N_0000,
	store_predec_rm_rn_w_M_1001_N_0000,
	store_predec_rm_rn_l_M_1001_N_0000,
	div0s_M_1001_N_0000,
	tst_rm_rn_M_1001_N_0000,
	and_rm_rn_M_1001_N_0000,
	xor_rm_rn_M_1001_N_0000,
	or_rm_rn_M_1001_N_0000,
	cmpstr_rm_rn_M_1001_N_0000,
	xtrct_M_1001_N_0000,
	mulu_w_M_1001_N_0000,
	muls_w_M_1001_N_0000,
	store_rm_rn_b_M_1010_N_0000,
	store_rm_rn_w_M_1010_N_0000,
	store_rm_rn_l_M_1010_N_0000,
	unimplemented,
	store_predec_rm_rn_b_M_1010_N_0000,
	store_predec_rm_rn_w_M_1010_N_0000,
	store_predec_rm_rn_l_M_1010_N_0000,
	div0s_M_1010_N_0000,
	tst_rm_rn_M_1010_N_0000,
	and_rm_rn_M_1010_N_0000,
	xor_rm_rn_M_1010_N_0000,
	or_rm_rn_M_1010_N_0000,
	cmpstr_rm_rn_M_1010_N_0000,
	xtrct_M_1010_N_0000,
	mulu_w_M_1010_N_0000,
	muls_w_M_1010_N_0000,
	store_rm_rn_b_M_1011_N_0000,
	store_rm_rn_w_M_1011_N_0000,
	store_rm_rn_l_M_1011_N_0000,
	unimplemented,
	store_predec_rm_rn_b_M_1011_N_0000,
	store_predec_rm_rn_w_M_1011_N_0000,
	store_predec_rm_rn_l_M_1011_N_0000,
	div0s_M_1011_N_0000,
	tst_rm_rn_M_1011_N_0000,
	and_rm_rn_M_1011_N_0000,
	xor_rm_rn_M_1011_N_0000,
	or_rm_rn_M_1011_N_0000,
	cmpstr_rm_rn_M_1011_N_0000,
	xtrct_M_1011_N_0000,
	mulu_w_M_1011_N_0000,
	muls_w_M_1011_N_0000,
	store_rm_rn_b_M_1100_N_0000,
	store_rm_rn_w_M_1100_N_0000,
	store_rm_rn_l_M_1100_N_0000,
	unimplemented,
	store_predec_rm_rn_b_M_1100_N_0000,
	store_predec_rm_rn_w_M_1100_N_0000,
	store_predec_rm_rn_l_M_1100_N_0000,
	div0s_M_1100_N_0000,
	tst_rm_rn_M_1100_N_0000,
	and_rm_rn_M_1100_N_0000,
	xor_rm_rn_M_1100_N_0000,
	or_rm_rn_M_1100_N_0000,
	cmpstr_rm_rn_M_1100_N_0000,
	xtrct_M_1100_N_0000,
	mulu_w_M_1100_N_0000,
	muls_w_M_1100_N_0000,
	store_rm_rn_b_M_1101_N_0000,
	store_rm_rn_w_M_1101_N_0000,
	store_rm_rn_l_M_1101_N_0000,
	unimplemented,
	store_predec_rm_rn_b_M_1101_N_0000,
	store_predec_rm_rn_w_M_1101_N_0000,
	store_predec_rm_rn_l_M_1101_N_0000,
	div0s_M_1101_N_0000,
	tst_rm_rn_M_1101_N_0000,
	and_rm_rn_M_1101_N_0000,
	xor_rm_rn_M_1101_N_0000,
	or_rm_rn_M_1101_N_0000,
	cmpstr_rm_rn_M_1101_N_0000,
	xtrct_M_1101_N_0000,
	mulu_w_M_1101_N_0000,
	muls_w_M_1101_N_0000,
	store_rm_rn_b_M_1110_N_0000,
	store_rm_rn_w_M_1110_N_0000,
	store_rm_rn_l_M_1110_N_0000,
	unimplemented,
	store_predec_rm_rn_b_M_1110_N_0000,
	store_predec_rm_rn_w_M_1110_N_0000,
	store_predec_rm_rn_l_M_1110_N_0000,
	div0s_M_1110_N_0000,
	tst_rm_rn_M_1110_N_0000,
	and_rm_rn_M_1110_N_0000,
	xor_rm_rn_M_1110_N_0000,
	or_rm_rn_M_1110_N_0000,
	cmpstr_rm_rn_M_1110_N_0000,
	xtrct_M_1110_N_0000,
	mulu_w_M_1110_N_0000,
	muls_w_M_1110_N_0000,
	store_rm_rn_b_M_1111_N_0000,
	store_rm_rn_w_M_1111_N_0000,
	store_rm_rn_l_M_1111_N_0000,
	unimplemented,
	store_predec_rm_rn_b_M_1111_N_0000,
	store_predec_rm_rn_w_M_1111_N_0000,
	store_predec_rm_rn_l_M_1111_N_0000,
	div0s_M_1111_N_0000,
	tst_rm_rn_M_1111_N_0000,
	and_rm_rn_M_1111_N_0000,
	xor_rm_rn_M_1111_N_0000,
	or_rm_rn_M_1111_N_0000,
	cmpstr_rm_rn_M_1111_N_0000,
	xtrct_M_1111_N_0000,
	mulu_w_M_1111_N_0000,
	muls_w_M_1111_N_0000,
	store_rm_rn_b_M_0000_N_0001,
	store_rm_rn_w_M_0000_N_0001,
	store_rm_rn_l_M_0000_N_0001,
	unimplemented,
	store_predec_rm_rn_b_M_0000_N_0001,
	store_predec_rm_rn_w_M_0000_N_0001,
	store_predec_rm_rn_l_M_0000_N_0001,
	div0s_M_0000_N_0001,
	tst_rm_rn_M_0000_N_0001,
	and_rm_rn_M_0000_N_0001,
	xor_rm_rn_M_0000_N_0001,
	or_rm_rn_M_0000_N_0001,
	cmpstr_rm_rn_M_0000_N_0001,
	xtrct_M_0000_N_0001,
	mulu_w_M_0000_N_0001,
	muls_w_M_0000_N_0001,
	store_rm_rn_b_M_0001_N_0001,
	store_rm_rn_w_M_0001_N_0001,
	store_rm_rn_l_M_0001_N_0001,
	unimplemented,
	store_predec_rm_rn_b_M_0001_N_0001,
	store_predec_rm_rn_w_M_0001_N_0001,
	store_predec_rm_rn_l_M_0001_N_0001,
	div0s_M_0001_N_0001,
	tst_rm_rn_M_0001_N_0001,
	and_rm_rn_M_0001_N_0001,
	xor_rm_rn_M_0001_N_0001,
	or_rm_rn_M_0001_N_0001,
	cmpstr_rm_rn_M_0001_N_0001,
	xtrct_M_0001_N_0001,
	mulu_w_M_0001_N_0001,
	muls_w_M_0001_N_0001,
	store_rm_rn_b_M_0010_N_0001,
	store_rm_rn_w_M_0010_N_0001,
	store_rm_rn_l_M_0010_N_0001,
	unimplemented,
	store_predec_rm_rn_b_M_0010_N_0001,
	store_predec_rm_rn_w_M_0010_N_0001,
	store_predec_rm_rn_l_M_0010_N_0001,
	div0s_M_0010_N_0001,
	tst_rm_rn_M_0010_N_0001,
	and_rm_rn_M_0010_N_0001,
	xor_rm_rn_M_0010_N_0001,
	or_rm_rn_M_0010_N_0001,
	cmpstr_rm_rn_M_0010_N_0001,
	xtrct_M_0010_N_0001,
	mulu_w_M_0010_N_0001,
	muls_w_M_0010_N_0001,
	store_rm_rn_b_M_0011_N_0001,
	store_rm_rn_w_M_0011_N_0001,
	store_rm_rn_l_M_0011_N_0001,
	unimplemented,
	store_predec_rm_rn_b_M_0011_N_0001,
	store_predec_rm_rn_w_M_0011_N_0001,
	store_predec_rm_rn_l_M_0011_N_0001,
	div0s_M_0011_N_0001,
	tst_rm_rn_M_0011_N_0001,
	and_rm_rn_M_0011_N_0001,
	xor_rm_rn_M_0011_N_0001,
	or_rm_rn_M_0011_N_0001,
	cmpstr_rm_rn_M_0011_N_0001,
	xtrct_M_0011_N_0001,
	mulu_w_M_0011_N_0001,
	muls_w_M_0011_N_0001,
	store_rm_rn_b_M_0100_N_0001,
	store_rm_rn_w_M_0100_N_0001,
	store_rm_rn_l_M_0100_N_0001,
	unimplemented,
	store_predec_rm_rn_b_M_0100_N_0001,
	store_predec_rm_rn_w_M_0100_N_0001,
	store_predec_rm_rn_l_M_0100_N_0001,
	div0s_M_0100_N_0001,
	tst_rm_rn_M_0100_N_0001,
	and_rm_rn_M_0100_N_0001,
	xor_rm_rn_M_0100_N_0001,
	or_rm_rn_M_0100_N_0001,
	cmpstr_rm_rn_M_0100_N_0001,
	xtrct_M_0100_N_0001,
	mulu_w_M_0100_N_0001,
	muls_w_M_0100_N_0001,
	store_rm_rn_b_M_0101_N_0001,
	store_rm_rn_w_M_0101_N_0001,
	store_rm_rn_l_M_0101_N_0001,
	unimplemented,
	store_predec_rm_rn_b_M_0101_N_0001,
	store_predec_rm_rn_w_M_0101_N_0001,
	store_predec_rm_rn_l_M_0101_N_0001,
	div0s_M_0101_N_0001,
	tst_rm_rn_M_0101_N_0001,
	and_rm_rn_M_0101_N_0001,
	xor_rm_rn_M_0101_N_0001,
	or_rm_rn_M_0101_N_0001,
	cmpstr_rm_rn_M_0101_N_0001,
	xtrct_M_0101_N_0001,
	mulu_w_M_0101_N_0001,
	muls_w_M_0101_N_0001,
	store_rm_rn_b_M_0110_N_0001,
	store_rm_rn_w_M_0110_N_0001,
	store_rm_rn_l_M_0110_N_0001,
	unimplemented,
	store_predec_rm_rn_b_M_0110_N_0001,
	store_predec_rm_rn_w_M_0110_N_0001,
	store_predec_rm_rn_l_M_0110_N_0001,
	div0s_M_0110_N_0001,
	tst_rm_rn_M_0110_N_0001,
	and_rm_rn_M_0110_N_0001,
	xor_rm_rn_M_0110_N_0001,
	or_rm_rn_M_0110_N_0001,
	cmpstr_rm_rn_M_0110_N_0001,
	xtrct_M_0110_N_0001,
	mulu_w_M_0110_N_0001,
	muls_w_M_0110_N_0001,
	store_rm_rn_b_M_0111_N_0001,
	store_rm_rn_w_M_0111_N_0001,
	store_rm_rn_l_M_0111_N_0001,
	unimplemented,
	store_predec_rm_rn_b_M_0111_N_0001,
	store_predec_rm_rn_w_M_0111_N_0001,
	store_predec_rm_rn_l_M_0111_N_0001,
	div0s_M_0111_N_0001,
	tst_rm_rn_M_0111_N_0001,
	and_rm_rn_M_0111_N_0001,
	xor_rm_rn_M_0111_N_0001,
	or_rm_rn_M_0111_N_0001,
	cmpstr_rm_rn_M_0111_N_0001,
	xtrct_M_0111_N_0001,
	mulu_w_M_0111_N_0001,
	muls_w_M_0111_N_0001,
	store_rm_rn_b_M_1000_N_0001,
	store_rm_rn_w_M_1000_N_0001,
	store_rm_rn_l_M_1000_N_0001,
	unimplemented,
	store_predec_rm_rn_b_M_1000_N_0001,
	store_predec_rm_rn_w_M_1000_N_0001,
	store_predec_rm_rn_l_M_1000_N_0001,
	div0s_M_1000_N_0001,
	tst_rm_rn_M_1000_N_0001,
	and_rm_rn_M_1000_N_0001,
	xor_rm_rn_M_1000_N_0001,
	or_rm_rn_M_1000_N_0001,
	cmpstr_rm_rn_M_1000_N_0001,
	xtrct_M_1000_N_0001,
	mulu_w_M_1000_N_0001,
	muls_w_M_1000_N_0001,
	store_rm_rn_b_M_1001_N_0001,
	store_rm_rn_w_M_1001_N_0001,
	store_rm_rn_l_M_1001_N_0001,
	unimplemented,
	store_predec_rm_rn_b_M_1001_N_0001,
	store_predec_rm_rn_w_M_1001_N_0001,
	store_predec_rm_rn_l_M_1001_N_0001,
	div0s_M_1001_N_0001,
	tst_rm_rn_M_1001_N_0001,
	and_rm_rn_M_1001_N_0001,
	xor_rm_rn_M_1001_N_0001,
	or_rm_rn_M_1001_N_0001,
	cmpstr_rm_rn_M_1001_N_0001,
	xtrct_M_1001_N_0001,
	mulu_w_M_1001_N_0001,
	muls_w_M_1001_N_0001,
	store_rm_rn_b_M_1010_N_0001,
	store_rm_rn_w_M_1010_N_0001,
	store_rm_rn_l_M_1010_N_0001,
	unimplemented,
	store_predec_rm_rn_b_M_1010_N_0001,
	store_predec_rm_rn_w_M_1010_N_0001,
	store_predec_rm_rn_l_M_1010_N_0001,
	div0s_M_1010_N_0001,
	tst_rm_rn_M_1010_N_0001,
	and_rm_rn_M_1010_N_0001,
	xor_rm_rn_M_1010_N_0001,
	or_rm_rn_M_1010_N_0001,
	cmpstr_rm_rn_M_1010_N_0001,
	xtrct_M_1010_N_0001,
	mulu_w_M_1010_N_0001,
	muls_w_M_1010_N_0001,
	store_rm_rn_b_M_1011_N_0001,
	store_rm_rn_w_M_1011_N_0001,
	store_rm_rn_l_M_1011_N_0001,
	unimplemented,
	store_predec_rm_rn_b_M_1011_N_0001,
	store_predec_rm_rn_w_M_1011_N_0001,
	store_predec_rm_rn_l_M_1011_N_0001,
	div0s_M_1011_N_0001,
	tst_rm_rn_M_1011_N_0001,
	and_rm_rn_M_1011_N_0001,
	xor_rm_rn_M_1011_N_0001,
	or_rm_rn_M_1011_N_0001,
	cmpstr_rm_rn_M_1011_N_0001,
	xtrct_M_1011_N_0001,
	mulu_w_M_1011_N_0001,
	muls_w_M_1011_N_0001,
	store_rm_rn_b_M_1100_N_0001,
	store_rm_rn_w_M_1100_N_0001,
	store_rm_rn_l_M_1100_N_0001,
	unimplemented,
	store_predec_rm_rn_b_M_1100_N_0001,
	store_predec_rm_rn_w_M_1100_N_0001,
	store_predec_rm_rn_l_M_1100_N_0001,
	div0s_M_1100_N_0001,
	tst_rm_rn_M_1100_N_0001,
	and_rm_rn_M_1100_N_0001,
	xor_rm_rn_M_1100_N_0001,
	or_rm_rn_M_1100_N_0001,
	cmpstr_rm_rn_M_1100_N_0001,
	xtrct_M_1100_N_0001,
	mulu_w_M_1100_N_0001,
	muls_w_M_1100_N_0001,
	store_rm_rn_b_M_1101_N_0001,
	store_rm_rn_w_M_1101_N_0001,
	store_rm_rn_l_M_1101_N_0001,
	unimplemented,
	store_predec_rm_rn_b_M_1101_N_0001,
	store_predec_rm_rn_w_M_1101_N_0001,
	store_predec_rm_rn_l_M_1101_N_0001,
	div0s_M_1101_N_0001,
	tst_rm_rn_M_1101_N_0001,
	and_rm_rn_M_1101_N_0001,
	xor_rm_rn_M_1101_N_0001,
	or_rm_rn_M_1101_N_0001,
	cmpstr_rm_rn_M_1101_N_0001,
	xtrct_M_1101_N_0001,
	mulu_w_M_1101_N_0001,
	muls_w_M_1101_N_0001,
	store_rm_rn_b_M_1110_N_0001,
	store_rm_rn_w_M_1110_N_0001,
	store_rm_rn_l_M_1110_N_0001,
	unimplemented,
	store_predec_rm_rn_b_M_1110_N_0001,
	store_predec_rm_rn_w_M_1110_N_0001,
	store_predec_rm_rn_l_M_1110_N_0001,
	div0s_M_1110_N_0001,
	tst_rm_rn_M_1110_N_0001,
	and_rm_rn_M_1110_N_0001,
	xor_rm_rn_M_1110_N_0001,
	or_rm_rn_M_1110_N_0001,
	cmpstr_rm_rn_M_1110_N_0001,
	xtrct_M_1110_N_0001,
	mulu_w_M_1110_N_0001,
	muls_w_M_1110_N_0001,
	store_rm_rn_b_M_1111_N_0001,
	store_rm_rn_w_M_1111_N_0001,
	store_rm_rn_l_M_1111_N_0001,
	unimplemented,
	store_predec_rm_rn_b_M_1111_N_0001,
	store_predec_rm_rn_w_M_1111_N_0001,
	store_predec_rm_rn_l_M_1111_N_0001,
	div0s_M_1111_N_0001,
	tst_rm_rn_M_1111_N_0001,
	and_rm_rn_M_1111_N_0001,
	xor_rm_rn_M_1111_N_0001,
	or_rm_rn_M_1111_N_0001,
	cmpstr_rm_rn_M_1111_N_0001,
	xtrct_M_1111_N_0001,
	mulu_w_M_1111_N_0001,
	muls_w_M_1111_N_0001,
	store_rm_rn_b_M_0000_N_0010,
	store_rm_rn_w_M_0000_N_0010,
	store_rm_rn_l_M_0000_N_0010,
	unimplemented,
	store_predec_rm_rn_b_M_0000_N_0010,
	store_predec_rm_rn_w_M_0000_N_0010,
	store_predec_rm_rn_l_M_0000_N_0010,
	div0s_M_0000_N_0010,
	tst_rm_rn_M_0000_N_0010,
	and_rm_rn_M_0000_N_0010,
	xor_rm_rn_M_0000_N_0010,
	or_rm_rn_M_0000_N_0010,
	cmpstr_rm_rn_M_0000_N_0010,
	xtrct_M_0000_N_0010,
	mulu_w_M_0000_N_0010,
	muls_w_M_0000_N_0010,
	store_rm_rn_b_M_0001_N_0010,
	store_rm_rn_w_M_0001_N_0010,
	store_rm_rn_l_M_0001_N_0010,
	unimplemented,
	store_predec_rm_rn_b_M_0001_N_0010,
	store_predec_rm_rn_w_M_0001_N_0010,
	store_predec_rm_rn_l_M_0001_N_0010,
	div0s_M_0001_N_0010,
	tst_rm_rn_M_0001_N_0010,
	and_rm_rn_M_0001_N_0010,
	xor_rm_rn_M_0001_N_0010,
	or_rm_rn_M_0001_N_0010,
	cmpstr_rm_rn_M_0001_N_0010,
	xtrct_M_0001_N_0010,
	mulu_w_M_0001_N_0010,
	muls_w_M_0001_N_0010,
	store_rm_rn_b_M_0010_N_0010,
	store_rm_rn_w_M_0010_N_0010,
	store_rm_rn_l_M_0010_N_0010,
	unimplemented,
	store_predec_rm_rn_b_M_0010_N_0010,
	store_predec_rm_rn_w_M_0010_N_0010,
	store_predec_rm_rn_l_M_0010_N_0010,
	div0s_M_0010_N_0010,
	tst_rm_rn_M_0010_N_0010,
	and_rm_rn_M_0010_N_0010,
	xor_rm_rn_M_0010_N_0010,
	or_rm_rn_M_0010_N_0010,
	cmpstr_rm_rn_M_0010_N_0010,
	xtrct_M_0010_N_0010,
	mulu_w_M_0010_N_0010,
	muls_w_M_0010_N_0010,
	store_rm_rn_b_M_0011_N_0010,
	store_rm_rn_w_M_0011_N_0010,
	store_rm_rn_l_M_0011_N_0010,
	unimplemented,
	store_predec_rm_rn_b_M_0011_N_0010,
	store_predec_rm_rn_w_M_0011_N_0010,
	store_predec_rm_rn_l_M_0011_N_0010,
	div0s_M_0011_N_0010,
	tst_rm_rn_M_0011_N_0010,
	and_rm_rn_M_0011_N_0010,
	xor_rm_rn_M_0011_N_0010,
	or_rm_rn_M_0011_N_0010,
	cmpstr_rm_rn_M_0011_N_0010,
	xtrct_M_0011_N_0010,
	mulu_w_M_0011_N_0010,
	muls_w_M_0011_N_0010,
	store_rm_rn_b_M_0100_N_0010,
	store_rm_rn_w_M_0100_N_0010,
	store_rm_rn_l_M_0100_N_0010,
	unimplemented,
	store_predec_rm_rn_b_M_0100_N_0010,
	store_predec_rm_rn_w_M_0100_N_0010,
	store_predec_rm_rn_l_M_0100_N_0010,
	div0s_M_0100_N_0010,
	tst_rm_rn_M_0100_N_0010,
	and_rm_rn_M_0100_N_0010,
	xor_rm_rn_M_0100_N_0010,
	or_rm_rn_M_0100_N_0010,
	cmpstr_rm_rn_M_0100_N_0010,
	xtrct_M_0100_N_0010,
	mulu_w_M_0100_N_0010,
	muls_w_M_0100_N_0010,
	store_rm_rn_b_M_0101_N_0010,
	store_rm_rn_w_M_0101_N_0010,
	store_rm_rn_l_M_0101_N_0010,
	unimplemented,
	store_predec_rm_rn_b_M_0101_N_0010,
	store_predec_rm_rn_w_M_0101_N_0010,
	store_predec_rm_rn_l_M_0101_N_0010,
	div0s_M_0101_N_0010,
	tst_rm_rn_M_0101_N_0010,
	and_rm_rn_M_0101_N_0010,
	xor_rm_rn_M_0101_N_0010,
	or_rm_rn_M_0101_N_0010,
	cmpstr_rm_rn_M_0101_N_0010,
	xtrct_M_0101_N_0010,
	mulu_w_M_0101_N_0010,
	muls_w_M_0101_N_0010,
	store_rm_rn_b_M_0110_N_0010,
	store_rm_rn_w_M_0110_N_0010,
	store_rm_rn_l_M_0110_N_0010,
	unimplemented,
	store_predec_rm_rn_b_M_0110_N_0010,
	store_predec_rm_rn_w_M_0110_N_0010,
	store_predec_rm_rn_l_M_0110_N_0010,
	div0s_M_0110_N_0010,
	tst_rm_rn_M_0110_N_0010,
	and_rm_rn_M_0110_N_0010,
	xor_rm_rn_M_0110_N_0010,
	or_rm_rn_M_0110_N_0010,
	cmpstr_rm_rn_M_0110_N_0010,
	xtrct_M_0110_N_0010,
	mulu_w_M_0110_N_0010,
	muls_w_M_0110_N_0010,
	store_rm_rn_b_M_0111_N_0010,
	store_rm_rn_w_M_0111_N_0010,
	store_rm_rn_l_M_0111_N_0010,
	unimplemented,
	store_predec_rm_rn_b_M_0111_N_0010,
	store_predec_rm_rn_w_M_0111_N_0010,
	store_predec_rm_rn_l_M_0111_N_0010,
	div0s_M_0111_N_0010,
	tst_rm_rn_M_0111_N_0010,
	and_rm_rn_M_0111_N_0010,
	xor_rm_rn_M_0111_N_0010,
	or_rm_rn_M_0111_N_0010,
	cmpstr_rm_rn_M_0111_N_0010,
	xtrct_M_0111_N_0010,
	mulu_w_M_0111_N_0010,
	muls_w_M_0111_N_0010,
	store_rm_rn_b_M_1000_N_0010,
	store_rm_rn_w_M_1000_N_0010,
	store_rm_rn_l_M_1000_N_0010,
	unimplemented,
	store_predec_rm_rn_b_M_1000_N_0010,
	store_predec_rm_rn_w_M_1000_N_0010,
	store_predec_rm_rn_l_M_1000_N_0010,
	div0s_M_1000_N_0010,
	tst_rm_rn_M_1000_N_0010,
	and_rm_rn_M_1000_N_0010,
	xor_rm_rn_M_1000_N_0010,
	or_rm_rn_M_1000_N_0010,
	cmpstr_rm_rn_M_1000_N_0010,
	xtrct_M_1000_N_0010,
	mulu_w_M_1000_N_0010,
	muls_w_M_1000_N_0010,
	store_rm_rn_b_M_1001_N_0010,
	store_rm_rn_w_M_1001_N_0010,
	store_rm_rn_l_M_1001_N_0010,
	unimplemented,
	store_predec_rm_rn_b_M_1001_N_0010,
	store_predec_rm_rn_w_M_1001_N_0010,
	store_predec_rm_rn_l_M_1001_N_0010,
	div0s_M_1001_N_0010,
	tst_rm_rn_M_1001_N_0010,
	and_rm_rn_M_1001_N_0010,
	xor_rm_rn_M_1001_N_0010,
	or_rm_rn_M_1001_N_0010,
	cmpstr_rm_rn_M_1001_N_0010,
	xtrct_M_1001_N_0010,
	mulu_w_M_1001_N_0010,
	muls_w_M_1001_N_0010,
	store_rm_rn_b_M_1010_N_0010,
	store_rm_rn_w_M_1010_N_0010,
	store_rm_rn_l_M_1010_N_0010,
	unimplemented,
	store_predec_rm_rn_b_M_1010_N_0010,
	store_predec_rm_rn_w_M_1010_N_0010,
	store_predec_rm_rn_l_M_1010_N_0010,
	div0s_M_1010_N_0010,
	tst_rm_rn_M_1010_N_0010,
	and_rm_rn_M_1010_N_0010,
	xor_rm_rn_M_1010_N_0010,
	or_rm_rn_M_1010_N_0010,
	cmpstr_rm_rn_M_1010_N_0010,
	xtrct_M_1010_N_0010,
	mulu_w_M_1010_N_0010,
	muls_w_M_1010_N_0010,
	store_rm_rn_b_M_1011_N_0010,
	store_rm_rn_w_M_1011_N_0010,
	store_rm_rn_l_M_1011_N_0010,
	unimplemented,
	store_predec_rm_rn_b_M_1011_N_0010,
	store_predec_rm_rn_w_M_1011_N_0010,
	store_predec_rm_rn_l_M_1011_N_0010,
	div0s_M_1011_N_0010,
	tst_rm_rn_M_1011_N_0010,
	and_rm_rn_M_1011_N_0010,
	xor_rm_rn_M_1011_N_0010,
	or_rm_rn_M_1011_N_0010,
	cmpstr_rm_rn_M_1011_N_0010,
	xtrct_M_1011_N_0010,
	mulu_w_M_1011_N_0010,
	muls_w_M_1011_N_0010,
	store_rm_rn_b_M_1100_N_0010,
	store_rm_rn_w_M_1100_N_0010,
	store_rm_rn_l_M_1100_N_0010,
	unimplemented,
	store_predec_rm_rn_b_M_1100_N_0010,
	store_predec_rm_rn_w_M_1100_N_0010,
	store_predec_rm_rn_l_M_1100_N_0010,
	div0s_M_1100_N_0010,
	tst_rm_rn_M_1100_N_0010,
	and_rm_rn_M_1100_N_0010,
	xor_rm_rn_M_1100_N_0010,
	or_rm_rn_M_1100_N_0010,
	cmpstr_rm_rn_M_1100_N_0010,
	xtrct_M_1100_N_0010,
	mulu_w_M_1100_N_0010,
	muls_w_M_1100_N_0010,
	store_rm_rn_b_M_1101_N_0010,
	store_rm_rn_w_M_1101_N_0010,
	store_rm_rn_l_M_1101_N_0010,
	unimplemented,
	store_predec_rm_rn_b_M_1101_N_0010,
	store_predec_rm_rn_w_M_1101_N_0010,
	store_predec_rm_rn_l_M_1101_N_0010,
	div0s_M_1101_N_0010,
	tst_rm_rn_M_1101_N_0010,
	and_rm_rn_M_1101_N_0010,
	xor_rm_rn_M_1101_N_0010,
	or_rm_rn_M_1101_N_0010,
	cmpstr_rm_rn_M_1101_N_0010,
	xtrct_M_1101_N_0010,
	mulu_w_M_1101_N_0010,
	muls_w_M_1101_N_0010,
	store_rm_rn_b_M_1110_N_0010,
	store_rm_rn_w_M_1110_N_0010,
	store_rm_rn_l_M_1110_N_0010,
	unimplemented,
	store_predec_rm_rn_b_M_1110_N_0010,
	store_predec_rm_rn_w_M_1110_N_0010,
	store_predec_rm_rn_l_M_1110_N_0010,
	div0s_M_1110_N_0010,
	tst_rm_rn_M_1110_N_0010,
	and_rm_rn_M_1110_N_0010,
	xor_rm_rn_M_1110_N_0010,
	or_rm_rn_M_1110_N_0010,
	cmpstr_rm_rn_M_1110_N_0010,
	xtrct_M_1110_N_0010,
	mulu_w_M_1110_N_0010,
	muls_w_M_1110_N_0010,
	store_rm_rn_b_M_1111_N_0010,
	store_rm_rn_w_M_1111_N_0010,
	store_rm_rn_l_M_1111_N_0010,
	unimplemented,
	store_predec_rm_rn_b_M_1111_N_0010,
	store_predec_rm_rn_w_M_1111_N_0010,
	store_predec_rm_rn_l_M_1111_N_0010,
	div0s_M_1111_N_0010,
	tst_rm_rn_M_1111_N_0010,
	and_rm_rn_M_1111_N_0010,
	xor_rm_rn_M_1111_N_0010,
	or_rm_rn_M_1111_N_0010,
	cmpstr_rm_rn_M_1111_N_0010,
	xtrct_M_1111_N_0010,
	mulu_w_M_1111_N_0010,
	muls_w_M_1111_N_0010,
	store_rm_rn_b_M_0000_N_0011,
	store_rm_rn_w_M_0000_N_0011,
	store_rm_rn_l_M_0000_N_0011,
	unimplemented,
	store_predec_rm_rn_b_M_0000_N_0011,
	store_predec_rm_rn_w_M_0000_N_0011,
	store_predec_rm_rn_l_M_0000_N_0011,
	div0s_M_0000_N_0011,
	tst_rm_rn_M_0000_N_0011,
	and_rm_rn_M_0000_N_0011,
	xor_rm_rn_M_0000_N_0011,
	or_rm_rn_M_0000_N_0011,
	cmpstr_rm_rn_M_0000_N_0011,
	xtrct_M_0000_N_0011,
	mulu_w_M_0000_N_0011,
	muls_w_M_0000_N_0011,
	store_rm_rn_b_M_0001_N_0011,
	store_rm_rn_w_M_0001_N_0011,
	store_rm_rn_l_M_0001_N_0011,
	unimplemented,
	store_predec_rm_rn_b_M_0001_N_0011,
	store_predec_rm_rn_w_M_0001_N_0011,
	store_predec_rm_rn_l_M_0001_N_0011,
	div0s_M_0001_N_0011,
	tst_rm_rn_M_0001_N_0011,
	and_rm_rn_M_0001_N_0011,
	xor_rm_rn_M_0001_N_0011,
	or_rm_rn_M_0001_N_0011,
	cmpstr_rm_rn_M_0001_N_0011,
	xtrct_M_0001_N_0011,
	mulu_w_M_0001_N_0011,
	muls_w_M_0001_N_0011,
	store_rm_rn_b_M_0010_N_0011,
	store_rm_rn_w_M_0010_N_0011,
	store_rm_rn_l_M_0010_N_0011,
	unimplemented,
	store_predec_rm_rn_b_M_0010_N_0011,
	store_predec_rm_rn_w_M_0010_N_0011,
	store_predec_rm_rn_l_M_0010_N_0011,
	div0s_M_0010_N_0011,
	tst_rm_rn_M_0010_N_0011,
	and_rm_rn_M_0010_N_0011,
	xor_rm_rn_M_0010_N_0011,
	or_rm_rn_M_0010_N_0011,
	cmpstr_rm_rn_M_0010_N_0011,
	xtrct_M_0010_N_0011,
	mulu_w_M_0010_N_0011,
	muls_w_M_0010_N_0011,
	store_rm_rn_b_M_0011_N_0011,
	store_rm_rn_w_M_0011_N_0011,
	store_rm_rn_l_M_0011_N_0011,
	unimplemented,
	store_predec_rm_rn_b_M_0011_N_0011,
	store_predec_rm_rn_w_M_0011_N_0011,
	store_predec_rm_rn_l_M_0011_N_0011,
	div0s_M_0011_N_0011,
	tst_rm_rn_M_0011_N_0011,
	and_rm_rn_M_0011_N_0011,
	xor_rm_rn_M_0011_N_0011,
	or_rm_rn_M_0011_N_0011,
	cmpstr_rm_rn_M_0011_N_0011,
	xtrct_M_0011_N_0011,
	mulu_w_M_0011_N_0011,
	muls_w_M_0011_N_0011,
	store_rm_rn_b_M_0100_N_0011,
	store_rm_rn_w_M_0100_N_0011,
	store_rm_rn_l_M_0100_N_0011,
	unimplemented,
	store_predec_rm_rn_b_M_0100_N_0011,
	store_predec_rm_rn_w_M_0100_N_0011,
	store_predec_rm_rn_l_M_0100_N_0011,
	div0s_M_0100_N_0011,
	tst_rm_rn_M_0100_N_0011,
	and_rm_rn_M_0100_N_0011,
	xor_rm_rn_M_0100_N_0011,
	or_rm_rn_M_0100_N_0011,
	cmpstr_rm_rn_M_0100_N_0011,
	xtrct_M_0100_N_0011,
	mulu_w_M_0100_N_0011,
	muls_w_M_0100_N_0011,
	store_rm_rn_b_M_0101_N_0011,
	store_rm_rn_w_M_0101_N_0011,
	store_rm_rn_l_M_0101_N_0011,
	unimplemented,
	store_predec_rm_rn_b_M_0101_N_0011,
	store_predec_rm_rn_w_M_0101_N_0011,
	store_predec_rm_rn_l_M_0101_N_0011,
	div0s_M_0101_N_0011,
	tst_rm_rn_M_0101_N_0011,
	and_rm_rn_M_0101_N_0011,
	xor_rm_rn_M_0101_N_0011,
	or_rm_rn_M_0101_N_0011,
	cmpstr_rm_rn_M_0101_N_0011,
	xtrct_M_0101_N_0011,
	mulu_w_M_0101_N_0011,
	muls_w_M_0101_N_0011,
	store_rm_rn_b_M_0110_N_0011,
	store_rm_rn_w_M_0110_N_0011,
	store_rm_rn_l_M_0110_N_0011,
	unimplemented,
	store_predec_rm_rn_b_M_0110_N_0011,
	store_predec_rm_rn_w_M_0110_N_0011,
	store_predec_rm_rn_l_M_0110_N_0011,
	div0s_M_0110_N_0011,
	tst_rm_rn_M_0110_N_0011,
	and_rm_rn_M_0110_N_0011,
	xor_rm_rn_M_0110_N_0011,
	or_rm_rn_M_0110_N_0011,
	cmpstr_rm_rn_M_0110_N_0011,
	xtrct_M_0110_N_0011,
	mulu_w_M_0110_N_0011,
	muls_w_M_0110_N_0011,
	store_rm_rn_b_M_0111_N_0011,
	store_rm_rn_w_M_0111_N_0011,
	store_rm_rn_l_M_0111_N_0011,
	unimplemented,
	store_predec_rm_rn_b_M_0111_N_0011,
	store_predec_rm_rn_w_M_0111_N_0011,
	store_predec_rm_rn_l_M_0111_N_0011,
	div0s_M_0111_N_0011,
	tst_rm_rn_M_0111_N_0011,
	and_rm_rn_M_0111_N_0011,
	xor_rm_rn_M_0111_N_0011,
	or_rm_rn_M_0111_N_0011,
	cmpstr_rm_rn_M_0111_N_0011,
	xtrct_M_0111_N_0011,
	mulu_w_M_0111_N_0011,
	muls_w_M_0111_N_0011,
	store_rm_rn_b_M_1000_N_0011,
	store_rm_rn_w_M_1000_N_0011,
	store_rm_rn_l_M_1000_N_0011,
	unimplemented,
	store_predec_rm_rn_b_M_1000_N_0011,
	store_predec_rm_rn_w_M_1000_N_0011,
	store_predec_rm_rn_l_M_1000_N_0011,
	div0s_M_1000_N_0011,
	tst_rm_rn_M_1000_N_0011,
	and_rm_rn_M_1000_N_0011,
	xor_rm_rn_M_1000_N_0011,
	or_rm_rn_M_1000_N_0011,
	cmpstr_rm_rn_M_1000_N_0011,
	xtrct_M_1000_N_0011,
	mulu_w_M_1000_N_0011,
	muls_w_M_1000_N_0011,
	store_rm_rn_b_M_1001_N_0011,
	store_rm_rn_w_M_1001_N_0011,
	store_rm_rn_l_M_1001_N_0011,
	unimplemented,
	store_predec_rm_rn_b_M_1001_N_0011,
	store_predec_rm_rn_w_M_1001_N_0011,
	store_predec_rm_rn_l_M_1001_N_0011,
	div0s_M_1001_N_0011,
	tst_rm_rn_M_1001_N_0011,
	and_rm_rn_M_1001_N_0011,
	xor_rm_rn_M_1001_N_0011,
	or_rm_rn_M_1001_N_0011,
	cmpstr_rm_rn_M_1001_N_0011,
	xtrct_M_1001_N_0011,
	mulu_w_M_1001_N_0011,
	muls_w_M_1001_N_0011,
	store_rm_rn_b_M_1010_N_0011,
	store_rm_rn_w_M_1010_N_0011,
	store_rm_rn_l_M_1010_N_0011,
	unimplemented,
	store_predec_rm_rn_b_M_1010_N_0011,
	store_predec_rm_rn_w_M_1010_N_0011,
	store_predec_rm_rn_l_M_1010_N_0011,
	div0s_M_1010_N_0011,
	tst_rm_rn_M_1010_N_0011,
	and_rm_rn_M_1010_N_0011,
	xor_rm_rn_M_1010_N_0011,
	or_rm_rn_M_1010_N_0011,
	cmpstr_rm_rn_M_1010_N_0011,
	xtrct_M_1010_N_0011,
	mulu_w_M_1010_N_0011,
	muls_w_M_1010_N_0011,
	store_rm_rn_b_M_1011_N_0011,
	store_rm_rn_w_M_1011_N_0011,
	store_rm_rn_l_M_1011_N_0011,
	unimplemented,
	store_predec_rm_rn_b_M_1011_N_0011,
	store_predec_rm_rn_w_M_1011_N_0011,
	store_predec_rm_rn_l_M_1011_N_0011,
	div0s_M_1011_N_0011,
	tst_rm_rn_M_1011_N_0011,
	and_rm_rn_M_1011_N_0011,
	xor_rm_rn_M_1011_N_0011,
	or_rm_rn_M_1011_N_0011,
	cmpstr_rm_rn_M_1011_N_0011,
	xtrct_M_1011_N_0011,
	mulu_w_M_1011_N_0011,
	muls_w_M_1011_N_0011,
	store_rm_rn_b_M_1100_N_0011,
	store_rm_rn_w_M_1100_N_0011,
	store_rm_rn_l_M_1100_N_0011,
	unimplemented,
	store_predec_rm_rn_b_M_1100_N_0011,
	store_predec_rm_rn_w_M_1100_N_0011,
	store_predec_rm_rn_l_M_1100_N_0011,
	div0s_M_1100_N_0011,
	tst_rm_rn_M_1100_N_0011,
	and_rm_rn_M_1100_N_0011,
	xor_rm_rn_M_1100_N_0011,
	or_rm_rn_M_1100_N_0011,
	cmpstr_rm_rn_M_1100_N_0011,
	xtrct_M_1100_N_0011,
	mulu_w_M_1100_N_0011,
	muls_w_M_1100_N_0011,
	store_rm_rn_b_M_1101_N_0011,
	store_rm_rn_w_M_1101_N_0011,
	store_rm_rn_l_M_1101_N_0011,
	unimplemented,
	store_predec_rm_rn_b_M_1101_N_0011,
	store_predec_rm_rn_w_M_1101_N_0011,
	store_predec_rm_rn_l_M_1101_N_0011,
	div0s_M_1101_N_0011,
	tst_rm_rn_M_1101_N_0011,
	and_rm_rn_M_1101_N_0011,
	xor_rm_rn_M_1101_N_0011,
	or_rm_rn_M_1101_N_0011,
	cmpstr_rm_rn_M_1101_N_0011,
	xtrct_M_1101_N_0011,
	mulu_w_M_1101_N_0011,
	muls_w_M_1101_N_0011,
	store_rm_rn_b_M_1110_N_0011,
	store_rm_rn_w_M_1110_N_0011,
	store_rm_rn_l_M_1110_N_0011,
	unimplemented,
	store_predec_rm_rn_b_M_1110_N_0011,
	store_predec_rm_rn_w_M_1110_N_0011,
	store_predec_rm_rn_l_M_1110_N_0011,
	div0s_M_1110_N_0011,
	tst_rm_rn_M_1110_N_0011,
	and_rm_rn_M_1110_N_0011,
	xor_rm_rn_M_1110_N_0011,
	or_rm_rn_M_1110_N_0011,
	cmpstr_rm_rn_M_1110_N_0011,
	xtrct_M_1110_N_0011,
	mulu_w_M_1110_N_0011,
	muls_w_M_1110_N_0011,
	store_rm_rn_b_M_1111_N_0011,
	store_rm_rn_w_M_1111_N_0011,
	store_rm_rn_l_M_1111_N_0011,
	unimplemented,
	store_predec_rm_rn_b_M_1111_N_0011,
	store_predec_rm_rn_w_M_1111_N_0011,
	store_predec_rm_rn_l_M_1111_N_0011,
	div0s_M_1111_N_0011,
	tst_rm_rn_M_1111_N_0011,
	and_rm_rn_M_1111_N_0011,
	xor_rm_rn_M_1111_N_0011,
	or_rm_rn_M_1111_N_0011,
	cmpstr_rm_rn_M_1111_N_0011,
	xtrct_M_1111_N_0011,
	mulu_w_M_1111_N_0011,
	muls_w_M_1111_N_0011,
	store_rm_rn_b_M_0000_N_0100,
	store_rm_rn_w_M_0000_N_0100,
	store_rm_rn_l_M_0000_N_0100,
	unimplemented,
	store_predec_rm_rn_b_M_0000_N_0100,
	store_predec_rm_rn_w_M_0000_N_0100,
	store_predec_rm_rn_l_M_0000_N_0100,
	div0s_M_0000_N_0100,
	tst_rm_rn_M_0000_N_0100,
	and_rm_rn_M_0000_N_0100,
	xor_rm_rn_M_0000_N_0100,
	or_rm_rn_M_0000_N_0100,
	cmpstr_rm_rn_M_0000_N_0100,
	xtrct_M_0000_N_0100,
	mulu_w_M_0000_N_0100,
	muls_w_M_0000_N_0100,
	store_rm_rn_b_M_0001_N_0100,
	store_rm_rn_w_M_0001_N_0100,
	store_rm_rn_l_M_0001_N_0100,
	unimplemented,
	store_predec_rm_rn_b_M_0001_N_0100,
	store_predec_rm_rn_w_M_0001_N_0100,
	store_predec_rm_rn_l_M_0001_N_0100,
	div0s_M_0001_N_0100,
	tst_rm_rn_M_0001_N_0100,
	and_rm_rn_M_0001_N_0100,
	xor_rm_rn_M_0001_N_0100,
	or_rm_rn_M_0001_N_0100,
	cmpstr_rm_rn_M_0001_N_0100,
	xtrct_M_0001_N_0100,
	mulu_w_M_0001_N_0100,
	muls_w_M_0001_N_0100,
	store_rm_rn_b_M_0010_N_0100,
	store_rm_rn_w_M_0010_N_0100,
	store_rm_rn_l_M_0010_N_0100,
	unimplemented,
	store_predec_rm_rn_b_M_0010_N_0100,
	store_predec_rm_rn_w_M_0010_N_0100,
	store_predec_rm_rn_l_M_0010_N_0100,
	div0s_M_0010_N_0100,
	tst_rm_rn_M_0010_N_0100,
	and_rm_rn_M_0010_N_0100,
	xor_rm_rn_M_0010_N_0100,
	or_rm_rn_M_0010_N_0100,
	cmpstr_rm_rn_M_0010_N_0100,
	xtrct_M_0010_N_0100,
	mulu_w_M_0010_N_0100,
	muls_w_M_0010_N_0100,
	store_rm_rn_b_M_0011_N_0100,
	store_rm_rn_w_M_0011_N_0100,
	store_rm_rn_l_M_0011_N_0100,
	unimplemented,
	store_predec_rm_rn_b_M_0011_N_0100,
	store_predec_rm_rn_w_M_0011_N_0100,
	store_predec_rm_rn_l_M_0011_N_0100,
	div0s_M_0011_N_0100,
	tst_rm_rn_M_0011_N_0100,
	and_rm_rn_M_0011_N_0100,
	xor_rm_rn_M_0011_N_0100,
	or_rm_rn_M_0011_N_0100,
	cmpstr_rm_rn_M_0011_N_0100,
	xtrct_M_0011_N_0100,
	mulu_w_M_0011_N_0100,
	muls_w_M_0011_N_0100,
	store_rm_rn_b_M_0100_N_0100,
	store_rm_rn_w_M_0100_N_0100,
	store_rm_rn_l_M_0100_N_0100,
	unimplemented,
	store_predec_rm_rn_b_M_0100_N_0100,
	store_predec_rm_rn_w_M_0100_N_0100,
	store_predec_rm_rn_l_M_0100_N_0100,
	div0s_M_0100_N_0100,
	tst_rm_rn_M_0100_N_0100,
	and_rm_rn_M_0100_N_0100,
	xor_rm_rn_M_0100_N_0100,
	or_rm_rn_M_0100_N_0100,
	cmpstr_rm_rn_M_0100_N_0100,
	xtrct_M_0100_N_0100,
	mulu_w_M_0100_N_0100,
	muls_w_M_0100_N_0100,
	store_rm_rn_b_M_0101_N_0100,
	store_rm_rn_w_M_0101_N_0100,
	store_rm_rn_l_M_0101_N_0100,
	unimplemented,
	store_predec_rm_rn_b_M_0101_N_0100,
	store_predec_rm_rn_w_M_0101_N_0100,
	store_predec_rm_rn_l_M_0101_N_0100,
	div0s_M_0101_N_0100,
	tst_rm_rn_M_0101_N_0100,
	and_rm_rn_M_0101_N_0100,
	xor_rm_rn_M_0101_N_0100,
	or_rm_rn_M_0101_N_0100,
	cmpstr_rm_rn_M_0101_N_0100,
	xtrct_M_0101_N_0100,
	mulu_w_M_0101_N_0100,
	muls_w_M_0101_N_0100,
	store_rm_rn_b_M_0110_N_0100,
	store_rm_rn_w_M_0110_N_0100,
	store_rm_rn_l_M_0110_N_0100,
	unimplemented,
	store_predec_rm_rn_b_M_0110_N_0100,
	store_predec_rm_rn_w_M_0110_N_0100,
	store_predec_rm_rn_l_M_0110_N_0100,
	div0s_M_0110_N_0100,
	tst_rm_rn_M_0110_N_0100,
	and_rm_rn_M_0110_N_0100,
	xor_rm_rn_M_0110_N_0100,
	or_rm_rn_M_0110_N_0100,
	cmpstr_rm_rn_M_0110_N_0100,
	xtrct_M_0110_N_0100,
	mulu_w_M_0110_N_0100,
	muls_w_M_0110_N_0100,
	store_rm_rn_b_M_0111_N_0100,
	store_rm_rn_w_M_0111_N_0100,
	store_rm_rn_l_M_0111_N_0100,
	unimplemented,
	store_predec_rm_rn_b_M_0111_N_0100,
	store_predec_rm_rn_w_M_0111_N_0100,
	store_predec_rm_rn_l_M_0111_N_0100,
	div0s_M_0111_N_0100,
	tst_rm_rn_M_0111_N_0100,
	and_rm_rn_M_0111_N_0100,
	xor_rm_rn_M_0111_N_0100,
	or_rm_rn_M_0111_N_0100,
	cmpstr_rm_rn_M_0111_N_0100,
	xtrct_M_0111_N_0100,
	mulu_w_M_0111_N_0100,
	muls_w_M_0111_N_0100,
	store_rm_rn_b_M_1000_N_0100,
	store_rm_rn_w_M_1000_N_0100,
	store_rm_rn_l_M_1000_N_0100,
	unimplemented,
	store_predec_rm_rn_b_M_1000_N_0100,
	store_predec_rm_rn_w_M_1000_N_0100,
	store_predec_rm_rn_l_M_1000_N_0100,
	div0s_M_1000_N_0100,
	tst_rm_rn_M_1000_N_0100,
	and_rm_rn_M_1000_N_0100,
	xor_rm_rn_M_1000_N_0100,
	or_rm_rn_M_1000_N_0100,
	cmpstr_rm_rn_M_1000_N_0100,
	xtrct_M_1000_N_0100,
	mulu_w_M_1000_N_0100,
	muls_w_M_1000_N_0100,
	store_rm_rn_b_M_1001_N_0100,
	store_rm_rn_w_M_1001_N_0100,
	store_rm_rn_l_M_1001_N_0100,
	unimplemented,
	store_predec_rm_rn_b_M_1001_N_0100,
	store_predec_rm_rn_w_M_1001_N_0100,
	store_predec_rm_rn_l_M_1001_N_0100,
	div0s_M_1001_N_0100,
	tst_rm_rn_M_1001_N_0100,
	and_rm_rn_M_1001_N_0100,
	xor_rm_rn_M_1001_N_0100,
	or_rm_rn_M_1001_N_0100,
	cmpstr_rm_rn_M_1001_N_0100,
	xtrct_M_1001_N_0100,
	mulu_w_M_1001_N_0100,
	muls_w_M_1001_N_0100,
	store_rm_rn_b_M_1010_N_0100,
	store_rm_rn_w_M_1010_N_0100,
	store_rm_rn_l_M_1010_N_0100,
	unimplemented,
	store_predec_rm_rn_b_M_1010_N_0100,
	store_predec_rm_rn_w_M_1010_N_0100,
	store_predec_rm_rn_l_M_1010_N_0100,
	div0s_M_1010_N_0100,
	tst_rm_rn_M_1010_N_0100,
	and_rm_rn_M_1010_N_0100,
	xor_rm_rn_M_1010_N_0100,
	or_rm_rn_M_1010_N_0100,
	cmpstr_rm_rn_M_1010_N_0100,
	xtrct_M_1010_N_0100,
	mulu_w_M_1010_N_0100,
	muls_w_M_1010_N_0100,
	store_rm_rn_b_M_1011_N_0100,
	store_rm_rn_w_M_1011_N_0100,
	store_rm_rn_l_M_1011_N_0100,
	unimplemented,
	store_predec_rm_rn_b_M_1011_N_0100,
	store_predec_rm_rn_w_M_1011_N_0100,
	store_predec_rm_rn_l_M_1011_N_0100,
	div0s_M_1011_N_0100,
	tst_rm_rn_M_1011_N_0100,
	and_rm_rn_M_1011_N_0100,
	xor_rm_rn_M_1011_N_0100,
	or_rm_rn_M_1011_N_0100,
	cmpstr_rm_rn_M_1011_N_0100,
	xtrct_M_1011_N_0100,
	mulu_w_M_1011_N_0100,
	muls_w_M_1011_N_0100,
	store_rm_rn_b_M_1100_N_0100,
	store_rm_rn_w_M_1100_N_0100,
	store_rm_rn_l_M_1100_N_0100,
	unimplemented,
	store_predec_rm_rn_b_M_1100_N_0100,
	store_predec_rm_rn_w_M_1100_N_0100,
	store_predec_rm_rn_l_M_1100_N_0100,
	div0s_M_1100_N_0100,
	tst_rm_rn_M_1100_N_0100,
	and_rm_rn_M_1100_N_0100,
	xor_rm_rn_M_1100_N_0100,
	or_rm_rn_M_1100_N_0100,
	cmpstr_rm_rn_M_1100_N_0100,
	xtrct_M_1100_N_0100,
	mulu_w_M_1100_N_0100,
	muls_w_M_1100_N_0100,
	store_rm_rn_b_M_1101_N_0100,
	store_rm_rn_w_M_1101_N_0100,
	store_rm_rn_l_M_1101_N_0100,
	unimplemented,
	store_predec_rm_rn_b_M_1101_N_0100,
	store_predec_rm_rn_w_M_1101_N_0100,
	store_predec_rm_rn_l_M_1101_N_0100,
	div0s_M_1101_N_0100,
	tst_rm_rn_M_1101_N_0100,
	and_rm_rn_M_1101_N_0100,
	xor_rm_rn_M_1101_N_0100,
	or_rm_rn_M_1101_N_0100,
	cmpstr_rm_rn_M_1101_N_0100,
	xtrct_M_1101_N_0100,
	mulu_w_M_1101_N_0100,
	muls_w_M_1101_N_0100,
	store_rm_rn_b_M_1110_N_0100,
	store_rm_rn_w_M_1110_N_0100,
	store_rm_rn_l_M_1110_N_0100,
	unimplemented,
	store_predec_rm_rn_b_M_1110_N_0100,
	store_predec_rm_rn_w_M_1110_N_0100,
	store_predec_rm_rn_l_M_1110_N_0100,
	div0s_M_1110_N_0100,
	tst_rm_rn_M_1110_N_0100,
	and_rm_rn_M_1110_N_0100,
	xor_rm_rn_M_1110_N_0100,
	or_rm_rn_M_1110_N_0100,
	cmpstr_rm_rn_M_1110_N_0100,
	xtrct_M_1110_N_0100,
	mulu_w_M_1110_N_0100,
	muls_w_M_1110_N_0100,
	store_rm_rn_b_M_1111_N_0100,
	store_rm_rn_w_M_1111_N_0100,
	store_rm_rn_l_M_1111_N_0100,
	unimplemented,
	store_predec_rm_rn_b_M_1111_N_0100,
	store_predec_rm_rn_w_M_1111_N_0100,
	store_predec_rm_rn_l_M_1111_N_0100,
	div0s_M_1111_N_0100,
	tst_rm_rn_M_1111_N_0100,
	and_rm_rn_M_1111_N_0100,
	xor_rm_rn_M_1111_N_0100,
	or_rm_rn_M_1111_N_0100,
	cmpstr_rm_rn_M_1111_N_0100,
	xtrct_M_1111_N_0100,
	mulu_w_M_1111_N_0100,
	muls_w_M_1111_N_0100,
	store_rm_rn_b_M_0000_N_0101,
	store_rm_rn_w_M_0000_N_0101,
	store_rm_rn_l_M_0000_N_0101,
	unimplemented,
	store_predec_rm_rn_b_M_0000_N_0101,
	store_predec_rm_rn_w_M_0000_N_0101,
	store_predec_rm_rn_l_M_0000_N_0101,
	div0s_M_0000_N_0101,
	tst_rm_rn_M_0000_N_0101,
	and_rm_rn_M_0000_N_0101,
	xor_rm_rn_M_0000_N_0101,
	or_rm_rn_M_0000_N_0101,
	cmpstr_rm_rn_M_0000_N_0101,
	xtrct_M_0000_N_0101,
	mulu_w_M_0000_N_0101,
	muls_w_M_0000_N_0101,
	store_rm_rn_b_M_0001_N_0101,
	store_rm_rn_w_M_0001_N_0101,
	store_rm_rn_l_M_0001_N_0101,
	unimplemented,
	store_predec_rm_rn_b_M_0001_N_0101,
	store_predec_rm_rn_w_M_0001_N_0101,
	store_predec_rm_rn_l_M_0001_N_0101,
	div0s_M_0001_N_0101,
	tst_rm_rn_M_0001_N_0101,
	and_rm_rn_M_0001_N_0101,
	xor_rm_rn_M_0001_N_0101,
	or_rm_rn_M_0001_N_0101,
	cmpstr_rm_rn_M_0001_N_0101,
	xtrct_M_0001_N_0101,
	mulu_w_M_0001_N_0101,
	muls_w_M_0001_N_0101,
	store_rm_rn_b_M_0010_N_0101,
	store_rm_rn_w_M_0010_N_0101,
	store_rm_rn_l_M_0010_N_0101,
	unimplemented,
	store_predec_rm_rn_b_M_0010_N_0101,
	store_predec_rm_rn_w_M_0010_N_0101,
	store_predec_rm_rn_l_M_0010_N_0101,
	div0s_M_0010_N_0101,
	tst_rm_rn_M_0010_N_0101,
	and_rm_rn_M_0010_N_0101,
	xor_rm_rn_M_0010_N_0101,
	or_rm_rn_M_0010_N_0101,
	cmpstr_rm_rn_M_0010_N_0101,
	xtrct_M_0010_N_0101,
	mulu_w_M_0010_N_0101,
	muls_w_M_0010_N_0101,
	store_rm_rn_b_M_0011_N_0101,
	store_rm_rn_w_M_0011_N_0101,
	store_rm_rn_l_M_0011_N_0101,
	unimplemented,
	store_predec_rm_rn_b_M_0011_N_0101,
	store_predec_rm_rn_w_M_0011_N_0101,
	store_predec_rm_rn_l_M_0011_N_0101,
	div0s_M_0011_N_0101,
	tst_rm_rn_M_0011_N_0101,
	and_rm_rn_M_0011_N_0101,
	xor_rm_rn_M_0011_N_0101,
	or_rm_rn_M_0011_N_0101,
	cmpstr_rm_rn_M_0011_N_0101,
	xtrct_M_0011_N_0101,
	mulu_w_M_0011_N_0101,
	muls_w_M_0011_N_0101,
	store_rm_rn_b_M_0100_N_0101,
	store_rm_rn_w_M_0100_N_0101,
	store_rm_rn_l_M_0100_N_0101,
	unimplemented,
	store_predec_rm_rn_b_M_0100_N_0101,
	store_predec_rm_rn_w_M_0100_N_0101,
	store_predec_rm_rn_l_M_0100_N_0101,
	div0s_M_0100_N_0101,
	tst_rm_rn_M_0100_N_0101,
	and_rm_rn_M_0100_N_0101,
	xor_rm_rn_M_0100_N_0101,
	or_rm_rn_M_0100_N_0101,
	cmpstr_rm_rn_M_0100_N_0101,
	xtrct_M_0100_N_0101,
	mulu_w_M_0100_N_0101,
	muls_w_M_0100_N_0101,
	store_rm_rn_b_M_0101_N_0101,
	store_rm_rn_w_M_0101_N_0101,
	store_rm_rn_l_M_0101_N_0101,
	unimplemented,
	store_predec_rm_rn_b_M_0101_N_0101,
	store_predec_rm_rn_w_M_0101_N_0101,
	store_predec_rm_rn_l_M_0101_N_0101,
	div0s_M_0101_N_0101,
	tst_rm_rn_M_0101_N_0101,
	and_rm_rn_M_0101_N_0101,
	xor_rm_rn_M_0101_N_0101,
	or_rm_rn_M_0101_N_0101,
	cmpstr_rm_rn_M_0101_N_0101,
	xtrct_M_0101_N_0101,
	mulu_w_M_0101_N_0101,
	muls_w_M_0101_N_0101,
	store_rm_rn_b_M_0110_N_0101,
	store_rm_rn_w_M_0110_N_0101,
	store_rm_rn_l_M_0110_N_0101,
	unimplemented,
	store_predec_rm_rn_b_M_0110_N_0101,
	store_predec_rm_rn_w_M_0110_N_0101,
	store_predec_rm_rn_l_M_0110_N_0101,
	div0s_M_0110_N_0101,
	tst_rm_rn_M_0110_N_0101,
	and_rm_rn_M_0110_N_0101,
	xor_rm_rn_M_0110_N_0101,
	or_rm_rn_M_0110_N_0101,
	cmpstr_rm_rn_M_0110_N_0101,
	xtrct_M_0110_N_0101,
	mulu_w_M_0110_N_0101,
	muls_w_M_0110_N_0101,
	store_rm_rn_b_M_0111_N_0101,
	store_rm_rn_w_M_0111_N_0101,
	store_rm_rn_l_M_0111_N_0101,
	unimplemented,
	store_predec_rm_rn_b_M_0111_N_0101,
	store_predec_rm_rn_w_M_0111_N_0101,
	store_predec_rm_rn_l_M_0111_N_0101,
	div0s_M_0111_N_0101,
	tst_rm_rn_M_0111_N_0101,
	and_rm_rn_M_0111_N_0101,
	xor_rm_rn_M_0111_N_0101,
	or_rm_rn_M_0111_N_0101,
	cmpstr_rm_rn_M_0111_N_0101,
	xtrct_M_0111_N_0101,
	mulu_w_M_0111_N_0101,
	muls_w_M_0111_N_0101,
	store_rm_rn_b_M_1000_N_0101,
	store_rm_rn_w_M_1000_N_0101,
	store_rm_rn_l_M_1000_N_0101,
	unimplemented,
	store_predec_rm_rn_b_M_1000_N_0101,
	store_predec_rm_rn_w_M_1000_N_0101,
	store_predec_rm_rn_l_M_1000_N_0101,
	div0s_M_1000_N_0101,
	tst_rm_rn_M_1000_N_0101,
	and_rm_rn_M_1000_N_0101,
	xor_rm_rn_M_1000_N_0101,
	or_rm_rn_M_1000_N_0101,
	cmpstr_rm_rn_M_1000_N_0101,
	xtrct_M_1000_N_0101,
	mulu_w_M_1000_N_0101,
	muls_w_M_1000_N_0101,
	store_rm_rn_b_M_1001_N_0101,
	store_rm_rn_w_M_1001_N_0101,
	store_rm_rn_l_M_1001_N_0101,
	unimplemented,
	store_predec_rm_rn_b_M_1001_N_0101,
	store_predec_rm_rn_w_M_1001_N_0101,
	store_predec_rm_rn_l_M_1001_N_0101,
	div0s_M_1001_N_0101,
	tst_rm_rn_M_1001_N_0101,
	and_rm_rn_M_1001_N_0101,
	xor_rm_rn_M_1001_N_0101,
	or_rm_rn_M_1001_N_0101,
	cmpstr_rm_rn_M_1001_N_0101,
	xtrct_M_1001_N_0101,
	mulu_w_M_1001_N_0101,
	muls_w_M_1001_N_0101,
	store_rm_rn_b_M_1010_N_0101,
	store_rm_rn_w_M_1010_N_0101,
	store_rm_rn_l_M_1010_N_0101,
	unimplemented,
	store_predec_rm_rn_b_M_1010_N_0101,
	store_predec_rm_rn_w_M_1010_N_0101,
	store_predec_rm_rn_l_M_1010_N_0101,
	div0s_M_1010_N_0101,
	tst_rm_rn_M_1010_N_0101,
	and_rm_rn_M_1010_N_0101,
	xor_rm_rn_M_1010_N_0101,
	or_rm_rn_M_1010_N_0101,
	cmpstr_rm_rn_M_1010_N_0101,
	xtrct_M_1010_N_0101,
	mulu_w_M_1010_N_0101,
	muls_w_M_1010_N_0101,
	store_rm_rn_b_M_1011_N_0101,
	store_rm_rn_w_M_1011_N_0101,
	store_rm_rn_l_M_1011_N_0101,
	unimplemented,
	store_predec_rm_rn_b_M_1011_N_0101,
	store_predec_rm_rn_w_M_1011_N_0101,
	store_predec_rm_rn_l_M_1011_N_0101,
	div0s_M_1011_N_0101,
	tst_rm_rn_M_1011_N_0101,
	and_rm_rn_M_1011_N_0101,
	xor_rm_rn_M_1011_N_0101,
	or_rm_rn_M_1011_N_0101,
	cmpstr_rm_rn_M_1011_N_0101,
	xtrct_M_1011_N_0101,
	mulu_w_M_1011_N_0101,
	muls_w_M_1011_N_0101,
	store_rm_rn_b_M_1100_N_0101,
	store_rm_rn_w_M_1100_N_0101,
	store_rm_rn_l_M_1100_N_0101,
	unimplemented,
	store_predec_rm_rn_b_M_1100_N_0101,
	store_predec_rm_rn_w_M_1100_N_0101,
	store_predec_rm_rn_l_M_1100_N_0101,
	div0s_M_1100_N_0101,
	tst_rm_rn_M_1100_N_0101,
	and_rm_rn_M_1100_N_0101,
	xor_rm_rn_M_1100_N_0101,
	or_rm_rn_M_1100_N_0101,
	cmpstr_rm_rn_M_1100_N_0101,
	xtrct_M_1100_N_0101,
	mulu_w_M_1100_N_0101,
	muls_w_M_1100_N_0101,
	store_rm_rn_b_M_1101_N_0101,
	store_rm_rn_w_M_1101_N_0101,
	store_rm_rn_l_M_1101_N_0101,
	unimplemented,
	store_predec_rm_rn_b_M_1101_N_0101,
	store_predec_rm_rn_w_M_1101_N_0101,
	store_predec_rm_rn_l_M_1101_N_0101,
	div0s_M_1101_N_0101,
	tst_rm_rn_M_1101_N_0101,
	and_rm_rn_M_1101_N_0101,
	xor_rm_rn_M_1101_N_0101,
	or_rm_rn_M_1101_N_0101,
	cmpstr_rm_rn_M_1101_N_0101,
	xtrct_M_1101_N_0101,
	mulu_w_M_1101_N_0101,
	muls_w_M_1101_N_0101,
	store_rm_rn_b_M_1110_N_0101,
	store_rm_rn_w_M_1110_N_0101,
	store_rm_rn_l_M_1110_N_0101,
	unimplemented,
	store_predec_rm_rn_b_M_1110_N_0101,
	store_predec_rm_rn_w_M_1110_N_0101,
	store_predec_rm_rn_l_M_1110_N_0101,
	div0s_M_1110_N_0101,
	tst_rm_rn_M_1110_N_0101,
	and_rm_rn_M_1110_N_0101,
	xor_rm_rn_M_1110_N_0101,
	or_rm_rn_M_1110_N_0101,
	cmpstr_rm_rn_M_1110_N_0101,
	xtrct_M_1110_N_0101,
	mulu_w_M_1110_N_0101,
	muls_w_M_1110_N_0101,
	store_rm_rn_b_M_1111_N_0101,
	store_rm_rn_w_M_1111_N_0101,
	store_rm_rn_l_M_1111_N_0101,
	unimplemented,
	store_predec_rm_rn_b_M_1111_N_0101,
	store_predec_rm_rn_w_M_1111_N_0101,
	store_predec_rm_rn_l_M_1111_N_0101,
	div0s_M_1111_N_0101,
	tst_rm_rn_M_1111_N_0101,
	and_rm_rn_M_1111_N_0101,
	xor_rm_rn_M_1111_N_0101,
	or_rm_rn_M_1111_N_0101,
	cmpstr_rm_rn_M_1111_N_0101,
	xtrct_M_1111_N_0101,
	mulu_w_M_1111_N_0101,
	muls_w_M_1111_N_0101,
	store_rm_rn_b_M_0000_N_0110,
	store_rm_rn_w_M_0000_N_0110,
	store_rm_rn_l_M_0000_N_0110,
	unimplemented,
	store_predec_rm_rn_b_M_0000_N_0110,
	store_predec_rm_rn_w_M_0000_N_0110,
	store_predec_rm_rn_l_M_0000_N_0110,
	div0s_M_0000_N_0110,
	tst_rm_rn_M_0000_N_0110,
	and_rm_rn_M_0000_N_0110,
	xor_rm_rn_M_0000_N_0110,
	or_rm_rn_M_0000_N_0110,
	cmpstr_rm_rn_M_0000_N_0110,
	xtrct_M_0000_N_0110,
	mulu_w_M_0000_N_0110,
	muls_w_M_0000_N_0110,
	store_rm_rn_b_M_0001_N_0110,
	store_rm_rn_w_M_0001_N_0110,
	store_rm_rn_l_M_0001_N_0110,
	unimplemented,
	store_predec_rm_rn_b_M_0001_N_0110,
	store_predec_rm_rn_w_M_0001_N_0110,
	store_predec_rm_rn_l_M_0001_N_0110,
	div0s_M_0001_N_0110,
	tst_rm_rn_M_0001_N_0110,
	and_rm_rn_M_0001_N_0110,
	xor_rm_rn_M_0001_N_0110,
	or_rm_rn_M_0001_N_0110,
	cmpstr_rm_rn_M_0001_N_0110,
	xtrct_M_0001_N_0110,
	mulu_w_M_0001_N_0110,
	muls_w_M_0001_N_0110,
	store_rm_rn_b_M_0010_N_0110,
	store_rm_rn_w_M_0010_N_0110,
	store_rm_rn_l_M_0010_N_0110,
	unimplemented,
	store_predec_rm_rn_b_M_0010_N_0110,
	store_predec_rm_rn_w_M_0010_N_0110,
	store_predec_rm_rn_l_M_0010_N_0110,
	div0s_M_0010_N_0110,
	tst_rm_rn_M_0010_N_0110,
	and_rm_rn_M_0010_N_0110,
	xor_rm_rn_M_0010_N_0110,
	or_rm_rn_M_0010_N_0110,
	cmpstr_rm_rn_M_0010_N_0110,
	xtrct_M_0010_N_0110,
	mulu_w_M_0010_N_0110,
	muls_w_M_0010_N_0110,
	store_rm_rn_b_M_0011_N_0110,
	store_rm_rn_w_M_0011_N_0110,
	store_rm_rn_l_M_0011_N_0110,
	unimplemented,
	store_predec_rm_rn_b_M_0011_N_0110,
	store_predec_rm_rn_w_M_0011_N_0110,
	store_predec_rm_rn_l_M_0011_N_0110,
	div0s_M_0011_N_0110,
	tst_rm_rn_M_0011_N_0110,
	and_rm_rn_M_0011_N_0110,
	xor_rm_rn_M_0011_N_0110,
	or_rm_rn_M_0011_N_0110,
	cmpstr_rm_rn_M_0011_N_0110,
	xtrct_M_0011_N_0110,
	mulu_w_M_0011_N_0110,
	muls_w_M_0011_N_0110,
	store_rm_rn_b_M_0100_N_0110,
	store_rm_rn_w_M_0100_N_0110,
	store_rm_rn_l_M_0100_N_0110,
	unimplemented,
	store_predec_rm_rn_b_M_0100_N_0110,
	store_predec_rm_rn_w_M_0100_N_0110,
	store_predec_rm_rn_l_M_0100_N_0110,
	div0s_M_0100_N_0110,
	tst_rm_rn_M_0100_N_0110,
	and_rm_rn_M_0100_N_0110,
	xor_rm_rn_M_0100_N_0110,
	or_rm_rn_M_0100_N_0110,
	cmpstr_rm_rn_M_0100_N_0110,
	xtrct_M_0100_N_0110,
	mulu_w_M_0100_N_0110,
	muls_w_M_0100_N_0110,
	store_rm_rn_b_M_0101_N_0110,
	store_rm_rn_w_M_0101_N_0110,
	store_rm_rn_l_M_0101_N_0110,
	unimplemented,
	store_predec_rm_rn_b_M_0101_N_0110,
	store_predec_rm_rn_w_M_0101_N_0110,
	store_predec_rm_rn_l_M_0101_N_0110,
	div0s_M_0101_N_0110,
	tst_rm_rn_M_0101_N_0110,
	and_rm_rn_M_0101_N_0110,
	xor_rm_rn_M_0101_N_0110,
	or_rm_rn_M_0101_N_0110,
	cmpstr_rm_rn_M_0101_N_0110,
	xtrct_M_0101_N_0110,
	mulu_w_M_0101_N_0110,
	muls_w_M_0101_N_0110,
	store_rm_rn_b_M_0110_N_0110,
	store_rm_rn_w_M_0110_N_0110,
	store_rm_rn_l_M_0110_N_0110,
	unimplemented,
	store_predec_rm_rn_b_M_0110_N_0110,
	store_predec_rm_rn_w_M_0110_N_0110,
	store_predec_rm_rn_l_M_0110_N_0110,
	div0s_M_0110_N_0110,
	tst_rm_rn_M_0110_N_0110,
	and_rm_rn_M_0110_N_0110,
	xor_rm_rn_M_0110_N_0110,
	or_rm_rn_M_0110_N_0110,
	cmpstr_rm_rn_M_0110_N_0110,
	xtrct_M_0110_N_0110,
	mulu_w_M_0110_N_0110,
	muls_w_M_0110_N_0110,
	store_rm_rn_b_M_0111_N_0110,
	store_rm_rn_w_M_0111_N_0110,
	store_rm_rn_l_M_0111_N_0110,
	unimplemented,
	store_predec_rm_rn_b_M_0111_N_0110,
	store_predec_rm_rn_w_M_0111_N_0110,
	store_predec_rm_rn_l_M_0111_N_0110,
	div0s_M_0111_N_0110,
	tst_rm_rn_M_0111_N_0110,
	and_rm_rn_M_0111_N_0110,
	xor_rm_rn_M_0111_N_0110,
	or_rm_rn_M_0111_N_0110,
	cmpstr_rm_rn_M_0111_N_0110,
	xtrct_M_0111_N_0110,
	mulu_w_M_0111_N_0110,
	muls_w_M_0111_N_0110,
	store_rm_rn_b_M_1000_N_0110,
	store_rm_rn_w_M_1000_N_0110,
	store_rm_rn_l_M_1000_N_0110,
	unimplemented,
	store_predec_rm_rn_b_M_1000_N_0110,
	store_predec_rm_rn_w_M_1000_N_0110,
	store_predec_rm_rn_l_M_1000_N_0110,
	div0s_M_1000_N_0110,
	tst_rm_rn_M_1000_N_0110,
	and_rm_rn_M_1000_N_0110,
	xor_rm_rn_M_1000_N_0110,
	or_rm_rn_M_1000_N_0110,
	cmpstr_rm_rn_M_1000_N_0110,
	xtrct_M_1000_N_0110,
	mulu_w_M_1000_N_0110,
	muls_w_M_1000_N_0110,
	store_rm_rn_b_M_1001_N_0110,
	store_rm_rn_w_M_1001_N_0110,
	store_rm_rn_l_M_1001_N_0110,
	unimplemented,
	store_predec_rm_rn_b_M_1001_N_0110,
	store_predec_rm_rn_w_M_1001_N_0110,
	store_predec_rm_rn_l_M_1001_N_0110,
	div0s_M_1001_N_0110,
	tst_rm_rn_M_1001_N_0110,
	and_rm_rn_M_1001_N_0110,
	xor_rm_rn_M_1001_N_0110,
	or_rm_rn_M_1001_N_0110,
	cmpstr_rm_rn_M_1001_N_0110,
	xtrct_M_1001_N_0110,
	mulu_w_M_1001_N_0110,
	muls_w_M_1001_N_0110,
	store_rm_rn_b_M_1010_N_0110,
	store_rm_rn_w_M_1010_N_0110,
	store_rm_rn_l_M_1010_N_0110,
	unimplemented,
	store_predec_rm_rn_b_M_1010_N_0110,
	store_predec_rm_rn_w_M_1010_N_0110,
	store_predec_rm_rn_l_M_1010_N_0110,
	div0s_M_1010_N_0110,
	tst_rm_rn_M_1010_N_0110,
	and_rm_rn_M_1010_N_0110,
	xor_rm_rn_M_1010_N_0110,
	or_rm_rn_M_1010_N_0110,
	cmpstr_rm_rn_M_1010_N_0110,
	xtrct_M_1010_N_0110,
	mulu_w_M_1010_N_0110,
	muls_w_M_1010_N_0110,
	store_rm_rn_b_M_1011_N_0110,
	store_rm_rn_w_M_1011_N_0110,
	store_rm_rn_l_M_1011_N_0110,
	unimplemented,
	store_predec_rm_rn_b_M_1011_N_0110,
	store_predec_rm_rn_w_M_1011_N_0110,
	store_predec_rm_rn_l_M_1011_N_0110,
	div0s_M_1011_N_0110,
	tst_rm_rn_M_1011_N_0110,
	and_rm_rn_M_1011_N_0110,
	xor_rm_rn_M_1011_N_0110,
	or_rm_rn_M_1011_N_0110,
	cmpstr_rm_rn_M_1011_N_0110,
	xtrct_M_1011_N_0110,
	mulu_w_M_1011_N_0110,
	muls_w_M_1011_N_0110,
	store_rm_rn_b_M_1100_N_0110,
	store_rm_rn_w_M_1100_N_0110,
	store_rm_rn_l_M_1100_N_0110,
	unimplemented,
	store_predec_rm_rn_b_M_1100_N_0110,
	store_predec_rm_rn_w_M_1100_N_0110,
	store_predec_rm_rn_l_M_1100_N_0110,
	div0s_M_1100_N_0110,
	tst_rm_rn_M_1100_N_0110,
	and_rm_rn_M_1100_N_0110,
	xor_rm_rn_M_1100_N_0110,
	or_rm_rn_M_1100_N_0110,
	cmpstr_rm_rn_M_1100_N_0110,
	xtrct_M_1100_N_0110,
	mulu_w_M_1100_N_0110,
	muls_w_M_1100_N_0110,
	store_rm_rn_b_M_1101_N_0110,
	store_rm_rn_w_M_1101_N_0110,
	store_rm_rn_l_M_1101_N_0110,
	unimplemented,
	store_predec_rm_rn_b_M_1101_N_0110,
	store_predec_rm_rn_w_M_1101_N_0110,
	store_predec_rm_rn_l_M_1101_N_0110,
	div0s_M_1101_N_0110,
	tst_rm_rn_M_1101_N_0110,
	and_rm_rn_M_1101_N_0110,
	xor_rm_rn_M_1101_N_0110,
	or_rm_rn_M_1101_N_0110,
	cmpstr_rm_rn_M_1101_N_0110,
	xtrct_M_1101_N_0110,
	mulu_w_M_1101_N_0110,
	muls_w_M_1101_N_0110,
	store_rm_rn_b_M_1110_N_0110,
	store_rm_rn_w_M_1110_N_0110,
	store_rm_rn_l_M_1110_N_0110,
	unimplemented,
	store_predec_rm_rn_b_M_1110_N_0110,
	store_predec_rm_rn_w_M_1110_N_0110,
	store_predec_rm_rn_l_M_1110_N_0110,
	div0s_M_1110_N_0110,
	tst_rm_rn_M_1110_N_0110,
	and_rm_rn_M_1110_N_0110,
	xor_rm_rn_M_1110_N_0110,
	or_rm_rn_M_1110_N_0110,
	cmpstr_rm_rn_M_1110_N_0110,
	xtrct_M_1110_N_0110,
	mulu_w_M_1110_N_0110,
	muls_w_M_1110_N_0110,
	store_rm_rn_b_M_1111_N_0110,
	store_rm_rn_w_M_1111_N_0110,
	store_rm_rn_l_M_1111_N_0110,
	unimplemented,
	store_predec_rm_rn_b_M_1111_N_0110,
	store_predec_rm_rn_w_M_1111_N_0110,
	store_predec_rm_rn_l_M_1111_N_0110,
	div0s_M_1111_N_0110,
	tst_rm_rn_M_1111_N_0110,
	and_rm_rn_M_1111_N_0110,
	xor_rm_rn_M_1111_N_0110,
	or_rm_rn_M_1111_N_0110,
	cmpstr_rm_rn_M_1111_N_0110,
	xtrct_M_1111_N_0110,
	mulu_w_M_1111_N_0110,
	muls_w_M_1111_N_0110,
	store_rm_rn_b_M_0000_N_0111,
	store_rm_rn_w_M_0000_N_0111,
	store_rm_rn_l_M_0000_N_0111,
	unimplemented,
	store_predec_rm_rn_b_M_0000_N_0111,
	store_predec_rm_rn_w_M_0000_N_0111,
	store_predec_rm_rn_l_M_0000_N_0111,
	div0s_M_0000_N_0111,
	tst_rm_rn_M_0000_N_0111,
	and_rm_rn_M_0000_N_0111,
	xor_rm_rn_M_0000_N_0111,
	or_rm_rn_M_0000_N_0111,
	cmpstr_rm_rn_M_0000_N_0111,
	xtrct_M_0000_N_0111,
	mulu_w_M_0000_N_0111,
	muls_w_M_0000_N_0111,
	store_rm_rn_b_M_0001_N_0111,
	store_rm_rn_w_M_0001_N_0111,
	store_rm_rn_l_M_0001_N_0111,
	unimplemented,
	store_predec_rm_rn_b_M_0001_N_0111,
	store_predec_rm_rn_w_M_0001_N_0111,
	store_predec_rm_rn_l_M_0001_N_0111,
	div0s_M_0001_N_0111,
	tst_rm_rn_M_0001_N_0111,
	and_rm_rn_M_0001_N_0111,
	xor_rm_rn_M_0001_N_0111,
	or_rm_rn_M_0001_N_0111,
	cmpstr_rm_rn_M_0001_N_0111,
	xtrct_M_0001_N_0111,
	mulu_w_M_0001_N_0111,
	muls_w_M_0001_N_0111,
	store_rm_rn_b_M_0010_N_0111,
	store_rm_rn_w_M_0010_N_0111,
	store_rm_rn_l_M_0010_N_0111,
	unimplemented,
	store_predec_rm_rn_b_M_0010_N_0111,
	store_predec_rm_rn_w_M_0010_N_0111,
	store_predec_rm_rn_l_M_0010_N_0111,
	div0s_M_0010_N_0111,
	tst_rm_rn_M_0010_N_0111,
	and_rm_rn_M_0010_N_0111,
	xor_rm_rn_M_0010_N_0111,
	or_rm_rn_M_0010_N_0111,
	cmpstr_rm_rn_M_0010_N_0111,
	xtrct_M_0010_N_0111,
	mulu_w_M_0010_N_0111,
	muls_w_M_0010_N_0111,
	store_rm_rn_b_M_0011_N_0111,
	store_rm_rn_w_M_0011_N_0111,
	store_rm_rn_l_M_0011_N_0111,
	unimplemented,
	store_predec_rm_rn_b_M_0011_N_0111,
	store_predec_rm_rn_w_M_0011_N_0111,
	store_predec_rm_rn_l_M_0011_N_0111,
	div0s_M_0011_N_0111,
	tst_rm_rn_M_0011_N_0111,
	and_rm_rn_M_0011_N_0111,
	xor_rm_rn_M_0011_N_0111,
	or_rm_rn_M_0011_N_0111,
	cmpstr_rm_rn_M_0011_N_0111,
	xtrct_M_0011_N_0111,
	mulu_w_M_0011_N_0111,
	muls_w_M_0011_N_0111,
	store_rm_rn_b_M_0100_N_0111,
	store_rm_rn_w_M_0100_N_0111,
	store_rm_rn_l_M_0100_N_0111,
	unimplemented,
	store_predec_rm_rn_b_M_0100_N_0111,
	store_predec_rm_rn_w_M_0100_N_0111,
	store_predec_rm_rn_l_M_0100_N_0111,
	div0s_M_0100_N_0111,
	tst_rm_rn_M_0100_N_0111,
	and_rm_rn_M_0100_N_0111,
	xor_rm_rn_M_0100_N_0111,
	or_rm_rn_M_0100_N_0111,
	cmpstr_rm_rn_M_0100_N_0111,
	xtrct_M_0100_N_0111,
	mulu_w_M_0100_N_0111,
	muls_w_M_0100_N_0111,
	store_rm_rn_b_M_0101_N_0111,
	store_rm_rn_w_M_0101_N_0111,
	store_rm_rn_l_M_0101_N_0111,
	unimplemented,
	store_predec_rm_rn_b_M_0101_N_0111,
	store_predec_rm_rn_w_M_0101_N_0111,
	store_predec_rm_rn_l_M_0101_N_0111,
	div0s_M_0101_N_0111,
	tst_rm_rn_M_0101_N_0111,
	and_rm_rn_M_0101_N_0111,
	xor_rm_rn_M_0101_N_0111,
	or_rm_rn_M_0101_N_0111,
	cmpstr_rm_rn_M_0101_N_0111,
	xtrct_M_0101_N_0111,
	mulu_w_M_0101_N_0111,
	muls_w_M_0101_N_0111,
	store_rm_rn_b_M_0110_N_0111,
	store_rm_rn_w_M_0110_N_0111,
	store_rm_rn_l_M_0110_N_0111,
	unimplemented,
	store_predec_rm_rn_b_M_0110_N_0111,
	store_predec_rm_rn_w_M_0110_N_0111,
	store_predec_rm_rn_l_M_0110_N_0111,
	div0s_M_0110_N_0111,
	tst_rm_rn_M_0110_N_0111,
	and_rm_rn_M_0110_N_0111,
	xor_rm_rn_M_0110_N_0111,
	or_rm_rn_M_0110_N_0111,
	cmpstr_rm_rn_M_0110_N_0111,
	xtrct_M_0110_N_0111,
	mulu_w_M_0110_N_0111,
	muls_w_M_0110_N_0111,
	store_rm_rn_b_M_0111_N_0111,
	store_rm_rn_w_M_0111_N_0111,
	store_rm_rn_l_M_0111_N_0111,
	unimplemented,
	store_predec_rm_rn_b_M_0111_N_0111,
	store_predec_rm_rn_w_M_0111_N_0111,
	store_predec_rm_rn_l_M_0111_N_0111,
	div0s_M_0111_N_0111,
	tst_rm_rn_M_0111_N_0111,
	and_rm_rn_M_0111_N_0111,
	xor_rm_rn_M_0111_N_0111,
	or_rm_rn_M_0111_N_0111,
	cmpstr_rm_rn_M_0111_N_0111,
	xtrct_M_0111_N_0111,
	mulu_w_M_0111_N_0111,
	muls_w_M_0111_N_0111,
	store_rm_rn_b_M_1000_N_0111,
	store_rm_rn_w_M_1000_N_0111,
	store_rm_rn_l_M_1000_N_0111,
	unimplemented,
	store_predec_rm_rn_b_M_1000_N_0111,
	store_predec_rm_rn_w_M_1000_N_0111,
	store_predec_rm_rn_l_M_1000_N_0111,
	div0s_M_1000_N_0111,
	tst_rm_rn_M_1000_N_0111,
	and_rm_rn_M_1000_N_0111,
	xor_rm_rn_M_1000_N_0111,
	or_rm_rn_M_1000_N_0111,
	cmpstr_rm_rn_M_1000_N_0111,
	xtrct_M_1000_N_0111,
	mulu_w_M_1000_N_0111,
	muls_w_M_1000_N_0111,
	store_rm_rn_b_M_1001_N_0111,
	store_rm_rn_w_M_1001_N_0111,
	store_rm_rn_l_M_1001_N_0111,
	unimplemented,
	store_predec_rm_rn_b_M_1001_N_0111,
	store_predec_rm_rn_w_M_1001_N_0111,
	store_predec_rm_rn_l_M_1001_N_0111,
	div0s_M_1001_N_0111,
	tst_rm_rn_M_1001_N_0111,
	and_rm_rn_M_1001_N_0111,
	xor_rm_rn_M_1001_N_0111,
	or_rm_rn_M_1001_N_0111,
	cmpstr_rm_rn_M_1001_N_0111,
	xtrct_M_1001_N_0111,
	mulu_w_M_1001_N_0111,
	muls_w_M_1001_N_0111,
	store_rm_rn_b_M_1010_N_0111,
	store_rm_rn_w_M_1010_N_0111,
	store_rm_rn_l_M_1010_N_0111,
	unimplemented,
	store_predec_rm_rn_b_M_1010_N_0111,
	store_predec_rm_rn_w_M_1010_N_0111,
	store_predec_rm_rn_l_M_1010_N_0111,
	div0s_M_1010_N_0111,
	tst_rm_rn_M_1010_N_0111,
	and_rm_rn_M_1010_N_0111,
	xor_rm_rn_M_1010_N_0111,
	or_rm_rn_M_1010_N_0111,
	cmpstr_rm_rn_M_1010_N_0111,
	xtrct_M_1010_N_0111,
	mulu_w_M_1010_N_0111,
	muls_w_M_1010_N_0111,
	store_rm_rn_b_M_1011_N_0111,
	store_rm_rn_w_M_1011_N_0111,
	store_rm_rn_l_M_1011_N_0111,
	unimplemented,
	store_predec_rm_rn_b_M_1011_N_0111,
	store_predec_rm_rn_w_M_1011_N_0111,
	store_predec_rm_rn_l_M_1011_N_0111,
	div0s_M_1011_N_0111,
	tst_rm_rn_M_1011_N_0111,
	and_rm_rn_M_1011_N_0111,
	xor_rm_rn_M_1011_N_0111,
	or_rm_rn_M_1011_N_0111,
	cmpstr_rm_rn_M_1011_N_0111,
	xtrct_M_1011_N_0111,
	mulu_w_M_1011_N_0111,
	muls_w_M_1011_N_0111,
	store_rm_rn_b_M_1100_N_0111,
	store_rm_rn_w_M_1100_N_0111,
	store_rm_rn_l_M_1100_N_0111,
	unimplemented,
	store_predec_rm_rn_b_M_1100_N_0111,
	store_predec_rm_rn_w_M_1100_N_0111,
	store_predec_rm_rn_l_M_1100_N_0111,
	div0s_M_1100_N_0111,
	tst_rm_rn_M_1100_N_0111,
	and_rm_rn_M_1100_N_0111,
	xor_rm_rn_M_1100_N_0111,
	or_rm_rn_M_1100_N_0111,
	cmpstr_rm_rn_M_1100_N_0111,
	xtrct_M_1100_N_0111,
	mulu_w_M_1100_N_0111,
	muls_w_M_1100_N_0111,
	store_rm_rn_b_M_1101_N_0111,
	store_rm_rn_w_M_1101_N_0111,
	store_rm_rn_l_M_1101_N_0111,
	unimplemented,
	store_predec_rm_rn_b_M_1101_N_0111,
	store_predec_rm_rn_w_M_1101_N_0111,
	store_predec_rm_rn_l_M_1101_N_0111,
	div0s_M_1101_N_0111,
	tst_rm_rn_M_1101_N_0111,
	and_rm_rn_M_1101_N_0111,
	xor_rm_rn_M_1101_N_0111,
	or_rm_rn_M_1101_N_0111,
	cmpstr_rm_rn_M_1101_N_0111,
	xtrct_M_1101_N_0111,
	mulu_w_M_1101_N_0111,
	muls_w_M_1101_N_0111,
	store_rm_rn_b_M_1110_N_0111,
	store_rm_rn_w_M_1110_N_0111,
	store_rm_rn_l_M_1110_N_0111,
	unimplemented,
	store_predec_rm_rn_b_M_1110_N_0111,
	store_predec_rm_rn_w_M_1110_N_0111,
	store_predec_rm_rn_l_M_1110_N_0111,
	div0s_M_1110_N_0111,
	tst_rm_rn_M_1110_N_0111,
	and_rm_rn_M_1110_N_0111,
	xor_rm_rn_M_1110_N_0111,
	or_rm_rn_M_1110_N_0111,
	cmpstr_rm_rn_M_1110_N_0111,
	xtrct_M_1110_N_0111,
	mulu_w_M_1110_N_0111,
	muls_w_M_1110_N_0111,
	store_rm_rn_b_M_1111_N_0111,
	store_rm_rn_w_M_1111_N_0111,
	store_rm_rn_l_M_1111_N_0111,
	unimplemented,
	store_predec_rm_rn_b_M_1111_N_0111,
	store_predec_rm_rn_w_M_1111_N_0111,
	store_predec_rm_rn_l_M_1111_N_0111,
	div0s_M_1111_N_0111,
	tst_rm_rn_M_1111_N_0111,
	and_rm_rn_M_1111_N_0111,
	xor_rm_rn_M_1111_N_0111,
	or_rm_rn_M_1111_N_0111,
	cmpstr_rm_rn_M_1111_N_0111,
	xtrct_M_1111_N_0111,
	mulu_w_M_1111_N_0111,
	muls_w_M_1111_N_0111,
	store_rm_rn_b_M_0000_N_1000,
	store_rm_rn_w_M_0000_N_1000,
	store_rm_rn_l_M_0000_N_1000,
	unimplemented,
	store_predec_rm_rn_b_M_0000_N_1000,
	store_predec_rm_rn_w_M_0000_N_1000,
	store_predec_rm_rn_l_M_0000_N_1000,
	div0s_M_0000_N_1000,
	tst_rm_rn_M_0000_N_1000,
	and_rm_rn_M_0000_N_1000,
	xor_rm_rn_M_0000_N_1000,
	or_rm_rn_M_0000_N_1000,
	cmpstr_rm_rn_M_0000_N_1000,
	xtrct_M_0000_N_1000,
	mulu_w_M_0000_N_1000,
	muls_w_M_0000_N_1000,
	store_rm_rn_b_M_0001_N_1000,
	store_rm_rn_w_M_0001_N_1000,
	store_rm_rn_l_M_0001_N_1000,
	unimplemented,
	store_predec_rm_rn_b_M_0001_N_1000,
	store_predec_rm_rn_w_M_0001_N_1000,
	store_predec_rm_rn_l_M_0001_N_1000,
	div0s_M_0001_N_1000,
	tst_rm_rn_M_0001_N_1000,
	and_rm_rn_M_0001_N_1000,
	xor_rm_rn_M_0001_N_1000,
	or_rm_rn_M_0001_N_1000,
	cmpstr_rm_rn_M_0001_N_1000,
	xtrct_M_0001_N_1000,
	mulu_w_M_0001_N_1000,
	muls_w_M_0001_N_1000,
	store_rm_rn_b_M_0010_N_1000,
	store_rm_rn_w_M_0010_N_1000,
	store_rm_rn_l_M_0010_N_1000,
	unimplemented,
	store_predec_rm_rn_b_M_0010_N_1000,
	store_predec_rm_rn_w_M_0010_N_1000,
	store_predec_rm_rn_l_M_0010_N_1000,
	div0s_M_0010_N_1000,
	tst_rm_rn_M_0010_N_1000,
	and_rm_rn_M_0010_N_1000,
	xor_rm_rn_M_0010_N_1000,
	or_rm_rn_M_0010_N_1000,
	cmpstr_rm_rn_M_0010_N_1000,
	xtrct_M_0010_N_1000,
	mulu_w_M_0010_N_1000,
	muls_w_M_0010_N_1000,
	store_rm_rn_b_M_0011_N_1000,
	store_rm_rn_w_M_0011_N_1000,
	store_rm_rn_l_M_0011_N_1000,
	unimplemented,
	store_predec_rm_rn_b_M_0011_N_1000,
	store_predec_rm_rn_w_M_0011_N_1000,
	store_predec_rm_rn_l_M_0011_N_1000,
	div0s_M_0011_N_1000,
	tst_rm_rn_M_0011_N_1000,
	and_rm_rn_M_0011_N_1000,
	xor_rm_rn_M_0011_N_1000,
	or_rm_rn_M_0011_N_1000,
	cmpstr_rm_rn_M_0011_N_1000,
	xtrct_M_0011_N_1000,
	mulu_w_M_0011_N_1000,
	muls_w_M_0011_N_1000,
	store_rm_rn_b_M_0100_N_1000,
	store_rm_rn_w_M_0100_N_1000,
	store_rm_rn_l_M_0100_N_1000,
	unimplemented,
	store_predec_rm_rn_b_M_0100_N_1000,
	store_predec_rm_rn_w_M_0100_N_1000,
	store_predec_rm_rn_l_M_0100_N_1000,
	div0s_M_0100_N_1000,
	tst_rm_rn_M_0100_N_1000,
	and_rm_rn_M_0100_N_1000,
	xor_rm_rn_M_0100_N_1000,
	or_rm_rn_M_0100_N_1000,
	cmpstr_rm_rn_M_0100_N_1000,
	xtrct_M_0100_N_1000,
	mulu_w_M_0100_N_1000,
	muls_w_M_0100_N_1000,
	store_rm_rn_b_M_0101_N_1000,
	store_rm_rn_w_M_0101_N_1000,
	store_rm_rn_l_M_0101_N_1000,
	unimplemented,
	store_predec_rm_rn_b_M_0101_N_1000,
	store_predec_rm_rn_w_M_0101_N_1000,
	store_predec_rm_rn_l_M_0101_N_1000,
	div0s_M_0101_N_1000,
	tst_rm_rn_M_0101_N_1000,
	and_rm_rn_M_0101_N_1000,
	xor_rm_rn_M_0101_N_1000,
	or_rm_rn_M_0101_N_1000,
	cmpstr_rm_rn_M_0101_N_1000,
	xtrct_M_0101_N_1000,
	mulu_w_M_0101_N_1000,
	muls_w_M_0101_N_1000,
	store_rm_rn_b_M_0110_N_1000,
	store_rm_rn_w_M_0110_N_1000,
	store_rm_rn_l_M_0110_N_1000,
	unimplemented,
	store_predec_rm_rn_b_M_0110_N_1000,
	store_predec_rm_rn_w_M_0110_N_1000,
	store_predec_rm_rn_l_M_0110_N_1000,
	div0s_M_0110_N_1000,
	tst_rm_rn_M_0110_N_1000,
	and_rm_rn_M_0110_N_1000,
	xor_rm_rn_M_0110_N_1000,
	or_rm_rn_M_0110_N_1000,
	cmpstr_rm_rn_M_0110_N_1000,
	xtrct_M_0110_N_1000,
	mulu_w_M_0110_N_1000,
	muls_w_M_0110_N_1000,
	store_rm_rn_b_M_0111_N_1000,
	store_rm_rn_w_M_0111_N_1000,
	store_rm_rn_l_M_0111_N_1000,
	unimplemented,
	store_predec_rm_rn_b_M_0111_N_1000,
	store_predec_rm_rn_w_M_0111_N_1000,
	store_predec_rm_rn_l_M_0111_N_1000,
	div0s_M_0111_N_1000,
	tst_rm_rn_M_0111_N_1000,
	and_rm_rn_M_0111_N_1000,
	xor_rm_rn_M_0111_N_1000,
	or_rm_rn_M_0111_N_1000,
	cmpstr_rm_rn_M_0111_N_1000,
	xtrct_M_0111_N_1000,
	mulu_w_M_0111_N_1000,
	muls_w_M_0111_N_1000,
	store_rm_rn_b_M_1000_N_1000,
	store_rm_rn_w_M_1000_N_1000,
	store_rm_rn_l_M_1000_N_1000,
	unimplemented,
	store_predec_rm_rn_b_M_1000_N_1000,
	store_predec_rm_rn_w_M_1000_N_1000,
	store_predec_rm_rn_l_M_1000_N_1000,
	div0s_M_1000_N_1000,
	tst_rm_rn_M_1000_N_1000,
	and_rm_rn_M_1000_N_1000,
	xor_rm_rn_M_1000_N_1000,
	or_rm_rn_M_1000_N_1000,
	cmpstr_rm_rn_M_1000_N_1000,
	xtrct_M_1000_N_1000,
	mulu_w_M_1000_N_1000,
	muls_w_M_1000_N_1000,
	store_rm_rn_b_M_1001_N_1000,
	store_rm_rn_w_M_1001_N_1000,
	store_rm_rn_l_M_1001_N_1000,
	unimplemented,
	store_predec_rm_rn_b_M_1001_N_1000,
	store_predec_rm_rn_w_M_1001_N_1000,
	store_predec_rm_rn_l_M_1001_N_1000,
	div0s_M_1001_N_1000,
	tst_rm_rn_M_1001_N_1000,
	and_rm_rn_M_1001_N_1000,
	xor_rm_rn_M_1001_N_1000,
	or_rm_rn_M_1001_N_1000,
	cmpstr_rm_rn_M_1001_N_1000,
	xtrct_M_1001_N_1000,
	mulu_w_M_1001_N_1000,
	muls_w_M_1001_N_1000,
	store_rm_rn_b_M_1010_N_1000,
	store_rm_rn_w_M_1010_N_1000,
	store_rm_rn_l_M_1010_N_1000,
	unimplemented,
	store_predec_rm_rn_b_M_1010_N_1000,
	store_predec_rm_rn_w_M_1010_N_1000,
	store_predec_rm_rn_l_M_1010_N_1000,
	div0s_M_1010_N_1000,
	tst_rm_rn_M_1010_N_1000,
	and_rm_rn_M_1010_N_1000,
	xor_rm_rn_M_1010_N_1000,
	or_rm_rn_M_1010_N_1000,
	cmpstr_rm_rn_M_1010_N_1000,
	xtrct_M_1010_N_1000,
	mulu_w_M_1010_N_1000,
	muls_w_M_1010_N_1000,
	store_rm_rn_b_M_1011_N_1000,
	store_rm_rn_w_M_1011_N_1000,
	store_rm_rn_l_M_1011_N_1000,
	unimplemented,
	store_predec_rm_rn_b_M_1011_N_1000,
	store_predec_rm_rn_w_M_1011_N_1000,
	store_predec_rm_rn_l_M_1011_N_1000,
	div0s_M_1011_N_1000,
	tst_rm_rn_M_1011_N_1000,
	and_rm_rn_M_1011_N_1000,
	xor_rm_rn_M_1011_N_1000,
	or_rm_rn_M_1011_N_1000,
	cmpstr_rm_rn_M_1011_N_1000,
	xtrct_M_1011_N_1000,
	mulu_w_M_1011_N_1000,
	muls_w_M_1011_N_1000,
	store_rm_rn_b_M_1100_N_1000,
	store_rm_rn_w_M_1100_N_1000,
	store_rm_rn_l_M_1100_N_1000,
	unimplemented,
	store_predec_rm_rn_b_M_1100_N_1000,
	store_predec_rm_rn_w_M_1100_N_1000,
	store_predec_rm_rn_l_M_1100_N_1000,
	div0s_M_1100_N_1000,
	tst_rm_rn_M_1100_N_1000,
	and_rm_rn_M_1100_N_1000,
	xor_rm_rn_M_1100_N_1000,
	or_rm_rn_M_1100_N_1000,
	cmpstr_rm_rn_M_1100_N_1000,
	xtrct_M_1100_N_1000,
	mulu_w_M_1100_N_1000,
	muls_w_M_1100_N_1000,
	store_rm_rn_b_M_1101_N_1000,
	store_rm_rn_w_M_1101_N_1000,
	store_rm_rn_l_M_1101_N_1000,
	unimplemented,
	store_predec_rm_rn_b_M_1101_N_1000,
	store_predec_rm_rn_w_M_1101_N_1000,
	store_predec_rm_rn_l_M_1101_N_1000,
	div0s_M_1101_N_1000,
	tst_rm_rn_M_1101_N_1000,
	and_rm_rn_M_1101_N_1000,
	xor_rm_rn_M_1101_N_1000,
	or_rm_rn_M_1101_N_1000,
	cmpstr_rm_rn_M_1101_N_1000,
	xtrct_M_1101_N_1000,
	mulu_w_M_1101_N_1000,
	muls_w_M_1101_N_1000,
	store_rm_rn_b_M_1110_N_1000,
	store_rm_rn_w_M_1110_N_1000,
	store_rm_rn_l_M_1110_N_1000,
	unimplemented,
	store_predec_rm_rn_b_M_1110_N_1000,
	store_predec_rm_rn_w_M_1110_N_1000,
	store_predec_rm_rn_l_M_1110_N_1000,
	div0s_M_1110_N_1000,
	tst_rm_rn_M_1110_N_1000,
	and_rm_rn_M_1110_N_1000,
	xor_rm_rn_M_1110_N_1000,
	or_rm_rn_M_1110_N_1000,
	cmpstr_rm_rn_M_1110_N_1000,
	xtrct_M_1110_N_1000,
	mulu_w_M_1110_N_1000,
	muls_w_M_1110_N_1000,
	store_rm_rn_b_M_1111_N_1000,
	store_rm_rn_w_M_1111_N_1000,
	store_rm_rn_l_M_1111_N_1000,
	unimplemented,
	store_predec_rm_rn_b_M_1111_N_1000,
	store_predec_rm_rn_w_M_1111_N_1000,
	store_predec_rm_rn_l_M_1111_N_1000,
	div0s_M_1111_N_1000,
	tst_rm_rn_M_1111_N_1000,
	and_rm_rn_M_1111_N_1000,
	xor_rm_rn_M_1111_N_1000,
	or_rm_rn_M_1111_N_1000,
	cmpstr_rm_rn_M_1111_N_1000,
	xtrct_M_1111_N_1000,
	mulu_w_M_1111_N_1000,
	muls_w_M_1111_N_1000,
	store_rm_rn_b_M_0000_N_1001,
	store_rm_rn_w_M_0000_N_1001,
	store_rm_rn_l_M_0000_N_1001,
	unimplemented,
	store_predec_rm_rn_b_M_0000_N_1001,
	store_predec_rm_rn_w_M_0000_N_1001,
	store_predec_rm_rn_l_M_0000_N_1001,
	div0s_M_0000_N_1001,
	tst_rm_rn_M_0000_N_1001,
	and_rm_rn_M_0000_N_1001,
	xor_rm_rn_M_0000_N_1001,
	or_rm_rn_M_0000_N_1001,
	cmpstr_rm_rn_M_0000_N_1001,
	xtrct_M_0000_N_1001,
	mulu_w_M_0000_N_1001,
	muls_w_M_0000_N_1001,
	store_rm_rn_b_M_0001_N_1001,
	store_rm_rn_w_M_0001_N_1001,
	store_rm_rn_l_M_0001_N_1001,
	unimplemented,
	store_predec_rm_rn_b_M_0001_N_1001,
	store_predec_rm_rn_w_M_0001_N_1001,
	store_predec_rm_rn_l_M_0001_N_1001,
	div0s_M_0001_N_1001,
	tst_rm_rn_M_0001_N_1001,
	and_rm_rn_M_0001_N_1001,
	xor_rm_rn_M_0001_N_1001,
	or_rm_rn_M_0001_N_1001,
	cmpstr_rm_rn_M_0001_N_1001,
	xtrct_M_0001_N_1001,
	mulu_w_M_0001_N_1001,
	muls_w_M_0001_N_1001,
	store_rm_rn_b_M_0010_N_1001,
	store_rm_rn_w_M_0010_N_1001,
	store_rm_rn_l_M_0010_N_1001,
	unimplemented,
	store_predec_rm_rn_b_M_0010_N_1001,
	store_predec_rm_rn_w_M_0010_N_1001,
	store_predec_rm_rn_l_M_0010_N_1001,
	div0s_M_0010_N_1001,
	tst_rm_rn_M_0010_N_1001,
	and_rm_rn_M_0010_N_1001,
	xor_rm_rn_M_0010_N_1001,
	or_rm_rn_M_0010_N_1001,
	cmpstr_rm_rn_M_0010_N_1001,
	xtrct_M_0010_N_1001,
	mulu_w_M_0010_N_1001,
	muls_w_M_0010_N_1001,
	store_rm_rn_b_M_0011_N_1001,
	store_rm_rn_w_M_0011_N_1001,
	store_rm_rn_l_M_0011_N_1001,
	unimplemented,
	store_predec_rm_rn_b_M_0011_N_1001,
	store_predec_rm_rn_w_M_0011_N_1001,
	store_predec_rm_rn_l_M_0011_N_1001,
	div0s_M_0011_N_1001,
	tst_rm_rn_M_0011_N_1001,
	and_rm_rn_M_0011_N_1001,
	xor_rm_rn_M_0011_N_1001,
	or_rm_rn_M_0011_N_1001,
	cmpstr_rm_rn_M_0011_N_1001,
	xtrct_M_0011_N_1001,
	mulu_w_M_0011_N_1001,
	muls_w_M_0011_N_1001,
	store_rm_rn_b_M_0100_N_1001,
	store_rm_rn_w_M_0100_N_1001,
	store_rm_rn_l_M_0100_N_1001,
	unimplemented,
	store_predec_rm_rn_b_M_0100_N_1001,
	store_predec_rm_rn_w_M_0100_N_1001,
	store_predec_rm_rn_l_M_0100_N_1001,
	div0s_M_0100_N_1001,
	tst_rm_rn_M_0100_N_1001,
	and_rm_rn_M_0100_N_1001,
	xor_rm_rn_M_0100_N_1001,
	or_rm_rn_M_0100_N_1001,
	cmpstr_rm_rn_M_0100_N_1001,
	xtrct_M_0100_N_1001,
	mulu_w_M_0100_N_1001,
	muls_w_M_0100_N_1001,
	store_rm_rn_b_M_0101_N_1001,
	store_rm_rn_w_M_0101_N_1001,
	store_rm_rn_l_M_0101_N_1001,
	unimplemented,
	store_predec_rm_rn_b_M_0101_N_1001,
	store_predec_rm_rn_w_M_0101_N_1001,
	store_predec_rm_rn_l_M_0101_N_1001,
	div0s_M_0101_N_1001,
	tst_rm_rn_M_0101_N_1001,
	and_rm_rn_M_0101_N_1001,
	xor_rm_rn_M_0101_N_1001,
	or_rm_rn_M_0101_N_1001,
	cmpstr_rm_rn_M_0101_N_1001,
	xtrct_M_0101_N_1001,
	mulu_w_M_0101_N_1001,
	muls_w_M_0101_N_1001,
	store_rm_rn_b_M_0110_N_1001,
	store_rm_rn_w_M_0110_N_1001,
	store_rm_rn_l_M_0110_N_1001,
	unimplemented,
	store_predec_rm_rn_b_M_0110_N_1001,
	store_predec_rm_rn_w_M_0110_N_1001,
	store_predec_rm_rn_l_M_0110_N_1001,
	div0s_M_0110_N_1001,
	tst_rm_rn_M_0110_N_1001,
	and_rm_rn_M_0110_N_1001,
	xor_rm_rn_M_0110_N_1001,
	or_rm_rn_M_0110_N_1001,
	cmpstr_rm_rn_M_0110_N_1001,
	xtrct_M_0110_N_1001,
	mulu_w_M_0110_N_1001,
	muls_w_M_0110_N_1001,
	store_rm_rn_b_M_0111_N_1001,
	store_rm_rn_w_M_0111_N_1001,
	store_rm_rn_l_M_0111_N_1001,
	unimplemented,
	store_predec_rm_rn_b_M_0111_N_1001,
	store_predec_rm_rn_w_M_0111_N_1001,
	store_predec_rm_rn_l_M_0111_N_1001,
	div0s_M_0111_N_1001,
	tst_rm_rn_M_0111_N_1001,
	and_rm_rn_M_0111_N_1001,
	xor_rm_rn_M_0111_N_1001,
	or_rm_rn_M_0111_N_1001,
	cmpstr_rm_rn_M_0111_N_1001,
	xtrct_M_0111_N_1001,
	mulu_w_M_0111_N_1001,
	muls_w_M_0111_N_1001,
	store_rm_rn_b_M_1000_N_1001,
	store_rm_rn_w_M_1000_N_1001,
	store_rm_rn_l_M_1000_N_1001,
	unimplemented,
	store_predec_rm_rn_b_M_1000_N_1001,
	store_predec_rm_rn_w_M_1000_N_1001,
	store_predec_rm_rn_l_M_1000_N_1001,
	div0s_M_1000_N_1001,
	tst_rm_rn_M_1000_N_1001,
	and_rm_rn_M_1000_N_1001,
	xor_rm_rn_M_1000_N_1001,
	or_rm_rn_M_1000_N_1001,
	cmpstr_rm_rn_M_1000_N_1001,
	xtrct_M_1000_N_1001,
	mulu_w_M_1000_N_1001,
	muls_w_M_1000_N_1001,
	store_rm_rn_b_M_1001_N_1001,
	store_rm_rn_w_M_1001_N_1001,
	store_rm_rn_l_M_1001_N_1001,
	unimplemented,
	store_predec_rm_rn_b_M_1001_N_1001,
	store_predec_rm_rn_w_M_1001_N_1001,
	store_predec_rm_rn_l_M_1001_N_1001,
	div0s_M_1001_N_1001,
	tst_rm_rn_M_1001_N_1001,
	and_rm_rn_M_1001_N_1001,
	xor_rm_rn_M_1001_N_1001,
	or_rm_rn_M_1001_N_1001,
	cmpstr_rm_rn_M_1001_N_1001,
	xtrct_M_1001_N_1001,
	mulu_w_M_1001_N_1001,
	muls_w_M_1001_N_1001,
	store_rm_rn_b_M_1010_N_1001,
	store_rm_rn_w_M_1010_N_1001,
	store_rm_rn_l_M_1010_N_1001,
	unimplemented,
	store_predec_rm_rn_b_M_1010_N_1001,
	store_predec_rm_rn_w_M_1010_N_1001,
	store_predec_rm_rn_l_M_1010_N_1001,
	div0s_M_1010_N_1001,
	tst_rm_rn_M_1010_N_1001,
	and_rm_rn_M_1010_N_1001,
	xor_rm_rn_M_1010_N_1001,
	or_rm_rn_M_1010_N_1001,
	cmpstr_rm_rn_M_1010_N_1001,
	xtrct_M_1010_N_1001,
	mulu_w_M_1010_N_1001,
	muls_w_M_1010_N_1001,
	store_rm_rn_b_M_1011_N_1001,
	store_rm_rn_w_M_1011_N_1001,
	store_rm_rn_l_M_1011_N_1001,
	unimplemented,
	store_predec_rm_rn_b_M_1011_N_1001,
	store_predec_rm_rn_w_M_1011_N_1001,
	store_predec_rm_rn_l_M_1011_N_1001,
	div0s_M_1011_N_1001,
	tst_rm_rn_M_1011_N_1001,
	and_rm_rn_M_1011_N_1001,
	xor_rm_rn_M_1011_N_1001,
	or_rm_rn_M_1011_N_1001,
	cmpstr_rm_rn_M_1011_N_1001,
	xtrct_M_1011_N_1001,
	mulu_w_M_1011_N_1001,
	muls_w_M_1011_N_1001,
	store_rm_rn_b_M_1100_N_1001,
	store_rm_rn_w_M_1100_N_1001,
	store_rm_rn_l_M_1100_N_1001,
	unimplemented,
	store_predec_rm_rn_b_M_1100_N_1001,
	store_predec_rm_rn_w_M_1100_N_1001,
	store_predec_rm_rn_l_M_1100_N_1001,
	div0s_M_1100_N_1001,
	tst_rm_rn_M_1100_N_1001,
	and_rm_rn_M_1100_N_1001,
	xor_rm_rn_M_1100_N_1001,
	or_rm_rn_M_1100_N_1001,
	cmpstr_rm_rn_M_1100_N_1001,
	xtrct_M_1100_N_1001,
	mulu_w_M_1100_N_1001,
	muls_w_M_1100_N_1001,
	store_rm_rn_b_M_1101_N_1001,
	store_rm_rn_w_M_1101_N_1001,
	store_rm_rn_l_M_1101_N_1001,
	unimplemented,
	store_predec_rm_rn_b_M_1101_N_1001,
	store_predec_rm_rn_w_M_1101_N_1001,
	store_predec_rm_rn_l_M_1101_N_1001,
	div0s_M_1101_N_1001,
	tst_rm_rn_M_1101_N_1001,
	and_rm_rn_M_1101_N_1001,
	xor_rm_rn_M_1101_N_1001,
	or_rm_rn_M_1101_N_1001,
	cmpstr_rm_rn_M_1101_N_1001,
	xtrct_M_1101_N_1001,
	mulu_w_M_1101_N_1001,
	muls_w_M_1101_N_1001,
	store_rm_rn_b_M_1110_N_1001,
	store_rm_rn_w_M_1110_N_1001,
	store_rm_rn_l_M_1110_N_1001,
	unimplemented,
	store_predec_rm_rn_b_M_1110_N_1001,
	store_predec_rm_rn_w_M_1110_N_1001,
	store_predec_rm_rn_l_M_1110_N_1001,
	div0s_M_1110_N_1001,
	tst_rm_rn_M_1110_N_1001,
	and_rm_rn_M_1110_N_1001,
	xor_rm_rn_M_1110_N_1001,
	or_rm_rn_M_1110_N_1001,
	cmpstr_rm_rn_M_1110_N_1001,
	xtrct_M_1110_N_1001,
	mulu_w_M_1110_N_1001,
	muls_w_M_1110_N_1001,
	store_rm_rn_b_M_1111_N_1001,
	store_rm_rn_w_M_1111_N_1001,
	store_rm_rn_l_M_1111_N_1001,
	unimplemented,
	store_predec_rm_rn_b_M_1111_N_1001,
	store_predec_rm_rn_w_M_1111_N_1001,
	store_predec_rm_rn_l_M_1111_N_1001,
	div0s_M_1111_N_1001,
	tst_rm_rn_M_1111_N_1001,
	and_rm_rn_M_1111_N_1001,
	xor_rm_rn_M_1111_N_1001,
	or_rm_rn_M_1111_N_1001,
	cmpstr_rm_rn_M_1111_N_1001,
	xtrct_M_1111_N_1001,
	mulu_w_M_1111_N_1001,
	muls_w_M_1111_N_1001,
	store_rm_rn_b_M_0000_N_1010,
	store_rm_rn_w_M_0000_N_1010,
	store_rm_rn_l_M_0000_N_1010,
	unimplemented,
	store_predec_rm_rn_b_M_0000_N_1010,
	store_predec_rm_rn_w_M_0000_N_1010,
	store_predec_rm_rn_l_M_0000_N_1010,
	div0s_M_0000_N_1010,
	tst_rm_rn_M_0000_N_1010,
	and_rm_rn_M_0000_N_1010,
	xor_rm_rn_M_0000_N_1010,
	or_rm_rn_M_0000_N_1010,
	cmpstr_rm_rn_M_0000_N_1010,
	xtrct_M_0000_N_1010,
	mulu_w_M_0000_N_1010,
	muls_w_M_0000_N_1010,
	store_rm_rn_b_M_0001_N_1010,
	store_rm_rn_w_M_0001_N_1010,
	store_rm_rn_l_M_0001_N_1010,
	unimplemented,
	store_predec_rm_rn_b_M_0001_N_1010,
	store_predec_rm_rn_w_M_0001_N_1010,
	store_predec_rm_rn_l_M_0001_N_1010,
	div0s_M_0001_N_1010,
	tst_rm_rn_M_0001_N_1010,
	and_rm_rn_M_0001_N_1010,
	xor_rm_rn_M_0001_N_1010,
	or_rm_rn_M_0001_N_1010,
	cmpstr_rm_rn_M_0001_N_1010,
	xtrct_M_0001_N_1010,
	mulu_w_M_0001_N_1010,
	muls_w_M_0001_N_1010,
	store_rm_rn_b_M_0010_N_1010,
	store_rm_rn_w_M_0010_N_1010,
	store_rm_rn_l_M_0010_N_1010,
	unimplemented,
	store_predec_rm_rn_b_M_0010_N_1010,
	store_predec_rm_rn_w_M_0010_N_1010,
	store_predec_rm_rn_l_M_0010_N_1010,
	div0s_M_0010_N_1010,
	tst_rm_rn_M_0010_N_1010,
	and_rm_rn_M_0010_N_1010,
	xor_rm_rn_M_0010_N_1010,
	or_rm_rn_M_0010_N_1010,
	cmpstr_rm_rn_M_0010_N_1010,
	xtrct_M_0010_N_1010,
	mulu_w_M_0010_N_1010,
	muls_w_M_0010_N_1010,
	store_rm_rn_b_M_0011_N_1010,
	store_rm_rn_w_M_0011_N_1010,
	store_rm_rn_l_M_0011_N_1010,
	unimplemented,
	store_predec_rm_rn_b_M_0011_N_1010,
	store_predec_rm_rn_w_M_0011_N_1010,
	store_predec_rm_rn_l_M_0011_N_1010,
	div0s_M_0011_N_1010,
	tst_rm_rn_M_0011_N_1010,
	and_rm_rn_M_0011_N_1010,
	xor_rm_rn_M_0011_N_1010,
	or_rm_rn_M_0011_N_1010,
	cmpstr_rm_rn_M_0011_N_1010,
	xtrct_M_0011_N_1010,
	mulu_w_M_0011_N_1010,
	muls_w_M_0011_N_1010,
	store_rm_rn_b_M_0100_N_1010,
	store_rm_rn_w_M_0100_N_1010,
	store_rm_rn_l_M_0100_N_1010,
	unimplemented,
	store_predec_rm_rn_b_M_0100_N_1010,
	store_predec_rm_rn_w_M_0100_N_1010,
	store_predec_rm_rn_l_M_0100_N_1010,
	div0s_M_0100_N_1010,
	tst_rm_rn_M_0100_N_1010,
	and_rm_rn_M_0100_N_1010,
	xor_rm_rn_M_0100_N_1010,
	or_rm_rn_M_0100_N_1010,
	cmpstr_rm_rn_M_0100_N_1010,
	xtrct_M_0100_N_1010,
	mulu_w_M_0100_N_1010,
	muls_w_M_0100_N_1010,
	store_rm_rn_b_M_0101_N_1010,
	store_rm_rn_w_M_0101_N_1010,
	store_rm_rn_l_M_0101_N_1010,
	unimplemented,
	store_predec_rm_rn_b_M_0101_N_1010,
	store_predec_rm_rn_w_M_0101_N_1010,
	store_predec_rm_rn_l_M_0101_N_1010,
	div0s_M_0101_N_1010,
	tst_rm_rn_M_0101_N_1010,
	and_rm_rn_M_0101_N_1010,
	xor_rm_rn_M_0101_N_1010,
	or_rm_rn_M_0101_N_1010,
	cmpstr_rm_rn_M_0101_N_1010,
	xtrct_M_0101_N_1010,
	mulu_w_M_0101_N_1010,
	muls_w_M_0101_N_1010,
	store_rm_rn_b_M_0110_N_1010,
	store_rm_rn_w_M_0110_N_1010,
	store_rm_rn_l_M_0110_N_1010,
	unimplemented,
	store_predec_rm_rn_b_M_0110_N_1010,
	store_predec_rm_rn_w_M_0110_N_1010,
	store_predec_rm_rn_l_M_0110_N_1010,
	div0s_M_0110_N_1010,
	tst_rm_rn_M_0110_N_1010,
	and_rm_rn_M_0110_N_1010,
	xor_rm_rn_M_0110_N_1010,
	or_rm_rn_M_0110_N_1010,
	cmpstr_rm_rn_M_0110_N_1010,
	xtrct_M_0110_N_1010,
	mulu_w_M_0110_N_1010,
	muls_w_M_0110_N_1010,
	store_rm_rn_b_M_0111_N_1010,
	store_rm_rn_w_M_0111_N_1010,
	store_rm_rn_l_M_0111_N_1010,
	unimplemented,
	store_predec_rm_rn_b_M_0111_N_1010,
	store_predec_rm_rn_w_M_0111_N_1010,
	store_predec_rm_rn_l_M_0111_N_1010,
	div0s_M_0111_N_1010,
	tst_rm_rn_M_0111_N_1010,
	and_rm_rn_M_0111_N_1010,
	xor_rm_rn_M_0111_N_1010,
	or_rm_rn_M_0111_N_1010,
	cmpstr_rm_rn_M_0111_N_1010,
	xtrct_M_0111_N_1010,
	mulu_w_M_0111_N_1010,
	muls_w_M_0111_N_1010,
	store_rm_rn_b_M_1000_N_1010,
	store_rm_rn_w_M_1000_N_1010,
	store_rm_rn_l_M_1000_N_1010,
	unimplemented,
	store_predec_rm_rn_b_M_1000_N_1010,
	store_predec_rm_rn_w_M_1000_N_1010,
	store_predec_rm_rn_l_M_1000_N_1010,
	div0s_M_1000_N_1010,
	tst_rm_rn_M_1000_N_1010,
	and_rm_rn_M_1000_N_1010,
	xor_rm_rn_M_1000_N_1010,
	or_rm_rn_M_1000_N_1010,
	cmpstr_rm_rn_M_1000_N_1010,
	xtrct_M_1000_N_1010,
	mulu_w_M_1000_N_1010,
	muls_w_M_1000_N_1010,
	store_rm_rn_b_M_1001_N_1010,
	store_rm_rn_w_M_1001_N_1010,
	store_rm_rn_l_M_1001_N_1010,
	unimplemented,
	store_predec_rm_rn_b_M_1001_N_1010,
	store_predec_rm_rn_w_M_1001_N_1010,
	store_predec_rm_rn_l_M_1001_N_1010,
	div0s_M_1001_N_1010,
	tst_rm_rn_M_1001_N_1010,
	and_rm_rn_M_1001_N_1010,
	xor_rm_rn_M_1001_N_1010,
	or_rm_rn_M_1001_N_1010,
	cmpstr_rm_rn_M_1001_N_1010,
	xtrct_M_1001_N_1010,
	mulu_w_M_1001_N_1010,
	muls_w_M_1001_N_1010,
	store_rm_rn_b_M_1010_N_1010,
	store_rm_rn_w_M_1010_N_1010,
	store_rm_rn_l_M_1010_N_1010,
	unimplemented,
	store_predec_rm_rn_b_M_1010_N_1010,
	store_predec_rm_rn_w_M_1010_N_1010,
	store_predec_rm_rn_l_M_1010_N_1010,
	div0s_M_1010_N_1010,
	tst_rm_rn_M_1010_N_1010,
	and_rm_rn_M_1010_N_1010,
	xor_rm_rn_M_1010_N_1010,
	or_rm_rn_M_1010_N_1010,
	cmpstr_rm_rn_M_1010_N_1010,
	xtrct_M_1010_N_1010,
	mulu_w_M_1010_N_1010,
	muls_w_M_1010_N_1010,
	store_rm_rn_b_M_1011_N_1010,
	store_rm_rn_w_M_1011_N_1010,
	store_rm_rn_l_M_1011_N_1010,
	unimplemented,
	store_predec_rm_rn_b_M_1011_N_1010,
	store_predec_rm_rn_w_M_1011_N_1010,
	store_predec_rm_rn_l_M_1011_N_1010,
	div0s_M_1011_N_1010,
	tst_rm_rn_M_1011_N_1010,
	and_rm_rn_M_1011_N_1010,
	xor_rm_rn_M_1011_N_1010,
	or_rm_rn_M_1011_N_1010,
	cmpstr_rm_rn_M_1011_N_1010,
	xtrct_M_1011_N_1010,
	mulu_w_M_1011_N_1010,
	muls_w_M_1011_N_1010,
	store_rm_rn_b_M_1100_N_1010,
	store_rm_rn_w_M_1100_N_1010,
	store_rm_rn_l_M_1100_N_1010,
	unimplemented,
	store_predec_rm_rn_b_M_1100_N_1010,
	store_predec_rm_rn_w_M_1100_N_1010,
	store_predec_rm_rn_l_M_1100_N_1010,
	div0s_M_1100_N_1010,
	tst_rm_rn_M_1100_N_1010,
	and_rm_rn_M_1100_N_1010,
	xor_rm_rn_M_1100_N_1010,
	or_rm_rn_M_1100_N_1010,
	cmpstr_rm_rn_M_1100_N_1010,
	xtrct_M_1100_N_1010,
	mulu_w_M_1100_N_1010,
	muls_w_M_1100_N_1010,
	store_rm_rn_b_M_1101_N_1010,
	store_rm_rn_w_M_1101_N_1010,
	store_rm_rn_l_M_1101_N_1010,
	unimplemented,
	store_predec_rm_rn_b_M_1101_N_1010,
	store_predec_rm_rn_w_M_1101_N_1010,
	store_predec_rm_rn_l_M_1101_N_1010,
	div0s_M_1101_N_1010,
	tst_rm_rn_M_1101_N_1010,
	and_rm_rn_M_1101_N_1010,
	xor_rm_rn_M_1101_N_1010,
	or_rm_rn_M_1101_N_1010,
	cmpstr_rm_rn_M_1101_N_1010,
	xtrct_M_1101_N_1010,
	mulu_w_M_1101_N_1010,
	muls_w_M_1101_N_1010,
	store_rm_rn_b_M_1110_N_1010,
	store_rm_rn_w_M_1110_N_1010,
	store_rm_rn_l_M_1110_N_1010,
	unimplemented,
	store_predec_rm_rn_b_M_1110_N_1010,
	store_predec_rm_rn_w_M_1110_N_1010,
	store_predec_rm_rn_l_M_1110_N_1010,
	div0s_M_1110_N_1010,
	tst_rm_rn_M_1110_N_1010,
	and_rm_rn_M_1110_N_1010,
	xor_rm_rn_M_1110_N_1010,
	or_rm_rn_M_1110_N_1010,
	cmpstr_rm_rn_M_1110_N_1010,
	xtrct_M_1110_N_1010,
	mulu_w_M_1110_N_1010,
	muls_w_M_1110_N_1010,
	store_rm_rn_b_M_1111_N_1010,
	store_rm_rn_w_M_1111_N_1010,
	store_rm_rn_l_M_1111_N_1010,
	unimplemented,
	store_predec_rm_rn_b_M_1111_N_1010,
	store_predec_rm_rn_w_M_1111_N_1010,
	store_predec_rm_rn_l_M_1111_N_1010,
	div0s_M_1111_N_1010,
	tst_rm_rn_M_1111_N_1010,
	and_rm_rn_M_1111_N_1010,
	xor_rm_rn_M_1111_N_1010,
	or_rm_rn_M_1111_N_1010,
	cmpstr_rm_rn_M_1111_N_1010,
	xtrct_M_1111_N_1010,
	mulu_w_M_1111_N_1010,
	muls_w_M_1111_N_1010,
	store_rm_rn_b_M_0000_N_1011,
	store_rm_rn_w_M_0000_N_1011,
	store_rm_rn_l_M_0000_N_1011,
	unimplemented,
	store_predec_rm_rn_b_M_0000_N_1011,
	store_predec_rm_rn_w_M_0000_N_1011,
	store_predec_rm_rn_l_M_0000_N_1011,
	div0s_M_0000_N_1011,
	tst_rm_rn_M_0000_N_1011,
	and_rm_rn_M_0000_N_1011,
	xor_rm_rn_M_0000_N_1011,
	or_rm_rn_M_0000_N_1011,
	cmpstr_rm_rn_M_0000_N_1011,
	xtrct_M_0000_N_1011,
	mulu_w_M_0000_N_1011,
	muls_w_M_0000_N_1011,
	store_rm_rn_b_M_0001_N_1011,
	store_rm_rn_w_M_0001_N_1011,
	store_rm_rn_l_M_0001_N_1011,
	unimplemented,
	store_predec_rm_rn_b_M_0001_N_1011,
	store_predec_rm_rn_w_M_0001_N_1011,
	store_predec_rm_rn_l_M_0001_N_1011,
	div0s_M_0001_N_1011,
	tst_rm_rn_M_0001_N_1011,
	and_rm_rn_M_0001_N_1011,
	xor_rm_rn_M_0001_N_1011,
	or_rm_rn_M_0001_N_1011,
	cmpstr_rm_rn_M_0001_N_1011,
	xtrct_M_0001_N_1011,
	mulu_w_M_0001_N_1011,
	muls_w_M_0001_N_1011,
	store_rm_rn_b_M_0010_N_1011,
	store_rm_rn_w_M_0010_N_1011,
	store_rm_rn_l_M_0010_N_1011,
	unimplemented,
	store_predec_rm_rn_b_M_0010_N_1011,
	store_predec_rm_rn_w_M_0010_N_1011,
	store_predec_rm_rn_l_M_0010_N_1011,
	div0s_M_0010_N_1011,
	tst_rm_rn_M_0010_N_1011,
	and_rm_rn_M_0010_N_1011,
	xor_rm_rn_M_0010_N_1011,
	or_rm_rn_M_0010_N_1011,
	cmpstr_rm_rn_M_0010_N_1011,
	xtrct_M_0010_N_1011,
	mulu_w_M_0010_N_1011,
	muls_w_M_0010_N_1011,
	store_rm_rn_b_M_0011_N_1011,
	store_rm_rn_w_M_0011_N_1011,
	store_rm_rn_l_M_0011_N_1011,
	unimplemented,
	store_predec_rm_rn_b_M_0011_N_1011,
	store_predec_rm_rn_w_M_0011_N_1011,
	store_predec_rm_rn_l_M_0011_N_1011,
	div0s_M_0011_N_1011,
	tst_rm_rn_M_0011_N_1011,
	and_rm_rn_M_0011_N_1011,
	xor_rm_rn_M_0011_N_1011,
	or_rm_rn_M_0011_N_1011,
	cmpstr_rm_rn_M_0011_N_1011,
	xtrct_M_0011_N_1011,
	mulu_w_M_0011_N_1011,
	muls_w_M_0011_N_1011,
	store_rm_rn_b_M_0100_N_1011,
	store_rm_rn_w_M_0100_N_1011,
	store_rm_rn_l_M_0100_N_1011,
	unimplemented,
	store_predec_rm_rn_b_M_0100_N_1011,
	store_predec_rm_rn_w_M_0100_N_1011,
	store_predec_rm_rn_l_M_0100_N_1011,
	div0s_M_0100_N_1011,
	tst_rm_rn_M_0100_N_1011,
	and_rm_rn_M_0100_N_1011,
	xor_rm_rn_M_0100_N_1011,
	or_rm_rn_M_0100_N_1011,
	cmpstr_rm_rn_M_0100_N_1011,
	xtrct_M_0100_N_1011,
	mulu_w_M_0100_N_1011,
	muls_w_M_0100_N_1011,
	store_rm_rn_b_M_0101_N_1011,
	store_rm_rn_w_M_0101_N_1011,
	store_rm_rn_l_M_0101_N_1011,
	unimplemented,
	store_predec_rm_rn_b_M_0101_N_1011,
	store_predec_rm_rn_w_M_0101_N_1011,
	store_predec_rm_rn_l_M_0101_N_1011,
	div0s_M_0101_N_1011,
	tst_rm_rn_M_0101_N_1011,
	and_rm_rn_M_0101_N_1011,
	xor_rm_rn_M_0101_N_1011,
	or_rm_rn_M_0101_N_1011,
	cmpstr_rm_rn_M_0101_N_1011,
	xtrct_M_0101_N_1011,
	mulu_w_M_0101_N_1011,
	muls_w_M_0101_N_1011,
	store_rm_rn_b_M_0110_N_1011,
	store_rm_rn_w_M_0110_N_1011,
	store_rm_rn_l_M_0110_N_1011,
	unimplemented,
	store_predec_rm_rn_b_M_0110_N_1011,
	store_predec_rm_rn_w_M_0110_N_1011,
	store_predec_rm_rn_l_M_0110_N_1011,
	div0s_M_0110_N_1011,
	tst_rm_rn_M_0110_N_1011,
	and_rm_rn_M_0110_N_1011,
	xor_rm_rn_M_0110_N_1011,
	or_rm_rn_M_0110_N_1011,
	cmpstr_rm_rn_M_0110_N_1011,
	xtrct_M_0110_N_1011,
	mulu_w_M_0110_N_1011,
	muls_w_M_0110_N_1011,
	store_rm_rn_b_M_0111_N_1011,
	store_rm_rn_w_M_0111_N_1011,
	store_rm_rn_l_M_0111_N_1011,
	unimplemented,
	store_predec_rm_rn_b_M_0111_N_1011,
	store_predec_rm_rn_w_M_0111_N_1011,
	store_predec_rm_rn_l_M_0111_N_1011,
	div0s_M_0111_N_1011,
	tst_rm_rn_M_0111_N_1011,
	and_rm_rn_M_0111_N_1011,
	xor_rm_rn_M_0111_N_1011,
	or_rm_rn_M_0111_N_1011,
	cmpstr_rm_rn_M_0111_N_1011,
	xtrct_M_0111_N_1011,
	mulu_w_M_0111_N_1011,
	muls_w_M_0111_N_1011,
	store_rm_rn_b_M_1000_N_1011,
	store_rm_rn_w_M_1000_N_1011,
	store_rm_rn_l_M_1000_N_1011,
	unimplemented,
	store_predec_rm_rn_b_M_1000_N_1011,
	store_predec_rm_rn_w_M_1000_N_1011,
	store_predec_rm_rn_l_M_1000_N_1011,
	div0s_M_1000_N_1011,
	tst_rm_rn_M_1000_N_1011,
	and_rm_rn_M_1000_N_1011,
	xor_rm_rn_M_1000_N_1011,
	or_rm_rn_M_1000_N_1011,
	cmpstr_rm_rn_M_1000_N_1011,
	xtrct_M_1000_N_1011,
	mulu_w_M_1000_N_1011,
	muls_w_M_1000_N_1011,
	store_rm_rn_b_M_1001_N_1011,
	store_rm_rn_w_M_1001_N_1011,
	store_rm_rn_l_M_1001_N_1011,
	unimplemented,
	store_predec_rm_rn_b_M_1001_N_1011,
	store_predec_rm_rn_w_M_1001_N_1011,
	store_predec_rm_rn_l_M_1001_N_1011,
	div0s_M_1001_N_1011,
	tst_rm_rn_M_1001_N_1011,
	and_rm_rn_M_1001_N_1011,
	xor_rm_rn_M_1001_N_1011,
	or_rm_rn_M_1001_N_1011,
	cmpstr_rm_rn_M_1001_N_1011,
	xtrct_M_1001_N_1011,
	mulu_w_M_1001_N_1011,
	muls_w_M_1001_N_1011,
	store_rm_rn_b_M_1010_N_1011,
	store_rm_rn_w_M_1010_N_1011,
	store_rm_rn_l_M_1010_N_1011,
	unimplemented,
	store_predec_rm_rn_b_M_1010_N_1011,
	store_predec_rm_rn_w_M_1010_N_1011,
	store_predec_rm_rn_l_M_1010_N_1011,
	div0s_M_1010_N_1011,
	tst_rm_rn_M_1010_N_1011,
	and_rm_rn_M_1010_N_1011,
	xor_rm_rn_M_1010_N_1011,
	or_rm_rn_M_1010_N_1011,
	cmpstr_rm_rn_M_1010_N_1011,
	xtrct_M_1010_N_1011,
	mulu_w_M_1010_N_1011,
	muls_w_M_1010_N_1011,
	store_rm_rn_b_M_1011_N_1011,
	store_rm_rn_w_M_1011_N_1011,
	store_rm_rn_l_M_1011_N_1011,
	unimplemented,
	store_predec_rm_rn_b_M_1011_N_1011,
	store_predec_rm_rn_w_M_1011_N_1011,
	store_predec_rm_rn_l_M_1011_N_1011,
	div0s_M_1011_N_1011,
	tst_rm_rn_M_1011_N_1011,
	and_rm_rn_M_1011_N_1011,
	xor_rm_rn_M_1011_N_1011,
	or_rm_rn_M_1011_N_1011,
	cmpstr_rm_rn_M_1011_N_1011,
	xtrct_M_1011_N_1011,
	mulu_w_M_1011_N_1011,
	muls_w_M_1011_N_1011,
	store_rm_rn_b_M_1100_N_1011,
	store_rm_rn_w_M_1100_N_1011,
	store_rm_rn_l_M_1100_N_1011,
	unimplemented,
	store_predec_rm_rn_b_M_1100_N_1011,
	store_predec_rm_rn_w_M_1100_N_1011,
	store_predec_rm_rn_l_M_1100_N_1011,
	div0s_M_1100_N_1011,
	tst_rm_rn_M_1100_N_1011,
	and_rm_rn_M_1100_N_1011,
	xor_rm_rn_M_1100_N_1011,
	or_rm_rn_M_1100_N_1011,
	cmpstr_rm_rn_M_1100_N_1011,
	xtrct_M_1100_N_1011,
	mulu_w_M_1100_N_1011,
	muls_w_M_1100_N_1011,
	store_rm_rn_b_M_1101_N_1011,
	store_rm_rn_w_M_1101_N_1011,
	store_rm_rn_l_M_1101_N_1011,
	unimplemented,
	store_predec_rm_rn_b_M_1101_N_1011,
	store_predec_rm_rn_w_M_1101_N_1011,
	store_predec_rm_rn_l_M_1101_N_1011,
	div0s_M_1101_N_1011,
	tst_rm_rn_M_1101_N_1011,
	and_rm_rn_M_1101_N_1011,
	xor_rm_rn_M_1101_N_1011,
	or_rm_rn_M_1101_N_1011,
	cmpstr_rm_rn_M_1101_N_1011,
	xtrct_M_1101_N_1011,
	mulu_w_M_1101_N_1011,
	muls_w_M_1101_N_1011,
	store_rm_rn_b_M_1110_N_1011,
	store_rm_rn_w_M_1110_N_1011,
	store_rm_rn_l_M_1110_N_1011,
	unimplemented,
	store_predec_rm_rn_b_M_1110_N_1011,
	store_predec_rm_rn_w_M_1110_N_1011,
	store_predec_rm_rn_l_M_1110_N_1011,
	div0s_M_1110_N_1011,
	tst_rm_rn_M_1110_N_1011,
	and_rm_rn_M_1110_N_1011,
	xor_rm_rn_M_1110_N_1011,
	or_rm_rn_M_1110_N_1011,
	cmpstr_rm_rn_M_1110_N_1011,
	xtrct_M_1110_N_1011,
	mulu_w_M_1110_N_1011,
	muls_w_M_1110_N_1011,
	store_rm_rn_b_M_1111_N_1011,
	store_rm_rn_w_M_1111_N_1011,
	store_rm_rn_l_M_1111_N_1011,
	unimplemented,
	store_predec_rm_rn_b_M_1111_N_1011,
	store_predec_rm_rn_w_M_1111_N_1011,
	store_predec_rm_rn_l_M_1111_N_1011,
	div0s_M_1111_N_1011,
	tst_rm_rn_M_1111_N_1011,
	and_rm_rn_M_1111_N_1011,
	xor_rm_rn_M_1111_N_1011,
	or_rm_rn_M_1111_N_1011,
	cmpstr_rm_rn_M_1111_N_1011,
	xtrct_M_1111_N_1011,
	mulu_w_M_1111_N_1011,
	muls_w_M_1111_N_1011,
	store_rm_rn_b_M_0000_N_1100,
	store_rm_rn_w_M_0000_N_1100,
	store_rm_rn_l_M_0000_N_1100,
	unimplemented,
	store_predec_rm_rn_b_M_0000_N_1100,
	store_predec_rm_rn_w_M_0000_N_1100,
	store_predec_rm_rn_l_M_0000_N_1100,
	div0s_M_0000_N_1100,
	tst_rm_rn_M_0000_N_1100,
	and_rm_rn_M_0000_N_1100,
	xor_rm_rn_M_0000_N_1100,
	or_rm_rn_M_0000_N_1100,
	cmpstr_rm_rn_M_0000_N_1100,
	xtrct_M_0000_N_1100,
	mulu_w_M_0000_N_1100,
	muls_w_M_0000_N_1100,
	store_rm_rn_b_M_0001_N_1100,
	store_rm_rn_w_M_0001_N_1100,
	store_rm_rn_l_M_0001_N_1100,
	unimplemented,
	store_predec_rm_rn_b_M_0001_N_1100,
	store_predec_rm_rn_w_M_0001_N_1100,
	store_predec_rm_rn_l_M_0001_N_1100,
	div0s_M_0001_N_1100,
	tst_rm_rn_M_0001_N_1100,
	and_rm_rn_M_0001_N_1100,
	xor_rm_rn_M_0001_N_1100,
	or_rm_rn_M_0001_N_1100,
	cmpstr_rm_rn_M_0001_N_1100,
	xtrct_M_0001_N_1100,
	mulu_w_M_0001_N_1100,
	muls_w_M_0001_N_1100,
	store_rm_rn_b_M_0010_N_1100,
	store_rm_rn_w_M_0010_N_1100,
	store_rm_rn_l_M_0010_N_1100,
	unimplemented,
	store_predec_rm_rn_b_M_0010_N_1100,
	store_predec_rm_rn_w_M_0010_N_1100,
	store_predec_rm_rn_l_M_0010_N_1100,
	div0s_M_0010_N_1100,
	tst_rm_rn_M_0010_N_1100,
	and_rm_rn_M_0010_N_1100,
	xor_rm_rn_M_0010_N_1100,
	or_rm_rn_M_0010_N_1100,
	cmpstr_rm_rn_M_0010_N_1100,
	xtrct_M_0010_N_1100,
	mulu_w_M_0010_N_1100,
	muls_w_M_0010_N_1100,
	store_rm_rn_b_M_0011_N_1100,
	store_rm_rn_w_M_0011_N_1100,
	store_rm_rn_l_M_0011_N_1100,
	unimplemented,
	store_predec_rm_rn_b_M_0011_N_1100,
	store_predec_rm_rn_w_M_0011_N_1100,
	store_predec_rm_rn_l_M_0011_N_1100,
	div0s_M_0011_N_1100,
	tst_rm_rn_M_0011_N_1100,
	and_rm_rn_M_0011_N_1100,
	xor_rm_rn_M_0011_N_1100,
	or_rm_rn_M_0011_N_1100,
	cmpstr_rm_rn_M_0011_N_1100,
	xtrct_M_0011_N_1100,
	mulu_w_M_0011_N_1100,
	muls_w_M_0011_N_1100,
	store_rm_rn_b_M_0100_N_1100,
	store_rm_rn_w_M_0100_N_1100,
	store_rm_rn_l_M_0100_N_1100,
	unimplemented,
	store_predec_rm_rn_b_M_0100_N_1100,
	store_predec_rm_rn_w_M_0100_N_1100,
	store_predec_rm_rn_l_M_0100_N_1100,
	div0s_M_0100_N_1100,
	tst_rm_rn_M_0100_N_1100,
	and_rm_rn_M_0100_N_1100,
	xor_rm_rn_M_0100_N_1100,
	or_rm_rn_M_0100_N_1100,
	cmpstr_rm_rn_M_0100_N_1100,
	xtrct_M_0100_N_1100,
	mulu_w_M_0100_N_1100,
	muls_w_M_0100_N_1100,
	store_rm_rn_b_M_0101_N_1100,
	store_rm_rn_w_M_0101_N_1100,
	store_rm_rn_l_M_0101_N_1100,
	unimplemented,
	store_predec_rm_rn_b_M_0101_N_1100,
	store_predec_rm_rn_w_M_0101_N_1100,
	store_predec_rm_rn_l_M_0101_N_1100,
	div0s_M_0101_N_1100,
	tst_rm_rn_M_0101_N_1100,
	and_rm_rn_M_0101_N_1100,
	xor_rm_rn_M_0101_N_1100,
	or_rm_rn_M_0101_N_1100,
	cmpstr_rm_rn_M_0101_N_1100,
	xtrct_M_0101_N_1100,
	mulu_w_M_0101_N_1100,
	muls_w_M_0101_N_1100,
	store_rm_rn_b_M_0110_N_1100,
	store_rm_rn_w_M_0110_N_1100,
	store_rm_rn_l_M_0110_N_1100,
	unimplemented,
	store_predec_rm_rn_b_M_0110_N_1100,
	store_predec_rm_rn_w_M_0110_N_1100,
	store_predec_rm_rn_l_M_0110_N_1100,
	div0s_M_0110_N_1100,
	tst_rm_rn_M_0110_N_1100,
	and_rm_rn_M_0110_N_1100,
	xor_rm_rn_M_0110_N_1100,
	or_rm_rn_M_0110_N_1100,
	cmpstr_rm_rn_M_0110_N_1100,
	xtrct_M_0110_N_1100,
	mulu_w_M_0110_N_1100,
	muls_w_M_0110_N_1100,
	store_rm_rn_b_M_0111_N_1100,
	store_rm_rn_w_M_0111_N_1100,
	store_rm_rn_l_M_0111_N_1100,
	unimplemented,
	store_predec_rm_rn_b_M_0111_N_1100,
	store_predec_rm_rn_w_M_0111_N_1100,
	store_predec_rm_rn_l_M_0111_N_1100,
	div0s_M_0111_N_1100,
	tst_rm_rn_M_0111_N_1100,
	and_rm_rn_M_0111_N_1100,
	xor_rm_rn_M_0111_N_1100,
	or_rm_rn_M_0111_N_1100,
	cmpstr_rm_rn_M_0111_N_1100,
	xtrct_M_0111_N_1100,
	mulu_w_M_0111_N_1100,
	muls_w_M_0111_N_1100,
	store_rm_rn_b_M_1000_N_1100,
	store_rm_rn_w_M_1000_N_1100,
	store_rm_rn_l_M_1000_N_1100,
	unimplemented,
	store_predec_rm_rn_b_M_1000_N_1100,
	store_predec_rm_rn_w_M_1000_N_1100,
	store_predec_rm_rn_l_M_1000_N_1100,
	div0s_M_1000_N_1100,
	tst_rm_rn_M_1000_N_1100,
	and_rm_rn_M_1000_N_1100,
	xor_rm_rn_M_1000_N_1100,
	or_rm_rn_M_1000_N_1100,
	cmpstr_rm_rn_M_1000_N_1100,
	xtrct_M_1000_N_1100,
	mulu_w_M_1000_N_1100,
	muls_w_M_1000_N_1100,
	store_rm_rn_b_M_1001_N_1100,
	store_rm_rn_w_M_1001_N_1100,
	store_rm_rn_l_M_1001_N_1100,
	unimplemented,
	store_predec_rm_rn_b_M_1001_N_1100,
	store_predec_rm_rn_w_M_1001_N_1100,
	store_predec_rm_rn_l_M_1001_N_1100,
	div0s_M_1001_N_1100,
	tst_rm_rn_M_1001_N_1100,
	and_rm_rn_M_1001_N_1100,
	xor_rm_rn_M_1001_N_1100,
	or_rm_rn_M_1001_N_1100,
	cmpstr_rm_rn_M_1001_N_1100,
	xtrct_M_1001_N_1100,
	mulu_w_M_1001_N_1100,
	muls_w_M_1001_N_1100,
	store_rm_rn_b_M_1010_N_1100,
	store_rm_rn_w_M_1010_N_1100,
	store_rm_rn_l_M_1010_N_1100,
	unimplemented,
	store_predec_rm_rn_b_M_1010_N_1100,
	store_predec_rm_rn_w_M_1010_N_1100,
	store_predec_rm_rn_l_M_1010_N_1100,
	div0s_M_1010_N_1100,
	tst_rm_rn_M_1010_N_1100,
	and_rm_rn_M_1010_N_1100,
	xor_rm_rn_M_1010_N_1100,
	or_rm_rn_M_1010_N_1100,
	cmpstr_rm_rn_M_1010_N_1100,
	xtrct_M_1010_N_1100,
	mulu_w_M_1010_N_1100,
	muls_w_M_1010_N_1100,
	store_rm_rn_b_M_1011_N_1100,
	store_rm_rn_w_M_1011_N_1100,
	store_rm_rn_l_M_1011_N_1100,
	unimplemented,
	store_predec_rm_rn_b_M_1011_N_1100,
	store_predec_rm_rn_w_M_1011_N_1100,
	store_predec_rm_rn_l_M_1011_N_1100,
	div0s_M_1011_N_1100,
	tst_rm_rn_M_1011_N_1100,
	and_rm_rn_M_1011_N_1100,
	xor_rm_rn_M_1011_N_1100,
	or_rm_rn_M_1011_N_1100,
	cmpstr_rm_rn_M_1011_N_1100,
	xtrct_M_1011_N_1100,
	mulu_w_M_1011_N_1100,
	muls_w_M_1011_N_1100,
	store_rm_rn_b_M_1100_N_1100,
	store_rm_rn_w_M_1100_N_1100,
	store_rm_rn_l_M_1100_N_1100,
	unimplemented,
	store_predec_rm_rn_b_M_1100_N_1100,
	store_predec_rm_rn_w_M_1100_N_1100,
	store_predec_rm_rn_l_M_1100_N_1100,
	div0s_M_1100_N_1100,
	tst_rm_rn_M_1100_N_1100,
	and_rm_rn_M_1100_N_1100,
	xor_rm_rn_M_1100_N_1100,
	or_rm_rn_M_1100_N_1100,
	cmpstr_rm_rn_M_1100_N_1100,
	xtrct_M_1100_N_1100,
	mulu_w_M_1100_N_1100,
	muls_w_M_1100_N_1100,
	store_rm_rn_b_M_1101_N_1100,
	store_rm_rn_w_M_1101_N_1100,
	store_rm_rn_l_M_1101_N_1100,
	unimplemented,
	store_predec_rm_rn_b_M_1101_N_1100,
	store_predec_rm_rn_w_M_1101_N_1100,
	store_predec_rm_rn_l_M_1101_N_1100,
	div0s_M_1101_N_1100,
	tst_rm_rn_M_1101_N_1100,
	and_rm_rn_M_1101_N_1100,
	xor_rm_rn_M_1101_N_1100,
	or_rm_rn_M_1101_N_1100,
	cmpstr_rm_rn_M_1101_N_1100,
	xtrct_M_1101_N_1100,
	mulu_w_M_1101_N_1100,
	muls_w_M_1101_N_1100,
	store_rm_rn_b_M_1110_N_1100,
	store_rm_rn_w_M_1110_N_1100,
	store_rm_rn_l_M_1110_N_1100,
	unimplemented,
	store_predec_rm_rn_b_M_1110_N_1100,
	store_predec_rm_rn_w_M_1110_N_1100,
	store_predec_rm_rn_l_M_1110_N_1100,
	div0s_M_1110_N_1100,
	tst_rm_rn_M_1110_N_1100,
	and_rm_rn_M_1110_N_1100,
	xor_rm_rn_M_1110_N_1100,
	or_rm_rn_M_1110_N_1100,
	cmpstr_rm_rn_M_1110_N_1100,
	xtrct_M_1110_N_1100,
	mulu_w_M_1110_N_1100,
	muls_w_M_1110_N_1100,
	store_rm_rn_b_M_1111_N_1100,
	store_rm_rn_w_M_1111_N_1100,
	store_rm_rn_l_M_1111_N_1100,
	unimplemented,
	store_predec_rm_rn_b_M_1111_N_1100,
	store_predec_rm_rn_w_M_1111_N_1100,
	store_predec_rm_rn_l_M_1111_N_1100,
	div0s_M_1111_N_1100,
	tst_rm_rn_M_1111_N_1100,
	and_rm_rn_M_1111_N_1100,
	xor_rm_rn_M_1111_N_1100,
	or_rm_rn_M_1111_N_1100,
	cmpstr_rm_rn_M_1111_N_1100,
	xtrct_M_1111_N_1100,
	mulu_w_M_1111_N_1100,
	muls_w_M_1111_N_1100,
	store_rm_rn_b_M_0000_N_1101,
	store_rm_rn_w_M_0000_N_1101,
	store_rm_rn_l_M_0000_N_1101,
	unimplemented,
	store_predec_rm_rn_b_M_0000_N_1101,
	store_predec_rm_rn_w_M_0000_N_1101,
	store_predec_rm_rn_l_M_0000_N_1101,
	div0s_M_0000_N_1101,
	tst_rm_rn_M_0000_N_1101,
	and_rm_rn_M_0000_N_1101,
	xor_rm_rn_M_0000_N_1101,
	or_rm_rn_M_0000_N_1101,
	cmpstr_rm_rn_M_0000_N_1101,
	xtrct_M_0000_N_1101,
	mulu_w_M_0000_N_1101,
	muls_w_M_0000_N_1101,
	store_rm_rn_b_M_0001_N_1101,
	store_rm_rn_w_M_0001_N_1101,
	store_rm_rn_l_M_0001_N_1101,
	unimplemented,
	store_predec_rm_rn_b_M_0001_N_1101,
	store_predec_rm_rn_w_M_0001_N_1101,
	store_predec_rm_rn_l_M_0001_N_1101,
	div0s_M_0001_N_1101,
	tst_rm_rn_M_0001_N_1101,
	and_rm_rn_M_0001_N_1101,
	xor_rm_rn_M_0001_N_1101,
	or_rm_rn_M_0001_N_1101,
	cmpstr_rm_rn_M_0001_N_1101,
	xtrct_M_0001_N_1101,
	mulu_w_M_0001_N_1101,
	muls_w_M_0001_N_1101,
	store_rm_rn_b_M_0010_N_1101,
	store_rm_rn_w_M_0010_N_1101,
	store_rm_rn_l_M_0010_N_1101,
	unimplemented,
	store_predec_rm_rn_b_M_0010_N_1101,
	store_predec_rm_rn_w_M_0010_N_1101,
	store_predec_rm_rn_l_M_0010_N_1101,
	div0s_M_0010_N_1101,
	tst_rm_rn_M_0010_N_1101,
	and_rm_rn_M_0010_N_1101,
	xor_rm_rn_M_0010_N_1101,
	or_rm_rn_M_0010_N_1101,
	cmpstr_rm_rn_M_0010_N_1101,
	xtrct_M_0010_N_1101,
	mulu_w_M_0010_N_1101,
	muls_w_M_0010_N_1101,
	store_rm_rn_b_M_0011_N_1101,
	store_rm_rn_w_M_0011_N_1101,
	store_rm_rn_l_M_0011_N_1101,
	unimplemented,
	store_predec_rm_rn_b_M_0011_N_1101,
	store_predec_rm_rn_w_M_0011_N_1101,
	store_predec_rm_rn_l_M_0011_N_1101,
	div0s_M_0011_N_1101,
	tst_rm_rn_M_0011_N_1101,
	and_rm_rn_M_0011_N_1101,
	xor_rm_rn_M_0011_N_1101,
	or_rm_rn_M_0011_N_1101,
	cmpstr_rm_rn_M_0011_N_1101,
	xtrct_M_0011_N_1101,
	mulu_w_M_0011_N_1101,
	muls_w_M_0011_N_1101,
	store_rm_rn_b_M_0100_N_1101,
	store_rm_rn_w_M_0100_N_1101,
	store_rm_rn_l_M_0100_N_1101,
	unimplemented,
	store_predec_rm_rn_b_M_0100_N_1101,
	store_predec_rm_rn_w_M_0100_N_1101,
	store_predec_rm_rn_l_M_0100_N_1101,
	div0s_M_0100_N_1101,
	tst_rm_rn_M_0100_N_1101,
	and_rm_rn_M_0100_N_1101,
	xor_rm_rn_M_0100_N_1101,
	or_rm_rn_M_0100_N_1101,
	cmpstr_rm_rn_M_0100_N_1101,
	xtrct_M_0100_N_1101,
	mulu_w_M_0100_N_1101,
	muls_w_M_0100_N_1101,
	store_rm_rn_b_M_0101_N_1101,
	store_rm_rn_w_M_0101_N_1101,
	store_rm_rn_l_M_0101_N_1101,
	unimplemented,
	store_predec_rm_rn_b_M_0101_N_1101,
	store_predec_rm_rn_w_M_0101_N_1101,
	store_predec_rm_rn_l_M_0101_N_1101,
	div0s_M_0101_N_1101,
	tst_rm_rn_M_0101_N_1101,
	and_rm_rn_M_0101_N_1101,
	xor_rm_rn_M_0101_N_1101,
	or_rm_rn_M_0101_N_1101,
	cmpstr_rm_rn_M_0101_N_1101,
	xtrct_M_0101_N_1101,
	mulu_w_M_0101_N_1101,
	muls_w_M_0101_N_1101,
	store_rm_rn_b_M_0110_N_1101,
	store_rm_rn_w_M_0110_N_1101,
	store_rm_rn_l_M_0110_N_1101,
	unimplemented,
	store_predec_rm_rn_b_M_0110_N_1101,
	store_predec_rm_rn_w_M_0110_N_1101,
	store_predec_rm_rn_l_M_0110_N_1101,
	div0s_M_0110_N_1101,
	tst_rm_rn_M_0110_N_1101,
	and_rm_rn_M_0110_N_1101,
	xor_rm_rn_M_0110_N_1101,
	or_rm_rn_M_0110_N_1101,
	cmpstr_rm_rn_M_0110_N_1101,
	xtrct_M_0110_N_1101,
	mulu_w_M_0110_N_1101,
	muls_w_M_0110_N_1101,
	store_rm_rn_b_M_0111_N_1101,
	store_rm_rn_w_M_0111_N_1101,
	store_rm_rn_l_M_0111_N_1101,
	unimplemented,
	store_predec_rm_rn_b_M_0111_N_1101,
	store_predec_rm_rn_w_M_0111_N_1101,
	store_predec_rm_rn_l_M_0111_N_1101,
	div0s_M_0111_N_1101,
	tst_rm_rn_M_0111_N_1101,
	and_rm_rn_M_0111_N_1101,
	xor_rm_rn_M_0111_N_1101,
	or_rm_rn_M_0111_N_1101,
	cmpstr_rm_rn_M_0111_N_1101,
	xtrct_M_0111_N_1101,
	mulu_w_M_0111_N_1101,
	muls_w_M_0111_N_1101,
	store_rm_rn_b_M_1000_N_1101,
	store_rm_rn_w_M_1000_N_1101,
	store_rm_rn_l_M_1000_N_1101,
	unimplemented,
	store_predec_rm_rn_b_M_1000_N_1101,
	store_predec_rm_rn_w_M_1000_N_1101,
	store_predec_rm_rn_l_M_1000_N_1101,
	div0s_M_1000_N_1101,
	tst_rm_rn_M_1000_N_1101,
	and_rm_rn_M_1000_N_1101,
	xor_rm_rn_M_1000_N_1101,
	or_rm_rn_M_1000_N_1101,
	cmpstr_rm_rn_M_1000_N_1101,
	xtrct_M_1000_N_1101,
	mulu_w_M_1000_N_1101,
	muls_w_M_1000_N_1101,
	store_rm_rn_b_M_1001_N_1101,
	store_rm_rn_w_M_1001_N_1101,
	store_rm_rn_l_M_1001_N_1101,
	unimplemented,
	store_predec_rm_rn_b_M_1001_N_1101,
	store_predec_rm_rn_w_M_1001_N_1101,
	store_predec_rm_rn_l_M_1001_N_1101,
	div0s_M_1001_N_1101,
	tst_rm_rn_M_1001_N_1101,
	and_rm_rn_M_1001_N_1101,
	xor_rm_rn_M_1001_N_1101,
	or_rm_rn_M_1001_N_1101,
	cmpstr_rm_rn_M_1001_N_1101,
	xtrct_M_1001_N_1101,
	mulu_w_M_1001_N_1101,
	muls_w_M_1001_N_1101,
	store_rm_rn_b_M_1010_N_1101,
	store_rm_rn_w_M_1010_N_1101,
	store_rm_rn_l_M_1010_N_1101,
	unimplemented,
	store_predec_rm_rn_b_M_1010_N_1101,
	store_predec_rm_rn_w_M_1010_N_1101,
	store_predec_rm_rn_l_M_1010_N_1101,
	div0s_M_1010_N_1101,
	tst_rm_rn_M_1010_N_1101,
	and_rm_rn_M_1010_N_1101,
	xor_rm_rn_M_1010_N_1101,
	or_rm_rn_M_1010_N_1101,
	cmpstr_rm_rn_M_1010_N_1101,
	xtrct_M_1010_N_1101,
	mulu_w_M_1010_N_1101,
	muls_w_M_1010_N_1101,
	store_rm_rn_b_M_1011_N_1101,
	store_rm_rn_w_M_1011_N_1101,
	store_rm_rn_l_M_1011_N_1101,
	unimplemented,
	store_predec_rm_rn_b_M_1011_N_1101,
	store_predec_rm_rn_w_M_1011_N_1101,
	store_predec_rm_rn_l_M_1011_N_1101,
	div0s_M_1011_N_1101,
	tst_rm_rn_M_1011_N_1101,
	and_rm_rn_M_1011_N_1101,
	xor_rm_rn_M_1011_N_1101,
	or_rm_rn_M_1011_N_1101,
	cmpstr_rm_rn_M_1011_N_1101,
	xtrct_M_1011_N_1101,
	mulu_w_M_1011_N_1101,
	muls_w_M_1011_N_1101,
	store_rm_rn_b_M_1100_N_1101,
	store_rm_rn_w_M_1100_N_1101,
	store_rm_rn_l_M_1100_N_1101,
	unimplemented,
	store_predec_rm_rn_b_M_1100_N_1101,
	store_predec_rm_rn_w_M_1100_N_1101,
	store_predec_rm_rn_l_M_1100_N_1101,
	div0s_M_1100_N_1101,
	tst_rm_rn_M_1100_N_1101,
	and_rm_rn_M_1100_N_1101,
	xor_rm_rn_M_1100_N_1101,
	or_rm_rn_M_1100_N_1101,
	cmpstr_rm_rn_M_1100_N_1101,
	xtrct_M_1100_N_1101,
	mulu_w_M_1100_N_1101,
	muls_w_M_1100_N_1101,
	store_rm_rn_b_M_1101_N_1101,
	store_rm_rn_w_M_1101_N_1101,
	store_rm_rn_l_M_1101_N_1101,
	unimplemented,
	store_predec_rm_rn_b_M_1101_N_1101,
	store_predec_rm_rn_w_M_1101_N_1101,
	store_predec_rm_rn_l_M_1101_N_1101,
	div0s_M_1101_N_1101,
	tst_rm_rn_M_1101_N_1101,
	and_rm_rn_M_1101_N_1101,
	xor_rm_rn_M_1101_N_1101,
	or_rm_rn_M_1101_N_1101,
	cmpstr_rm_rn_M_1101_N_1101,
	xtrct_M_1101_N_1101,
	mulu_w_M_1101_N_1101,
	muls_w_M_1101_N_1101,
	store_rm_rn_b_M_1110_N_1101,
	store_rm_rn_w_M_1110_N_1101,
	store_rm_rn_l_M_1110_N_1101,
	unimplemented,
	store_predec_rm_rn_b_M_1110_N_1101,
	store_predec_rm_rn_w_M_1110_N_1101,
	store_predec_rm_rn_l_M_1110_N_1101,
	div0s_M_1110_N_1101,
	tst_rm_rn_M_1110_N_1101,
	and_rm_rn_M_1110_N_1101,
	xor_rm_rn_M_1110_N_1101,
	or_rm_rn_M_1110_N_1101,
	cmpstr_rm_rn_M_1110_N_1101,
	xtrct_M_1110_N_1101,
	mulu_w_M_1110_N_1101,
	muls_w_M_1110_N_1101,
	store_rm_rn_b_M_1111_N_1101,
	store_rm_rn_w_M_1111_N_1101,
	store_rm_rn_l_M_1111_N_1101,
	unimplemented,
	store_predec_rm_rn_b_M_1111_N_1101,
	store_predec_rm_rn_w_M_1111_N_1101,
	store_predec_rm_rn_l_M_1111_N_1101,
	div0s_M_1111_N_1101,
	tst_rm_rn_M_1111_N_1101,
	and_rm_rn_M_1111_N_1101,
	xor_rm_rn_M_1111_N_1101,
	or_rm_rn_M_1111_N_1101,
	cmpstr_rm_rn_M_1111_N_1101,
	xtrct_M_1111_N_1101,
	mulu_w_M_1111_N_1101,
	muls_w_M_1111_N_1101,
	store_rm_rn_b_M_0000_N_1110,
	store_rm_rn_w_M_0000_N_1110,
	store_rm_rn_l_M_0000_N_1110,
	unimplemented,
	store_predec_rm_rn_b_M_0000_N_1110,
	store_predec_rm_rn_w_M_0000_N_1110,
	store_predec_rm_rn_l_M_0000_N_1110,
	div0s_M_0000_N_1110,
	tst_rm_rn_M_0000_N_1110,
	and_rm_rn_M_0000_N_1110,
	xor_rm_rn_M_0000_N_1110,
	or_rm_rn_M_0000_N_1110,
	cmpstr_rm_rn_M_0000_N_1110,
	xtrct_M_0000_N_1110,
	mulu_w_M_0000_N_1110,
	muls_w_M_0000_N_1110,
	store_rm_rn_b_M_0001_N_1110,
	store_rm_rn_w_M_0001_N_1110,
	store_rm_rn_l_M_0001_N_1110,
	unimplemented,
	store_predec_rm_rn_b_M_0001_N_1110,
	store_predec_rm_rn_w_M_0001_N_1110,
	store_predec_rm_rn_l_M_0001_N_1110,
	div0s_M_0001_N_1110,
	tst_rm_rn_M_0001_N_1110,
	and_rm_rn_M_0001_N_1110,
	xor_rm_rn_M_0001_N_1110,
	or_rm_rn_M_0001_N_1110,
	cmpstr_rm_rn_M_0001_N_1110,
	xtrct_M_0001_N_1110,
	mulu_w_M_0001_N_1110,
	muls_w_M_0001_N_1110,
	store_rm_rn_b_M_0010_N_1110,
	store_rm_rn_w_M_0010_N_1110,
	store_rm_rn_l_M_0010_N_1110,
	unimplemented,
	store_predec_rm_rn_b_M_0010_N_1110,
	store_predec_rm_rn_w_M_0010_N_1110,
	store_predec_rm_rn_l_M_0010_N_1110,
	div0s_M_0010_N_1110,
	tst_rm_rn_M_0010_N_1110,
	and_rm_rn_M_0010_N_1110,
	xor_rm_rn_M_0010_N_1110,
	or_rm_rn_M_0010_N_1110,
	cmpstr_rm_rn_M_0010_N_1110,
	xtrct_M_0010_N_1110,
	mulu_w_M_0010_N_1110,
	muls_w_M_0010_N_1110,
	store_rm_rn_b_M_0011_N_1110,
	store_rm_rn_w_M_0011_N_1110,
	store_rm_rn_l_M_0011_N_1110,
	unimplemented,
	store_predec_rm_rn_b_M_0011_N_1110,
	store_predec_rm_rn_w_M_0011_N_1110,
	store_predec_rm_rn_l_M_0011_N_1110,
	div0s_M_0011_N_1110,
	tst_rm_rn_M_0011_N_1110,
	and_rm_rn_M_0011_N_1110,
	xor_rm_rn_M_0011_N_1110,
	or_rm_rn_M_0011_N_1110,
	cmpstr_rm_rn_M_0011_N_1110,
	xtrct_M_0011_N_1110,
	mulu_w_M_0011_N_1110,
	muls_w_M_0011_N_1110,
	store_rm_rn_b_M_0100_N_1110,
	store_rm_rn_w_M_0100_N_1110,
	store_rm_rn_l_M_0100_N_1110,
	unimplemented,
	store_predec_rm_rn_b_M_0100_N_1110,
	store_predec_rm_rn_w_M_0100_N_1110,
	store_predec_rm_rn_l_M_0100_N_1110,
	div0s_M_0100_N_1110,
	tst_rm_rn_M_0100_N_1110,
	and_rm_rn_M_0100_N_1110,
	xor_rm_rn_M_0100_N_1110,
	or_rm_rn_M_0100_N_1110,
	cmpstr_rm_rn_M_0100_N_1110,
	xtrct_M_0100_N_1110,
	mulu_w_M_0100_N_1110,
	muls_w_M_0100_N_1110,
	store_rm_rn_b_M_0101_N_1110,
	store_rm_rn_w_M_0101_N_1110,
	store_rm_rn_l_M_0101_N_1110,
	unimplemented,
	store_predec_rm_rn_b_M_0101_N_1110,
	store_predec_rm_rn_w_M_0101_N_1110,
	store_predec_rm_rn_l_M_0101_N_1110,
	div0s_M_0101_N_1110,
	tst_rm_rn_M_0101_N_1110,
	and_rm_rn_M_0101_N_1110,
	xor_rm_rn_M_0101_N_1110,
	or_rm_rn_M_0101_N_1110,
	cmpstr_rm_rn_M_0101_N_1110,
	xtrct_M_0101_N_1110,
	mulu_w_M_0101_N_1110,
	muls_w_M_0101_N_1110,
	store_rm_rn_b_M_0110_N_1110,
	store_rm_rn_w_M_0110_N_1110,
	store_rm_rn_l_M_0110_N_1110,
	unimplemented,
	store_predec_rm_rn_b_M_0110_N_1110,
	store_predec_rm_rn_w_M_0110_N_1110,
	store_predec_rm_rn_l_M_0110_N_1110,
	div0s_M_0110_N_1110,
	tst_rm_rn_M_0110_N_1110,
	and_rm_rn_M_0110_N_1110,
	xor_rm_rn_M_0110_N_1110,
	or_rm_rn_M_0110_N_1110,
	cmpstr_rm_rn_M_0110_N_1110,
	xtrct_M_0110_N_1110,
	mulu_w_M_0110_N_1110,
	muls_w_M_0110_N_1110,
	store_rm_rn_b_M_0111_N_1110,
	store_rm_rn_w_M_0111_N_1110,
	store_rm_rn_l_M_0111_N_1110,
	unimplemented,
	store_predec_rm_rn_b_M_0111_N_1110,
	store_predec_rm_rn_w_M_0111_N_1110,
	store_predec_rm_rn_l_M_0111_N_1110,
	div0s_M_0111_N_1110,
	tst_rm_rn_M_0111_N_1110,
	and_rm_rn_M_0111_N_1110,
	xor_rm_rn_M_0111_N_1110,
	or_rm_rn_M_0111_N_1110,
	cmpstr_rm_rn_M_0111_N_1110,
	xtrct_M_0111_N_1110,
	mulu_w_M_0111_N_1110,
	muls_w_M_0111_N_1110,
	store_rm_rn_b_M_1000_N_1110,
	store_rm_rn_w_M_1000_N_1110,
	store_rm_rn_l_M_1000_N_1110,
	unimplemented,
	store_predec_rm_rn_b_M_1000_N_1110,
	store_predec_rm_rn_w_M_1000_N_1110,
	store_predec_rm_rn_l_M_1000_N_1110,
	div0s_M_1000_N_1110,
	tst_rm_rn_M_1000_N_1110,
	and_rm_rn_M_1000_N_1110,
	xor_rm_rn_M_1000_N_1110,
	or_rm_rn_M_1000_N_1110,
	cmpstr_rm_rn_M_1000_N_1110,
	xtrct_M_1000_N_1110,
	mulu_w_M_1000_N_1110,
	muls_w_M_1000_N_1110,
	store_rm_rn_b_M_1001_N_1110,
	store_rm_rn_w_M_1001_N_1110,
	store_rm_rn_l_M_1001_N_1110,
	unimplemented,
	store_predec_rm_rn_b_M_1001_N_1110,
	store_predec_rm_rn_w_M_1001_N_1110,
	store_predec_rm_rn_l_M_1001_N_1110,
	div0s_M_1001_N_1110,
	tst_rm_rn_M_1001_N_1110,
	and_rm_rn_M_1001_N_1110,
	xor_rm_rn_M_1001_N_1110,
	or_rm_rn_M_1001_N_1110,
	cmpstr_rm_rn_M_1001_N_1110,
	xtrct_M_1001_N_1110,
	mulu_w_M_1001_N_1110,
	muls_w_M_1001_N_1110,
	store_rm_rn_b_M_1010_N_1110,
	store_rm_rn_w_M_1010_N_1110,
	store_rm_rn_l_M_1010_N_1110,
	unimplemented,
	store_predec_rm_rn_b_M_1010_N_1110,
	store_predec_rm_rn_w_M_1010_N_1110,
	store_predec_rm_rn_l_M_1010_N_1110,
	div0s_M_1010_N_1110,
	tst_rm_rn_M_1010_N_1110,
	and_rm_rn_M_1010_N_1110,
	xor_rm_rn_M_1010_N_1110,
	or_rm_rn_M_1010_N_1110,
	cmpstr_rm_rn_M_1010_N_1110,
	xtrct_M_1010_N_1110,
	mulu_w_M_1010_N_1110,
	muls_w_M_1010_N_1110,
	store_rm_rn_b_M_1011_N_1110,
	store_rm_rn_w_M_1011_N_1110,
	store_rm_rn_l_M_1011_N_1110,
	unimplemented,
	store_predec_rm_rn_b_M_1011_N_1110,
	store_predec_rm_rn_w_M_1011_N_1110,
	store_predec_rm_rn_l_M_1011_N_1110,
	div0s_M_1011_N_1110,
	tst_rm_rn_M_1011_N_1110,
	and_rm_rn_M_1011_N_1110,
	xor_rm_rn_M_1011_N_1110,
	or_rm_rn_M_1011_N_1110,
	cmpstr_rm_rn_M_1011_N_1110,
	xtrct_M_1011_N_1110,
	mulu_w_M_1011_N_1110,
	muls_w_M_1011_N_1110,
	store_rm_rn_b_M_1100_N_1110,
	store_rm_rn_w_M_1100_N_1110,
	store_rm_rn_l_M_1100_N_1110,
	unimplemented,
	store_predec_rm_rn_b_M_1100_N_1110,
	store_predec_rm_rn_w_M_1100_N_1110,
	store_predec_rm_rn_l_M_1100_N_1110,
	div0s_M_1100_N_1110,
	tst_rm_rn_M_1100_N_1110,
	and_rm_rn_M_1100_N_1110,
	xor_rm_rn_M_1100_N_1110,
	or_rm_rn_M_1100_N_1110,
	cmpstr_rm_rn_M_1100_N_1110,
	xtrct_M_1100_N_1110,
	mulu_w_M_1100_N_1110,
	muls_w_M_1100_N_1110,
	store_rm_rn_b_M_1101_N_1110,
	store_rm_rn_w_M_1101_N_1110,
	store_rm_rn_l_M_1101_N_1110,
	unimplemented,
	store_predec_rm_rn_b_M_1101_N_1110,
	store_predec_rm_rn_w_M_1101_N_1110,
	store_predec_rm_rn_l_M_1101_N_1110,
	div0s_M_1101_N_1110,
	tst_rm_rn_M_1101_N_1110,
	and_rm_rn_M_1101_N_1110,
	xor_rm_rn_M_1101_N_1110,
	or_rm_rn_M_1101_N_1110,
	cmpstr_rm_rn_M_1101_N_1110,
	xtrct_M_1101_N_1110,
	mulu_w_M_1101_N_1110,
	muls_w_M_1101_N_1110,
	store_rm_rn_b_M_1110_N_1110,
	store_rm_rn_w_M_1110_N_1110,
	store_rm_rn_l_M_1110_N_1110,
	unimplemented,
	store_predec_rm_rn_b_M_1110_N_1110,
	store_predec_rm_rn_w_M_1110_N_1110,
	store_predec_rm_rn_l_M_1110_N_1110,
	div0s_M_1110_N_1110,
	tst_rm_rn_M_1110_N_1110,
	and_rm_rn_M_1110_N_1110,
	xor_rm_rn_M_1110_N_1110,
	or_rm_rn_M_1110_N_1110,
	cmpstr_rm_rn_M_1110_N_1110,
	xtrct_M_1110_N_1110,
	mulu_w_M_1110_N_1110,
	muls_w_M_1110_N_1110,
	store_rm_rn_b_M_1111_N_1110,
	store_rm_rn_w_M_1111_N_1110,
	store_rm_rn_l_M_1111_N_1110,
	unimplemented,
	store_predec_rm_rn_b_M_1111_N_1110,
	store_predec_rm_rn_w_M_1111_N_1110,
	store_predec_rm_rn_l_M_1111_N_1110,
	div0s_M_1111_N_1110,
	tst_rm_rn_M_1111_N_1110,
	and_rm_rn_M_1111_N_1110,
	xor_rm_rn_M_1111_N_1110,
	or_rm_rn_M_1111_N_1110,
	cmpstr_rm_rn_M_1111_N_1110,
	xtrct_M_1111_N_1110,
	mulu_w_M_1111_N_1110,
	muls_w_M_1111_N_1110,
	store_rm_rn_b_M_0000_N_1111,
	store_rm_rn_w_M_0000_N_1111,
	store_rm_rn_l_M_0000_N_1111,
	unimplemented,
	store_predec_rm_rn_b_M_0000_N_1111,
	store_predec_rm_rn_w_M_0000_N_1111,
	store_predec_rm_rn_l_M_0000_N_1111,
	div0s_M_0000_N_1111,
	tst_rm_rn_M_0000_N_1111,
	and_rm_rn_M_0000_N_1111,
	xor_rm_rn_M_0000_N_1111,
	or_rm_rn_M_0000_N_1111,
	cmpstr_rm_rn_M_0000_N_1111,
	xtrct_M_0000_N_1111,
	mulu_w_M_0000_N_1111,
	muls_w_M_0000_N_1111,
	store_rm_rn_b_M_0001_N_1111,
	store_rm_rn_w_M_0001_N_1111,
	store_rm_rn_l_M_0001_N_1111,
	unimplemented,
	store_predec_rm_rn_b_M_0001_N_1111,
	store_predec_rm_rn_w_M_0001_N_1111,
	store_predec_rm_rn_l_M_0001_N_1111,
	div0s_M_0001_N_1111,
	tst_rm_rn_M_0001_N_1111,
	and_rm_rn_M_0001_N_1111,
	xor_rm_rn_M_0001_N_1111,
	or_rm_rn_M_0001_N_1111,
	cmpstr_rm_rn_M_0001_N_1111,
	xtrct_M_0001_N_1111,
	mulu_w_M_0001_N_1111,
	muls_w_M_0001_N_1111,
	store_rm_rn_b_M_0010_N_1111,
	store_rm_rn_w_M_0010_N_1111,
	store_rm_rn_l_M_0010_N_1111,
	unimplemented,
	store_predec_rm_rn_b_M_0010_N_1111,
	store_predec_rm_rn_w_M_0010_N_1111,
	store_predec_rm_rn_l_M_0010_N_1111,
	div0s_M_0010_N_1111,
	tst_rm_rn_M_0010_N_1111,
	and_rm_rn_M_0010_N_1111,
	xor_rm_rn_M_0010_N_1111,
	or_rm_rn_M_0010_N_1111,
	cmpstr_rm_rn_M_0010_N_1111,
	xtrct_M_0010_N_1111,
	mulu_w_M_0010_N_1111,
	muls_w_M_0010_N_1111,
	store_rm_rn_b_M_0011_N_1111,
	store_rm_rn_w_M_0011_N_1111,
	store_rm_rn_l_M_0011_N_1111,
	unimplemented,
	store_predec_rm_rn_b_M_0011_N_1111,
	store_predec_rm_rn_w_M_0011_N_1111,
	store_predec_rm_rn_l_M_0011_N_1111,
	div0s_M_0011_N_1111,
	tst_rm_rn_M_0011_N_1111,
	and_rm_rn_M_0011_N_1111,
	xor_rm_rn_M_0011_N_1111,
	or_rm_rn_M_0011_N_1111,
	cmpstr_rm_rn_M_0011_N_1111,
	xtrct_M_0011_N_1111,
	mulu_w_M_0011_N_1111,
	muls_w_M_0011_N_1111,
	store_rm_rn_b_M_0100_N_1111,
	store_rm_rn_w_M_0100_N_1111,
	store_rm_rn_l_M_0100_N_1111,
	unimplemented,
	store_predec_rm_rn_b_M_0100_N_1111,
	store_predec_rm_rn_w_M_0100_N_1111,
	store_predec_rm_rn_l_M_0100_N_1111,
	div0s_M_0100_N_1111,
	tst_rm_rn_M_0100_N_1111,
	and_rm_rn_M_0100_N_1111,
	xor_rm_rn_M_0100_N_1111,
	or_rm_rn_M_0100_N_1111,
	cmpstr_rm_rn_M_0100_N_1111,
	xtrct_M_0100_N_1111,
	mulu_w_M_0100_N_1111,
	muls_w_M_0100_N_1111,
	store_rm_rn_b_M_0101_N_1111,
	store_rm_rn_w_M_0101_N_1111,
	store_rm_rn_l_M_0101_N_1111,
	unimplemented,
	store_predec_rm_rn_b_M_0101_N_1111,
	store_predec_rm_rn_w_M_0101_N_1111,
	store_predec_rm_rn_l_M_0101_N_1111,
	div0s_M_0101_N_1111,
	tst_rm_rn_M_0101_N_1111,
	and_rm_rn_M_0101_N_1111,
	xor_rm_rn_M_0101_N_1111,
	or_rm_rn_M_0101_N_1111,
	cmpstr_rm_rn_M_0101_N_1111,
	xtrct_M_0101_N_1111,
	mulu_w_M_0101_N_1111,
	muls_w_M_0101_N_1111,
	store_rm_rn_b_M_0110_N_1111,
	store_rm_rn_w_M_0110_N_1111,
	store_rm_rn_l_M_0110_N_1111,
	unimplemented,
	store_predec_rm_rn_b_M_0110_N_1111,
	store_predec_rm_rn_w_M_0110_N_1111,
	store_predec_rm_rn_l_M_0110_N_1111,
	div0s_M_0110_N_1111,
	tst_rm_rn_M_0110_N_1111,
	and_rm_rn_M_0110_N_1111,
	xor_rm_rn_M_0110_N_1111,
	or_rm_rn_M_0110_N_1111,
	cmpstr_rm_rn_M_0110_N_1111,
	xtrct_M_0110_N_1111,
	mulu_w_M_0110_N_1111,
	muls_w_M_0110_N_1111,
	store_rm_rn_b_M_0111_N_1111,
	store_rm_rn_w_M_0111_N_1111,
	store_rm_rn_l_M_0111_N_1111,
	unimplemented,
	store_predec_rm_rn_b_M_0111_N_1111,
	store_predec_rm_rn_w_M_0111_N_1111,
	store_predec_rm_rn_l_M_0111_N_1111,
	div0s_M_0111_N_1111,
	tst_rm_rn_M_0111_N_1111,
	and_rm_rn_M_0111_N_1111,
	xor_rm_rn_M_0111_N_1111,
	or_rm_rn_M_0111_N_1111,
	cmpstr_rm_rn_M_0111_N_1111,
	xtrct_M_0111_N_1111,
	mulu_w_M_0111_N_1111,
	muls_w_M_0111_N_1111,
	store_rm_rn_b_M_1000_N_1111,
	store_rm_rn_w_M_1000_N_1111,
	store_rm_rn_l_M_1000_N_1111,
	unimplemented,
	store_predec_rm_rn_b_M_1000_N_1111,
	store_predec_rm_rn_w_M_1000_N_1111,
	store_predec_rm_rn_l_M_1000_N_1111,
	div0s_M_1000_N_1111,
	tst_rm_rn_M_1000_N_1111,
	and_rm_rn_M_1000_N_1111,
	xor_rm_rn_M_1000_N_1111,
	or_rm_rn_M_1000_N_1111,
	cmpstr_rm_rn_M_1000_N_1111,
	xtrct_M_1000_N_1111,
	mulu_w_M_1000_N_1111,
	muls_w_M_1000_N_1111,
	store_rm_rn_b_M_1001_N_1111,
	store_rm_rn_w_M_1001_N_1111,
	store_rm_rn_l_M_1001_N_1111,
	unimplemented,
	store_predec_rm_rn_b_M_1001_N_1111,
	store_predec_rm_rn_w_M_1001_N_1111,
	store_predec_rm_rn_l_M_1001_N_1111,
	div0s_M_1001_N_1111,
	tst_rm_rn_M_1001_N_1111,
	and_rm_rn_M_1001_N_1111,
	xor_rm_rn_M_1001_N_1111,
	or_rm_rn_M_1001_N_1111,
	cmpstr_rm_rn_M_1001_N_1111,
	xtrct_M_1001_N_1111,
	mulu_w_M_1001_N_1111,
	muls_w_M_1001_N_1111,
	store_rm_rn_b_M_1010_N_1111,
	store_rm_rn_w_M_1010_N_1111,
	store_rm_rn_l_M_1010_N_1111,
	unimplemented,
	store_predec_rm_rn_b_M_1010_N_1111,
	store_predec_rm_rn_w_M_1010_N_1111,
	store_predec_rm_rn_l_M_1010_N_1111,
	div0s_M_1010_N_1111,
	tst_rm_rn_M_1010_N_1111,
	and_rm_rn_M_1010_N_1111,
	xor_rm_rn_M_1010_N_1111,
	or_rm_rn_M_1010_N_1111,
	cmpstr_rm_rn_M_1010_N_1111,
	xtrct_M_1010_N_1111,
	mulu_w_M_1010_N_1111,
	muls_w_M_1010_N_1111,
	store_rm_rn_b_M_1011_N_1111,
	store_rm_rn_w_M_1011_N_1111,
	store_rm_rn_l_M_1011_N_1111,
	unimplemented,
	store_predec_rm_rn_b_M_1011_N_1111,
	store_predec_rm_rn_w_M_1011_N_1111,
	store_predec_rm_rn_l_M_1011_N_1111,
	div0s_M_1011_N_1111,
	tst_rm_rn_M_1011_N_1111,
	and_rm_rn_M_1011_N_1111,
	xor_rm_rn_M_1011_N_1111,
	or_rm_rn_M_1011_N_1111,
	cmpstr_rm_rn_M_1011_N_1111,
	xtrct_M_1011_N_1111,
	mulu_w_M_1011_N_1111,
	muls_w_M_1011_N_1111,
	store_rm_rn_b_M_1100_N_1111,
	store_rm_rn_w_M_1100_N_1111,
	store_rm_rn_l_M_1100_N_1111,
	unimplemented,
	store_predec_rm_rn_b_M_1100_N_1111,
	store_predec_rm_rn_w_M_1100_N_1111,
	store_predec_rm_rn_l_M_1100_N_1111,
	div0s_M_1100_N_1111,
	tst_rm_rn_M_1100_N_1111,
	and_rm_rn_M_1100_N_1111,
	xor_rm_rn_M_1100_N_1111,
	or_rm_rn_M_1100_N_1111,
	cmpstr_rm_rn_M_1100_N_1111,
	xtrct_M_1100_N_1111,
	mulu_w_M_1100_N_1111,
	muls_w_M_1100_N_1111,
	store_rm_rn_b_M_1101_N_1111,
	store_rm_rn_w_M_1101_N_1111,
	store_rm_rn_l_M_1101_N_1111,
	unimplemented,
	store_predec_rm_rn_b_M_1101_N_1111,
	store_predec_rm_rn_w_M_1101_N_1111,
	store_predec_rm_rn_l_M_1101_N_1111,
	div0s_M_1101_N_1111,
	tst_rm_rn_M_1101_N_1111,
	and_rm_rn_M_1101_N_1111,
	xor_rm_rn_M_1101_N_1111,
	or_rm_rn_M_1101_N_1111,
	cmpstr_rm_rn_M_1101_N_1111,
	xtrct_M_1101_N_1111,
	mulu_w_M_1101_N_1111,
	muls_w_M_1101_N_1111,
	store_rm_rn_b_M_1110_N_1111,
	store_rm_rn_w_M_1110_N_1111,
	store_rm_rn_l_M_1110_N_1111,
	unimplemented,
	store_predec_rm_rn_b_M_1110_N_1111,
	store_predec_rm_rn_w_M_1110_N_1111,
	store_predec_rm_rn_l_M_1110_N_1111,
	div0s_M_1110_N_1111,
	tst_rm_rn_M_1110_N_1111,
	and_rm_rn_M_1110_N_1111,
	xor_rm_rn_M_1110_N_1111,
	or_rm_rn_M_1110_N_1111,
	cmpstr_rm_rn_M_1110_N_1111,
	xtrct_M_1110_N_1111,
	mulu_w_M_1110_N_1111,
	muls_w_M_1110_N_1111,
	store_rm_rn_b_M_1111_N_1111,
	store_rm_rn_w_M_1111_N_1111,
	store_rm_rn_l_M_1111_N_1111,
	unimplemented,
	store_predec_rm_rn_b_M_1111_N_1111,
	store_predec_rm_rn_w_M_1111_N_1111,
	store_predec_rm_rn_l_M_1111_N_1111,
	div0s_M_1111_N_1111,
	tst_rm_rn_M_1111_N_1111,
	and_rm_rn_M_1111_N_1111,
	xor_rm_rn_M_1111_N_1111,
	or_rm_rn_M_1111_N_1111,
	cmpstr_rm_rn_M_1111_N_1111,
	xtrct_M_1111_N_1111,
	mulu_w_M_1111_N_1111,
	muls_w_M_1111_N_1111,
	cmpeq_rm_rn_M_0000_N_0000,
	unimplemented,
	cmphs_rm_rn_M_0000_N_0000,
	cmpge_rm_rn_M_0000_N_0000,
	div1_M_0000_N_0000,
	dmulu_M_0000_N_0000,
	cmphi_rm_rn_M_0000_N_0000,
	cmpgt_rm_rn_M_0000_N_0000,
	sub_M_0000_N_0000,
	unimplemented,
	subc_M_0000_N_0000,
	subv_M_0000_N_0000,
	add_rm_rn_M_0000_N_0000,
	dmuls_M_0000_N_0000,
	addc_rm_rn_M_0000_N_0000,
	addv_rm_rn_M_0000_N_0000,
	cmpeq_rm_rn_M_0001_N_0000,
	unimplemented,
	cmphs_rm_rn_M_0001_N_0000,
	cmpge_rm_rn_M_0001_N_0000,
	div1_M_0001_N_0000,
	dmulu_M_0001_N_0000,
	cmphi_rm_rn_M_0001_N_0000,
	cmpgt_rm_rn_M_0001_N_0000,
	sub_M_0001_N_0000,
	unimplemented,
	subc_M_0001_N_0000,
	subv_M_0001_N_0000,
	add_rm_rn_M_0001_N_0000,
	dmuls_M_0001_N_0000,
	addc_rm_rn_M_0001_N_0000,
	addv_rm_rn_M_0001_N_0000,
	cmpeq_rm_rn_M_0010_N_0000,
	unimplemented,
	cmphs_rm_rn_M_0010_N_0000,
	cmpge_rm_rn_M_0010_N_0000,
	div1_M_0010_N_0000,
	dmulu_M_0010_N_0000,
	cmphi_rm_rn_M_0010_N_0000,
	cmpgt_rm_rn_M_0010_N_0000,
	sub_M_0010_N_0000,
	unimplemented,
	subc_M_0010_N_0000,
	subv_M_0010_N_0000,
	add_rm_rn_M_0010_N_0000,
	dmuls_M_0010_N_0000,
	addc_rm_rn_M_0010_N_0000,
	addv_rm_rn_M_0010_N_0000,
	cmpeq_rm_rn_M_0011_N_0000,
	unimplemented,
	cmphs_rm_rn_M_0011_N_0000,
	cmpge_rm_rn_M_0011_N_0000,
	div1_M_0011_N_0000,
	dmulu_M_0011_N_0000,
	cmphi_rm_rn_M_0011_N_0000,
	cmpgt_rm_rn_M_0011_N_0000,
	sub_M_0011_N_0000,
	unimplemented,
	subc_M_0011_N_0000,
	subv_M_0011_N_0000,
	add_rm_rn_M_0011_N_0000,
	dmuls_M_0011_N_0000,
	addc_rm_rn_M_0011_N_0000,
	addv_rm_rn_M_0011_N_0000,
	cmpeq_rm_rn_M_0100_N_0000,
	unimplemented,
	cmphs_rm_rn_M_0100_N_0000,
	cmpge_rm_rn_M_0100_N_0000,
	div1_M_0100_N_0000,
	dmulu_M_0100_N_0000,
	cmphi_rm_rn_M_0100_N_0000,
	cmpgt_rm_rn_M_0100_N_0000,
	sub_M_0100_N_0000,
	unimplemented,
	subc_M_0100_N_0000,
	subv_M_0100_N_0000,
	add_rm_rn_M_0100_N_0000,
	dmuls_M_0100_N_0000,
	addc_rm_rn_M_0100_N_0000,
	addv_rm_rn_M_0100_N_0000,
	cmpeq_rm_rn_M_0101_N_0000,
	unimplemented,
	cmphs_rm_rn_M_0101_N_0000,
	cmpge_rm_rn_M_0101_N_0000,
	div1_M_0101_N_0000,
	dmulu_M_0101_N_0000,
	cmphi_rm_rn_M_0101_N_0000,
	cmpgt_rm_rn_M_0101_N_0000,
	sub_M_0101_N_0000,
	unimplemented,
	subc_M_0101_N_0000,
	subv_M_0101_N_0000,
	add_rm_rn_M_0101_N_0000,
	dmuls_M_0101_N_0000,
	addc_rm_rn_M_0101_N_0000,
	addv_rm_rn_M_0101_N_0000,
	cmpeq_rm_rn_M_0110_N_0000,
	unimplemented,
	cmphs_rm_rn_M_0110_N_0000,
	cmpge_rm_rn_M_0110_N_0000,
	div1_M_0110_N_0000,
	dmulu_M_0110_N_0000,
	cmphi_rm_rn_M_0110_N_0000,
	cmpgt_rm_rn_M_0110_N_0000,
	sub_M_0110_N_0000,
	unimplemented,
	subc_M_0110_N_0000,
	subv_M_0110_N_0000,
	add_rm_rn_M_0110_N_0000,
	dmuls_M_0110_N_0000,
	addc_rm_rn_M_0110_N_0000,
	addv_rm_rn_M_0110_N_0000,
	cmpeq_rm_rn_M_0111_N_0000,
	unimplemented,
	cmphs_rm_rn_M_0111_N_0000,
	cmpge_rm_rn_M_0111_N_0000,
	div1_M_0111_N_0000,
	dmulu_M_0111_N_0000,
	cmphi_rm_rn_M_0111_N_0000,
	cmpgt_rm_rn_M_0111_N_0000,
	sub_M_0111_N_0000,
	unimplemented,
	subc_M_0111_N_0000,
	subv_M_0111_N_0000,
	add_rm_rn_M_0111_N_0000,
	dmuls_M_0111_N_0000,
	addc_rm_rn_M_0111_N_0000,
	addv_rm_rn_M_0111_N_0000,
	cmpeq_rm_rn_M_1000_N_0000,
	unimplemented,
	cmphs_rm_rn_M_1000_N_0000,
	cmpge_rm_rn_M_1000_N_0000,
	div1_M_1000_N_0000,
	dmulu_M_1000_N_0000,
	cmphi_rm_rn_M_1000_N_0000,
	cmpgt_rm_rn_M_1000_N_0000,
	sub_M_1000_N_0000,
	unimplemented,
	subc_M_1000_N_0000,
	subv_M_1000_N_0000,
	add_rm_rn_M_1000_N_0000,
	dmuls_M_1000_N_0000,
	addc_rm_rn_M_1000_N_0000,
	addv_rm_rn_M_1000_N_0000,
	cmpeq_rm_rn_M_1001_N_0000,
	unimplemented,
	cmphs_rm_rn_M_1001_N_0000,
	cmpge_rm_rn_M_1001_N_0000,
	div1_M_1001_N_0000,
	dmulu_M_1001_N_0000,
	cmphi_rm_rn_M_1001_N_0000,
	cmpgt_rm_rn_M_1001_N_0000,
	sub_M_1001_N_0000,
	unimplemented,
	subc_M_1001_N_0000,
	subv_M_1001_N_0000,
	add_rm_rn_M_1001_N_0000,
	dmuls_M_1001_N_0000,
	addc_rm_rn_M_1001_N_0000,
	addv_rm_rn_M_1001_N_0000,
	cmpeq_rm_rn_M_1010_N_0000,
	unimplemented,
	cmphs_rm_rn_M_1010_N_0000,
	cmpge_rm_rn_M_1010_N_0000,
	div1_M_1010_N_0000,
	dmulu_M_1010_N_0000,
	cmphi_rm_rn_M_1010_N_0000,
	cmpgt_rm_rn_M_1010_N_0000,
	sub_M_1010_N_0000,
	unimplemented,
	subc_M_1010_N_0000,
	subv_M_1010_N_0000,
	add_rm_rn_M_1010_N_0000,
	dmuls_M_1010_N_0000,
	addc_rm_rn_M_1010_N_0000,
	addv_rm_rn_M_1010_N_0000,
	cmpeq_rm_rn_M_1011_N_0000,
	unimplemented,
	cmphs_rm_rn_M_1011_N_0000,
	cmpge_rm_rn_M_1011_N_0000,
	div1_M_1011_N_0000,
	dmulu_M_1011_N_0000,
	cmphi_rm_rn_M_1011_N_0000,
	cmpgt_rm_rn_M_1011_N_0000,
	sub_M_1011_N_0000,
	unimplemented,
	subc_M_1011_N_0000,
	subv_M_1011_N_0000,
	add_rm_rn_M_1011_N_0000,
	dmuls_M_1011_N_0000,
	addc_rm_rn_M_1011_N_0000,
	addv_rm_rn_M_1011_N_0000,
	cmpeq_rm_rn_M_1100_N_0000,
	unimplemented,
	cmphs_rm_rn_M_1100_N_0000,
	cmpge_rm_rn_M_1100_N_0000,
	div1_M_1100_N_0000,
	dmulu_M_1100_N_0000,
	cmphi_rm_rn_M_1100_N_0000,
	cmpgt_rm_rn_M_1100_N_0000,
	sub_M_1100_N_0000,
	unimplemented,
	subc_M_1100_N_0000,
	subv_M_1100_N_0000,
	add_rm_rn_M_1100_N_0000,
	dmuls_M_1100_N_0000,
	addc_rm_rn_M_1100_N_0000,
	addv_rm_rn_M_1100_N_0000,
	cmpeq_rm_rn_M_1101_N_0000,
	unimplemented,
	cmphs_rm_rn_M_1101_N_0000,
	cmpge_rm_rn_M_1101_N_0000,
	div1_M_1101_N_0000,
	dmulu_M_1101_N_0000,
	cmphi_rm_rn_M_1101_N_0000,
	cmpgt_rm_rn_M_1101_N_0000,
	sub_M_1101_N_0000,
	unimplemented,
	subc_M_1101_N_0000,
	subv_M_1101_N_0000,
	add_rm_rn_M_1101_N_0000,
	dmuls_M_1101_N_0000,
	addc_rm_rn_M_1101_N_0000,
	addv_rm_rn_M_1101_N_0000,
	cmpeq_rm_rn_M_1110_N_0000,
	unimplemented,
	cmphs_rm_rn_M_1110_N_0000,
	cmpge_rm_rn_M_1110_N_0000,
	div1_M_1110_N_0000,
	dmulu_M_1110_N_0000,
	cmphi_rm_rn_M_1110_N_0000,
	cmpgt_rm_rn_M_1110_N_0000,
	sub_M_1110_N_0000,
	unimplemented,
	subc_M_1110_N_0000,
	subv_M_1110_N_0000,
	add_rm_rn_M_1110_N_0000,
	dmuls_M_1110_N_0000,
	addc_rm_rn_M_1110_N_0000,
	addv_rm_rn_M_1110_N_0000,
	cmpeq_rm_rn_M_1111_N_0000,
	unimplemented,
	cmphs_rm_rn_M_1111_N_0000,
	cmpge_rm_rn_M_1111_N_0000,
	div1_M_1111_N_0000,
	dmulu_M_1111_N_0000,
	cmphi_rm_rn_M_1111_N_0000,
	cmpgt_rm_rn_M_1111_N_0000,
	sub_M_1111_N_0000,
	unimplemented,
	subc_M_1111_N_0000,
	subv_M_1111_N_0000,
	add_rm_rn_M_1111_N_0000,
	dmuls_M_1111_N_0000,
	addc_rm_rn_M_1111_N_0000,
	addv_rm_rn_M_1111_N_0000,
	cmpeq_rm_rn_M_0000_N_0001,
	unimplemented,
	cmphs_rm_rn_M_0000_N_0001,
	cmpge_rm_rn_M_0000_N_0001,
	div1_M_0000_N_0001,
	dmulu_M_0000_N_0001,
	cmphi_rm_rn_M_0000_N_0001,
	cmpgt_rm_rn_M_0000_N_0001,
	sub_M_0000_N_0001,
	unimplemented,
	subc_M_0000_N_0001,
	subv_M_0000_N_0001,
	add_rm_rn_M_0000_N_0001,
	dmuls_M_0000_N_0001,
	addc_rm_rn_M_0000_N_0001,
	addv_rm_rn_M_0000_N_0001,
	cmpeq_rm_rn_M_0001_N_0001,
	unimplemented,
	cmphs_rm_rn_M_0001_N_0001,
	cmpge_rm_rn_M_0001_N_0001,
	div1_M_0001_N_0001,
	dmulu_M_0001_N_0001,
	cmphi_rm_rn_M_0001_N_0001,
	cmpgt_rm_rn_M_0001_N_0001,
	sub_M_0001_N_0001,
	unimplemented,
	subc_M_0001_N_0001,
	subv_M_0001_N_0001,
	add_rm_rn_M_0001_N_0001,
	dmuls_M_0001_N_0001,
	addc_rm_rn_M_0001_N_0001,
	addv_rm_rn_M_0001_N_0001,
	cmpeq_rm_rn_M_0010_N_0001,
	unimplemented,
	cmphs_rm_rn_M_0010_N_0001,
	cmpge_rm_rn_M_0010_N_0001,
	div1_M_0010_N_0001,
	dmulu_M_0010_N_0001,
	cmphi_rm_rn_M_0010_N_0001,
	cmpgt_rm_rn_M_0010_N_0001,
	sub_M_0010_N_0001,
	unimplemented,
	subc_M_0010_N_0001,
	subv_M_0010_N_0001,
	add_rm_rn_M_0010_N_0001,
	dmuls_M_0010_N_0001,
	addc_rm_rn_M_0010_N_0001,
	addv_rm_rn_M_0010_N_0001,
	cmpeq_rm_rn_M_0011_N_0001,
	unimplemented,
	cmphs_rm_rn_M_0011_N_0001,
	cmpge_rm_rn_M_0011_N_0001,
	div1_M_0011_N_0001,
	dmulu_M_0011_N_0001,
	cmphi_rm_rn_M_0011_N_0001,
	cmpgt_rm_rn_M_0011_N_0001,
	sub_M_0011_N_0001,
	unimplemented,
	subc_M_0011_N_0001,
	subv_M_0011_N_0001,
	add_rm_rn_M_0011_N_0001,
	dmuls_M_0011_N_0001,
	addc_rm_rn_M_0011_N_0001,
	addv_rm_rn_M_0011_N_0001,
	cmpeq_rm_rn_M_0100_N_0001,
	unimplemented,
	cmphs_rm_rn_M_0100_N_0001,
	cmpge_rm_rn_M_0100_N_0001,
	div1_M_0100_N_0001,
	dmulu_M_0100_N_0001,
	cmphi_rm_rn_M_0100_N_0001,
	cmpgt_rm_rn_M_0100_N_0001,
	sub_M_0100_N_0001,
	unimplemented,
	subc_M_0100_N_0001,
	subv_M_0100_N_0001,
	add_rm_rn_M_0100_N_0001,
	dmuls_M_0100_N_0001,
	addc_rm_rn_M_0100_N_0001,
	addv_rm_rn_M_0100_N_0001,
	cmpeq_rm_rn_M_0101_N_0001,
	unimplemented,
	cmphs_rm_rn_M_0101_N_0001,
	cmpge_rm_rn_M_0101_N_0001,
	div1_M_0101_N_0001,
	dmulu_M_0101_N_0001,
	cmphi_rm_rn_M_0101_N_0001,
	cmpgt_rm_rn_M_0101_N_0001,
	sub_M_0101_N_0001,
	unimplemented,
	subc_M_0101_N_0001,
	subv_M_0101_N_0001,
	add_rm_rn_M_0101_N_0001,
	dmuls_M_0101_N_0001,
	addc_rm_rn_M_0101_N_0001,
	addv_rm_rn_M_0101_N_0001,
	cmpeq_rm_rn_M_0110_N_0001,
	unimplemented,
	cmphs_rm_rn_M_0110_N_0001,
	cmpge_rm_rn_M_0110_N_0001,
	div1_M_0110_N_0001,
	dmulu_M_0110_N_0001,
	cmphi_rm_rn_M_0110_N_0001,
	cmpgt_rm_rn_M_0110_N_0001,
	sub_M_0110_N_0001,
	unimplemented,
	subc_M_0110_N_0001,
	subv_M_0110_N_0001,
	add_rm_rn_M_0110_N_0001,
	dmuls_M_0110_N_0001,
	addc_rm_rn_M_0110_N_0001,
	addv_rm_rn_M_0110_N_0001,
	cmpeq_rm_rn_M_0111_N_0001,
	unimplemented,
	cmphs_rm_rn_M_0111_N_0001,
	cmpge_rm_rn_M_0111_N_0001,
	div1_M_0111_N_0001,
	dmulu_M_0111_N_0001,
	cmphi_rm_rn_M_0111_N_0001,
	cmpgt_rm_rn_M_0111_N_0001,
	sub_M_0111_N_0001,
	unimplemented,
	subc_M_0111_N_0001,
	subv_M_0111_N_0001,
	add_rm_rn_M_0111_N_0001,
	dmuls_M_0111_N_0001,
	addc_rm_rn_M_0111_N_0001,
	addv_rm_rn_M_0111_N_0001,
	cmpeq_rm_rn_M_1000_N_0001,
	unimplemented,
	cmphs_rm_rn_M_1000_N_0001,
	cmpge_rm_rn_M_1000_N_0001,
	div1_M_1000_N_0001,
	dmulu_M_1000_N_0001,
	cmphi_rm_rn_M_1000_N_0001,
	cmpgt_rm_rn_M_1000_N_0001,
	sub_M_1000_N_0001,
	unimplemented,
	subc_M_1000_N_0001,
	subv_M_1000_N_0001,
	add_rm_rn_M_1000_N_0001,
	dmuls_M_1000_N_0001,
	addc_rm_rn_M_1000_N_0001,
	addv_rm_rn_M_1000_N_0001,
	cmpeq_rm_rn_M_1001_N_0001,
	unimplemented,
	cmphs_rm_rn_M_1001_N_0001,
	cmpge_rm_rn_M_1001_N_0001,
	div1_M_1001_N_0001,
	dmulu_M_1001_N_0001,
	cmphi_rm_rn_M_1001_N_0001,
	cmpgt_rm_rn_M_1001_N_0001,
	sub_M_1001_N_0001,
	unimplemented,
	subc_M_1001_N_0001,
	subv_M_1001_N_0001,
	add_rm_rn_M_1001_N_0001,
	dmuls_M_1001_N_0001,
	addc_rm_rn_M_1001_N_0001,
	addv_rm_rn_M_1001_N_0001,
	cmpeq_rm_rn_M_1010_N_0001,
	unimplemented,
	cmphs_rm_rn_M_1010_N_0001,
	cmpge_rm_rn_M_1010_N_0001,
	div1_M_1010_N_0001,
	dmulu_M_1010_N_0001,
	cmphi_rm_rn_M_1010_N_0001,
	cmpgt_rm_rn_M_1010_N_0001,
	sub_M_1010_N_0001,
	unimplemented,
	subc_M_1010_N_0001,
	subv_M_1010_N_0001,
	add_rm_rn_M_1010_N_0001,
	dmuls_M_1010_N_0001,
	addc_rm_rn_M_1010_N_0001,
	addv_rm_rn_M_1010_N_0001,
	cmpeq_rm_rn_M_1011_N_0001,
	unimplemented,
	cmphs_rm_rn_M_1011_N_0001,
	cmpge_rm_rn_M_1011_N_0001,
	div1_M_1011_N_0001,
	dmulu_M_1011_N_0001,
	cmphi_rm_rn_M_1011_N_0001,
	cmpgt_rm_rn_M_1011_N_0001,
	sub_M_1011_N_0001,
	unimplemented,
	subc_M_1011_N_0001,
	subv_M_1011_N_0001,
	add_rm_rn_M_1011_N_0001,
	dmuls_M_1011_N_0001,
	addc_rm_rn_M_1011_N_0001,
	addv_rm_rn_M_1011_N_0001,
	cmpeq_rm_rn_M_1100_N_0001,
	unimplemented,
	cmphs_rm_rn_M_1100_N_0001,
	cmpge_rm_rn_M_1100_N_0001,
	div1_M_1100_N_0001,
	dmulu_M_1100_N_0001,
	cmphi_rm_rn_M_1100_N_0001,
	cmpgt_rm_rn_M_1100_N_0001,
	sub_M_1100_N_0001,
	unimplemented,
	subc_M_1100_N_0001,
	subv_M_1100_N_0001,
	add_rm_rn_M_1100_N_0001,
	dmuls_M_1100_N_0001,
	addc_rm_rn_M_1100_N_0001,
	addv_rm_rn_M_1100_N_0001,
	cmpeq_rm_rn_M_1101_N_0001,
	unimplemented,
	cmphs_rm_rn_M_1101_N_0001,
	cmpge_rm_rn_M_1101_N_0001,
	div1_M_1101_N_0001,
	dmulu_M_1101_N_0001,
	cmphi_rm_rn_M_1101_N_0001,
	cmpgt_rm_rn_M_1101_N_0001,
	sub_M_1101_N_0001,
	unimplemented,
	subc_M_1101_N_0001,
	subv_M_1101_N_0001,
	add_rm_rn_M_1101_N_0001,
	dmuls_M_1101_N_0001,
	addc_rm_rn_M_1101_N_0001,
	addv_rm_rn_M_1101_N_0001,
	cmpeq_rm_rn_M_1110_N_0001,
	unimplemented,
	cmphs_rm_rn_M_1110_N_0001,
	cmpge_rm_rn_M_1110_N_0001,
	div1_M_1110_N_0001,
	dmulu_M_1110_N_0001,
	cmphi_rm_rn_M_1110_N_0001,
	cmpgt_rm_rn_M_1110_N_0001,
	sub_M_1110_N_0001,
	unimplemented,
	subc_M_1110_N_0001,
	subv_M_1110_N_0001,
	add_rm_rn_M_1110_N_0001,
	dmuls_M_1110_N_0001,
	addc_rm_rn_M_1110_N_0001,
	addv_rm_rn_M_1110_N_0001,
	cmpeq_rm_rn_M_1111_N_0001,
	unimplemented,
	cmphs_rm_rn_M_1111_N_0001,
	cmpge_rm_rn_M_1111_N_0001,
	div1_M_1111_N_0001,
	dmulu_M_1111_N_0001,
	cmphi_rm_rn_M_1111_N_0001,
	cmpgt_rm_rn_M_1111_N_0001,
	sub_M_1111_N_0001,
	unimplemented,
	subc_M_1111_N_0001,
	subv_M_1111_N_0001,
	add_rm_rn_M_1111_N_0001,
	dmuls_M_1111_N_0001,
	addc_rm_rn_M_1111_N_0001,
	addv_rm_rn_M_1111_N_0001,
	cmpeq_rm_rn_M_0000_N_0010,
	unimplemented,
	cmphs_rm_rn_M_0000_N_0010,
	cmpge_rm_rn_M_0000_N_0010,
	div1_M_0000_N_0010,
	dmulu_M_0000_N_0010,
	cmphi_rm_rn_M_0000_N_0010,
	cmpgt_rm_rn_M_0000_N_0010,
	sub_M_0000_N_0010,
	unimplemented,
	subc_M_0000_N_0010,
	subv_M_0000_N_0010,
	add_rm_rn_M_0000_N_0010,
	dmuls_M_0000_N_0010,
	addc_rm_rn_M_0000_N_0010,
	addv_rm_rn_M_0000_N_0010,
	cmpeq_rm_rn_M_0001_N_0010,
	unimplemented,
	cmphs_rm_rn_M_0001_N_0010,
	cmpge_rm_rn_M_0001_N_0010,
	div1_M_0001_N_0010,
	dmulu_M_0001_N_0010,
	cmphi_rm_rn_M_0001_N_0010,
	cmpgt_rm_rn_M_0001_N_0010,
	sub_M_0001_N_0010,
	unimplemented,
	subc_M_0001_N_0010,
	subv_M_0001_N_0010,
	add_rm_rn_M_0001_N_0010,
	dmuls_M_0001_N_0010,
	addc_rm_rn_M_0001_N_0010,
	addv_rm_rn_M_0001_N_0010,
	cmpeq_rm_rn_M_0010_N_0010,
	unimplemented,
	cmphs_rm_rn_M_0010_N_0010,
	cmpge_rm_rn_M_0010_N_0010,
	div1_M_0010_N_0010,
	dmulu_M_0010_N_0010,
	cmphi_rm_rn_M_0010_N_0010,
	cmpgt_rm_rn_M_0010_N_0010,
	sub_M_0010_N_0010,
	unimplemented,
	subc_M_0010_N_0010,
	subv_M_0010_N_0010,
	add_rm_rn_M_0010_N_0010,
	dmuls_M_0010_N_0010,
	addc_rm_rn_M_0010_N_0010,
	addv_rm_rn_M_0010_N_0010,
	cmpeq_rm_rn_M_0011_N_0010,
	unimplemented,
	cmphs_rm_rn_M_0011_N_0010,
	cmpge_rm_rn_M_0011_N_0010,
	div1_M_0011_N_0010,
	dmulu_M_0011_N_0010,
	cmphi_rm_rn_M_0011_N_0010,
	cmpgt_rm_rn_M_0011_N_0010,
	sub_M_0011_N_0010,
	unimplemented,
	subc_M_0011_N_0010,
	subv_M_0011_N_0010,
	add_rm_rn_M_0011_N_0010,
	dmuls_M_0011_N_0010,
	addc_rm_rn_M_0011_N_0010,
	addv_rm_rn_M_0011_N_0010,
	cmpeq_rm_rn_M_0100_N_0010,
	unimplemented,
	cmphs_rm_rn_M_0100_N_0010,
	cmpge_rm_rn_M_0100_N_0010,
	div1_M_0100_N_0010,
	dmulu_M_0100_N_0010,
	cmphi_rm_rn_M_0100_N_0010,
	cmpgt_rm_rn_M_0100_N_0010,
	sub_M_0100_N_0010,
	unimplemented,
	subc_M_0100_N_0010,
	subv_M_0100_N_0010,
	add_rm_rn_M_0100_N_0010,
	dmuls_M_0100_N_0010,
	addc_rm_rn_M_0100_N_0010,
	addv_rm_rn_M_0100_N_0010,
	cmpeq_rm_rn_M_0101_N_0010,
	unimplemented,
	cmphs_rm_rn_M_0101_N_0010,
	cmpge_rm_rn_M_0101_N_0010,
	div1_M_0101_N_0010,
	dmulu_M_0101_N_0010,
	cmphi_rm_rn_M_0101_N_0010,
	cmpgt_rm_rn_M_0101_N_0010,
	sub_M_0101_N_0010,
	unimplemented,
	subc_M_0101_N_0010,
	subv_M_0101_N_0010,
	add_rm_rn_M_0101_N_0010,
	dmuls_M_0101_N_0010,
	addc_rm_rn_M_0101_N_0010,
	addv_rm_rn_M_0101_N_0010,
	cmpeq_rm_rn_M_0110_N_0010,
	unimplemented,
	cmphs_rm_rn_M_0110_N_0010,
	cmpge_rm_rn_M_0110_N_0010,
	div1_M_0110_N_0010,
	dmulu_M_0110_N_0010,
	cmphi_rm_rn_M_0110_N_0010,
	cmpgt_rm_rn_M_0110_N_0010,
	sub_M_0110_N_0010,
	unimplemented,
	subc_M_0110_N_0010,
	subv_M_0110_N_0010,
	add_rm_rn_M_0110_N_0010,
	dmuls_M_0110_N_0010,
	addc_rm_rn_M_0110_N_0010,
	addv_rm_rn_M_0110_N_0010,
	cmpeq_rm_rn_M_0111_N_0010,
	unimplemented,
	cmphs_rm_rn_M_0111_N_0010,
	cmpge_rm_rn_M_0111_N_0010,
	div1_M_0111_N_0010,
	dmulu_M_0111_N_0010,
	cmphi_rm_rn_M_0111_N_0010,
	cmpgt_rm_rn_M_0111_N_0010,
	sub_M_0111_N_0010,
	unimplemented,
	subc_M_0111_N_0010,
	subv_M_0111_N_0010,
	add_rm_rn_M_0111_N_0010,
	dmuls_M_0111_N_0010,
	addc_rm_rn_M_0111_N_0010,
	addv_rm_rn_M_0111_N_0010,
	cmpeq_rm_rn_M_1000_N_0010,
	unimplemented,
	cmphs_rm_rn_M_1000_N_0010,
	cmpge_rm_rn_M_1000_N_0010,
	div1_M_1000_N_0010,
	dmulu_M_1000_N_0010,
	cmphi_rm_rn_M_1000_N_0010,
	cmpgt_rm_rn_M_1000_N_0010,
	sub_M_1000_N_0010,
	unimplemented,
	subc_M_1000_N_0010,
	subv_M_1000_N_0010,
	add_rm_rn_M_1000_N_0010,
	dmuls_M_1000_N_0010,
	addc_rm_rn_M_1000_N_0010,
	addv_rm_rn_M_1000_N_0010,
	cmpeq_rm_rn_M_1001_N_0010,
	unimplemented,
	cmphs_rm_rn_M_1001_N_0010,
	cmpge_rm_rn_M_1001_N_0010,
	div1_M_1001_N_0010,
	dmulu_M_1001_N_0010,
	cmphi_rm_rn_M_1001_N_0010,
	cmpgt_rm_rn_M_1001_N_0010,
	sub_M_1001_N_0010,
	unimplemented,
	subc_M_1001_N_0010,
	subv_M_1001_N_0010,
	add_rm_rn_M_1001_N_0010,
	dmuls_M_1001_N_0010,
	addc_rm_rn_M_1001_N_0010,
	addv_rm_rn_M_1001_N_0010,
	cmpeq_rm_rn_M_1010_N_0010,
	unimplemented,
	cmphs_rm_rn_M_1010_N_0010,
	cmpge_rm_rn_M_1010_N_0010,
	div1_M_1010_N_0010,
	dmulu_M_1010_N_0010,
	cmphi_rm_rn_M_1010_N_0010,
	cmpgt_rm_rn_M_1010_N_0010,
	sub_M_1010_N_0010,
	unimplemented,
	subc_M_1010_N_0010,
	subv_M_1010_N_0010,
	add_rm_rn_M_1010_N_0010,
	dmuls_M_1010_N_0010,
	addc_rm_rn_M_1010_N_0010,
	addv_rm_rn_M_1010_N_0010,
	cmpeq_rm_rn_M_1011_N_0010,
	unimplemented,
	cmphs_rm_rn_M_1011_N_0010,
	cmpge_rm_rn_M_1011_N_0010,
	div1_M_1011_N_0010,
	dmulu_M_1011_N_0010,
	cmphi_rm_rn_M_1011_N_0010,
	cmpgt_rm_rn_M_1011_N_0010,
	sub_M_1011_N_0010,
	unimplemented,
	subc_M_1011_N_0010,
	subv_M_1011_N_0010,
	add_rm_rn_M_1011_N_0010,
	dmuls_M_1011_N_0010,
	addc_rm_rn_M_1011_N_0010,
	addv_rm_rn_M_1011_N_0010,
	cmpeq_rm_rn_M_1100_N_0010,
	unimplemented,
	cmphs_rm_rn_M_1100_N_0010,
	cmpge_rm_rn_M_1100_N_0010,
	div1_M_1100_N_0010,
	dmulu_M_1100_N_0010,
	cmphi_rm_rn_M_1100_N_0010,
	cmpgt_rm_rn_M_1100_N_0010,
	sub_M_1100_N_0010,
	unimplemented,
	subc_M_1100_N_0010,
	subv_M_1100_N_0010,
	add_rm_rn_M_1100_N_0010,
	dmuls_M_1100_N_0010,
	addc_rm_rn_M_1100_N_0010,
	addv_rm_rn_M_1100_N_0010,
	cmpeq_rm_rn_M_1101_N_0010,
	unimplemented,
	cmphs_rm_rn_M_1101_N_0010,
	cmpge_rm_rn_M_1101_N_0010,
	div1_M_1101_N_0010,
	dmulu_M_1101_N_0010,
	cmphi_rm_rn_M_1101_N_0010,
	cmpgt_rm_rn_M_1101_N_0010,
	sub_M_1101_N_0010,
	unimplemented,
	subc_M_1101_N_0010,
	subv_M_1101_N_0010,
	add_rm_rn_M_1101_N_0010,
	dmuls_M_1101_N_0010,
	addc_rm_rn_M_1101_N_0010,
	addv_rm_rn_M_1101_N_0010,
	cmpeq_rm_rn_M_1110_N_0010,
	unimplemented,
	cmphs_rm_rn_M_1110_N_0010,
	cmpge_rm_rn_M_1110_N_0010,
	div1_M_1110_N_0010,
	dmulu_M_1110_N_0010,
	cmphi_rm_rn_M_1110_N_0010,
	cmpgt_rm_rn_M_1110_N_0010,
	sub_M_1110_N_0010,
	unimplemented,
	subc_M_1110_N_0010,
	subv_M_1110_N_0010,
	add_rm_rn_M_1110_N_0010,
	dmuls_M_1110_N_0010,
	addc_rm_rn_M_1110_N_0010,
	addv_rm_rn_M_1110_N_0010,
	cmpeq_rm_rn_M_1111_N_0010,
	unimplemented,
	cmphs_rm_rn_M_1111_N_0010,
	cmpge_rm_rn_M_1111_N_0010,
	div1_M_1111_N_0010,
	dmulu_M_1111_N_0010,
	cmphi_rm_rn_M_1111_N_0010,
	cmpgt_rm_rn_M_1111_N_0010,
	sub_M_1111_N_0010,
	unimplemented,
	subc_M_1111_N_0010,
	subv_M_1111_N_0010,
	add_rm_rn_M_1111_N_0010,
	dmuls_M_1111_N_0010,
	addc_rm_rn_M_1111_N_0010,
	addv_rm_rn_M_1111_N_0010,
	cmpeq_rm_rn_M_0000_N_0011,
	unimplemented,
	cmphs_rm_rn_M_0000_N_0011,
	cmpge_rm_rn_M_0000_N_0011,
	div1_M_0000_N_0011,
	dmulu_M_0000_N_0011,
	cmphi_rm_rn_M_0000_N_0011,
	cmpgt_rm_rn_M_0000_N_0011,
	sub_M_0000_N_0011,
	unimplemented,
	subc_M_0000_N_0011,
	subv_M_0000_N_0011,
	add_rm_rn_M_0000_N_0011,
	dmuls_M_0000_N_0011,
	addc_rm_rn_M_0000_N_0011,
	addv_rm_rn_M_0000_N_0011,
	cmpeq_rm_rn_M_0001_N_0011,
	unimplemented,
	cmphs_rm_rn_M_0001_N_0011,
	cmpge_rm_rn_M_0001_N_0011,
	div1_M_0001_N_0011,
	dmulu_M_0001_N_0011,
	cmphi_rm_rn_M_0001_N_0011,
	cmpgt_rm_rn_M_0001_N_0011,
	sub_M_0001_N_0011,
	unimplemented,
	subc_M_0001_N_0011,
	subv_M_0001_N_0011,
	add_rm_rn_M_0001_N_0011,
	dmuls_M_0001_N_0011,
	addc_rm_rn_M_0001_N_0011,
	addv_rm_rn_M_0001_N_0011,
	cmpeq_rm_rn_M_0010_N_0011,
	unimplemented,
	cmphs_rm_rn_M_0010_N_0011,
	cmpge_rm_rn_M_0010_N_0011,
	div1_M_0010_N_0011,
	dmulu_M_0010_N_0011,
	cmphi_rm_rn_M_0010_N_0011,
	cmpgt_rm_rn_M_0010_N_0011,
	sub_M_0010_N_0011,
	unimplemented,
	subc_M_0010_N_0011,
	subv_M_0010_N_0011,
	add_rm_rn_M_0010_N_0011,
	dmuls_M_0010_N_0011,
	addc_rm_rn_M_0010_N_0011,
	addv_rm_rn_M_0010_N_0011,
	cmpeq_rm_rn_M_0011_N_0011,
	unimplemented,
	cmphs_rm_rn_M_0011_N_0011,
	cmpge_rm_rn_M_0011_N_0011,
	div1_M_0011_N_0011,
	dmulu_M_0011_N_0011,
	cmphi_rm_rn_M_0011_N_0011,
	cmpgt_rm_rn_M_0011_N_0011,
	sub_M_0011_N_0011,
	unimplemented,
	subc_M_0011_N_0011,
	subv_M_0011_N_0011,
	add_rm_rn_M_0011_N_0011,
	dmuls_M_0011_N_0011,
	addc_rm_rn_M_0011_N_0011,
	addv_rm_rn_M_0011_N_0011,
	cmpeq_rm_rn_M_0100_N_0011,
	unimplemented,
	cmphs_rm_rn_M_0100_N_0011,
	cmpge_rm_rn_M_0100_N_0011,
	div1_M_0100_N_0011,
	dmulu_M_0100_N_0011,
	cmphi_rm_rn_M_0100_N_0011,
	cmpgt_rm_rn_M_0100_N_0011,
	sub_M_0100_N_0011,
	unimplemented,
	subc_M_0100_N_0011,
	subv_M_0100_N_0011,
	add_rm_rn_M_0100_N_0011,
	dmuls_M_0100_N_0011,
	addc_rm_rn_M_0100_N_0011,
	addv_rm_rn_M_0100_N_0011,
	cmpeq_rm_rn_M_0101_N_0011,
	unimplemented,
	cmphs_rm_rn_M_0101_N_0011,
	cmpge_rm_rn_M_0101_N_0011,
	div1_M_0101_N_0011,
	dmulu_M_0101_N_0011,
	cmphi_rm_rn_M_0101_N_0011,
	cmpgt_rm_rn_M_0101_N_0011,
	sub_M_0101_N_0011,
	unimplemented,
	subc_M_0101_N_0011,
	subv_M_0101_N_0011,
	add_rm_rn_M_0101_N_0011,
	dmuls_M_0101_N_0011,
	addc_rm_rn_M_0101_N_0011,
	addv_rm_rn_M_0101_N_0011,
	cmpeq_rm_rn_M_0110_N_0011,
	unimplemented,
	cmphs_rm_rn_M_0110_N_0011,
	cmpge_rm_rn_M_0110_N_0011,
	div1_M_0110_N_0011,
	dmulu_M_0110_N_0011,
	cmphi_rm_rn_M_0110_N_0011,
	cmpgt_rm_rn_M_0110_N_0011,
	sub_M_0110_N_0011,
	unimplemented,
	subc_M_0110_N_0011,
	subv_M_0110_N_0011,
	add_rm_rn_M_0110_N_0011,
	dmuls_M_0110_N_0011,
	addc_rm_rn_M_0110_N_0011,
	addv_rm_rn_M_0110_N_0011,
	cmpeq_rm_rn_M_0111_N_0011,
	unimplemented,
	cmphs_rm_rn_M_0111_N_0011,
	cmpge_rm_rn_M_0111_N_0011,
	div1_M_0111_N_0011,
	dmulu_M_0111_N_0011,
	cmphi_rm_rn_M_0111_N_0011,
	cmpgt_rm_rn_M_0111_N_0011,
	sub_M_0111_N_0011,
	unimplemented,
	subc_M_0111_N_0011,
	subv_M_0111_N_0011,
	add_rm_rn_M_0111_N_0011,
	dmuls_M_0111_N_0011,
	addc_rm_rn_M_0111_N_0011,
	addv_rm_rn_M_0111_N_0011,
	cmpeq_rm_rn_M_1000_N_0011,
	unimplemented,
	cmphs_rm_rn_M_1000_N_0011,
	cmpge_rm_rn_M_1000_N_0011,
	div1_M_1000_N_0011,
	dmulu_M_1000_N_0011,
	cmphi_rm_rn_M_1000_N_0011,
	cmpgt_rm_rn_M_1000_N_0011,
	sub_M_1000_N_0011,
	unimplemented,
	subc_M_1000_N_0011,
	subv_M_1000_N_0011,
	add_rm_rn_M_1000_N_0011,
	dmuls_M_1000_N_0011,
	addc_rm_rn_M_1000_N_0011,
	addv_rm_rn_M_1000_N_0011,
	cmpeq_rm_rn_M_1001_N_0011,
	unimplemented,
	cmphs_rm_rn_M_1001_N_0011,
	cmpge_rm_rn_M_1001_N_0011,
	div1_M_1001_N_0011,
	dmulu_M_1001_N_0011,
	cmphi_rm_rn_M_1001_N_0011,
	cmpgt_rm_rn_M_1001_N_0011,
	sub_M_1001_N_0011,
	unimplemented,
	subc_M_1001_N_0011,
	subv_M_1001_N_0011,
	add_rm_rn_M_1001_N_0011,
	dmuls_M_1001_N_0011,
	addc_rm_rn_M_1001_N_0011,
	addv_rm_rn_M_1001_N_0011,
	cmpeq_rm_rn_M_1010_N_0011,
	unimplemented,
	cmphs_rm_rn_M_1010_N_0011,
	cmpge_rm_rn_M_1010_N_0011,
	div1_M_1010_N_0011,
	dmulu_M_1010_N_0011,
	cmphi_rm_rn_M_1010_N_0011,
	cmpgt_rm_rn_M_1010_N_0011,
	sub_M_1010_N_0011,
	unimplemented,
	subc_M_1010_N_0011,
	subv_M_1010_N_0011,
	add_rm_rn_M_1010_N_0011,
	dmuls_M_1010_N_0011,
	addc_rm_rn_M_1010_N_0011,
	addv_rm_rn_M_1010_N_0011,
	cmpeq_rm_rn_M_1011_N_0011,
	unimplemented,
	cmphs_rm_rn_M_1011_N_0011,
	cmpge_rm_rn_M_1011_N_0011,
	div1_M_1011_N_0011,
	dmulu_M_1011_N_0011,
	cmphi_rm_rn_M_1011_N_0011,
	cmpgt_rm_rn_M_1011_N_0011,
	sub_M_1011_N_0011,
	unimplemented,
	subc_M_1011_N_0011,
	subv_M_1011_N_0011,
	add_rm_rn_M_1011_N_0011,
	dmuls_M_1011_N_0011,
	addc_rm_rn_M_1011_N_0011,
	addv_rm_rn_M_1011_N_0011,
	cmpeq_rm_rn_M_1100_N_0011,
	unimplemented,
	cmphs_rm_rn_M_1100_N_0011,
	cmpge_rm_rn_M_1100_N_0011,
	div1_M_1100_N_0011,
	dmulu_M_1100_N_0011,
	cmphi_rm_rn_M_1100_N_0011,
	cmpgt_rm_rn_M_1100_N_0011,
	sub_M_1100_N_0011,
	unimplemented,
	subc_M_1100_N_0011,
	subv_M_1100_N_0011,
	add_rm_rn_M_1100_N_0011,
	dmuls_M_1100_N_0011,
	addc_rm_rn_M_1100_N_0011,
	addv_rm_rn_M_1100_N_0011,
	cmpeq_rm_rn_M_1101_N_0011,
	unimplemented,
	cmphs_rm_rn_M_1101_N_0011,
	cmpge_rm_rn_M_1101_N_0011,
	div1_M_1101_N_0011,
	dmulu_M_1101_N_0011,
	cmphi_rm_rn_M_1101_N_0011,
	cmpgt_rm_rn_M_1101_N_0011,
	sub_M_1101_N_0011,
	unimplemented,
	subc_M_1101_N_0011,
	subv_M_1101_N_0011,
	add_rm_rn_M_1101_N_0011,
	dmuls_M_1101_N_0011,
	addc_rm_rn_M_1101_N_0011,
	addv_rm_rn_M_1101_N_0011,
	cmpeq_rm_rn_M_1110_N_0011,
	unimplemented,
	cmphs_rm_rn_M_1110_N_0011,
	cmpge_rm_rn_M_1110_N_0011,
	div1_M_1110_N_0011,
	dmulu_M_1110_N_0011,
	cmphi_rm_rn_M_1110_N_0011,
	cmpgt_rm_rn_M_1110_N_0011,
	sub_M_1110_N_0011,
	unimplemented,
	subc_M_1110_N_0011,
	subv_M_1110_N_0011,
	add_rm_rn_M_1110_N_0011,
	dmuls_M_1110_N_0011,
	addc_rm_rn_M_1110_N_0011,
	addv_rm_rn_M_1110_N_0011,
	cmpeq_rm_rn_M_1111_N_0011,
	unimplemented,
	cmphs_rm_rn_M_1111_N_0011,
	cmpge_rm_rn_M_1111_N_0011,
	div1_M_1111_N_0011,
	dmulu_M_1111_N_0011,
	cmphi_rm_rn_M_1111_N_0011,
	cmpgt_rm_rn_M_1111_N_0011,
	sub_M_1111_N_0011,
	unimplemented,
	subc_M_1111_N_0011,
	subv_M_1111_N_0011,
	add_rm_rn_M_1111_N_0011,
	dmuls_M_1111_N_0011,
	addc_rm_rn_M_1111_N_0011,
	addv_rm_rn_M_1111_N_0011,
	cmpeq_rm_rn_M_0000_N_0100,
	unimplemented,
	cmphs_rm_rn_M_0000_N_0100,
	cmpge_rm_rn_M_0000_N_0100,
	div1_M_0000_N_0100,
	dmulu_M_0000_N_0100,
	cmphi_rm_rn_M_0000_N_0100,
	cmpgt_rm_rn_M_0000_N_0100,
	sub_M_0000_N_0100,
	unimplemented,
	subc_M_0000_N_0100,
	subv_M_0000_N_0100,
	add_rm_rn_M_0000_N_0100,
	dmuls_M_0000_N_0100,
	addc_rm_rn_M_0000_N_0100,
	addv_rm_rn_M_0000_N_0100,
	cmpeq_rm_rn_M_0001_N_0100,
	unimplemented,
	cmphs_rm_rn_M_0001_N_0100,
	cmpge_rm_rn_M_0001_N_0100,
	div1_M_0001_N_0100,
	dmulu_M_0001_N_0100,
	cmphi_rm_rn_M_0001_N_0100,
	cmpgt_rm_rn_M_0001_N_0100,
	sub_M_0001_N_0100,
	unimplemented,
	subc_M_0001_N_0100,
	subv_M_0001_N_0100,
	add_rm_rn_M_0001_N_0100,
	dmuls_M_0001_N_0100,
	addc_rm_rn_M_0001_N_0100,
	addv_rm_rn_M_0001_N_0100,
	cmpeq_rm_rn_M_0010_N_0100,
	unimplemented,
	cmphs_rm_rn_M_0010_N_0100,
	cmpge_rm_rn_M_0010_N_0100,
	div1_M_0010_N_0100,
	dmulu_M_0010_N_0100,
	cmphi_rm_rn_M_0010_N_0100,
	cmpgt_rm_rn_M_0010_N_0100,
	sub_M_0010_N_0100,
	unimplemented,
	subc_M_0010_N_0100,
	subv_M_0010_N_0100,
	add_rm_rn_M_0010_N_0100,
	dmuls_M_0010_N_0100,
	addc_rm_rn_M_0010_N_0100,
	addv_rm_rn_M_0010_N_0100,
	cmpeq_rm_rn_M_0011_N_0100,
	unimplemented,
	cmphs_rm_rn_M_0011_N_0100,
	cmpge_rm_rn_M_0011_N_0100,
	div1_M_0011_N_0100,
	dmulu_M_0011_N_0100,
	cmphi_rm_rn_M_0011_N_0100,
	cmpgt_rm_rn_M_0011_N_0100,
	sub_M_0011_N_0100,
	unimplemented,
	subc_M_0011_N_0100,
	subv_M_0011_N_0100,
	add_rm_rn_M_0011_N_0100,
	dmuls_M_0011_N_0100,
	addc_rm_rn_M_0011_N_0100,
	addv_rm_rn_M_0011_N_0100,
	cmpeq_rm_rn_M_0100_N_0100,
	unimplemented,
	cmphs_rm_rn_M_0100_N_0100,
	cmpge_rm_rn_M_0100_N_0100,
	div1_M_0100_N_0100,
	dmulu_M_0100_N_0100,
	cmphi_rm_rn_M_0100_N_0100,
	cmpgt_rm_rn_M_0100_N_0100,
	sub_M_0100_N_0100,
	unimplemented,
	subc_M_0100_N_0100,
	subv_M_0100_N_0100,
	add_rm_rn_M_0100_N_0100,
	dmuls_M_0100_N_0100,
	addc_rm_rn_M_0100_N_0100,
	addv_rm_rn_M_0100_N_0100,
	cmpeq_rm_rn_M_0101_N_0100,
	unimplemented,
	cmphs_rm_rn_M_0101_N_0100,
	cmpge_rm_rn_M_0101_N_0100,
	div1_M_0101_N_0100,
	dmulu_M_0101_N_0100,
	cmphi_rm_rn_M_0101_N_0100,
	cmpgt_rm_rn_M_0101_N_0100,
	sub_M_0101_N_0100,
	unimplemented,
	subc_M_0101_N_0100,
	subv_M_0101_N_0100,
	add_rm_rn_M_0101_N_0100,
	dmuls_M_0101_N_0100,
	addc_rm_rn_M_0101_N_0100,
	addv_rm_rn_M_0101_N_0100,
	cmpeq_rm_rn_M_0110_N_0100,
	unimplemented,
	cmphs_rm_rn_M_0110_N_0100,
	cmpge_rm_rn_M_0110_N_0100,
	div1_M_0110_N_0100,
	dmulu_M_0110_N_0100,
	cmphi_rm_rn_M_0110_N_0100,
	cmpgt_rm_rn_M_0110_N_0100,
	sub_M_0110_N_0100,
	unimplemented,
	subc_M_0110_N_0100,
	subv_M_0110_N_0100,
	add_rm_rn_M_0110_N_0100,
	dmuls_M_0110_N_0100,
	addc_rm_rn_M_0110_N_0100,
	addv_rm_rn_M_0110_N_0100,
	cmpeq_rm_rn_M_0111_N_0100,
	unimplemented,
	cmphs_rm_rn_M_0111_N_0100,
	cmpge_rm_rn_M_0111_N_0100,
	div1_M_0111_N_0100,
	dmulu_M_0111_N_0100,
	cmphi_rm_rn_M_0111_N_0100,
	cmpgt_rm_rn_M_0111_N_0100,
	sub_M_0111_N_0100,
	unimplemented,
	subc_M_0111_N_0100,
	subv_M_0111_N_0100,
	add_rm_rn_M_0111_N_0100,
	dmuls_M_0111_N_0100,
	addc_rm_rn_M_0111_N_0100,
	addv_rm_rn_M_0111_N_0100,
	cmpeq_rm_rn_M_1000_N_0100,
	unimplemented,
	cmphs_rm_rn_M_1000_N_0100,
	cmpge_rm_rn_M_1000_N_0100,
	div1_M_1000_N_0100,
	dmulu_M_1000_N_0100,
	cmphi_rm_rn_M_1000_N_0100,
	cmpgt_rm_rn_M_1000_N_0100,
	sub_M_1000_N_0100,
	unimplemented,
	subc_M_1000_N_0100,
	subv_M_1000_N_0100,
	add_rm_rn_M_1000_N_0100,
	dmuls_M_1000_N_0100,
	addc_rm_rn_M_1000_N_0100,
	addv_rm_rn_M_1000_N_0100,
	cmpeq_rm_rn_M_1001_N_0100,
	unimplemented,
	cmphs_rm_rn_M_1001_N_0100,
	cmpge_rm_rn_M_1001_N_0100,
	div1_M_1001_N_0100,
	dmulu_M_1001_N_0100,
	cmphi_rm_rn_M_1001_N_0100,
	cmpgt_rm_rn_M_1001_N_0100,
	sub_M_1001_N_0100,
	unimplemented,
	subc_M_1001_N_0100,
	subv_M_1001_N_0100,
	add_rm_rn_M_1001_N_0100,
	dmuls_M_1001_N_0100,
	addc_rm_rn_M_1001_N_0100,
	addv_rm_rn_M_1001_N_0100,
	cmpeq_rm_rn_M_1010_N_0100,
	unimplemented,
	cmphs_rm_rn_M_1010_N_0100,
	cmpge_rm_rn_M_1010_N_0100,
	div1_M_1010_N_0100,
	dmulu_M_1010_N_0100,
	cmphi_rm_rn_M_1010_N_0100,
	cmpgt_rm_rn_M_1010_N_0100,
	sub_M_1010_N_0100,
	unimplemented,
	subc_M_1010_N_0100,
	subv_M_1010_N_0100,
	add_rm_rn_M_1010_N_0100,
	dmuls_M_1010_N_0100,
	addc_rm_rn_M_1010_N_0100,
	addv_rm_rn_M_1010_N_0100,
	cmpeq_rm_rn_M_1011_N_0100,
	unimplemented,
	cmphs_rm_rn_M_1011_N_0100,
	cmpge_rm_rn_M_1011_N_0100,
	div1_M_1011_N_0100,
	dmulu_M_1011_N_0100,
	cmphi_rm_rn_M_1011_N_0100,
	cmpgt_rm_rn_M_1011_N_0100,
	sub_M_1011_N_0100,
	unimplemented,
	subc_M_1011_N_0100,
	subv_M_1011_N_0100,
	add_rm_rn_M_1011_N_0100,
	dmuls_M_1011_N_0100,
	addc_rm_rn_M_1011_N_0100,
	addv_rm_rn_M_1011_N_0100,
	cmpeq_rm_rn_M_1100_N_0100,
	unimplemented,
	cmphs_rm_rn_M_1100_N_0100,
	cmpge_rm_rn_M_1100_N_0100,
	div1_M_1100_N_0100,
	dmulu_M_1100_N_0100,
	cmphi_rm_rn_M_1100_N_0100,
	cmpgt_rm_rn_M_1100_N_0100,
	sub_M_1100_N_0100,
	unimplemented,
	subc_M_1100_N_0100,
	subv_M_1100_N_0100,
	add_rm_rn_M_1100_N_0100,
	dmuls_M_1100_N_0100,
	addc_rm_rn_M_1100_N_0100,
	addv_rm_rn_M_1100_N_0100,
	cmpeq_rm_rn_M_1101_N_0100,
	unimplemented,
	cmphs_rm_rn_M_1101_N_0100,
	cmpge_rm_rn_M_1101_N_0100,
	div1_M_1101_N_0100,
	dmulu_M_1101_N_0100,
	cmphi_rm_rn_M_1101_N_0100,
	cmpgt_rm_rn_M_1101_N_0100,
	sub_M_1101_N_0100,
	unimplemented,
	subc_M_1101_N_0100,
	subv_M_1101_N_0100,
	add_rm_rn_M_1101_N_0100,
	dmuls_M_1101_N_0100,
	addc_rm_rn_M_1101_N_0100,
	addv_rm_rn_M_1101_N_0100,
	cmpeq_rm_rn_M_1110_N_0100,
	unimplemented,
	cmphs_rm_rn_M_1110_N_0100,
	cmpge_rm_rn_M_1110_N_0100,
	div1_M_1110_N_0100,
	dmulu_M_1110_N_0100,
	cmphi_rm_rn_M_1110_N_0100,
	cmpgt_rm_rn_M_1110_N_0100,
	sub_M_1110_N_0100,
	unimplemented,
	subc_M_1110_N_0100,
	subv_M_1110_N_0100,
	add_rm_rn_M_1110_N_0100,
	dmuls_M_1110_N_0100,
	addc_rm_rn_M_1110_N_0100,
	addv_rm_rn_M_1110_N_0100,
	cmpeq_rm_rn_M_1111_N_0100,
	unimplemented,
	cmphs_rm_rn_M_1111_N_0100,
	cmpge_rm_rn_M_1111_N_0100,
	div1_M_1111_N_0100,
	dmulu_M_1111_N_0100,
	cmphi_rm_rn_M_1111_N_0100,
	cmpgt_rm_rn_M_1111_N_0100,
	sub_M_1111_N_0100,
	unimplemented,
	subc_M_1111_N_0100,
	subv_M_1111_N_0100,
	add_rm_rn_M_1111_N_0100,
	dmuls_M_1111_N_0100,
	addc_rm_rn_M_1111_N_0100,
	addv_rm_rn_M_1111_N_0100,
	cmpeq_rm_rn_M_0000_N_0101,
	unimplemented,
	cmphs_rm_rn_M_0000_N_0101,
	cmpge_rm_rn_M_0000_N_0101,
	div1_M_0000_N_0101,
	dmulu_M_0000_N_0101,
	cmphi_rm_rn_M_0000_N_0101,
	cmpgt_rm_rn_M_0000_N_0101,
	sub_M_0000_N_0101,
	unimplemented,
	subc_M_0000_N_0101,
	subv_M_0000_N_0101,
	add_rm_rn_M_0000_N_0101,
	dmuls_M_0000_N_0101,
	addc_rm_rn_M_0000_N_0101,
	addv_rm_rn_M_0000_N_0101,
	cmpeq_rm_rn_M_0001_N_0101,
	unimplemented,
	cmphs_rm_rn_M_0001_N_0101,
	cmpge_rm_rn_M_0001_N_0101,
	div1_M_0001_N_0101,
	dmulu_M_0001_N_0101,
	cmphi_rm_rn_M_0001_N_0101,
	cmpgt_rm_rn_M_0001_N_0101,
	sub_M_0001_N_0101,
	unimplemented,
	subc_M_0001_N_0101,
	subv_M_0001_N_0101,
	add_rm_rn_M_0001_N_0101,
	dmuls_M_0001_N_0101,
	addc_rm_rn_M_0001_N_0101,
	addv_rm_rn_M_0001_N_0101,
	cmpeq_rm_rn_M_0010_N_0101,
	unimplemented,
	cmphs_rm_rn_M_0010_N_0101,
	cmpge_rm_rn_M_0010_N_0101,
	div1_M_0010_N_0101,
	dmulu_M_0010_N_0101,
	cmphi_rm_rn_M_0010_N_0101,
	cmpgt_rm_rn_M_0010_N_0101,
	sub_M_0010_N_0101,
	unimplemented,
	subc_M_0010_N_0101,
	subv_M_0010_N_0101,
	add_rm_rn_M_0010_N_0101,
	dmuls_M_0010_N_0101,
	addc_rm_rn_M_0010_N_0101,
	addv_rm_rn_M_0010_N_0101,
	cmpeq_rm_rn_M_0011_N_0101,
	unimplemented,
	cmphs_rm_rn_M_0011_N_0101,
	cmpge_rm_rn_M_0011_N_0101,
	div1_M_0011_N_0101,
	dmulu_M_0011_N_0101,
	cmphi_rm_rn_M_0011_N_0101,
	cmpgt_rm_rn_M_0011_N_0101,
	sub_M_0011_N_0101,
	unimplemented,
	subc_M_0011_N_0101,
	subv_M_0011_N_0101,
	add_rm_rn_M_0011_N_0101,
	dmuls_M_0011_N_0101,
	addc_rm_rn_M_0011_N_0101,
	addv_rm_rn_M_0011_N_0101,
	cmpeq_rm_rn_M_0100_N_0101,
	unimplemented,
	cmphs_rm_rn_M_0100_N_0101,
	cmpge_rm_rn_M_0100_N_0101,
	div1_M_0100_N_0101,
	dmulu_M_0100_N_0101,
	cmphi_rm_rn_M_0100_N_0101,
	cmpgt_rm_rn_M_0100_N_0101,
	sub_M_0100_N_0101,
	unimplemented,
	subc_M_0100_N_0101,
	subv_M_0100_N_0101,
	add_rm_rn_M_0100_N_0101,
	dmuls_M_0100_N_0101,
	addc_rm_rn_M_0100_N_0101,
	addv_rm_rn_M_0100_N_0101,
	cmpeq_rm_rn_M_0101_N_0101,
	unimplemented,
	cmphs_rm_rn_M_0101_N_0101,
	cmpge_rm_rn_M_0101_N_0101,
	div1_M_0101_N_0101,
	dmulu_M_0101_N_0101,
	cmphi_rm_rn_M_0101_N_0101,
	cmpgt_rm_rn_M_0101_N_0101,
	sub_M_0101_N_0101,
	unimplemented,
	subc_M_0101_N_0101,
	subv_M_0101_N_0101,
	add_rm_rn_M_0101_N_0101,
	dmuls_M_0101_N_0101,
	addc_rm_rn_M_0101_N_0101,
	addv_rm_rn_M_0101_N_0101,
	cmpeq_rm_rn_M_0110_N_0101,
	unimplemented,
	cmphs_rm_rn_M_0110_N_0101,
	cmpge_rm_rn_M_0110_N_0101,
	div1_M_0110_N_0101,
	dmulu_M_0110_N_0101,
	cmphi_rm_rn_M_0110_N_0101,
	cmpgt_rm_rn_M_0110_N_0101,
	sub_M_0110_N_0101,
	unimplemented,
	subc_M_0110_N_0101,
	subv_M_0110_N_0101,
	add_rm_rn_M_0110_N_0101,
	dmuls_M_0110_N_0101,
	addc_rm_rn_M_0110_N_0101,
	addv_rm_rn_M_0110_N_0101,
	cmpeq_rm_rn_M_0111_N_0101,
	unimplemented,
	cmphs_rm_rn_M_0111_N_0101,
	cmpge_rm_rn_M_0111_N_0101,
	div1_M_0111_N_0101,
	dmulu_M_0111_N_0101,
	cmphi_rm_rn_M_0111_N_0101,
	cmpgt_rm_rn_M_0111_N_0101,
	sub_M_0111_N_0101,
	unimplemented,
	subc_M_0111_N_0101,
	subv_M_0111_N_0101,
	add_rm_rn_M_0111_N_0101,
	dmuls_M_0111_N_0101,
	addc_rm_rn_M_0111_N_0101,
	addv_rm_rn_M_0111_N_0101,
	cmpeq_rm_rn_M_1000_N_0101,
	unimplemented,
	cmphs_rm_rn_M_1000_N_0101,
	cmpge_rm_rn_M_1000_N_0101,
	div1_M_1000_N_0101,
	dmulu_M_1000_N_0101,
	cmphi_rm_rn_M_1000_N_0101,
	cmpgt_rm_rn_M_1000_N_0101,
	sub_M_1000_N_0101,
	unimplemented,
	subc_M_1000_N_0101,
	subv_M_1000_N_0101,
	add_rm_rn_M_1000_N_0101,
	dmuls_M_1000_N_0101,
	addc_rm_rn_M_1000_N_0101,
	addv_rm_rn_M_1000_N_0101,
	cmpeq_rm_rn_M_1001_N_0101,
	unimplemented,
	cmphs_rm_rn_M_1001_N_0101,
	cmpge_rm_rn_M_1001_N_0101,
	div1_M_1001_N_0101,
	dmulu_M_1001_N_0101,
	cmphi_rm_rn_M_1001_N_0101,
	cmpgt_rm_rn_M_1001_N_0101,
	sub_M_1001_N_0101,
	unimplemented,
	subc_M_1001_N_0101,
	subv_M_1001_N_0101,
	add_rm_rn_M_1001_N_0101,
	dmuls_M_1001_N_0101,
	addc_rm_rn_M_1001_N_0101,
	addv_rm_rn_M_1001_N_0101,
	cmpeq_rm_rn_M_1010_N_0101,
	unimplemented,
	cmphs_rm_rn_M_1010_N_0101,
	cmpge_rm_rn_M_1010_N_0101,
	div1_M_1010_N_0101,
	dmulu_M_1010_N_0101,
	cmphi_rm_rn_M_1010_N_0101,
	cmpgt_rm_rn_M_1010_N_0101,
	sub_M_1010_N_0101,
	unimplemented,
	subc_M_1010_N_0101,
	subv_M_1010_N_0101,
	add_rm_rn_M_1010_N_0101,
	dmuls_M_1010_N_0101,
	addc_rm_rn_M_1010_N_0101,
	addv_rm_rn_M_1010_N_0101,
	cmpeq_rm_rn_M_1011_N_0101,
	unimplemented,
	cmphs_rm_rn_M_1011_N_0101,
	cmpge_rm_rn_M_1011_N_0101,
	div1_M_1011_N_0101,
	dmulu_M_1011_N_0101,
	cmphi_rm_rn_M_1011_N_0101,
	cmpgt_rm_rn_M_1011_N_0101,
	sub_M_1011_N_0101,
	unimplemented,
	subc_M_1011_N_0101,
	subv_M_1011_N_0101,
	add_rm_rn_M_1011_N_0101,
	dmuls_M_1011_N_0101,
	addc_rm_rn_M_1011_N_0101,
	addv_rm_rn_M_1011_N_0101,
	cmpeq_rm_rn_M_1100_N_0101,
	unimplemented,
	cmphs_rm_rn_M_1100_N_0101,
	cmpge_rm_rn_M_1100_N_0101,
	div1_M_1100_N_0101,
	dmulu_M_1100_N_0101,
	cmphi_rm_rn_M_1100_N_0101,
	cmpgt_rm_rn_M_1100_N_0101,
	sub_M_1100_N_0101,
	unimplemented,
	subc_M_1100_N_0101,
	subv_M_1100_N_0101,
	add_rm_rn_M_1100_N_0101,
	dmuls_M_1100_N_0101,
	addc_rm_rn_M_1100_N_0101,
	addv_rm_rn_M_1100_N_0101,
	cmpeq_rm_rn_M_1101_N_0101,
	unimplemented,
	cmphs_rm_rn_M_1101_N_0101,
	cmpge_rm_rn_M_1101_N_0101,
	div1_M_1101_N_0101,
	dmulu_M_1101_N_0101,
	cmphi_rm_rn_M_1101_N_0101,
	cmpgt_rm_rn_M_1101_N_0101,
	sub_M_1101_N_0101,
	unimplemented,
	subc_M_1101_N_0101,
	subv_M_1101_N_0101,
	add_rm_rn_M_1101_N_0101,
	dmuls_M_1101_N_0101,
	addc_rm_rn_M_1101_N_0101,
	addv_rm_rn_M_1101_N_0101,
	cmpeq_rm_rn_M_1110_N_0101,
	unimplemented,
	cmphs_rm_rn_M_1110_N_0101,
	cmpge_rm_rn_M_1110_N_0101,
	div1_M_1110_N_0101,
	dmulu_M_1110_N_0101,
	cmphi_rm_rn_M_1110_N_0101,
	cmpgt_rm_rn_M_1110_N_0101,
	sub_M_1110_N_0101,
	unimplemented,
	subc_M_1110_N_0101,
	subv_M_1110_N_0101,
	add_rm_rn_M_1110_N_0101,
	dmuls_M_1110_N_0101,
	addc_rm_rn_M_1110_N_0101,
	addv_rm_rn_M_1110_N_0101,
	cmpeq_rm_rn_M_1111_N_0101,
	unimplemented,
	cmphs_rm_rn_M_1111_N_0101,
	cmpge_rm_rn_M_1111_N_0101,
	div1_M_1111_N_0101,
	dmulu_M_1111_N_0101,
	cmphi_rm_rn_M_1111_N_0101,
	cmpgt_rm_rn_M_1111_N_0101,
	sub_M_1111_N_0101,
	unimplemented,
	subc_M_1111_N_0101,
	subv_M_1111_N_0101,
	add_rm_rn_M_1111_N_0101,
	dmuls_M_1111_N_0101,
	addc_rm_rn_M_1111_N_0101,
	addv_rm_rn_M_1111_N_0101,
	cmpeq_rm_rn_M_0000_N_0110,
	unimplemented,
	cmphs_rm_rn_M_0000_N_0110,
	cmpge_rm_rn_M_0000_N_0110,
	div1_M_0000_N_0110,
	dmulu_M_0000_N_0110,
	cmphi_rm_rn_M_0000_N_0110,
	cmpgt_rm_rn_M_0000_N_0110,
	sub_M_0000_N_0110,
	unimplemented,
	subc_M_0000_N_0110,
	subv_M_0000_N_0110,
	add_rm_rn_M_0000_N_0110,
	dmuls_M_0000_N_0110,
	addc_rm_rn_M_0000_N_0110,
	addv_rm_rn_M_0000_N_0110,
	cmpeq_rm_rn_M_0001_N_0110,
	unimplemented,
	cmphs_rm_rn_M_0001_N_0110,
	cmpge_rm_rn_M_0001_N_0110,
	div1_M_0001_N_0110,
	dmulu_M_0001_N_0110,
	cmphi_rm_rn_M_0001_N_0110,
	cmpgt_rm_rn_M_0001_N_0110,
	sub_M_0001_N_0110,
	unimplemented,
	subc_M_0001_N_0110,
	subv_M_0001_N_0110,
	add_rm_rn_M_0001_N_0110,
	dmuls_M_0001_N_0110,
	addc_rm_rn_M_0001_N_0110,
	addv_rm_rn_M_0001_N_0110,
	cmpeq_rm_rn_M_0010_N_0110,
	unimplemented,
	cmphs_rm_rn_M_0010_N_0110,
	cmpge_rm_rn_M_0010_N_0110,
	div1_M_0010_N_0110,
	dmulu_M_0010_N_0110,
	cmphi_rm_rn_M_0010_N_0110,
	cmpgt_rm_rn_M_0010_N_0110,
	sub_M_0010_N_0110,
	unimplemented,
	subc_M_0010_N_0110,
	subv_M_0010_N_0110,
	add_rm_rn_M_0010_N_0110,
	dmuls_M_0010_N_0110,
	addc_rm_rn_M_0010_N_0110,
	addv_rm_rn_M_0010_N_0110,
	cmpeq_rm_rn_M_0011_N_0110,
	unimplemented,
	cmphs_rm_rn_M_0011_N_0110,
	cmpge_rm_rn_M_0011_N_0110,
	div1_M_0011_N_0110,
	dmulu_M_0011_N_0110,
	cmphi_rm_rn_M_0011_N_0110,
	cmpgt_rm_rn_M_0011_N_0110,
	sub_M_0011_N_0110,
	unimplemented,
	subc_M_0011_N_0110,
	subv_M_0011_N_0110,
	add_rm_rn_M_0011_N_0110,
	dmuls_M_0011_N_0110,
	addc_rm_rn_M_0011_N_0110,
	addv_rm_rn_M_0011_N_0110,
	cmpeq_rm_rn_M_0100_N_0110,
	unimplemented,
	cmphs_rm_rn_M_0100_N_0110,
	cmpge_rm_rn_M_0100_N_0110,
	div1_M_0100_N_0110,
	dmulu_M_0100_N_0110,
	cmphi_rm_rn_M_0100_N_0110,
	cmpgt_rm_rn_M_0100_N_0110,
	sub_M_0100_N_0110,
	unimplemented,
	subc_M_0100_N_0110,
	subv_M_0100_N_0110,
	add_rm_rn_M_0100_N_0110,
	dmuls_M_0100_N_0110,
	addc_rm_rn_M_0100_N_0110,
	addv_rm_rn_M_0100_N_0110,
	cmpeq_rm_rn_M_0101_N_0110,
	unimplemented,
	cmphs_rm_rn_M_0101_N_0110,
	cmpge_rm_rn_M_0101_N_0110,
	div1_M_0101_N_0110,
	dmulu_M_0101_N_0110,
	cmphi_rm_rn_M_0101_N_0110,
	cmpgt_rm_rn_M_0101_N_0110,
	sub_M_0101_N_0110,
	unimplemented,
	subc_M_0101_N_0110,
	subv_M_0101_N_0110,
	add_rm_rn_M_0101_N_0110,
	dmuls_M_0101_N_0110,
	addc_rm_rn_M_0101_N_0110,
	addv_rm_rn_M_0101_N_0110,
	cmpeq_rm_rn_M_0110_N_0110,
	unimplemented,
	cmphs_rm_rn_M_0110_N_0110,
	cmpge_rm_rn_M_0110_N_0110,
	div1_M_0110_N_0110,
	dmulu_M_0110_N_0110,
	cmphi_rm_rn_M_0110_N_0110,
	cmpgt_rm_rn_M_0110_N_0110,
	sub_M_0110_N_0110,
	unimplemented,
	subc_M_0110_N_0110,
	subv_M_0110_N_0110,
	add_rm_rn_M_0110_N_0110,
	dmuls_M_0110_N_0110,
	addc_rm_rn_M_0110_N_0110,
	addv_rm_rn_M_0110_N_0110,
	cmpeq_rm_rn_M_0111_N_0110,
	unimplemented,
	cmphs_rm_rn_M_0111_N_0110,
	cmpge_rm_rn_M_0111_N_0110,
	div1_M_0111_N_0110,
	dmulu_M_0111_N_0110,
	cmphi_rm_rn_M_0111_N_0110,
	cmpgt_rm_rn_M_0111_N_0110,
	sub_M_0111_N_0110,
	unimplemented,
	subc_M_0111_N_0110,
	subv_M_0111_N_0110,
	add_rm_rn_M_0111_N_0110,
	dmuls_M_0111_N_0110,
	addc_rm_rn_M_0111_N_0110,
	addv_rm_rn_M_0111_N_0110,
	cmpeq_rm_rn_M_1000_N_0110,
	unimplemented,
	cmphs_rm_rn_M_1000_N_0110,
	cmpge_rm_rn_M_1000_N_0110,
	div1_M_1000_N_0110,
	dmulu_M_1000_N_0110,
	cmphi_rm_rn_M_1000_N_0110,
	cmpgt_rm_rn_M_1000_N_0110,
	sub_M_1000_N_0110,
	unimplemented,
	subc_M_1000_N_0110,
	subv_M_1000_N_0110,
	add_rm_rn_M_1000_N_0110,
	dmuls_M_1000_N_0110,
	addc_rm_rn_M_1000_N_0110,
	addv_rm_rn_M_1000_N_0110,
	cmpeq_rm_rn_M_1001_N_0110,
	unimplemented,
	cmphs_rm_rn_M_1001_N_0110,
	cmpge_rm_rn_M_1001_N_0110,
	div1_M_1001_N_0110,
	dmulu_M_1001_N_0110,
	cmphi_rm_rn_M_1001_N_0110,
	cmpgt_rm_rn_M_1001_N_0110,
	sub_M_1001_N_0110,
	unimplemented,
	subc_M_1001_N_0110,
	subv_M_1001_N_0110,
	add_rm_rn_M_1001_N_0110,
	dmuls_M_1001_N_0110,
	addc_rm_rn_M_1001_N_0110,
	addv_rm_rn_M_1001_N_0110,
	cmpeq_rm_rn_M_1010_N_0110,
	unimplemented,
	cmphs_rm_rn_M_1010_N_0110,
	cmpge_rm_rn_M_1010_N_0110,
	div1_M_1010_N_0110,
	dmulu_M_1010_N_0110,
	cmphi_rm_rn_M_1010_N_0110,
	cmpgt_rm_rn_M_1010_N_0110,
	sub_M_1010_N_0110,
	unimplemented,
	subc_M_1010_N_0110,
	subv_M_1010_N_0110,
	add_rm_rn_M_1010_N_0110,
	dmuls_M_1010_N_0110,
	addc_rm_rn_M_1010_N_0110,
	addv_rm_rn_M_1010_N_0110,
	cmpeq_rm_rn_M_1011_N_0110,
	unimplemented,
	cmphs_rm_rn_M_1011_N_0110,
	cmpge_rm_rn_M_1011_N_0110,
	div1_M_1011_N_0110,
	dmulu_M_1011_N_0110,
	cmphi_rm_rn_M_1011_N_0110,
	cmpgt_rm_rn_M_1011_N_0110,
	sub_M_1011_N_0110,
	unimplemented,
	subc_M_1011_N_0110,
	subv_M_1011_N_0110,
	add_rm_rn_M_1011_N_0110,
	dmuls_M_1011_N_0110,
	addc_rm_rn_M_1011_N_0110,
	addv_rm_rn_M_1011_N_0110,
	cmpeq_rm_rn_M_1100_N_0110,
	unimplemented,
	cmphs_rm_rn_M_1100_N_0110,
	cmpge_rm_rn_M_1100_N_0110,
	div1_M_1100_N_0110,
	dmulu_M_1100_N_0110,
	cmphi_rm_rn_M_1100_N_0110,
	cmpgt_rm_rn_M_1100_N_0110,
	sub_M_1100_N_0110,
	unimplemented,
	subc_M_1100_N_0110,
	subv_M_1100_N_0110,
	add_rm_rn_M_1100_N_0110,
	dmuls_M_1100_N_0110,
	addc_rm_rn_M_1100_N_0110,
	addv_rm_rn_M_1100_N_0110,
	cmpeq_rm_rn_M_1101_N_0110,
	unimplemented,
	cmphs_rm_rn_M_1101_N_0110,
	cmpge_rm_rn_M_1101_N_0110,
	div1_M_1101_N_0110,
	dmulu_M_1101_N_0110,
	cmphi_rm_rn_M_1101_N_0110,
	cmpgt_rm_rn_M_1101_N_0110,
	sub_M_1101_N_0110,
	unimplemented,
	subc_M_1101_N_0110,
	subv_M_1101_N_0110,
	add_rm_rn_M_1101_N_0110,
	dmuls_M_1101_N_0110,
	addc_rm_rn_M_1101_N_0110,
	addv_rm_rn_M_1101_N_0110,
	cmpeq_rm_rn_M_1110_N_0110,
	unimplemented,
	cmphs_rm_rn_M_1110_N_0110,
	cmpge_rm_rn_M_1110_N_0110,
	div1_M_1110_N_0110,
	dmulu_M_1110_N_0110,
	cmphi_rm_rn_M_1110_N_0110,
	cmpgt_rm_rn_M_1110_N_0110,
	sub_M_1110_N_0110,
	unimplemented,
	subc_M_1110_N_0110,
	subv_M_1110_N_0110,
	add_rm_rn_M_1110_N_0110,
	dmuls_M_1110_N_0110,
	addc_rm_rn_M_1110_N_0110,
	addv_rm_rn_M_1110_N_0110,
	cmpeq_rm_rn_M_1111_N_0110,
	unimplemented,
	cmphs_rm_rn_M_1111_N_0110,
	cmpge_rm_rn_M_1111_N_0110,
	div1_M_1111_N_0110,
	dmulu_M_1111_N_0110,
	cmphi_rm_rn_M_1111_N_0110,
	cmpgt_rm_rn_M_1111_N_0110,
	sub_M_1111_N_0110,
	unimplemented,
	subc_M_1111_N_0110,
	subv_M_1111_N_0110,
	add_rm_rn_M_1111_N_0110,
	dmuls_M_1111_N_0110,
	addc_rm_rn_M_1111_N_0110,
	addv_rm_rn_M_1111_N_0110,
	cmpeq_rm_rn_M_0000_N_0111,
	unimplemented,
	cmphs_rm_rn_M_0000_N_0111,
	cmpge_rm_rn_M_0000_N_0111,
	div1_M_0000_N_0111,
	dmulu_M_0000_N_0111,
	cmphi_rm_rn_M_0000_N_0111,
	cmpgt_rm_rn_M_0000_N_0111,
	sub_M_0000_N_0111,
	unimplemented,
	subc_M_0000_N_0111,
	subv_M_0000_N_0111,
	add_rm_rn_M_0000_N_0111,
	dmuls_M_0000_N_0111,
	addc_rm_rn_M_0000_N_0111,
	addv_rm_rn_M_0000_N_0111,
	cmpeq_rm_rn_M_0001_N_0111,
	unimplemented,
	cmphs_rm_rn_M_0001_N_0111,
	cmpge_rm_rn_M_0001_N_0111,
	div1_M_0001_N_0111,
	dmulu_M_0001_N_0111,
	cmphi_rm_rn_M_0001_N_0111,
	cmpgt_rm_rn_M_0001_N_0111,
	sub_M_0001_N_0111,
	unimplemented,
	subc_M_0001_N_0111,
	subv_M_0001_N_0111,
	add_rm_rn_M_0001_N_0111,
	dmuls_M_0001_N_0111,
	addc_rm_rn_M_0001_N_0111,
	addv_rm_rn_M_0001_N_0111,
	cmpeq_rm_rn_M_0010_N_0111,
	unimplemented,
	cmphs_rm_rn_M_0010_N_0111,
	cmpge_rm_rn_M_0010_N_0111,
	div1_M_0010_N_0111,
	dmulu_M_0010_N_0111,
	cmphi_rm_rn_M_0010_N_0111,
	cmpgt_rm_rn_M_0010_N_0111,
	sub_M_0010_N_0111,
	unimplemented,
	subc_M_0010_N_0111,
	subv_M_0010_N_0111,
	add_rm_rn_M_0010_N_0111,
	dmuls_M_0010_N_0111,
	addc_rm_rn_M_0010_N_0111,
	addv_rm_rn_M_0010_N_0111,
	cmpeq_rm_rn_M_0011_N_0111,
	unimplemented,
	cmphs_rm_rn_M_0011_N_0111,
	cmpge_rm_rn_M_0011_N_0111,
	div1_M_0011_N_0111,
	dmulu_M_0011_N_0111,
	cmphi_rm_rn_M_0011_N_0111,
	cmpgt_rm_rn_M_0011_N_0111,
	sub_M_0011_N_0111,
	unimplemented,
	subc_M_0011_N_0111,
	subv_M_0011_N_0111,
	add_rm_rn_M_0011_N_0111,
	dmuls_M_0011_N_0111,
	addc_rm_rn_M_0011_N_0111,
	addv_rm_rn_M_0011_N_0111,
	cmpeq_rm_rn_M_0100_N_0111,
	unimplemented,
	cmphs_rm_rn_M_0100_N_0111,
	cmpge_rm_rn_M_0100_N_0111,
	div1_M_0100_N_0111,
	dmulu_M_0100_N_0111,
	cmphi_rm_rn_M_0100_N_0111,
	cmpgt_rm_rn_M_0100_N_0111,
	sub_M_0100_N_0111,
	unimplemented,
	subc_M_0100_N_0111,
	subv_M_0100_N_0111,
	add_rm_rn_M_0100_N_0111,
	dmuls_M_0100_N_0111,
	addc_rm_rn_M_0100_N_0111,
	addv_rm_rn_M_0100_N_0111,
	cmpeq_rm_rn_M_0101_N_0111,
	unimplemented,
	cmphs_rm_rn_M_0101_N_0111,
	cmpge_rm_rn_M_0101_N_0111,
	div1_M_0101_N_0111,
	dmulu_M_0101_N_0111,
	cmphi_rm_rn_M_0101_N_0111,
	cmpgt_rm_rn_M_0101_N_0111,
	sub_M_0101_N_0111,
	unimplemented,
	subc_M_0101_N_0111,
	subv_M_0101_N_0111,
	add_rm_rn_M_0101_N_0111,
	dmuls_M_0101_N_0111,
	addc_rm_rn_M_0101_N_0111,
	addv_rm_rn_M_0101_N_0111,
	cmpeq_rm_rn_M_0110_N_0111,
	unimplemented,
	cmphs_rm_rn_M_0110_N_0111,
	cmpge_rm_rn_M_0110_N_0111,
	div1_M_0110_N_0111,
	dmulu_M_0110_N_0111,
	cmphi_rm_rn_M_0110_N_0111,
	cmpgt_rm_rn_M_0110_N_0111,
	sub_M_0110_N_0111,
	unimplemented,
	subc_M_0110_N_0111,
	subv_M_0110_N_0111,
	add_rm_rn_M_0110_N_0111,
	dmuls_M_0110_N_0111,
	addc_rm_rn_M_0110_N_0111,
	addv_rm_rn_M_0110_N_0111,
	cmpeq_rm_rn_M_0111_N_0111,
	unimplemented,
	cmphs_rm_rn_M_0111_N_0111,
	cmpge_rm_rn_M_0111_N_0111,
	div1_M_0111_N_0111,
	dmulu_M_0111_N_0111,
	cmphi_rm_rn_M_0111_N_0111,
	cmpgt_rm_rn_M_0111_N_0111,
	sub_M_0111_N_0111,
	unimplemented,
	subc_M_0111_N_0111,
	subv_M_0111_N_0111,
	add_rm_rn_M_0111_N_0111,
	dmuls_M_0111_N_0111,
	addc_rm_rn_M_0111_N_0111,
	addv_rm_rn_M_0111_N_0111,
	cmpeq_rm_rn_M_1000_N_0111,
	unimplemented,
	cmphs_rm_rn_M_1000_N_0111,
	cmpge_rm_rn_M_1000_N_0111,
	div1_M_1000_N_0111,
	dmulu_M_1000_N_0111,
	cmphi_rm_rn_M_1000_N_0111,
	cmpgt_rm_rn_M_1000_N_0111,
	sub_M_1000_N_0111,
	unimplemented,
	subc_M_1000_N_0111,
	subv_M_1000_N_0111,
	add_rm_rn_M_1000_N_0111,
	dmuls_M_1000_N_0111,
	addc_rm_rn_M_1000_N_0111,
	addv_rm_rn_M_1000_N_0111,
	cmpeq_rm_rn_M_1001_N_0111,
	unimplemented,
	cmphs_rm_rn_M_1001_N_0111,
	cmpge_rm_rn_M_1001_N_0111,
	div1_M_1001_N_0111,
	dmulu_M_1001_N_0111,
	cmphi_rm_rn_M_1001_N_0111,
	cmpgt_rm_rn_M_1001_N_0111,
	sub_M_1001_N_0111,
	unimplemented,
	subc_M_1001_N_0111,
	subv_M_1001_N_0111,
	add_rm_rn_M_1001_N_0111,
	dmuls_M_1001_N_0111,
	addc_rm_rn_M_1001_N_0111,
	addv_rm_rn_M_1001_N_0111,
	cmpeq_rm_rn_M_1010_N_0111,
	unimplemented,
	cmphs_rm_rn_M_1010_N_0111,
	cmpge_rm_rn_M_1010_N_0111,
	div1_M_1010_N_0111,
	dmulu_M_1010_N_0111,
	cmphi_rm_rn_M_1010_N_0111,
	cmpgt_rm_rn_M_1010_N_0111,
	sub_M_1010_N_0111,
	unimplemented,
	subc_M_1010_N_0111,
	subv_M_1010_N_0111,
	add_rm_rn_M_1010_N_0111,
	dmuls_M_1010_N_0111,
	addc_rm_rn_M_1010_N_0111,
	addv_rm_rn_M_1010_N_0111,
	cmpeq_rm_rn_M_1011_N_0111,
	unimplemented,
	cmphs_rm_rn_M_1011_N_0111,
	cmpge_rm_rn_M_1011_N_0111,
	div1_M_1011_N_0111,
	dmulu_M_1011_N_0111,
	cmphi_rm_rn_M_1011_N_0111,
	cmpgt_rm_rn_M_1011_N_0111,
	sub_M_1011_N_0111,
	unimplemented,
	subc_M_1011_N_0111,
	subv_M_1011_N_0111,
	add_rm_rn_M_1011_N_0111,
	dmuls_M_1011_N_0111,
	addc_rm_rn_M_1011_N_0111,
	addv_rm_rn_M_1011_N_0111,
	cmpeq_rm_rn_M_1100_N_0111,
	unimplemented,
	cmphs_rm_rn_M_1100_N_0111,
	cmpge_rm_rn_M_1100_N_0111,
	div1_M_1100_N_0111,
	dmulu_M_1100_N_0111,
	cmphi_rm_rn_M_1100_N_0111,
	cmpgt_rm_rn_M_1100_N_0111,
	sub_M_1100_N_0111,
	unimplemented,
	subc_M_1100_N_0111,
	subv_M_1100_N_0111,
	add_rm_rn_M_1100_N_0111,
	dmuls_M_1100_N_0111,
	addc_rm_rn_M_1100_N_0111,
	addv_rm_rn_M_1100_N_0111,
	cmpeq_rm_rn_M_1101_N_0111,
	unimplemented,
	cmphs_rm_rn_M_1101_N_0111,
	cmpge_rm_rn_M_1101_N_0111,
	div1_M_1101_N_0111,
	dmulu_M_1101_N_0111,
	cmphi_rm_rn_M_1101_N_0111,
	cmpgt_rm_rn_M_1101_N_0111,
	sub_M_1101_N_0111,
	unimplemented,
	subc_M_1101_N_0111,
	subv_M_1101_N_0111,
	add_rm_rn_M_1101_N_0111,
	dmuls_M_1101_N_0111,
	addc_rm_rn_M_1101_N_0111,
	addv_rm_rn_M_1101_N_0111,
	cmpeq_rm_rn_M_1110_N_0111,
	unimplemented,
	cmphs_rm_rn_M_1110_N_0111,
	cmpge_rm_rn_M_1110_N_0111,
	div1_M_1110_N_0111,
	dmulu_M_1110_N_0111,
	cmphi_rm_rn_M_1110_N_0111,
	cmpgt_rm_rn_M_1110_N_0111,
	sub_M_1110_N_0111,
	unimplemented,
	subc_M_1110_N_0111,
	subv_M_1110_N_0111,
	add_rm_rn_M_1110_N_0111,
	dmuls_M_1110_N_0111,
	addc_rm_rn_M_1110_N_0111,
	addv_rm_rn_M_1110_N_0111,
	cmpeq_rm_rn_M_1111_N_0111,
	unimplemented,
	cmphs_rm_rn_M_1111_N_0111,
	cmpge_rm_rn_M_1111_N_0111,
	div1_M_1111_N_0111,
	dmulu_M_1111_N_0111,
	cmphi_rm_rn_M_1111_N_0111,
	cmpgt_rm_rn_M_1111_N_0111,
	sub_M_1111_N_0111,
	unimplemented,
	subc_M_1111_N_0111,
	subv_M_1111_N_0111,
	add_rm_rn_M_1111_N_0111,
	dmuls_M_1111_N_0111,
	addc_rm_rn_M_1111_N_0111,
	addv_rm_rn_M_1111_N_0111,
	cmpeq_rm_rn_M_0000_N_1000,
	unimplemented,
	cmphs_rm_rn_M_0000_N_1000,
	cmpge_rm_rn_M_0000_N_1000,
	div1_M_0000_N_1000,
	dmulu_M_0000_N_1000,
	cmphi_rm_rn_M_0000_N_1000,
	cmpgt_rm_rn_M_0000_N_1000,
	sub_M_0000_N_1000,
	unimplemented,
	subc_M_0000_N_1000,
	subv_M_0000_N_1000,
	add_rm_rn_M_0000_N_1000,
	dmuls_M_0000_N_1000,
	addc_rm_rn_M_0000_N_1000,
	addv_rm_rn_M_0000_N_1000,
	cmpeq_rm_rn_M_0001_N_1000,
	unimplemented,
	cmphs_rm_rn_M_0001_N_1000,
	cmpge_rm_rn_M_0001_N_1000,
	div1_M_0001_N_1000,
	dmulu_M_0001_N_1000,
	cmphi_rm_rn_M_0001_N_1000,
	cmpgt_rm_rn_M_0001_N_1000,
	sub_M_0001_N_1000,
	unimplemented,
	subc_M_0001_N_1000,
	subv_M_0001_N_1000,
	add_rm_rn_M_0001_N_1000,
	dmuls_M_0001_N_1000,
	addc_rm_rn_M_0001_N_1000,
	addv_rm_rn_M_0001_N_1000,
	cmpeq_rm_rn_M_0010_N_1000,
	unimplemented,
	cmphs_rm_rn_M_0010_N_1000,
	cmpge_rm_rn_M_0010_N_1000,
	div1_M_0010_N_1000,
	dmulu_M_0010_N_1000,
	cmphi_rm_rn_M_0010_N_1000,
	cmpgt_rm_rn_M_0010_N_1000,
	sub_M_0010_N_1000,
	unimplemented,
	subc_M_0010_N_1000,
	subv_M_0010_N_1000,
	add_rm_rn_M_0010_N_1000,
	dmuls_M_0010_N_1000,
	addc_rm_rn_M_0010_N_1000,
	addv_rm_rn_M_0010_N_1000,
	cmpeq_rm_rn_M_0011_N_1000,
	unimplemented,
	cmphs_rm_rn_M_0011_N_1000,
	cmpge_rm_rn_M_0011_N_1000,
	div1_M_0011_N_1000,
	dmulu_M_0011_N_1000,
	cmphi_rm_rn_M_0011_N_1000,
	cmpgt_rm_rn_M_0011_N_1000,
	sub_M_0011_N_1000,
	unimplemented,
	subc_M_0011_N_1000,
	subv_M_0011_N_1000,
	add_rm_rn_M_0011_N_1000,
	dmuls_M_0011_N_1000,
	addc_rm_rn_M_0011_N_1000,
	addv_rm_rn_M_0011_N_1000,
	cmpeq_rm_rn_M_0100_N_1000,
	unimplemented,
	cmphs_rm_rn_M_0100_N_1000,
	cmpge_rm_rn_M_0100_N_1000,
	div1_M_0100_N_1000,
	dmulu_M_0100_N_1000,
	cmphi_rm_rn_M_0100_N_1000,
	cmpgt_rm_rn_M_0100_N_1000,
	sub_M_0100_N_1000,
	unimplemented,
	subc_M_0100_N_1000,
	subv_M_0100_N_1000,
	add_rm_rn_M_0100_N_1000,
	dmuls_M_0100_N_1000,
	addc_rm_rn_M_0100_N_1000,
	addv_rm_rn_M_0100_N_1000,
	cmpeq_rm_rn_M_0101_N_1000,
	unimplemented,
	cmphs_rm_rn_M_0101_N_1000,
	cmpge_rm_rn_M_0101_N_1000,
	div1_M_0101_N_1000,
	dmulu_M_0101_N_1000,
	cmphi_rm_rn_M_0101_N_1000,
	cmpgt_rm_rn_M_0101_N_1000,
	sub_M_0101_N_1000,
	unimplemented,
	subc_M_0101_N_1000,
	subv_M_0101_N_1000,
	add_rm_rn_M_0101_N_1000,
	dmuls_M_0101_N_1000,
	addc_rm_rn_M_0101_N_1000,
	addv_rm_rn_M_0101_N_1000,
	cmpeq_rm_rn_M_0110_N_1000,
	unimplemented,
	cmphs_rm_rn_M_0110_N_1000,
	cmpge_rm_rn_M_0110_N_1000,
	div1_M_0110_N_1000,
	dmulu_M_0110_N_1000,
	cmphi_rm_rn_M_0110_N_1000,
	cmpgt_rm_rn_M_0110_N_1000,
	sub_M_0110_N_1000,
	unimplemented,
	subc_M_0110_N_1000,
	subv_M_0110_N_1000,
	add_rm_rn_M_0110_N_1000,
	dmuls_M_0110_N_1000,
	addc_rm_rn_M_0110_N_1000,
	addv_rm_rn_M_0110_N_1000,
	cmpeq_rm_rn_M_0111_N_1000,
	unimplemented,
	cmphs_rm_rn_M_0111_N_1000,
	cmpge_rm_rn_M_0111_N_1000,
	div1_M_0111_N_1000,
	dmulu_M_0111_N_1000,
	cmphi_rm_rn_M_0111_N_1000,
	cmpgt_rm_rn_M_0111_N_1000,
	sub_M_0111_N_1000,
	unimplemented,
	subc_M_0111_N_1000,
	subv_M_0111_N_1000,
	add_rm_rn_M_0111_N_1000,
	dmuls_M_0111_N_1000,
	addc_rm_rn_M_0111_N_1000,
	addv_rm_rn_M_0111_N_1000,
	cmpeq_rm_rn_M_1000_N_1000,
	unimplemented,
	cmphs_rm_rn_M_1000_N_1000,
	cmpge_rm_rn_M_1000_N_1000,
	div1_M_1000_N_1000,
	dmulu_M_1000_N_1000,
	cmphi_rm_rn_M_1000_N_1000,
	cmpgt_rm_rn_M_1000_N_1000,
	sub_M_1000_N_1000,
	unimplemented,
	subc_M_1000_N_1000,
	subv_M_1000_N_1000,
	add_rm_rn_M_1000_N_1000,
	dmuls_M_1000_N_1000,
	addc_rm_rn_M_1000_N_1000,
	addv_rm_rn_M_1000_N_1000,
	cmpeq_rm_rn_M_1001_N_1000,
	unimplemented,
	cmphs_rm_rn_M_1001_N_1000,
	cmpge_rm_rn_M_1001_N_1000,
	div1_M_1001_N_1000,
	dmulu_M_1001_N_1000,
	cmphi_rm_rn_M_1001_N_1000,
	cmpgt_rm_rn_M_1001_N_1000,
	sub_M_1001_N_1000,
	unimplemented,
	subc_M_1001_N_1000,
	subv_M_1001_N_1000,
	add_rm_rn_M_1001_N_1000,
	dmuls_M_1001_N_1000,
	addc_rm_rn_M_1001_N_1000,
	addv_rm_rn_M_1001_N_1000,
	cmpeq_rm_rn_M_1010_N_1000,
	unimplemented,
	cmphs_rm_rn_M_1010_N_1000,
	cmpge_rm_rn_M_1010_N_1000,
	div1_M_1010_N_1000,
	dmulu_M_1010_N_1000,
	cmphi_rm_rn_M_1010_N_1000,
	cmpgt_rm_rn_M_1010_N_1000,
	sub_M_1010_N_1000,
	unimplemented,
	subc_M_1010_N_1000,
	subv_M_1010_N_1000,
	add_rm_rn_M_1010_N_1000,
	dmuls_M_1010_N_1000,
	addc_rm_rn_M_1010_N_1000,
	addv_rm_rn_M_1010_N_1000,
	cmpeq_rm_rn_M_1011_N_1000,
	unimplemented,
	cmphs_rm_rn_M_1011_N_1000,
	cmpge_rm_rn_M_1011_N_1000,
	div1_M_1011_N_1000,
	dmulu_M_1011_N_1000,
	cmphi_rm_rn_M_1011_N_1000,
	cmpgt_rm_rn_M_1011_N_1000,
	sub_M_1011_N_1000,
	unimplemented,
	subc_M_1011_N_1000,
	subv_M_1011_N_1000,
	add_rm_rn_M_1011_N_1000,
	dmuls_M_1011_N_1000,
	addc_rm_rn_M_1011_N_1000,
	addv_rm_rn_M_1011_N_1000,
	cmpeq_rm_rn_M_1100_N_1000,
	unimplemented,
	cmphs_rm_rn_M_1100_N_1000,
	cmpge_rm_rn_M_1100_N_1000,
	div1_M_1100_N_1000,
	dmulu_M_1100_N_1000,
	cmphi_rm_rn_M_1100_N_1000,
	cmpgt_rm_rn_M_1100_N_1000,
	sub_M_1100_N_1000,
	unimplemented,
	subc_M_1100_N_1000,
	subv_M_1100_N_1000,
	add_rm_rn_M_1100_N_1000,
	dmuls_M_1100_N_1000,
	addc_rm_rn_M_1100_N_1000,
	addv_rm_rn_M_1100_N_1000,
	cmpeq_rm_rn_M_1101_N_1000,
	unimplemented,
	cmphs_rm_rn_M_1101_N_1000,
	cmpge_rm_rn_M_1101_N_1000,
	div1_M_1101_N_1000,
	dmulu_M_1101_N_1000,
	cmphi_rm_rn_M_1101_N_1000,
	cmpgt_rm_rn_M_1101_N_1000,
	sub_M_1101_N_1000,
	unimplemented,
	subc_M_1101_N_1000,
	subv_M_1101_N_1000,
	add_rm_rn_M_1101_N_1000,
	dmuls_M_1101_N_1000,
	addc_rm_rn_M_1101_N_1000,
	addv_rm_rn_M_1101_N_1000,
	cmpeq_rm_rn_M_1110_N_1000,
	unimplemented,
	cmphs_rm_rn_M_1110_N_1000,
	cmpge_rm_rn_M_1110_N_1000,
	div1_M_1110_N_1000,
	dmulu_M_1110_N_1000,
	cmphi_rm_rn_M_1110_N_1000,
	cmpgt_rm_rn_M_1110_N_1000,
	sub_M_1110_N_1000,
	unimplemented,
	subc_M_1110_N_1000,
	subv_M_1110_N_1000,
	add_rm_rn_M_1110_N_1000,
	dmuls_M_1110_N_1000,
	addc_rm_rn_M_1110_N_1000,
	addv_rm_rn_M_1110_N_1000,
	cmpeq_rm_rn_M_1111_N_1000,
	unimplemented,
	cmphs_rm_rn_M_1111_N_1000,
	cmpge_rm_rn_M_1111_N_1000,
	div1_M_1111_N_1000,
	dmulu_M_1111_N_1000,
	cmphi_rm_rn_M_1111_N_1000,
	cmpgt_rm_rn_M_1111_N_1000,
	sub_M_1111_N_1000,
	unimplemented,
	subc_M_1111_N_1000,
	subv_M_1111_N_1000,
	add_rm_rn_M_1111_N_1000,
	dmuls_M_1111_N_1000,
	addc_rm_rn_M_1111_N_1000,
	addv_rm_rn_M_1111_N_1000,
	cmpeq_rm_rn_M_0000_N_1001,
	unimplemented,
	cmphs_rm_rn_M_0000_N_1001,
	cmpge_rm_rn_M_0000_N_1001,
	div1_M_0000_N_1001,
	dmulu_M_0000_N_1001,
	cmphi_rm_rn_M_0000_N_1001,
	cmpgt_rm_rn_M_0000_N_1001,
	sub_M_0000_N_1001,
	unimplemented,
	subc_M_0000_N_1001,
	subv_M_0000_N_1001,
	add_rm_rn_M_0000_N_1001,
	dmuls_M_0000_N_1001,
	addc_rm_rn_M_0000_N_1001,
	addv_rm_rn_M_0000_N_1001,
	cmpeq_rm_rn_M_0001_N_1001,
	unimplemented,
	cmphs_rm_rn_M_0001_N_1001,
	cmpge_rm_rn_M_0001_N_1001,
	div1_M_0001_N_1001,
	dmulu_M_0001_N_1001,
	cmphi_rm_rn_M_0001_N_1001,
	cmpgt_rm_rn_M_0001_N_1001,
	sub_M_0001_N_1001,
	unimplemented,
	subc_M_0001_N_1001,
	subv_M_0001_N_1001,
	add_rm_rn_M_0001_N_1001,
	dmuls_M_0001_N_1001,
	addc_rm_rn_M_0001_N_1001,
	addv_rm_rn_M_0001_N_1001,
	cmpeq_rm_rn_M_0010_N_1001,
	unimplemented,
	cmphs_rm_rn_M_0010_N_1001,
	cmpge_rm_rn_M_0010_N_1001,
	div1_M_0010_N_1001,
	dmulu_M_0010_N_1001,
	cmphi_rm_rn_M_0010_N_1001,
	cmpgt_rm_rn_M_0010_N_1001,
	sub_M_0010_N_1001,
	unimplemented,
	subc_M_0010_N_1001,
	subv_M_0010_N_1001,
	add_rm_rn_M_0010_N_1001,
	dmuls_M_0010_N_1001,
	addc_rm_rn_M_0010_N_1001,
	addv_rm_rn_M_0010_N_1001,
	cmpeq_rm_rn_M_0011_N_1001,
	unimplemented,
	cmphs_rm_rn_M_0011_N_1001,
	cmpge_rm_rn_M_0011_N_1001,
	div1_M_0011_N_1001,
	dmulu_M_0011_N_1001,
	cmphi_rm_rn_M_0011_N_1001,
	cmpgt_rm_rn_M_0011_N_1001,
	sub_M_0011_N_1001,
	unimplemented,
	subc_M_0011_N_1001,
	subv_M_0011_N_1001,
	add_rm_rn_M_0011_N_1001,
	dmuls_M_0011_N_1001,
	addc_rm_rn_M_0011_N_1001,
	addv_rm_rn_M_0011_N_1001,
	cmpeq_rm_rn_M_0100_N_1001,
	unimplemented,
	cmphs_rm_rn_M_0100_N_1001,
	cmpge_rm_rn_M_0100_N_1001,
	div1_M_0100_N_1001,
	dmulu_M_0100_N_1001,
	cmphi_rm_rn_M_0100_N_1001,
	cmpgt_rm_rn_M_0100_N_1001,
	sub_M_0100_N_1001,
	unimplemented,
	subc_M_0100_N_1001,
	subv_M_0100_N_1001,
	add_rm_rn_M_0100_N_1001,
	dmuls_M_0100_N_1001,
	addc_rm_rn_M_0100_N_1001,
	addv_rm_rn_M_0100_N_1001,
	cmpeq_rm_rn_M_0101_N_1001,
	unimplemented,
	cmphs_rm_rn_M_0101_N_1001,
	cmpge_rm_rn_M_0101_N_1001,
	div1_M_0101_N_1001,
	dmulu_M_0101_N_1001,
	cmphi_rm_rn_M_0101_N_1001,
	cmpgt_rm_rn_M_0101_N_1001,
	sub_M_0101_N_1001,
	unimplemented,
	subc_M_0101_N_1001,
	subv_M_0101_N_1001,
	add_rm_rn_M_0101_N_1001,
	dmuls_M_0101_N_1001,
	addc_rm_rn_M_0101_N_1001,
	addv_rm_rn_M_0101_N_1001,
	cmpeq_rm_rn_M_0110_N_1001,
	unimplemented,
	cmphs_rm_rn_M_0110_N_1001,
	cmpge_rm_rn_M_0110_N_1001,
	div1_M_0110_N_1001,
	dmulu_M_0110_N_1001,
	cmphi_rm_rn_M_0110_N_1001,
	cmpgt_rm_rn_M_0110_N_1001,
	sub_M_0110_N_1001,
	unimplemented,
	subc_M_0110_N_1001,
	subv_M_0110_N_1001,
	add_rm_rn_M_0110_N_1001,
	dmuls_M_0110_N_1001,
	addc_rm_rn_M_0110_N_1001,
	addv_rm_rn_M_0110_N_1001,
	cmpeq_rm_rn_M_0111_N_1001,
	unimplemented,
	cmphs_rm_rn_M_0111_N_1001,
	cmpge_rm_rn_M_0111_N_1001,
	div1_M_0111_N_1001,
	dmulu_M_0111_N_1001,
	cmphi_rm_rn_M_0111_N_1001,
	cmpgt_rm_rn_M_0111_N_1001,
	sub_M_0111_N_1001,
	unimplemented,
	subc_M_0111_N_1001,
	subv_M_0111_N_1001,
	add_rm_rn_M_0111_N_1001,
	dmuls_M_0111_N_1001,
	addc_rm_rn_M_0111_N_1001,
	addv_rm_rn_M_0111_N_1001,
	cmpeq_rm_rn_M_1000_N_1001,
	unimplemented,
	cmphs_rm_rn_M_1000_N_1001,
	cmpge_rm_rn_M_1000_N_1001,
	div1_M_1000_N_1001,
	dmulu_M_1000_N_1001,
	cmphi_rm_rn_M_1000_N_1001,
	cmpgt_rm_rn_M_1000_N_1001,
	sub_M_1000_N_1001,
	unimplemented,
	subc_M_1000_N_1001,
	subv_M_1000_N_1001,
	add_rm_rn_M_1000_N_1001,
	dmuls_M_1000_N_1001,
	addc_rm_rn_M_1000_N_1001,
	addv_rm_rn_M_1000_N_1001,
	cmpeq_rm_rn_M_1001_N_1001,
	unimplemented,
	cmphs_rm_rn_M_1001_N_1001,
	cmpge_rm_rn_M_1001_N_1001,
	div1_M_1001_N_1001,
	dmulu_M_1001_N_1001,
	cmphi_rm_rn_M_1001_N_1001,
	cmpgt_rm_rn_M_1001_N_1001,
	sub_M_1001_N_1001,
	unimplemented,
	subc_M_1001_N_1001,
	subv_M_1001_N_1001,
	add_rm_rn_M_1001_N_1001,
	dmuls_M_1001_N_1001,
	addc_rm_rn_M_1001_N_1001,
	addv_rm_rn_M_1001_N_1001,
	cmpeq_rm_rn_M_1010_N_1001,
	unimplemented,
	cmphs_rm_rn_M_1010_N_1001,
	cmpge_rm_rn_M_1010_N_1001,
	div1_M_1010_N_1001,
	dmulu_M_1010_N_1001,
	cmphi_rm_rn_M_1010_N_1001,
	cmpgt_rm_rn_M_1010_N_1001,
	sub_M_1010_N_1001,
	unimplemented,
	subc_M_1010_N_1001,
	subv_M_1010_N_1001,
	add_rm_rn_M_1010_N_1001,
	dmuls_M_1010_N_1001,
	addc_rm_rn_M_1010_N_1001,
	addv_rm_rn_M_1010_N_1001,
	cmpeq_rm_rn_M_1011_N_1001,
	unimplemented,
	cmphs_rm_rn_M_1011_N_1001,
	cmpge_rm_rn_M_1011_N_1001,
	div1_M_1011_N_1001,
	dmulu_M_1011_N_1001,
	cmphi_rm_rn_M_1011_N_1001,
	cmpgt_rm_rn_M_1011_N_1001,
	sub_M_1011_N_1001,
	unimplemented,
	subc_M_1011_N_1001,
	subv_M_1011_N_1001,
	add_rm_rn_M_1011_N_1001,
	dmuls_M_1011_N_1001,
	addc_rm_rn_M_1011_N_1001,
	addv_rm_rn_M_1011_N_1001,
	cmpeq_rm_rn_M_1100_N_1001,
	unimplemented,
	cmphs_rm_rn_M_1100_N_1001,
	cmpge_rm_rn_M_1100_N_1001,
	div1_M_1100_N_1001,
	dmulu_M_1100_N_1001,
	cmphi_rm_rn_M_1100_N_1001,
	cmpgt_rm_rn_M_1100_N_1001,
	sub_M_1100_N_1001,
	unimplemented,
	subc_M_1100_N_1001,
	subv_M_1100_N_1001,
	add_rm_rn_M_1100_N_1001,
	dmuls_M_1100_N_1001,
	addc_rm_rn_M_1100_N_1001,
	addv_rm_rn_M_1100_N_1001,
	cmpeq_rm_rn_M_1101_N_1001,
	unimplemented,
	cmphs_rm_rn_M_1101_N_1001,
	cmpge_rm_rn_M_1101_N_1001,
	div1_M_1101_N_1001,
	dmulu_M_1101_N_1001,
	cmphi_rm_rn_M_1101_N_1001,
	cmpgt_rm_rn_M_1101_N_1001,
	sub_M_1101_N_1001,
	unimplemented,
	subc_M_1101_N_1001,
	subv_M_1101_N_1001,
	add_rm_rn_M_1101_N_1001,
	dmuls_M_1101_N_1001,
	addc_rm_rn_M_1101_N_1001,
	addv_rm_rn_M_1101_N_1001,
	cmpeq_rm_rn_M_1110_N_1001,
	unimplemented,
	cmphs_rm_rn_M_1110_N_1001,
	cmpge_rm_rn_M_1110_N_1001,
	div1_M_1110_N_1001,
	dmulu_M_1110_N_1001,
	cmphi_rm_rn_M_1110_N_1001,
	cmpgt_rm_rn_M_1110_N_1001,
	sub_M_1110_N_1001,
	unimplemented,
	subc_M_1110_N_1001,
	subv_M_1110_N_1001,
	add_rm_rn_M_1110_N_1001,
	dmuls_M_1110_N_1001,
	addc_rm_rn_M_1110_N_1001,
	addv_rm_rn_M_1110_N_1001,
	cmpeq_rm_rn_M_1111_N_1001,
	unimplemented,
	cmphs_rm_rn_M_1111_N_1001,
	cmpge_rm_rn_M_1111_N_1001,
	div1_M_1111_N_1001,
	dmulu_M_1111_N_1001,
	cmphi_rm_rn_M_1111_N_1001,
	cmpgt_rm_rn_M_1111_N_1001,
	sub_M_1111_N_1001,
	unimplemented,
	subc_M_1111_N_1001,
	subv_M_1111_N_1001,
	add_rm_rn_M_1111_N_1001,
	dmuls_M_1111_N_1001,
	addc_rm_rn_M_1111_N_1001,
	addv_rm_rn_M_1111_N_1001,
	cmpeq_rm_rn_M_0000_N_1010,
	unimplemented,
	cmphs_rm_rn_M_0000_N_1010,
	cmpge_rm_rn_M_0000_N_1010,
	div1_M_0000_N_1010,
	dmulu_M_0000_N_1010,
	cmphi_rm_rn_M_0000_N_1010,
	cmpgt_rm_rn_M_0000_N_1010,
	sub_M_0000_N_1010,
	unimplemented,
	subc_M_0000_N_1010,
	subv_M_0000_N_1010,
	add_rm_rn_M_0000_N_1010,
	dmuls_M_0000_N_1010,
	addc_rm_rn_M_0000_N_1010,
	addv_rm_rn_M_0000_N_1010,
	cmpeq_rm_rn_M_0001_N_1010,
	unimplemented,
	cmphs_rm_rn_M_0001_N_1010,
	cmpge_rm_rn_M_0001_N_1010,
	div1_M_0001_N_1010,
	dmulu_M_0001_N_1010,
	cmphi_rm_rn_M_0001_N_1010,
	cmpgt_rm_rn_M_0001_N_1010,
	sub_M_0001_N_1010,
	unimplemented,
	subc_M_0001_N_1010,
	subv_M_0001_N_1010,
	add_rm_rn_M_0001_N_1010,
	dmuls_M_0001_N_1010,
	addc_rm_rn_M_0001_N_1010,
	addv_rm_rn_M_0001_N_1010,
	cmpeq_rm_rn_M_0010_N_1010,
	unimplemented,
	cmphs_rm_rn_M_0010_N_1010,
	cmpge_rm_rn_M_0010_N_1010,
	div1_M_0010_N_1010,
	dmulu_M_0010_N_1010,
	cmphi_rm_rn_M_0010_N_1010,
	cmpgt_rm_rn_M_0010_N_1010,
	sub_M_0010_N_1010,
	unimplemented,
	subc_M_0010_N_1010,
	subv_M_0010_N_1010,
	add_rm_rn_M_0010_N_1010,
	dmuls_M_0010_N_1010,
	addc_rm_rn_M_0010_N_1010,
	addv_rm_rn_M_0010_N_1010,
	cmpeq_rm_rn_M_0011_N_1010,
	unimplemented,
	cmphs_rm_rn_M_0011_N_1010,
	cmpge_rm_rn_M_0011_N_1010,
	div1_M_0011_N_1010,
	dmulu_M_0011_N_1010,
	cmphi_rm_rn_M_0011_N_1010,
	cmpgt_rm_rn_M_0011_N_1010,
	sub_M_0011_N_1010,
	unimplemented,
	subc_M_0011_N_1010,
	subv_M_0011_N_1010,
	add_rm_rn_M_0011_N_1010,
	dmuls_M_0011_N_1010,
	addc_rm_rn_M_0011_N_1010,
	addv_rm_rn_M_0011_N_1010,
	cmpeq_rm_rn_M_0100_N_1010,
	unimplemented,
	cmphs_rm_rn_M_0100_N_1010,
	cmpge_rm_rn_M_0100_N_1010,
	div1_M_0100_N_1010,
	dmulu_M_0100_N_1010,
	cmphi_rm_rn_M_0100_N_1010,
	cmpgt_rm_rn_M_0100_N_1010,
	sub_M_0100_N_1010,
	unimplemented,
	subc_M_0100_N_1010,
	subv_M_0100_N_1010,
	add_rm_rn_M_0100_N_1010,
	dmuls_M_0100_N_1010,
	addc_rm_rn_M_0100_N_1010,
	addv_rm_rn_M_0100_N_1010,
	cmpeq_rm_rn_M_0101_N_1010,
	unimplemented,
	cmphs_rm_rn_M_0101_N_1010,
	cmpge_rm_rn_M_0101_N_1010,
	div1_M_0101_N_1010,
	dmulu_M_0101_N_1010,
	cmphi_rm_rn_M_0101_N_1010,
	cmpgt_rm_rn_M_0101_N_1010,
	sub_M_0101_N_1010,
	unimplemented,
	subc_M_0101_N_1010,
	subv_M_0101_N_1010,
	add_rm_rn_M_0101_N_1010,
	dmuls_M_0101_N_1010,
	addc_rm_rn_M_0101_N_1010,
	addv_rm_rn_M_0101_N_1010,
	cmpeq_rm_rn_M_0110_N_1010,
	unimplemented,
	cmphs_rm_rn_M_0110_N_1010,
	cmpge_rm_rn_M_0110_N_1010,
	div1_M_0110_N_1010,
	dmulu_M_0110_N_1010,
	cmphi_rm_rn_M_0110_N_1010,
	cmpgt_rm_rn_M_0110_N_1010,
	sub_M_0110_N_1010,
	unimplemented,
	subc_M_0110_N_1010,
	subv_M_0110_N_1010,
	add_rm_rn_M_0110_N_1010,
	dmuls_M_0110_N_1010,
	addc_rm_rn_M_0110_N_1010,
	addv_rm_rn_M_0110_N_1010,
	cmpeq_rm_rn_M_0111_N_1010,
	unimplemented,
	cmphs_rm_rn_M_0111_N_1010,
	cmpge_rm_rn_M_0111_N_1010,
	div1_M_0111_N_1010,
	dmulu_M_0111_N_1010,
	cmphi_rm_rn_M_0111_N_1010,
	cmpgt_rm_rn_M_0111_N_1010,
	sub_M_0111_N_1010,
	unimplemented,
	subc_M_0111_N_1010,
	subv_M_0111_N_1010,
	add_rm_rn_M_0111_N_1010,
	dmuls_M_0111_N_1010,
	addc_rm_rn_M_0111_N_1010,
	addv_rm_rn_M_0111_N_1010,
	cmpeq_rm_rn_M_1000_N_1010,
	unimplemented,
	cmphs_rm_rn_M_1000_N_1010,
	cmpge_rm_rn_M_1000_N_1010,
	div1_M_1000_N_1010,
	dmulu_M_1000_N_1010,
	cmphi_rm_rn_M_1000_N_1010,
	cmpgt_rm_rn_M_1000_N_1010,
	sub_M_1000_N_1010,
	unimplemented,
	subc_M_1000_N_1010,
	subv_M_1000_N_1010,
	add_rm_rn_M_1000_N_1010,
	dmuls_M_1000_N_1010,
	addc_rm_rn_M_1000_N_1010,
	addv_rm_rn_M_1000_N_1010,
	cmpeq_rm_rn_M_1001_N_1010,
	unimplemented,
	cmphs_rm_rn_M_1001_N_1010,
	cmpge_rm_rn_M_1001_N_1010,
	div1_M_1001_N_1010,
	dmulu_M_1001_N_1010,
	cmphi_rm_rn_M_1001_N_1010,
	cmpgt_rm_rn_M_1001_N_1010,
	sub_M_1001_N_1010,
	unimplemented,
	subc_M_1001_N_1010,
	subv_M_1001_N_1010,
	add_rm_rn_M_1001_N_1010,
	dmuls_M_1001_N_1010,
	addc_rm_rn_M_1001_N_1010,
	addv_rm_rn_M_1001_N_1010,
	cmpeq_rm_rn_M_1010_N_1010,
	unimplemented,
	cmphs_rm_rn_M_1010_N_1010,
	cmpge_rm_rn_M_1010_N_1010,
	div1_M_1010_N_1010,
	dmulu_M_1010_N_1010,
	cmphi_rm_rn_M_1010_N_1010,
	cmpgt_rm_rn_M_1010_N_1010,
	sub_M_1010_N_1010,
	unimplemented,
	subc_M_1010_N_1010,
	subv_M_1010_N_1010,
	add_rm_rn_M_1010_N_1010,
	dmuls_M_1010_N_1010,
	addc_rm_rn_M_1010_N_1010,
	addv_rm_rn_M_1010_N_1010,
	cmpeq_rm_rn_M_1011_N_1010,
	unimplemented,
	cmphs_rm_rn_M_1011_N_1010,
	cmpge_rm_rn_M_1011_N_1010,
	div1_M_1011_N_1010,
	dmulu_M_1011_N_1010,
	cmphi_rm_rn_M_1011_N_1010,
	cmpgt_rm_rn_M_1011_N_1010,
	sub_M_1011_N_1010,
	unimplemented,
	subc_M_1011_N_1010,
	subv_M_1011_N_1010,
	add_rm_rn_M_1011_N_1010,
	dmuls_M_1011_N_1010,
	addc_rm_rn_M_1011_N_1010,
	addv_rm_rn_M_1011_N_1010,
	cmpeq_rm_rn_M_1100_N_1010,
	unimplemented,
	cmphs_rm_rn_M_1100_N_1010,
	cmpge_rm_rn_M_1100_N_1010,
	div1_M_1100_N_1010,
	dmulu_M_1100_N_1010,
	cmphi_rm_rn_M_1100_N_1010,
	cmpgt_rm_rn_M_1100_N_1010,
	sub_M_1100_N_1010,
	unimplemented,
	subc_M_1100_N_1010,
	subv_M_1100_N_1010,
	add_rm_rn_M_1100_N_1010,
	dmuls_M_1100_N_1010,
	addc_rm_rn_M_1100_N_1010,
	addv_rm_rn_M_1100_N_1010,
	cmpeq_rm_rn_M_1101_N_1010,
	unimplemented,
	cmphs_rm_rn_M_1101_N_1010,
	cmpge_rm_rn_M_1101_N_1010,
	div1_M_1101_N_1010,
	dmulu_M_1101_N_1010,
	cmphi_rm_rn_M_1101_N_1010,
	cmpgt_rm_rn_M_1101_N_1010,
	sub_M_1101_N_1010,
	unimplemented,
	subc_M_1101_N_1010,
	subv_M_1101_N_1010,
	add_rm_rn_M_1101_N_1010,
	dmuls_M_1101_N_1010,
	addc_rm_rn_M_1101_N_1010,
	addv_rm_rn_M_1101_N_1010,
	cmpeq_rm_rn_M_1110_N_1010,
	unimplemented,
	cmphs_rm_rn_M_1110_N_1010,
	cmpge_rm_rn_M_1110_N_1010,
	div1_M_1110_N_1010,
	dmulu_M_1110_N_1010,
	cmphi_rm_rn_M_1110_N_1010,
	cmpgt_rm_rn_M_1110_N_1010,
	sub_M_1110_N_1010,
	unimplemented,
	subc_M_1110_N_1010,
	subv_M_1110_N_1010,
	add_rm_rn_M_1110_N_1010,
	dmuls_M_1110_N_1010,
	addc_rm_rn_M_1110_N_1010,
	addv_rm_rn_M_1110_N_1010,
	cmpeq_rm_rn_M_1111_N_1010,
	unimplemented,
	cmphs_rm_rn_M_1111_N_1010,
	cmpge_rm_rn_M_1111_N_1010,
	div1_M_1111_N_1010,
	dmulu_M_1111_N_1010,
	cmphi_rm_rn_M_1111_N_1010,
	cmpgt_rm_rn_M_1111_N_1010,
	sub_M_1111_N_1010,
	unimplemented,
	subc_M_1111_N_1010,
	subv_M_1111_N_1010,
	add_rm_rn_M_1111_N_1010,
	dmuls_M_1111_N_1010,
	addc_rm_rn_M_1111_N_1010,
	addv_rm_rn_M_1111_N_1010,
	cmpeq_rm_rn_M_0000_N_1011,
	unimplemented,
	cmphs_rm_rn_M_0000_N_1011,
	cmpge_rm_rn_M_0000_N_1011,
	div1_M_0000_N_1011,
	dmulu_M_0000_N_1011,
	cmphi_rm_rn_M_0000_N_1011,
	cmpgt_rm_rn_M_0000_N_1011,
	sub_M_0000_N_1011,
	unimplemented,
	subc_M_0000_N_1011,
	subv_M_0000_N_1011,
	add_rm_rn_M_0000_N_1011,
	dmuls_M_0000_N_1011,
	addc_rm_rn_M_0000_N_1011,
	addv_rm_rn_M_0000_N_1011,
	cmpeq_rm_rn_M_0001_N_1011,
	unimplemented,
	cmphs_rm_rn_M_0001_N_1011,
	cmpge_rm_rn_M_0001_N_1011,
	div1_M_0001_N_1011,
	dmulu_M_0001_N_1011,
	cmphi_rm_rn_M_0001_N_1011,
	cmpgt_rm_rn_M_0001_N_1011,
	sub_M_0001_N_1011,
	unimplemented,
	subc_M_0001_N_1011,
	subv_M_0001_N_1011,
	add_rm_rn_M_0001_N_1011,
	dmuls_M_0001_N_1011,
	addc_rm_rn_M_0001_N_1011,
	addv_rm_rn_M_0001_N_1011,
	cmpeq_rm_rn_M_0010_N_1011,
	unimplemented,
	cmphs_rm_rn_M_0010_N_1011,
	cmpge_rm_rn_M_0010_N_1011,
	div1_M_0010_N_1011,
	dmulu_M_0010_N_1011,
	cmphi_rm_rn_M_0010_N_1011,
	cmpgt_rm_rn_M_0010_N_1011,
	sub_M_0010_N_1011,
	unimplemented,
	subc_M_0010_N_1011,
	subv_M_0010_N_1011,
	add_rm_rn_M_0010_N_1011,
	dmuls_M_0010_N_1011,
	addc_rm_rn_M_0010_N_1011,
	addv_rm_rn_M_0010_N_1011,
	cmpeq_rm_rn_M_0011_N_1011,
	unimplemented,
	cmphs_rm_rn_M_0011_N_1011,
	cmpge_rm_rn_M_0011_N_1011,
	div1_M_0011_N_1011,
	dmulu_M_0011_N_1011,
	cmphi_rm_rn_M_0011_N_1011,
	cmpgt_rm_rn_M_0011_N_1011,
	sub_M_0011_N_1011,
	unimplemented,
	subc_M_0011_N_1011,
	subv_M_0011_N_1011,
	add_rm_rn_M_0011_N_1011,
	dmuls_M_0011_N_1011,
	addc_rm_rn_M_0011_N_1011,
	addv_rm_rn_M_0011_N_1011,
	cmpeq_rm_rn_M_0100_N_1011,
	unimplemented,
	cmphs_rm_rn_M_0100_N_1011,
	cmpge_rm_rn_M_0100_N_1011,
	div1_M_0100_N_1011,
	dmulu_M_0100_N_1011,
	cmphi_rm_rn_M_0100_N_1011,
	cmpgt_rm_rn_M_0100_N_1011,
	sub_M_0100_N_1011,
	unimplemented,
	subc_M_0100_N_1011,
	subv_M_0100_N_1011,
	add_rm_rn_M_0100_N_1011,
	dmuls_M_0100_N_1011,
	addc_rm_rn_M_0100_N_1011,
	addv_rm_rn_M_0100_N_1011,
	cmpeq_rm_rn_M_0101_N_1011,
	unimplemented,
	cmphs_rm_rn_M_0101_N_1011,
	cmpge_rm_rn_M_0101_N_1011,
	div1_M_0101_N_1011,
	dmulu_M_0101_N_1011,
	cmphi_rm_rn_M_0101_N_1011,
	cmpgt_rm_rn_M_0101_N_1011,
	sub_M_0101_N_1011,
	unimplemented,
	subc_M_0101_N_1011,
	subv_M_0101_N_1011,
	add_rm_rn_M_0101_N_1011,
	dmuls_M_0101_N_1011,
	addc_rm_rn_M_0101_N_1011,
	addv_rm_rn_M_0101_N_1011,
	cmpeq_rm_rn_M_0110_N_1011,
	unimplemented,
	cmphs_rm_rn_M_0110_N_1011,
	cmpge_rm_rn_M_0110_N_1011,
	div1_M_0110_N_1011,
	dmulu_M_0110_N_1011,
	cmphi_rm_rn_M_0110_N_1011,
	cmpgt_rm_rn_M_0110_N_1011,
	sub_M_0110_N_1011,
	unimplemented,
	subc_M_0110_N_1011,
	subv_M_0110_N_1011,
	add_rm_rn_M_0110_N_1011,
	dmuls_M_0110_N_1011,
	addc_rm_rn_M_0110_N_1011,
	addv_rm_rn_M_0110_N_1011,
	cmpeq_rm_rn_M_0111_N_1011,
	unimplemented,
	cmphs_rm_rn_M_0111_N_1011,
	cmpge_rm_rn_M_0111_N_1011,
	div1_M_0111_N_1011,
	dmulu_M_0111_N_1011,
	cmphi_rm_rn_M_0111_N_1011,
	cmpgt_rm_rn_M_0111_N_1011,
	sub_M_0111_N_1011,
	unimplemented,
	subc_M_0111_N_1011,
	subv_M_0111_N_1011,
	add_rm_rn_M_0111_N_1011,
	dmuls_M_0111_N_1011,
	addc_rm_rn_M_0111_N_1011,
	addv_rm_rn_M_0111_N_1011,
	cmpeq_rm_rn_M_1000_N_1011,
	unimplemented,
	cmphs_rm_rn_M_1000_N_1011,
	cmpge_rm_rn_M_1000_N_1011,
	div1_M_1000_N_1011,
	dmulu_M_1000_N_1011,
	cmphi_rm_rn_M_1000_N_1011,
	cmpgt_rm_rn_M_1000_N_1011,
	sub_M_1000_N_1011,
	unimplemented,
	subc_M_1000_N_1011,
	subv_M_1000_N_1011,
	add_rm_rn_M_1000_N_1011,
	dmuls_M_1000_N_1011,
	addc_rm_rn_M_1000_N_1011,
	addv_rm_rn_M_1000_N_1011,
	cmpeq_rm_rn_M_1001_N_1011,
	unimplemented,
	cmphs_rm_rn_M_1001_N_1011,
	cmpge_rm_rn_M_1001_N_1011,
	div1_M_1001_N_1011,
	dmulu_M_1001_N_1011,
	cmphi_rm_rn_M_1001_N_1011,
	cmpgt_rm_rn_M_1001_N_1011,
	sub_M_1001_N_1011,
	unimplemented,
	subc_M_1001_N_1011,
	subv_M_1001_N_1011,
	add_rm_rn_M_1001_N_1011,
	dmuls_M_1001_N_1011,
	addc_rm_rn_M_1001_N_1011,
	addv_rm_rn_M_1001_N_1011,
	cmpeq_rm_rn_M_1010_N_1011,
	unimplemented,
	cmphs_rm_rn_M_1010_N_1011,
	cmpge_rm_rn_M_1010_N_1011,
	div1_M_1010_N_1011,
	dmulu_M_1010_N_1011,
	cmphi_rm_rn_M_1010_N_1011,
	cmpgt_rm_rn_M_1010_N_1011,
	sub_M_1010_N_1011,
	unimplemented,
	subc_M_1010_N_1011,
	subv_M_1010_N_1011,
	add_rm_rn_M_1010_N_1011,
	dmuls_M_1010_N_1011,
	addc_rm_rn_M_1010_N_1011,
	addv_rm_rn_M_1010_N_1011,
	cmpeq_rm_rn_M_1011_N_1011,
	unimplemented,
	cmphs_rm_rn_M_1011_N_1011,
	cmpge_rm_rn_M_1011_N_1011,
	div1_M_1011_N_1011,
	dmulu_M_1011_N_1011,
	cmphi_rm_rn_M_1011_N_1011,
	cmpgt_rm_rn_M_1011_N_1011,
	sub_M_1011_N_1011,
	unimplemented,
	subc_M_1011_N_1011,
	subv_M_1011_N_1011,
	add_rm_rn_M_1011_N_1011,
	dmuls_M_1011_N_1011,
	addc_rm_rn_M_1011_N_1011,
	addv_rm_rn_M_1011_N_1011,
	cmpeq_rm_rn_M_1100_N_1011,
	unimplemented,
	cmphs_rm_rn_M_1100_N_1011,
	cmpge_rm_rn_M_1100_N_1011,
	div1_M_1100_N_1011,
	dmulu_M_1100_N_1011,
	cmphi_rm_rn_M_1100_N_1011,
	cmpgt_rm_rn_M_1100_N_1011,
	sub_M_1100_N_1011,
	unimplemented,
	subc_M_1100_N_1011,
	subv_M_1100_N_1011,
	add_rm_rn_M_1100_N_1011,
	dmuls_M_1100_N_1011,
	addc_rm_rn_M_1100_N_1011,
	addv_rm_rn_M_1100_N_1011,
	cmpeq_rm_rn_M_1101_N_1011,
	unimplemented,
	cmphs_rm_rn_M_1101_N_1011,
	cmpge_rm_rn_M_1101_N_1011,
	div1_M_1101_N_1011,
	dmulu_M_1101_N_1011,
	cmphi_rm_rn_M_1101_N_1011,
	cmpgt_rm_rn_M_1101_N_1011,
	sub_M_1101_N_1011,
	unimplemented,
	subc_M_1101_N_1011,
	subv_M_1101_N_1011,
	add_rm_rn_M_1101_N_1011,
	dmuls_M_1101_N_1011,
	addc_rm_rn_M_1101_N_1011,
	addv_rm_rn_M_1101_N_1011,
	cmpeq_rm_rn_M_1110_N_1011,
	unimplemented,
	cmphs_rm_rn_M_1110_N_1011,
	cmpge_rm_rn_M_1110_N_1011,
	div1_M_1110_N_1011,
	dmulu_M_1110_N_1011,
	cmphi_rm_rn_M_1110_N_1011,
	cmpgt_rm_rn_M_1110_N_1011,
	sub_M_1110_N_1011,
	unimplemented,
	subc_M_1110_N_1011,
	subv_M_1110_N_1011,
	add_rm_rn_M_1110_N_1011,
	dmuls_M_1110_N_1011,
	addc_rm_rn_M_1110_N_1011,
	addv_rm_rn_M_1110_N_1011,
	cmpeq_rm_rn_M_1111_N_1011,
	unimplemented,
	cmphs_rm_rn_M_1111_N_1011,
	cmpge_rm_rn_M_1111_N_1011,
	div1_M_1111_N_1011,
	dmulu_M_1111_N_1011,
	cmphi_rm_rn_M_1111_N_1011,
	cmpgt_rm_rn_M_1111_N_1011,
	sub_M_1111_N_1011,
	unimplemented,
	subc_M_1111_N_1011,
	subv_M_1111_N_1011,
	add_rm_rn_M_1111_N_1011,
	dmuls_M_1111_N_1011,
	addc_rm_rn_M_1111_N_1011,
	addv_rm_rn_M_1111_N_1011,
	cmpeq_rm_rn_M_0000_N_1100,
	unimplemented,
	cmphs_rm_rn_M_0000_N_1100,
	cmpge_rm_rn_M_0000_N_1100,
	div1_M_0000_N_1100,
	dmulu_M_0000_N_1100,
	cmphi_rm_rn_M_0000_N_1100,
	cmpgt_rm_rn_M_0000_N_1100,
	sub_M_0000_N_1100,
	unimplemented,
	subc_M_0000_N_1100,
	subv_M_0000_N_1100,
	add_rm_rn_M_0000_N_1100,
	dmuls_M_0000_N_1100,
	addc_rm_rn_M_0000_N_1100,
	addv_rm_rn_M_0000_N_1100,
	cmpeq_rm_rn_M_0001_N_1100,
	unimplemented,
	cmphs_rm_rn_M_0001_N_1100,
	cmpge_rm_rn_M_0001_N_1100,
	div1_M_0001_N_1100,
	dmulu_M_0001_N_1100,
	cmphi_rm_rn_M_0001_N_1100,
	cmpgt_rm_rn_M_0001_N_1100,
	sub_M_0001_N_1100,
	unimplemented,
	subc_M_0001_N_1100,
	subv_M_0001_N_1100,
	add_rm_rn_M_0001_N_1100,
	dmuls_M_0001_N_1100,
	addc_rm_rn_M_0001_N_1100,
	addv_rm_rn_M_0001_N_1100,
	cmpeq_rm_rn_M_0010_N_1100,
	unimplemented,
	cmphs_rm_rn_M_0010_N_1100,
	cmpge_rm_rn_M_0010_N_1100,
	div1_M_0010_N_1100,
	dmulu_M_0010_N_1100,
	cmphi_rm_rn_M_0010_N_1100,
	cmpgt_rm_rn_M_0010_N_1100,
	sub_M_0010_N_1100,
	unimplemented,
	subc_M_0010_N_1100,
	subv_M_0010_N_1100,
	add_rm_rn_M_0010_N_1100,
	dmuls_M_0010_N_1100,
	addc_rm_rn_M_0010_N_1100,
	addv_rm_rn_M_0010_N_1100,
	cmpeq_rm_rn_M_0011_N_1100,
	unimplemented,
	cmphs_rm_rn_M_0011_N_1100,
	cmpge_rm_rn_M_0011_N_1100,
	div1_M_0011_N_1100,
	dmulu_M_0011_N_1100,
	cmphi_rm_rn_M_0011_N_1100,
	cmpgt_rm_rn_M_0011_N_1100,
	sub_M_0011_N_1100,
	unimplemented,
	subc_M_0011_N_1100,
	subv_M_0011_N_1100,
	add_rm_rn_M_0011_N_1100,
	dmuls_M_0011_N_1100,
	addc_rm_rn_M_0011_N_1100,
	addv_rm_rn_M_0011_N_1100,
	cmpeq_rm_rn_M_0100_N_1100,
	unimplemented,
	cmphs_rm_rn_M_0100_N_1100,
	cmpge_rm_rn_M_0100_N_1100,
	div1_M_0100_N_1100,
	dmulu_M_0100_N_1100,
	cmphi_rm_rn_M_0100_N_1100,
	cmpgt_rm_rn_M_0100_N_1100,
	sub_M_0100_N_1100,
	unimplemented,
	subc_M_0100_N_1100,
	subv_M_0100_N_1100,
	add_rm_rn_M_0100_N_1100,
	dmuls_M_0100_N_1100,
	addc_rm_rn_M_0100_N_1100,
	addv_rm_rn_M_0100_N_1100,
	cmpeq_rm_rn_M_0101_N_1100,
	unimplemented,
	cmphs_rm_rn_M_0101_N_1100,
	cmpge_rm_rn_M_0101_N_1100,
	div1_M_0101_N_1100,
	dmulu_M_0101_N_1100,
	cmphi_rm_rn_M_0101_N_1100,
	cmpgt_rm_rn_M_0101_N_1100,
	sub_M_0101_N_1100,
	unimplemented,
	subc_M_0101_N_1100,
	subv_M_0101_N_1100,
	add_rm_rn_M_0101_N_1100,
	dmuls_M_0101_N_1100,
	addc_rm_rn_M_0101_N_1100,
	addv_rm_rn_M_0101_N_1100,
	cmpeq_rm_rn_M_0110_N_1100,
	unimplemented,
	cmphs_rm_rn_M_0110_N_1100,
	cmpge_rm_rn_M_0110_N_1100,
	div1_M_0110_N_1100,
	dmulu_M_0110_N_1100,
	cmphi_rm_rn_M_0110_N_1100,
	cmpgt_rm_rn_M_0110_N_1100,
	sub_M_0110_N_1100,
	unimplemented,
	subc_M_0110_N_1100,
	subv_M_0110_N_1100,
	add_rm_rn_M_0110_N_1100,
	dmuls_M_0110_N_1100,
	addc_rm_rn_M_0110_N_1100,
	addv_rm_rn_M_0110_N_1100,
	cmpeq_rm_rn_M_0111_N_1100,
	unimplemented,
	cmphs_rm_rn_M_0111_N_1100,
	cmpge_rm_rn_M_0111_N_1100,
	div1_M_0111_N_1100,
	dmulu_M_0111_N_1100,
	cmphi_rm_rn_M_0111_N_1100,
	cmpgt_rm_rn_M_0111_N_1100,
	sub_M_0111_N_1100,
	unimplemented,
	subc_M_0111_N_1100,
	subv_M_0111_N_1100,
	add_rm_rn_M_0111_N_1100,
	dmuls_M_0111_N_1100,
	addc_rm_rn_M_0111_N_1100,
	addv_rm_rn_M_0111_N_1100,
	cmpeq_rm_rn_M_1000_N_1100,
	unimplemented,
	cmphs_rm_rn_M_1000_N_1100,
	cmpge_rm_rn_M_1000_N_1100,
	div1_M_1000_N_1100,
	dmulu_M_1000_N_1100,
	cmphi_rm_rn_M_1000_N_1100,
	cmpgt_rm_rn_M_1000_N_1100,
	sub_M_1000_N_1100,
	unimplemented,
	subc_M_1000_N_1100,
	subv_M_1000_N_1100,
	add_rm_rn_M_1000_N_1100,
	dmuls_M_1000_N_1100,
	addc_rm_rn_M_1000_N_1100,
	addv_rm_rn_M_1000_N_1100,
	cmpeq_rm_rn_M_1001_N_1100,
	unimplemented,
	cmphs_rm_rn_M_1001_N_1100,
	cmpge_rm_rn_M_1001_N_1100,
	div1_M_1001_N_1100,
	dmulu_M_1001_N_1100,
	cmphi_rm_rn_M_1001_N_1100,
	cmpgt_rm_rn_M_1001_N_1100,
	sub_M_1001_N_1100,
	unimplemented,
	subc_M_1001_N_1100,
	subv_M_1001_N_1100,
	add_rm_rn_M_1001_N_1100,
	dmuls_M_1001_N_1100,
	addc_rm_rn_M_1001_N_1100,
	addv_rm_rn_M_1001_N_1100,
	cmpeq_rm_rn_M_1010_N_1100,
	unimplemented,
	cmphs_rm_rn_M_1010_N_1100,
	cmpge_rm_rn_M_1010_N_1100,
	div1_M_1010_N_1100,
	dmulu_M_1010_N_1100,
	cmphi_rm_rn_M_1010_N_1100,
	cmpgt_rm_rn_M_1010_N_1100,
	sub_M_1010_N_1100,
	unimplemented,
	subc_M_1010_N_1100,
	subv_M_1010_N_1100,
	add_rm_rn_M_1010_N_1100,
	dmuls_M_1010_N_1100,
	addc_rm_rn_M_1010_N_1100,
	addv_rm_rn_M_1010_N_1100,
	cmpeq_rm_rn_M_1011_N_1100,
	unimplemented,
	cmphs_rm_rn_M_1011_N_1100,
	cmpge_rm_rn_M_1011_N_1100,
	div1_M_1011_N_1100,
	dmulu_M_1011_N_1100,
	cmphi_rm_rn_M_1011_N_1100,
	cmpgt_rm_rn_M_1011_N_1100,
	sub_M_1011_N_1100,
	unimplemented,
	subc_M_1011_N_1100,
	subv_M_1011_N_1100,
	add_rm_rn_M_1011_N_1100,
	dmuls_M_1011_N_1100,
	addc_rm_rn_M_1011_N_1100,
	addv_rm_rn_M_1011_N_1100,
	cmpeq_rm_rn_M_1100_N_1100,
	unimplemented,
	cmphs_rm_rn_M_1100_N_1100,
	cmpge_rm_rn_M_1100_N_1100,
	div1_M_1100_N_1100,
	dmulu_M_1100_N_1100,
	cmphi_rm_rn_M_1100_N_1100,
	cmpgt_rm_rn_M_1100_N_1100,
	sub_M_1100_N_1100,
	unimplemented,
	subc_M_1100_N_1100,
	subv_M_1100_N_1100,
	add_rm_rn_M_1100_N_1100,
	dmuls_M_1100_N_1100,
	addc_rm_rn_M_1100_N_1100,
	addv_rm_rn_M_1100_N_1100,
	cmpeq_rm_rn_M_1101_N_1100,
	unimplemented,
	cmphs_rm_rn_M_1101_N_1100,
	cmpge_rm_rn_M_1101_N_1100,
	div1_M_1101_N_1100,
	dmulu_M_1101_N_1100,
	cmphi_rm_rn_M_1101_N_1100,
	cmpgt_rm_rn_M_1101_N_1100,
	sub_M_1101_N_1100,
	unimplemented,
	subc_M_1101_N_1100,
	subv_M_1101_N_1100,
	add_rm_rn_M_1101_N_1100,
	dmuls_M_1101_N_1100,
	addc_rm_rn_M_1101_N_1100,
	addv_rm_rn_M_1101_N_1100,
	cmpeq_rm_rn_M_1110_N_1100,
	unimplemented,
	cmphs_rm_rn_M_1110_N_1100,
	cmpge_rm_rn_M_1110_N_1100,
	div1_M_1110_N_1100,
	dmulu_M_1110_N_1100,
	cmphi_rm_rn_M_1110_N_1100,
	cmpgt_rm_rn_M_1110_N_1100,
	sub_M_1110_N_1100,
	unimplemented,
	subc_M_1110_N_1100,
	subv_M_1110_N_1100,
	add_rm_rn_M_1110_N_1100,
	dmuls_M_1110_N_1100,
	addc_rm_rn_M_1110_N_1100,
	addv_rm_rn_M_1110_N_1100,
	cmpeq_rm_rn_M_1111_N_1100,
	unimplemented,
	cmphs_rm_rn_M_1111_N_1100,
	cmpge_rm_rn_M_1111_N_1100,
	div1_M_1111_N_1100,
	dmulu_M_1111_N_1100,
	cmphi_rm_rn_M_1111_N_1100,
	cmpgt_rm_rn_M_1111_N_1100,
	sub_M_1111_N_1100,
	unimplemented,
	subc_M_1111_N_1100,
	subv_M_1111_N_1100,
	add_rm_rn_M_1111_N_1100,
	dmuls_M_1111_N_1100,
	addc_rm_rn_M_1111_N_1100,
	addv_rm_rn_M_1111_N_1100,
	cmpeq_rm_rn_M_0000_N_1101,
	unimplemented,
	cmphs_rm_rn_M_0000_N_1101,
	cmpge_rm_rn_M_0000_N_1101,
	div1_M_0000_N_1101,
	dmulu_M_0000_N_1101,
	cmphi_rm_rn_M_0000_N_1101,
	cmpgt_rm_rn_M_0000_N_1101,
	sub_M_0000_N_1101,
	unimplemented,
	subc_M_0000_N_1101,
	subv_M_0000_N_1101,
	add_rm_rn_M_0000_N_1101,
	dmuls_M_0000_N_1101,
	addc_rm_rn_M_0000_N_1101,
	addv_rm_rn_M_0000_N_1101,
	cmpeq_rm_rn_M_0001_N_1101,
	unimplemented,
	cmphs_rm_rn_M_0001_N_1101,
	cmpge_rm_rn_M_0001_N_1101,
	div1_M_0001_N_1101,
	dmulu_M_0001_N_1101,
	cmphi_rm_rn_M_0001_N_1101,
	cmpgt_rm_rn_M_0001_N_1101,
	sub_M_0001_N_1101,
	unimplemented,
	subc_M_0001_N_1101,
	subv_M_0001_N_1101,
	add_rm_rn_M_0001_N_1101,
	dmuls_M_0001_N_1101,
	addc_rm_rn_M_0001_N_1101,
	addv_rm_rn_M_0001_N_1101,
	cmpeq_rm_rn_M_0010_N_1101,
	unimplemented,
	cmphs_rm_rn_M_0010_N_1101,
	cmpge_rm_rn_M_0010_N_1101,
	div1_M_0010_N_1101,
	dmulu_M_0010_N_1101,
	cmphi_rm_rn_M_0010_N_1101,
	cmpgt_rm_rn_M_0010_N_1101,
	sub_M_0010_N_1101,
	unimplemented,
	subc_M_0010_N_1101,
	subv_M_0010_N_1101,
	add_rm_rn_M_0010_N_1101,
	dmuls_M_0010_N_1101,
	addc_rm_rn_M_0010_N_1101,
	addv_rm_rn_M_0010_N_1101,
	cmpeq_rm_rn_M_0011_N_1101,
	unimplemented,
	cmphs_rm_rn_M_0011_N_1101,
	cmpge_rm_rn_M_0011_N_1101,
	div1_M_0011_N_1101,
	dmulu_M_0011_N_1101,
	cmphi_rm_rn_M_0011_N_1101,
	cmpgt_rm_rn_M_0011_N_1101,
	sub_M_0011_N_1101,
	unimplemented,
	subc_M_0011_N_1101,
	subv_M_0011_N_1101,
	add_rm_rn_M_0011_N_1101,
	dmuls_M_0011_N_1101,
	addc_rm_rn_M_0011_N_1101,
	addv_rm_rn_M_0011_N_1101,
	cmpeq_rm_rn_M_0100_N_1101,
	unimplemented,
	cmphs_rm_rn_M_0100_N_1101,
	cmpge_rm_rn_M_0100_N_1101,
	div1_M_0100_N_1101,
	dmulu_M_0100_N_1101,
	cmphi_rm_rn_M_0100_N_1101,
	cmpgt_rm_rn_M_0100_N_1101,
	sub_M_0100_N_1101,
	unimplemented,
	subc_M_0100_N_1101,
	subv_M_0100_N_1101,
	add_rm_rn_M_0100_N_1101,
	dmuls_M_0100_N_1101,
	addc_rm_rn_M_0100_N_1101,
	addv_rm_rn_M_0100_N_1101,
	cmpeq_rm_rn_M_0101_N_1101,
	unimplemented,
	cmphs_rm_rn_M_0101_N_1101,
	cmpge_rm_rn_M_0101_N_1101,
	div1_M_0101_N_1101,
	dmulu_M_0101_N_1101,
	cmphi_rm_rn_M_0101_N_1101,
	cmpgt_rm_rn_M_0101_N_1101,
	sub_M_0101_N_1101,
	unimplemented,
	subc_M_0101_N_1101,
	subv_M_0101_N_1101,
	add_rm_rn_M_0101_N_1101,
	dmuls_M_0101_N_1101,
	addc_rm_rn_M_0101_N_1101,
	addv_rm_rn_M_0101_N_1101,
	cmpeq_rm_rn_M_0110_N_1101,
	unimplemented,
	cmphs_rm_rn_M_0110_N_1101,
	cmpge_rm_rn_M_0110_N_1101,
	div1_M_0110_N_1101,
	dmulu_M_0110_N_1101,
	cmphi_rm_rn_M_0110_N_1101,
	cmpgt_rm_rn_M_0110_N_1101,
	sub_M_0110_N_1101,
	unimplemented,
	subc_M_0110_N_1101,
	subv_M_0110_N_1101,
	add_rm_rn_M_0110_N_1101,
	dmuls_M_0110_N_1101,
	addc_rm_rn_M_0110_N_1101,
	addv_rm_rn_M_0110_N_1101,
	cmpeq_rm_rn_M_0111_N_1101,
	unimplemented,
	cmphs_rm_rn_M_0111_N_1101,
	cmpge_rm_rn_M_0111_N_1101,
	div1_M_0111_N_1101,
	dmulu_M_0111_N_1101,
	cmphi_rm_rn_M_0111_N_1101,
	cmpgt_rm_rn_M_0111_N_1101,
	sub_M_0111_N_1101,
	unimplemented,
	subc_M_0111_N_1101,
	subv_M_0111_N_1101,
	add_rm_rn_M_0111_N_1101,
	dmuls_M_0111_N_1101,
	addc_rm_rn_M_0111_N_1101,
	addv_rm_rn_M_0111_N_1101,
	cmpeq_rm_rn_M_1000_N_1101,
	unimplemented,
	cmphs_rm_rn_M_1000_N_1101,
	cmpge_rm_rn_M_1000_N_1101,
	div1_M_1000_N_1101,
	dmulu_M_1000_N_1101,
	cmphi_rm_rn_M_1000_N_1101,
	cmpgt_rm_rn_M_1000_N_1101,
	sub_M_1000_N_1101,
	unimplemented,
	subc_M_1000_N_1101,
	subv_M_1000_N_1101,
	add_rm_rn_M_1000_N_1101,
	dmuls_M_1000_N_1101,
	addc_rm_rn_M_1000_N_1101,
	addv_rm_rn_M_1000_N_1101,
	cmpeq_rm_rn_M_1001_N_1101,
	unimplemented,
	cmphs_rm_rn_M_1001_N_1101,
	cmpge_rm_rn_M_1001_N_1101,
	div1_M_1001_N_1101,
	dmulu_M_1001_N_1101,
	cmphi_rm_rn_M_1001_N_1101,
	cmpgt_rm_rn_M_1001_N_1101,
	sub_M_1001_N_1101,
	unimplemented,
	subc_M_1001_N_1101,
	subv_M_1001_N_1101,
	add_rm_rn_M_1001_N_1101,
	dmuls_M_1001_N_1101,
	addc_rm_rn_M_1001_N_1101,
	addv_rm_rn_M_1001_N_1101,
	cmpeq_rm_rn_M_1010_N_1101,
	unimplemented,
	cmphs_rm_rn_M_1010_N_1101,
	cmpge_rm_rn_M_1010_N_1101,
	div1_M_1010_N_1101,
	dmulu_M_1010_N_1101,
	cmphi_rm_rn_M_1010_N_1101,
	cmpgt_rm_rn_M_1010_N_1101,
	sub_M_1010_N_1101,
	unimplemented,
	subc_M_1010_N_1101,
	subv_M_1010_N_1101,
	add_rm_rn_M_1010_N_1101,
	dmuls_M_1010_N_1101,
	addc_rm_rn_M_1010_N_1101,
	addv_rm_rn_M_1010_N_1101,
	cmpeq_rm_rn_M_1011_N_1101,
	unimplemented,
	cmphs_rm_rn_M_1011_N_1101,
	cmpge_rm_rn_M_1011_N_1101,
	div1_M_1011_N_1101,
	dmulu_M_1011_N_1101,
	cmphi_rm_rn_M_1011_N_1101,
	cmpgt_rm_rn_M_1011_N_1101,
	sub_M_1011_N_1101,
	unimplemented,
	subc_M_1011_N_1101,
	subv_M_1011_N_1101,
	add_rm_rn_M_1011_N_1101,
	dmuls_M_1011_N_1101,
	addc_rm_rn_M_1011_N_1101,
	addv_rm_rn_M_1011_N_1101,
	cmpeq_rm_rn_M_1100_N_1101,
	unimplemented,
	cmphs_rm_rn_M_1100_N_1101,
	cmpge_rm_rn_M_1100_N_1101,
	div1_M_1100_N_1101,
	dmulu_M_1100_N_1101,
	cmphi_rm_rn_M_1100_N_1101,
	cmpgt_rm_rn_M_1100_N_1101,
	sub_M_1100_N_1101,
	unimplemented,
	subc_M_1100_N_1101,
	subv_M_1100_N_1101,
	add_rm_rn_M_1100_N_1101,
	dmuls_M_1100_N_1101,
	addc_rm_rn_M_1100_N_1101,
	addv_rm_rn_M_1100_N_1101,
	cmpeq_rm_rn_M_1101_N_1101,
	unimplemented,
	cmphs_rm_rn_M_1101_N_1101,
	cmpge_rm_rn_M_1101_N_1101,
	div1_M_1101_N_1101,
	dmulu_M_1101_N_1101,
	cmphi_rm_rn_M_1101_N_1101,
	cmpgt_rm_rn_M_1101_N_1101,
	sub_M_1101_N_1101,
	unimplemented,
	subc_M_1101_N_1101,
	subv_M_1101_N_1101,
	add_rm_rn_M_1101_N_1101,
	dmuls_M_1101_N_1101,
	addc_rm_rn_M_1101_N_1101,
	addv_rm_rn_M_1101_N_1101,
	cmpeq_rm_rn_M_1110_N_1101,
	unimplemented,
	cmphs_rm_rn_M_1110_N_1101,
	cmpge_rm_rn_M_1110_N_1101,
	div1_M_1110_N_1101,
	dmulu_M_1110_N_1101,
	cmphi_rm_rn_M_1110_N_1101,
	cmpgt_rm_rn_M_1110_N_1101,
	sub_M_1110_N_1101,
	unimplemented,
	subc_M_1110_N_1101,
	subv_M_1110_N_1101,
	add_rm_rn_M_1110_N_1101,
	dmuls_M_1110_N_1101,
	addc_rm_rn_M_1110_N_1101,
	addv_rm_rn_M_1110_N_1101,
	cmpeq_rm_rn_M_1111_N_1101,
	unimplemented,
	cmphs_rm_rn_M_1111_N_1101,
	cmpge_rm_rn_M_1111_N_1101,
	div1_M_1111_N_1101,
	dmulu_M_1111_N_1101,
	cmphi_rm_rn_M_1111_N_1101,
	cmpgt_rm_rn_M_1111_N_1101,
	sub_M_1111_N_1101,
	unimplemented,
	subc_M_1111_N_1101,
	subv_M_1111_N_1101,
	add_rm_rn_M_1111_N_1101,
	dmuls_M_1111_N_1101,
	addc_rm_rn_M_1111_N_1101,
	addv_rm_rn_M_1111_N_1101,
	cmpeq_rm_rn_M_0000_N_1110,
	unimplemented,
	cmphs_rm_rn_M_0000_N_1110,
	cmpge_rm_rn_M_0000_N_1110,
	div1_M_0000_N_1110,
	dmulu_M_0000_N_1110,
	cmphi_rm_rn_M_0000_N_1110,
	cmpgt_rm_rn_M_0000_N_1110,
	sub_M_0000_N_1110,
	unimplemented,
	subc_M_0000_N_1110,
	subv_M_0000_N_1110,
	add_rm_rn_M_0000_N_1110,
	dmuls_M_0000_N_1110,
	addc_rm_rn_M_0000_N_1110,
	addv_rm_rn_M_0000_N_1110,
	cmpeq_rm_rn_M_0001_N_1110,
	unimplemented,
	cmphs_rm_rn_M_0001_N_1110,
	cmpge_rm_rn_M_0001_N_1110,
	div1_M_0001_N_1110,
	dmulu_M_0001_N_1110,
	cmphi_rm_rn_M_0001_N_1110,
	cmpgt_rm_rn_M_0001_N_1110,
	sub_M_0001_N_1110,
	unimplemented,
	subc_M_0001_N_1110,
	subv_M_0001_N_1110,
	add_rm_rn_M_0001_N_1110,
	dmuls_M_0001_N_1110,
	addc_rm_rn_M_0001_N_1110,
	addv_rm_rn_M_0001_N_1110,
	cmpeq_rm_rn_M_0010_N_1110,
	unimplemented,
	cmphs_rm_rn_M_0010_N_1110,
	cmpge_rm_rn_M_0010_N_1110,
	div1_M_0010_N_1110,
	dmulu_M_0010_N_1110,
	cmphi_rm_rn_M_0010_N_1110,
	cmpgt_rm_rn_M_0010_N_1110,
	sub_M_0010_N_1110,
	unimplemented,
	subc_M_0010_N_1110,
	subv_M_0010_N_1110,
	add_rm_rn_M_0010_N_1110,
	dmuls_M_0010_N_1110,
	addc_rm_rn_M_0010_N_1110,
	addv_rm_rn_M_0010_N_1110,
	cmpeq_rm_rn_M_0011_N_1110,
	unimplemented,
	cmphs_rm_rn_M_0011_N_1110,
	cmpge_rm_rn_M_0011_N_1110,
	div1_M_0011_N_1110,
	dmulu_M_0011_N_1110,
	cmphi_rm_rn_M_0011_N_1110,
	cmpgt_rm_rn_M_0011_N_1110,
	sub_M_0011_N_1110,
	unimplemented,
	subc_M_0011_N_1110,
	subv_M_0011_N_1110,
	add_rm_rn_M_0011_N_1110,
	dmuls_M_0011_N_1110,
	addc_rm_rn_M_0011_N_1110,
	addv_rm_rn_M_0011_N_1110,
	cmpeq_rm_rn_M_0100_N_1110,
	unimplemented,
	cmphs_rm_rn_M_0100_N_1110,
	cmpge_rm_rn_M_0100_N_1110,
	div1_M_0100_N_1110,
	dmulu_M_0100_N_1110,
	cmphi_rm_rn_M_0100_N_1110,
	cmpgt_rm_rn_M_0100_N_1110,
	sub_M_0100_N_1110,
	unimplemented,
	subc_M_0100_N_1110,
	subv_M_0100_N_1110,
	add_rm_rn_M_0100_N_1110,
	dmuls_M_0100_N_1110,
	addc_rm_rn_M_0100_N_1110,
	addv_rm_rn_M_0100_N_1110,
	cmpeq_rm_rn_M_0101_N_1110,
	unimplemented,
	cmphs_rm_rn_M_0101_N_1110,
	cmpge_rm_rn_M_0101_N_1110,
	div1_M_0101_N_1110,
	dmulu_M_0101_N_1110,
	cmphi_rm_rn_M_0101_N_1110,
	cmpgt_rm_rn_M_0101_N_1110,
	sub_M_0101_N_1110,
	unimplemented,
	subc_M_0101_N_1110,
	subv_M_0101_N_1110,
	add_rm_rn_M_0101_N_1110,
	dmuls_M_0101_N_1110,
	addc_rm_rn_M_0101_N_1110,
	addv_rm_rn_M_0101_N_1110,
	cmpeq_rm_rn_M_0110_N_1110,
	unimplemented,
	cmphs_rm_rn_M_0110_N_1110,
	cmpge_rm_rn_M_0110_N_1110,
	div1_M_0110_N_1110,
	dmulu_M_0110_N_1110,
	cmphi_rm_rn_M_0110_N_1110,
	cmpgt_rm_rn_M_0110_N_1110,
	sub_M_0110_N_1110,
	unimplemented,
	subc_M_0110_N_1110,
	subv_M_0110_N_1110,
	add_rm_rn_M_0110_N_1110,
	dmuls_M_0110_N_1110,
	addc_rm_rn_M_0110_N_1110,
	addv_rm_rn_M_0110_N_1110,
	cmpeq_rm_rn_M_0111_N_1110,
	unimplemented,
	cmphs_rm_rn_M_0111_N_1110,
	cmpge_rm_rn_M_0111_N_1110,
	div1_M_0111_N_1110,
	dmulu_M_0111_N_1110,
	cmphi_rm_rn_M_0111_N_1110,
	cmpgt_rm_rn_M_0111_N_1110,
	sub_M_0111_N_1110,
	unimplemented,
	subc_M_0111_N_1110,
	subv_M_0111_N_1110,
	add_rm_rn_M_0111_N_1110,
	dmuls_M_0111_N_1110,
	addc_rm_rn_M_0111_N_1110,
	addv_rm_rn_M_0111_N_1110,
	cmpeq_rm_rn_M_1000_N_1110,
	unimplemented,
	cmphs_rm_rn_M_1000_N_1110,
	cmpge_rm_rn_M_1000_N_1110,
	div1_M_1000_N_1110,
	dmulu_M_1000_N_1110,
	cmphi_rm_rn_M_1000_N_1110,
	cmpgt_rm_rn_M_1000_N_1110,
	sub_M_1000_N_1110,
	unimplemented,
	subc_M_1000_N_1110,
	subv_M_1000_N_1110,
	add_rm_rn_M_1000_N_1110,
	dmuls_M_1000_N_1110,
	addc_rm_rn_M_1000_N_1110,
	addv_rm_rn_M_1000_N_1110,
	cmpeq_rm_rn_M_1001_N_1110,
	unimplemented,
	cmphs_rm_rn_M_1001_N_1110,
	cmpge_rm_rn_M_1001_N_1110,
	div1_M_1001_N_1110,
	dmulu_M_1001_N_1110,
	cmphi_rm_rn_M_1001_N_1110,
	cmpgt_rm_rn_M_1001_N_1110,
	sub_M_1001_N_1110,
	unimplemented,
	subc_M_1001_N_1110,
	subv_M_1001_N_1110,
	add_rm_rn_M_1001_N_1110,
	dmuls_M_1001_N_1110,
	addc_rm_rn_M_1001_N_1110,
	addv_rm_rn_M_1001_N_1110,
	cmpeq_rm_rn_M_1010_N_1110,
	unimplemented,
	cmphs_rm_rn_M_1010_N_1110,
	cmpge_rm_rn_M_1010_N_1110,
	div1_M_1010_N_1110,
	dmulu_M_1010_N_1110,
	cmphi_rm_rn_M_1010_N_1110,
	cmpgt_rm_rn_M_1010_N_1110,
	sub_M_1010_N_1110,
	unimplemented,
	subc_M_1010_N_1110,
	subv_M_1010_N_1110,
	add_rm_rn_M_1010_N_1110,
	dmuls_M_1010_N_1110,
	addc_rm_rn_M_1010_N_1110,
	addv_rm_rn_M_1010_N_1110,
	cmpeq_rm_rn_M_1011_N_1110,
	unimplemented,
	cmphs_rm_rn_M_1011_N_1110,
	cmpge_rm_rn_M_1011_N_1110,
	div1_M_1011_N_1110,
	dmulu_M_1011_N_1110,
	cmphi_rm_rn_M_1011_N_1110,
	cmpgt_rm_rn_M_1011_N_1110,
	sub_M_1011_N_1110,
	unimplemented,
	subc_M_1011_N_1110,
	subv_M_1011_N_1110,
	add_rm_rn_M_1011_N_1110,
	dmuls_M_1011_N_1110,
	addc_rm_rn_M_1011_N_1110,
	addv_rm_rn_M_1011_N_1110,
	cmpeq_rm_rn_M_1100_N_1110,
	unimplemented,
	cmphs_rm_rn_M_1100_N_1110,
	cmpge_rm_rn_M_1100_N_1110,
	div1_M_1100_N_1110,
	dmulu_M_1100_N_1110,
	cmphi_rm_rn_M_1100_N_1110,
	cmpgt_rm_rn_M_1100_N_1110,
	sub_M_1100_N_1110,
	unimplemented,
	subc_M_1100_N_1110,
	subv_M_1100_N_1110,
	add_rm_rn_M_1100_N_1110,
	dmuls_M_1100_N_1110,
	addc_rm_rn_M_1100_N_1110,
	addv_rm_rn_M_1100_N_1110,
	cmpeq_rm_rn_M_1101_N_1110,
	unimplemented,
	cmphs_rm_rn_M_1101_N_1110,
	cmpge_rm_rn_M_1101_N_1110,
	div1_M_1101_N_1110,
	dmulu_M_1101_N_1110,
	cmphi_rm_rn_M_1101_N_1110,
	cmpgt_rm_rn_M_1101_N_1110,
	sub_M_1101_N_1110,
	unimplemented,
	subc_M_1101_N_1110,
	subv_M_1101_N_1110,
	add_rm_rn_M_1101_N_1110,
	dmuls_M_1101_N_1110,
	addc_rm_rn_M_1101_N_1110,
	addv_rm_rn_M_1101_N_1110,
	cmpeq_rm_rn_M_1110_N_1110,
	unimplemented,
	cmphs_rm_rn_M_1110_N_1110,
	cmpge_rm_rn_M_1110_N_1110,
	div1_M_1110_N_1110,
	dmulu_M_1110_N_1110,
	cmphi_rm_rn_M_1110_N_1110,
	cmpgt_rm_rn_M_1110_N_1110,
	sub_M_1110_N_1110,
	unimplemented,
	subc_M_1110_N_1110,
	subv_M_1110_N_1110,
	add_rm_rn_M_1110_N_1110,
	dmuls_M_1110_N_1110,
	addc_rm_rn_M_1110_N_1110,
	addv_rm_rn_M_1110_N_1110,
	cmpeq_rm_rn_M_1111_N_1110,
	unimplemented,
	cmphs_rm_rn_M_1111_N_1110,
	cmpge_rm_rn_M_1111_N_1110,
	div1_M_1111_N_1110,
	dmulu_M_1111_N_1110,
	cmphi_rm_rn_M_1111_N_1110,
	cmpgt_rm_rn_M_1111_N_1110,
	sub_M_1111_N_1110,
	unimplemented,
	subc_M_1111_N_1110,
	subv_M_1111_N_1110,
	add_rm_rn_M_1111_N_1110,
	dmuls_M_1111_N_1110,
	addc_rm_rn_M_1111_N_1110,
	addv_rm_rn_M_1111_N_1110,
	cmpeq_rm_rn_M_0000_N_1111,
	unimplemented,
	cmphs_rm_rn_M_0000_N_1111,
	cmpge_rm_rn_M_0000_N_1111,
	div1_M_0000_N_1111,
	dmulu_M_0000_N_1111,
	cmphi_rm_rn_M_0000_N_1111,
	cmpgt_rm_rn_M_0000_N_1111,
	sub_M_0000_N_1111,
	unimplemented,
	subc_M_0000_N_1111,
	subv_M_0000_N_1111,
	add_rm_rn_M_0000_N_1111,
	dmuls_M_0000_N_1111,
	addc_rm_rn_M_0000_N_1111,
	addv_rm_rn_M_0000_N_1111,
	cmpeq_rm_rn_M_0001_N_1111,
	unimplemented,
	cmphs_rm_rn_M_0001_N_1111,
	cmpge_rm_rn_M_0001_N_1111,
	div1_M_0001_N_1111,
	dmulu_M_0001_N_1111,
	cmphi_rm_rn_M_0001_N_1111,
	cmpgt_rm_rn_M_0001_N_1111,
	sub_M_0001_N_1111,
	unimplemented,
	subc_M_0001_N_1111,
	subv_M_0001_N_1111,
	add_rm_rn_M_0001_N_1111,
	dmuls_M_0001_N_1111,
	addc_rm_rn_M_0001_N_1111,
	addv_rm_rn_M_0001_N_1111,
	cmpeq_rm_rn_M_0010_N_1111,
	unimplemented,
	cmphs_rm_rn_M_0010_N_1111,
	cmpge_rm_rn_M_0010_N_1111,
	div1_M_0010_N_1111,
	dmulu_M_0010_N_1111,
	cmphi_rm_rn_M_0010_N_1111,
	cmpgt_rm_rn_M_0010_N_1111,
	sub_M_0010_N_1111,
	unimplemented,
	subc_M_0010_N_1111,
	subv_M_0010_N_1111,
	add_rm_rn_M_0010_N_1111,
	dmuls_M_0010_N_1111,
	addc_rm_rn_M_0010_N_1111,
	addv_rm_rn_M_0010_N_1111,
	cmpeq_rm_rn_M_0011_N_1111,
	unimplemented,
	cmphs_rm_rn_M_0011_N_1111,
	cmpge_rm_rn_M_0011_N_1111,
	div1_M_0011_N_1111,
	dmulu_M_0011_N_1111,
	cmphi_rm_rn_M_0011_N_1111,
	cmpgt_rm_rn_M_0011_N_1111,
	sub_M_0011_N_1111,
	unimplemented,
	subc_M_0011_N_1111,
	subv_M_0011_N_1111,
	add_rm_rn_M_0011_N_1111,
	dmuls_M_0011_N_1111,
	addc_rm_rn_M_0011_N_1111,
	addv_rm_rn_M_0011_N_1111,
	cmpeq_rm_rn_M_0100_N_1111,
	unimplemented,
	cmphs_rm_rn_M_0100_N_1111,
	cmpge_rm_rn_M_0100_N_1111,
	div1_M_0100_N_1111,
	dmulu_M_0100_N_1111,
	cmphi_rm_rn_M_0100_N_1111,
	cmpgt_rm_rn_M_0100_N_1111,
	sub_M_0100_N_1111,
	unimplemented,
	subc_M_0100_N_1111,
	subv_M_0100_N_1111,
	add_rm_rn_M_0100_N_1111,
	dmuls_M_0100_N_1111,
	addc_rm_rn_M_0100_N_1111,
	addv_rm_rn_M_0100_N_1111,
	cmpeq_rm_rn_M_0101_N_1111,
	unimplemented,
	cmphs_rm_rn_M_0101_N_1111,
	cmpge_rm_rn_M_0101_N_1111,
	div1_M_0101_N_1111,
	dmulu_M_0101_N_1111,
	cmphi_rm_rn_M_0101_N_1111,
	cmpgt_rm_rn_M_0101_N_1111,
	sub_M_0101_N_1111,
	unimplemented,
	subc_M_0101_N_1111,
	subv_M_0101_N_1111,
	add_rm_rn_M_0101_N_1111,
	dmuls_M_0101_N_1111,
	addc_rm_rn_M_0101_N_1111,
	addv_rm_rn_M_0101_N_1111,
	cmpeq_rm_rn_M_0110_N_1111,
	unimplemented,
	cmphs_rm_rn_M_0110_N_1111,
	cmpge_rm_rn_M_0110_N_1111,
	div1_M_0110_N_1111,
	dmulu_M_0110_N_1111,
	cmphi_rm_rn_M_0110_N_1111,
	cmpgt_rm_rn_M_0110_N_1111,
	sub_M_0110_N_1111,
	unimplemented,
	subc_M_0110_N_1111,
	subv_M_0110_N_1111,
	add_rm_rn_M_0110_N_1111,
	dmuls_M_0110_N_1111,
	addc_rm_rn_M_0110_N_1111,
	addv_rm_rn_M_0110_N_1111,
	cmpeq_rm_rn_M_0111_N_1111,
	unimplemented,
	cmphs_rm_rn_M_0111_N_1111,
	cmpge_rm_rn_M_0111_N_1111,
	div1_M_0111_N_1111,
	dmulu_M_0111_N_1111,
	cmphi_rm_rn_M_0111_N_1111,
	cmpgt_rm_rn_M_0111_N_1111,
	sub_M_0111_N_1111,
	unimplemented,
	subc_M_0111_N_1111,
	subv_M_0111_N_1111,
	add_rm_rn_M_0111_N_1111,
	dmuls_M_0111_N_1111,
	addc_rm_rn_M_0111_N_1111,
	addv_rm_rn_M_0111_N_1111,
	cmpeq_rm_rn_M_1000_N_1111,
	unimplemented,
	cmphs_rm_rn_M_1000_N_1111,
	cmpge_rm_rn_M_1000_N_1111,
	div1_M_1000_N_1111,
	dmulu_M_1000_N_1111,
	cmphi_rm_rn_M_1000_N_1111,
	cmpgt_rm_rn_M_1000_N_1111,
	sub_M_1000_N_1111,
	unimplemented,
	subc_M_1000_N_1111,
	subv_M_1000_N_1111,
	add_rm_rn_M_1000_N_1111,
	dmuls_M_1000_N_1111,
	addc_rm_rn_M_1000_N_1111,
	addv_rm_rn_M_1000_N_1111,
	cmpeq_rm_rn_M_1001_N_1111,
	unimplemented,
	cmphs_rm_rn_M_1001_N_1111,
	cmpge_rm_rn_M_1001_N_1111,
	div1_M_1001_N_1111,
	dmulu_M_1001_N_1111,
	cmphi_rm_rn_M_1001_N_1111,
	cmpgt_rm_rn_M_1001_N_1111,
	sub_M_1001_N_1111,
	unimplemented,
	subc_M_1001_N_1111,
	subv_M_1001_N_1111,
	add_rm_rn_M_1001_N_1111,
	dmuls_M_1001_N_1111,
	addc_rm_rn_M_1001_N_1111,
	addv_rm_rn_M_1001_N_1111,
	cmpeq_rm_rn_M_1010_N_1111,
	unimplemented,
	cmphs_rm_rn_M_1010_N_1111,
	cmpge_rm_rn_M_1010_N_1111,
	div1_M_1010_N_1111,
	dmulu_M_1010_N_1111,
	cmphi_rm_rn_M_1010_N_1111,
	cmpgt_rm_rn_M_1010_N_1111,
	sub_M_1010_N_1111,
	unimplemented,
	subc_M_1010_N_1111,
	subv_M_1010_N_1111,
	add_rm_rn_M_1010_N_1111,
	dmuls_M_1010_N_1111,
	addc_rm_rn_M_1010_N_1111,
	addv_rm_rn_M_1010_N_1111,
	cmpeq_rm_rn_M_1011_N_1111,
	unimplemented,
	cmphs_rm_rn_M_1011_N_1111,
	cmpge_rm_rn_M_1011_N_1111,
	div1_M_1011_N_1111,
	dmulu_M_1011_N_1111,
	cmphi_rm_rn_M_1011_N_1111,
	cmpgt_rm_rn_M_1011_N_1111,
	sub_M_1011_N_1111,
	unimplemented,
	subc_M_1011_N_1111,
	subv_M_1011_N_1111,
	add_rm_rn_M_1011_N_1111,
	dmuls_M_1011_N_1111,
	addc_rm_rn_M_1011_N_1111,
	addv_rm_rn_M_1011_N_1111,
	cmpeq_rm_rn_M_1100_N_1111,
	unimplemented,
	cmphs_rm_rn_M_1100_N_1111,
	cmpge_rm_rn_M_1100_N_1111,
	div1_M_1100_N_1111,
	dmulu_M_1100_N_1111,
	cmphi_rm_rn_M_1100_N_1111,
	cmpgt_rm_rn_M_1100_N_1111,
	sub_M_1100_N_1111,
	unimplemented,
	subc_M_1100_N_1111,
	subv_M_1100_N_1111,
	add_rm_rn_M_1100_N_1111,
	dmuls_M_1100_N_1111,
	addc_rm_rn_M_1100_N_1111,
	addv_rm_rn_M_1100_N_1111,
	cmpeq_rm_rn_M_1101_N_1111,
	unimplemented,
	cmphs_rm_rn_M_1101_N_1111,
	cmpge_rm_rn_M_1101_N_1111,
	div1_M_1101_N_1111,
	dmulu_M_1101_N_1111,
	cmphi_rm_rn_M_1101_N_1111,
	cmpgt_rm_rn_M_1101_N_1111,
	sub_M_1101_N_1111,
	unimplemented,
	subc_M_1101_N_1111,
	subv_M_1101_N_1111,
	add_rm_rn_M_1101_N_1111,
	dmuls_M_1101_N_1111,
	addc_rm_rn_M_1101_N_1111,
	addv_rm_rn_M_1101_N_1111,
	cmpeq_rm_rn_M_1110_N_1111,
	unimplemented,
	cmphs_rm_rn_M_1110_N_1111,
	cmpge_rm_rn_M_1110_N_1111,
	div1_M_1110_N_1111,
	dmulu_M_1110_N_1111,
	cmphi_rm_rn_M_1110_N_1111,
	cmpgt_rm_rn_M_1110_N_1111,
	sub_M_1110_N_1111,
	unimplemented,
	subc_M_1110_N_1111,
	subv_M_1110_N_1111,
	add_rm_rn_M_1110_N_1111,
	dmuls_M_1110_N_1111,
	addc_rm_rn_M_1110_N_1111,
	addv_rm_rn_M_1110_N_1111,
	cmpeq_rm_rn_M_1111_N_1111,
	unimplemented,
	cmphs_rm_rn_M_1111_N_1111,
	cmpge_rm_rn_M_1111_N_1111,
	div1_M_1111_N_1111,
	dmulu_M_1111_N_1111,
	cmphi_rm_rn_M_1111_N_1111,
	cmpgt_rm_rn_M_1111_N_1111,
	sub_M_1111_N_1111,
	unimplemented,
	subc_M_1111_N_1111,
	subv_M_1111_N_1111,
	add_rm_rn_M_1111_N_1111,
	dmuls_M_1111_N_1111,
	addc_rm_rn_M_1111_N_1111,
	addv_rm_rn_M_1111_N_1111,
	shll_N_0000,
	shlr_N_0000,
	sts_mach_rn_predec_N_0000,
	stc_sr_rn_predec_N_0000,
	rotl_N_0000,
	rotr_N_0000,
	lds_rm_postinc_mach_M_0000,
	ldc_rm_postinc_sr_M_0000,
	shll2_N_0000,
	shlr2_N_0000,
	lds_mach_M_0000,
	jsr_M_0000,
	unimplemented,
	unimplemented,
	ldc_rm_sr_M_0000,
	mac_w_M_0000_N_0000,
	dt_N_0000,
	cmppz_rn_N_0000,
	sts_macl_rn_predec_N_0000,
	stc_gbr_rn_predec_N_0000,
	unimplemented,
	cmppl_rn_N_0000,
	lds_rm_postinc_macl_M_0000,
	ldc_rm_postinc_gbr_M_0000,
	shll8_N_0000,
	shlr8_N_0000,
	lds_macl_M_0000,
	tas_N_0000,
	unimplemented,
	unimplemented,
	ldc_rm_gbr_M_0000,
	mac_w_M_0001_N_0000,
	shal_N_0000,
	shar_N_0000,
	sts_pr_rn_predec_N_0000,
	stc_vbr_rn_predec_N_0000,
	rotcl_N_0000,
	rotcr_N_0000,
	lds_rm_postinc_pr_M_0000,
	ldc_rm_postinc_vbr_M_0000,
	shll16_N_0000,
	shlr16_N_0000,
	lds_pr_M_0000,
	jmp_M_0000,
	unimplemented,
	unimplemented,
	ldc_rm_vbr_M_0000,
	mac_w_M_0010_N_0000,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	mac_w_M_0011_N_0000,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	mac_w_M_0100_N_0000,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	mac_w_M_0101_N_0000,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	mac_w_M_0110_N_0000,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	mac_w_M_0111_N_0000,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	mac_w_M_1000_N_0000,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	mac_w_M_1001_N_0000,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	mac_w_M_1010_N_0000,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	mac_w_M_1011_N_0000,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	mac_w_M_1100_N_0000,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	mac_w_M_1101_N_0000,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	mac_w_M_1110_N_0000,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	mac_w_M_1111_N_0000,
	shll_N_0001,
	shlr_N_0001,
	sts_mach_rn_predec_N_0001,
	stc_sr_rn_predec_N_0001,
	rotl_N_0001,
	rotr_N_0001,
	lds_rm_postinc_mach_M_0001,
	ldc_rm_postinc_sr_M_0001,
	shll2_N_0001,
	shlr2_N_0001,
	lds_mach_M_0001,
	jsr_M_0001,
	unimplemented,
	unimplemented,
	ldc_rm_sr_M_0001,
	mac_w_M_0000_N_0001,
	dt_N_0001,
	cmppz_rn_N_0001,
	sts_macl_rn_predec_N_0001,
	stc_gbr_rn_predec_N_0001,
	unimplemented,
	cmppl_rn_N_0001,
	lds_rm_postinc_macl_M_0001,
	ldc_rm_postinc_gbr_M_0001,
	shll8_N_0001,
	shlr8_N_0001,
	lds_macl_M_0001,
	tas_N_0001,
	unimplemented,
	unimplemented,
	ldc_rm_gbr_M_0001,
	mac_w_M_0001_N_0001,
	shal_N_0001,
	shar_N_0001,
	sts_pr_rn_predec_N_0001,
	stc_vbr_rn_predec_N_0001,
	rotcl_N_0001,
	rotcr_N_0001,
	lds_rm_postinc_pr_M_0001,
	ldc_rm_postinc_vbr_M_0001,
	shll16_N_0001,
	shlr16_N_0001,
	lds_pr_M_0001,
	jmp_M_0001,
	unimplemented,
	unimplemented,
	ldc_rm_vbr_M_0001,
	mac_w_M_0010_N_0001,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	mac_w_M_0011_N_0001,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	mac_w_M_0100_N_0001,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	mac_w_M_0101_N_0001,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	mac_w_M_0110_N_0001,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	mac_w_M_0111_N_0001,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	mac_w_M_1000_N_0001,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	mac_w_M_1001_N_0001,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	mac_w_M_1010_N_0001,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	mac_w_M_1011_N_0001,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	mac_w_M_1100_N_0001,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	mac_w_M_1101_N_0001,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	mac_w_M_1110_N_0001,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	mac_w_M_1111_N_0001,
	shll_N_0010,
	shlr_N_0010,
	sts_mach_rn_predec_N_0010,
	stc_sr_rn_predec_N_0010,
	rotl_N_0010,
	rotr_N_0010,
	lds_rm_postinc_mach_M_0010,
	ldc_rm_postinc_sr_M_0010,
	shll2_N_0010,
	shlr2_N_0010,
	lds_mach_M_0010,
	jsr_M_0010,
	unimplemented,
	unimplemented,
	ldc_rm_sr_M_0010,
	mac_w_M_0000_N_0010,
	dt_N_0010,
	cmppz_rn_N_0010,
	sts_macl_rn_predec_N_0010,
	stc_gbr_rn_predec_N_0010,
	unimplemented,
	cmppl_rn_N_0010,
	lds_rm_postinc_macl_M_0010,
	ldc_rm_postinc_gbr_M_0010,
	shll8_N_0010,
	shlr8_N_0010,
	lds_macl_M_0010,
	tas_N_0010,
	unimplemented,
	unimplemented,
	ldc_rm_gbr_M_0010,
	mac_w_M_0001_N_0010,
	shal_N_0010,
	shar_N_0010,
	sts_pr_rn_predec_N_0010,
	stc_vbr_rn_predec_N_0010,
	rotcl_N_0010,
	rotcr_N_0010,
	lds_rm_postinc_pr_M_0010,
	ldc_rm_postinc_vbr_M_0010,
	shll16_N_0010,
	shlr16_N_0010,
	lds_pr_M_0010,
	jmp_M_0010,
	unimplemented,
	unimplemented,
	ldc_rm_vbr_M_0010,
	mac_w_M_0010_N_0010,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	mac_w_M_0011_N_0010,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	mac_w_M_0100_N_0010,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	mac_w_M_0101_N_0010,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	mac_w_M_0110_N_0010,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	mac_w_M_0111_N_0010,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	mac_w_M_1000_N_0010,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	mac_w_M_1001_N_0010,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	mac_w_M_1010_N_0010,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	mac_w_M_1011_N_0010,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	mac_w_M_1100_N_0010,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	mac_w_M_1101_N_0010,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	mac_w_M_1110_N_0010,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	mac_w_M_1111_N_0010,
	shll_N_0011,
	shlr_N_0011,
	sts_mach_rn_predec_N_0011,
	stc_sr_rn_predec_N_0011,
	rotl_N_0011,
	rotr_N_0011,
	lds_rm_postinc_mach_M_0011,
	ldc_rm_postinc_sr_M_0011,
	shll2_N_0011,
	shlr2_N_0011,
	lds_mach_M_0011,
	jsr_M_0011,
	unimplemented,
	unimplemented,
	ldc_rm_sr_M_0011,
	mac_w_M_0000_N_0011,
	dt_N_0011,
	cmppz_rn_N_0011,
	sts_macl_rn_predec_N_0011,
	stc_gbr_rn_predec_N_0011,
	unimplemented,
	cmppl_rn_N_0011,
	lds_rm_postinc_macl_M_0011,
	ldc_rm_postinc_gbr_M_0011,
	shll8_N_0011,
	shlr8_N_0011,
	lds_macl_M_0011,
	tas_N_0011,
	unimplemented,
	unimplemented,
	ldc_rm_gbr_M_0011,
	mac_w_M_0001_N_0011,
	shal_N_0011,
	shar_N_0011,
	sts_pr_rn_predec_N_0011,
	stc_vbr_rn_predec_N_0011,
	rotcl_N_0011,
	rotcr_N_0011,
	lds_rm_postinc_pr_M_0011,
	ldc_rm_postinc_vbr_M_0011,
	shll16_N_0011,
	shlr16_N_0011,
	lds_pr_M_0011,
	jmp_M_0011,
	unimplemented,
	unimplemented,
	ldc_rm_vbr_M_0011,
	mac_w_M_0010_N_0011,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	mac_w_M_0011_N_0011,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	mac_w_M_0100_N_0011,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	mac_w_M_0101_N_0011,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	mac_w_M_0110_N_0011,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	mac_w_M_0111_N_0011,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	mac_w_M_1000_N_0011,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	mac_w_M_1001_N_0011,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	mac_w_M_1010_N_0011,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	mac_w_M_1011_N_0011,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	mac_w_M_1100_N_0011,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	mac_w_M_1101_N_0011,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	mac_w_M_1110_N_0011,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	mac_w_M_1111_N_0011,
	shll_N_0100,
	shlr_N_0100,
	sts_mach_rn_predec_N_0100,
	stc_sr_rn_predec_N_0100,
	rotl_N_0100,
	rotr_N_0100,
	lds_rm_postinc_mach_M_0100,
	ldc_rm_postinc_sr_M_0100,
	shll2_N_0100,
	shlr2_N_0100,
	lds_mach_M_0100,
	jsr_M_0100,
	unimplemented,
	unimplemented,
	ldc_rm_sr_M_0100,
	mac_w_M_0000_N_0100,
	dt_N_0100,
	cmppz_rn_N_0100,
	sts_macl_rn_predec_N_0100,
	stc_gbr_rn_predec_N_0100,
	unimplemented,
	cmppl_rn_N_0100,
	lds_rm_postinc_macl_M_0100,
	ldc_rm_postinc_gbr_M_0100,
	shll8_N_0100,
	shlr8_N_0100,
	lds_macl_M_0100,
	tas_N_0100,
	unimplemented,
	unimplemented,
	ldc_rm_gbr_M_0100,
	mac_w_M_0001_N_0100,
	shal_N_0100,
	shar_N_0100,
	sts_pr_rn_predec_N_0100,
	stc_vbr_rn_predec_N_0100,
	rotcl_N_0100,
	rotcr_N_0100,
	lds_rm_postinc_pr_M_0100,
	ldc_rm_postinc_vbr_M_0100,
	shll16_N_0100,
	shlr16_N_0100,
	lds_pr_M_0100,
	jmp_M_0100,
	unimplemented,
	unimplemented,
	ldc_rm_vbr_M_0100,
	mac_w_M_0010_N_0100,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	mac_w_M_0011_N_0100,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	mac_w_M_0100_N_0100,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	mac_w_M_0101_N_0100,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	mac_w_M_0110_N_0100,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	mac_w_M_0111_N_0100,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	mac_w_M_1000_N_0100,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	mac_w_M_1001_N_0100,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	mac_w_M_1010_N_0100,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	mac_w_M_1011_N_0100,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	mac_w_M_1100_N_0100,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	mac_w_M_1101_N_0100,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	mac_w_M_1110_N_0100,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	mac_w_M_1111_N_0100,
	shll_N_0101,
	shlr_N_0101,
	sts_mach_rn_predec_N_0101,
	stc_sr_rn_predec_N_0101,
	rotl_N_0101,
	rotr_N_0101,
	lds_rm_postinc_mach_M_0101,
	ldc_rm_postinc_sr_M_0101,
	shll2_N_0101,
	shlr2_N_0101,
	lds_mach_M_0101,
	jsr_M_0101,
	unimplemented,
	unimplemented,
	ldc_rm_sr_M_0101,
	mac_w_M_0000_N_0101,
	dt_N_0101,
	cmppz_rn_N_0101,
	sts_macl_rn_predec_N_0101,
	stc_gbr_rn_predec_N_0101,
	unimplemented,
	cmppl_rn_N_0101,
	lds_rm_postinc_macl_M_0101,
	ldc_rm_postinc_gbr_M_0101,
	shll8_N_0101,
	shlr8_N_0101,
	lds_macl_M_0101,
	tas_N_0101,
	unimplemented,
	unimplemented,
	ldc_rm_gbr_M_0101,
	mac_w_M_0001_N_0101,
	shal_N_0101,
	shar_N_0101,
	sts_pr_rn_predec_N_0101,
	stc_vbr_rn_predec_N_0101,
	rotcl_N_0101,
	rotcr_N_0101,
	lds_rm_postinc_pr_M_0101,
	ldc_rm_postinc_vbr_M_0101,
	shll16_N_0101,
	shlr16_N_0101,
	lds_pr_M_0101,
	jmp_M_0101,
	unimplemented,
	unimplemented,
	ldc_rm_vbr_M_0101,
	mac_w_M_0010_N_0101,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	mac_w_M_0011_N_0101,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	mac_w_M_0100_N_0101,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	mac_w_M_0101_N_0101,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	mac_w_M_0110_N_0101,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	mac_w_M_0111_N_0101,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	mac_w_M_1000_N_0101,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	mac_w_M_1001_N_0101,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	mac_w_M_1010_N_0101,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	mac_w_M_1011_N_0101,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	mac_w_M_1100_N_0101,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	mac_w_M_1101_N_0101,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	mac_w_M_1110_N_0101,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	mac_w_M_1111_N_0101,
	shll_N_0110,
	shlr_N_0110,
	sts_mach_rn_predec_N_0110,
	stc_sr_rn_predec_N_0110,
	rotl_N_0110,
	rotr_N_0110,
	lds_rm_postinc_mach_M_0110,
	ldc_rm_postinc_sr_M_0110,
	shll2_N_0110,
	shlr2_N_0110,
	lds_mach_M_0110,
	jsr_M_0110,
	unimplemented,
	unimplemented,
	ldc_rm_sr_M_0110,
	mac_w_M_0000_N_0110,
	dt_N_0110,
	cmppz_rn_N_0110,
	sts_macl_rn_predec_N_0110,
	stc_gbr_rn_predec_N_0110,
	unimplemented,
	cmppl_rn_N_0110,
	lds_rm_postinc_macl_M_0110,
	ldc_rm_postinc_gbr_M_0110,
	shll8_N_0110,
	shlr8_N_0110,
	lds_macl_M_0110,
	tas_N_0110,
	unimplemented,
	unimplemented,
	ldc_rm_gbr_M_0110,
	mac_w_M_0001_N_0110,
	shal_N_0110,
	shar_N_0110,
	sts_pr_rn_predec_N_0110,
	stc_vbr_rn_predec_N_0110,
	rotcl_N_0110,
	rotcr_N_0110,
	lds_rm_postinc_pr_M_0110,
	ldc_rm_postinc_vbr_M_0110,
	shll16_N_0110,
	shlr16_N_0110,
	lds_pr_M_0110,
	jmp_M_0110,
	unimplemented,
	unimplemented,
	ldc_rm_vbr_M_0110,
	mac_w_M_0010_N_0110,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	mac_w_M_0011_N_0110,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	mac_w_M_0100_N_0110,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	mac_w_M_0101_N_0110,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	mac_w_M_0110_N_0110,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	mac_w_M_0111_N_0110,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	mac_w_M_1000_N_0110,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	mac_w_M_1001_N_0110,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	mac_w_M_1010_N_0110,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	mac_w_M_1011_N_0110,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	mac_w_M_1100_N_0110,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	mac_w_M_1101_N_0110,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	mac_w_M_1110_N_0110,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	mac_w_M_1111_N_0110,
	shll_N_0111,
	shlr_N_0111,
	sts_mach_rn_predec_N_0111,
	stc_sr_rn_predec_N_0111,
	rotl_N_0111,
	rotr_N_0111,
	lds_rm_postinc_mach_M_0111,
	ldc_rm_postinc_sr_M_0111,
	shll2_N_0111,
	shlr2_N_0111,
	lds_mach_M_0111,
	jsr_M_0111,
	unimplemented,
	unimplemented,
	ldc_rm_sr_M_0111,
	mac_w_M_0000_N_0111,
	dt_N_0111,
	cmppz_rn_N_0111,
	sts_macl_rn_predec_N_0111,
	stc_gbr_rn_predec_N_0111,
	unimplemented,
	cmppl_rn_N_0111,
	lds_rm_postinc_macl_M_0111,
	ldc_rm_postinc_gbr_M_0111,
	shll8_N_0111,
	shlr8_N_0111,
	lds_macl_M_0111,
	tas_N_0111,
	unimplemented,
	unimplemented,
	ldc_rm_gbr_M_0111,
	mac_w_M_0001_N_0111,
	shal_N_0111,
	shar_N_0111,
	sts_pr_rn_predec_N_0111,
	stc_vbr_rn_predec_N_0111,
	rotcl_N_0111,
	rotcr_N_0111,
	lds_rm_postinc_pr_M_0111,
	ldc_rm_postinc_vbr_M_0111,
	shll16_N_0111,
	shlr16_N_0111,
	lds_pr_M_0111,
	jmp_M_0111,
	unimplemented,
	unimplemented,
	ldc_rm_vbr_M_0111,
	mac_w_M_0010_N_0111,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	mac_w_M_0011_N_0111,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	mac_w_M_0100_N_0111,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	mac_w_M_0101_N_0111,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	mac_w_M_0110_N_0111,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	mac_w_M_0111_N_0111,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	mac_w_M_1000_N_0111,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	mac_w_M_1001_N_0111,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	mac_w_M_1010_N_0111,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	mac_w_M_1011_N_0111,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	mac_w_M_1100_N_0111,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	mac_w_M_1101_N_0111,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	mac_w_M_1110_N_0111,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	mac_w_M_1111_N_0111,
	shll_N_1000,
	shlr_N_1000,
	sts_mach_rn_predec_N_1000,
	stc_sr_rn_predec_N_1000,
	rotl_N_1000,
	rotr_N_1000,
	lds_rm_postinc_mach_M_1000,
	ldc_rm_postinc_sr_M_1000,
	shll2_N_1000,
	shlr2_N_1000,
	lds_mach_M_1000,
	jsr_M_1000,
	unimplemented,
	unimplemented,
	ldc_rm_sr_M_1000,
	mac_w_M_0000_N_1000,
	dt_N_1000,
	cmppz_rn_N_1000,
	sts_macl_rn_predec_N_1000,
	stc_gbr_rn_predec_N_1000,
	unimplemented,
	cmppl_rn_N_1000,
	lds_rm_postinc_macl_M_1000,
	ldc_rm_postinc_gbr_M_1000,
	shll8_N_1000,
	shlr8_N_1000,
	lds_macl_M_1000,
	tas_N_1000,
	unimplemented,
	unimplemented,
	ldc_rm_gbr_M_1000,
	mac_w_M_0001_N_1000,
	shal_N_1000,
	shar_N_1000,
	sts_pr_rn_predec_N_1000,
	stc_vbr_rn_predec_N_1000,
	rotcl_N_1000,
	rotcr_N_1000,
	lds_rm_postinc_pr_M_1000,
	ldc_rm_postinc_vbr_M_1000,
	shll16_N_1000,
	shlr16_N_1000,
	lds_pr_M_1000,
	jmp_M_1000,
	unimplemented,
	unimplemented,
	ldc_rm_vbr_M_1000,
	mac_w_M_0010_N_1000,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	mac_w_M_0011_N_1000,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	mac_w_M_0100_N_1000,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	mac_w_M_0101_N_1000,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	mac_w_M_0110_N_1000,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	mac_w_M_0111_N_1000,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	mac_w_M_1000_N_1000,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	mac_w_M_1001_N_1000,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	mac_w_M_1010_N_1000,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	mac_w_M_1011_N_1000,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	mac_w_M_1100_N_1000,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	mac_w_M_1101_N_1000,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	mac_w_M_1110_N_1000,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	mac_w_M_1111_N_1000,
	shll_N_1001,
	shlr_N_1001,
	sts_mach_rn_predec_N_1001,
	stc_sr_rn_predec_N_1001,
	rotl_N_1001,
	rotr_N_1001,
	lds_rm_postinc_mach_M_1001,
	ldc_rm_postinc_sr_M_1001,
	shll2_N_1001,
	shlr2_N_1001,
	lds_mach_M_1001,
	jsr_M_1001,
	unimplemented,
	unimplemented,
	ldc_rm_sr_M_1001,
	mac_w_M_0000_N_1001,
	dt_N_1001,
	cmppz_rn_N_1001,
	sts_macl_rn_predec_N_1001,
	stc_gbr_rn_predec_N_1001,
	unimplemented,
	cmppl_rn_N_1001,
	lds_rm_postinc_macl_M_1001,
	ldc_rm_postinc_gbr_M_1001,
	shll8_N_1001,
	shlr8_N_1001,
	lds_macl_M_1001,
	tas_N_1001,
	unimplemented,
	unimplemented,
	ldc_rm_gbr_M_1001,
	mac_w_M_0001_N_1001,
	shal_N_1001,
	shar_N_1001,
	sts_pr_rn_predec_N_1001,
	stc_vbr_rn_predec_N_1001,
	rotcl_N_1001,
	rotcr_N_1001,
	lds_rm_postinc_pr_M_1001,
	ldc_rm_postinc_vbr_M_1001,
	shll16_N_1001,
	shlr16_N_1001,
	lds_pr_M_1001,
	jmp_M_1001,
	unimplemented,
	unimplemented,
	ldc_rm_vbr_M_1001,
	mac_w_M_0010_N_1001,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	mac_w_M_0011_N_1001,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	mac_w_M_0100_N_1001,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	mac_w_M_0101_N_1001,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	mac_w_M_0110_N_1001,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	mac_w_M_0111_N_1001,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	mac_w_M_1000_N_1001,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	mac_w_M_1001_N_1001,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	mac_w_M_1010_N_1001,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	mac_w_M_1011_N_1001,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	mac_w_M_1100_N_1001,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	mac_w_M_1101_N_1001,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	mac_w_M_1110_N_1001,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	mac_w_M_1111_N_1001,
	shll_N_1010,
	shlr_N_1010,
	sts_mach_rn_predec_N_1010,
	stc_sr_rn_predec_N_1010,
	rotl_N_1010,
	rotr_N_1010,
	lds_rm_postinc_mach_M_1010,
	ldc_rm_postinc_sr_M_1010,
	shll2_N_1010,
	shlr2_N_1010,
	lds_mach_M_1010,
	jsr_M_1010,
	unimplemented,
	unimplemented,
	ldc_rm_sr_M_1010,
	mac_w_M_0000_N_1010,
	dt_N_1010,
	cmppz_rn_N_1010,
	sts_macl_rn_predec_N_1010,
	stc_gbr_rn_predec_N_1010,
	unimplemented,
	cmppl_rn_N_1010,
	lds_rm_postinc_macl_M_1010,
	ldc_rm_postinc_gbr_M_1010,
	shll8_N_1010,
	shlr8_N_1010,
	lds_macl_M_1010,
	tas_N_1010,
	unimplemented,
	unimplemented,
	ldc_rm_gbr_M_1010,
	mac_w_M_0001_N_1010,
	shal_N_1010,
	shar_N_1010,
	sts_pr_rn_predec_N_1010,
	stc_vbr_rn_predec_N_1010,
	rotcl_N_1010,
	rotcr_N_1010,
	lds_rm_postinc_pr_M_1010,
	ldc_rm_postinc_vbr_M_1010,
	shll16_N_1010,
	shlr16_N_1010,
	lds_pr_M_1010,
	jmp_M_1010,
	unimplemented,
	unimplemented,
	ldc_rm_vbr_M_1010,
	mac_w_M_0010_N_1010,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	mac_w_M_0011_N_1010,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	mac_w_M_0100_N_1010,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	mac_w_M_0101_N_1010,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	mac_w_M_0110_N_1010,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	mac_w_M_0111_N_1010,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	mac_w_M_1000_N_1010,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	mac_w_M_1001_N_1010,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	mac_w_M_1010_N_1010,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	mac_w_M_1011_N_1010,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	mac_w_M_1100_N_1010,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	mac_w_M_1101_N_1010,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	mac_w_M_1110_N_1010,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	mac_w_M_1111_N_1010,
	shll_N_1011,
	shlr_N_1011,
	sts_mach_rn_predec_N_1011,
	stc_sr_rn_predec_N_1011,
	rotl_N_1011,
	rotr_N_1011,
	lds_rm_postinc_mach_M_1011,
	ldc_rm_postinc_sr_M_1011,
	shll2_N_1011,
	shlr2_N_1011,
	lds_mach_M_1011,
	jsr_M_1011,
	unimplemented,
	unimplemented,
	ldc_rm_sr_M_1011,
	mac_w_M_0000_N_1011,
	dt_N_1011,
	cmppz_rn_N_1011,
	sts_macl_rn_predec_N_1011,
	stc_gbr_rn_predec_N_1011,
	unimplemented,
	cmppl_rn_N_1011,
	lds_rm_postinc_macl_M_1011,
	ldc_rm_postinc_gbr_M_1011,
	shll8_N_1011,
	shlr8_N_1011,
	lds_macl_M_1011,
	tas_N_1011,
	unimplemented,
	unimplemented,
	ldc_rm_gbr_M_1011,
	mac_w_M_0001_N_1011,
	shal_N_1011,
	shar_N_1011,
	sts_pr_rn_predec_N_1011,
	stc_vbr_rn_predec_N_1011,
	rotcl_N_1011,
	rotcr_N_1011,
	lds_rm_postinc_pr_M_1011,
	ldc_rm_postinc_vbr_M_1011,
	shll16_N_1011,
	shlr16_N_1011,
	lds_pr_M_1011,
	jmp_M_1011,
	unimplemented,
	unimplemented,
	ldc_rm_vbr_M_1011,
	mac_w_M_0010_N_1011,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	mac_w_M_0011_N_1011,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	mac_w_M_0100_N_1011,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	mac_w_M_0101_N_1011,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	mac_w_M_0110_N_1011,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	mac_w_M_0111_N_1011,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	mac_w_M_1000_N_1011,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	mac_w_M_1001_N_1011,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	mac_w_M_1010_N_1011,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	mac_w_M_1011_N_1011,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	mac_w_M_1100_N_1011,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	mac_w_M_1101_N_1011,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	mac_w_M_1110_N_1011,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	mac_w_M_1111_N_1011,
	shll_N_1100,
	shlr_N_1100,
	sts_mach_rn_predec_N_1100,
	stc_sr_rn_predec_N_1100,
	rotl_N_1100,
	rotr_N_1100,
	lds_rm_postinc_mach_M_1100,
	ldc_rm_postinc_sr_M_1100,
	shll2_N_1100,
	shlr2_N_1100,
	lds_mach_M_1100,
	jsr_M_1100,
	unimplemented,
	unimplemented,
	ldc_rm_sr_M_1100,
	mac_w_M_0000_N_1100,
	dt_N_1100,
	cmppz_rn_N_1100,
	sts_macl_rn_predec_N_1100,
	stc_gbr_rn_predec_N_1100,
	unimplemented,
	cmppl_rn_N_1100,
	lds_rm_postinc_macl_M_1100,
	ldc_rm_postinc_gbr_M_1100,
	shll8_N_1100,
	shlr8_N_1100,
	lds_macl_M_1100,
	tas_N_1100,
	unimplemented,
	unimplemented,
	ldc_rm_gbr_M_1100,
	mac_w_M_0001_N_1100,
	shal_N_1100,
	shar_N_1100,
	sts_pr_rn_predec_N_1100,
	stc_vbr_rn_predec_N_1100,
	rotcl_N_1100,
	rotcr_N_1100,
	lds_rm_postinc_pr_M_1100,
	ldc_rm_postinc_vbr_M_1100,
	shll16_N_1100,
	shlr16_N_1100,
	lds_pr_M_1100,
	jmp_M_1100,
	unimplemented,
	unimplemented,
	ldc_rm_vbr_M_1100,
	mac_w_M_0010_N_1100,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	mac_w_M_0011_N_1100,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	mac_w_M_0100_N_1100,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	mac_w_M_0101_N_1100,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	mac_w_M_0110_N_1100,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	mac_w_M_0111_N_1100,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	mac_w_M_1000_N_1100,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	mac_w_M_1001_N_1100,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	mac_w_M_1010_N_1100,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	mac_w_M_1011_N_1100,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	mac_w_M_1100_N_1100,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	mac_w_M_1101_N_1100,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	mac_w_M_1110_N_1100,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	mac_w_M_1111_N_1100,
	shll_N_1101,
	shlr_N_1101,
	sts_mach_rn_predec_N_1101,
	stc_sr_rn_predec_N_1101,
	rotl_N_1101,
	rotr_N_1101,
	lds_rm_postinc_mach_M_1101,
	ldc_rm_postinc_sr_M_1101,
	shll2_N_1101,
	shlr2_N_1101,
	lds_mach_M_1101,
	jsr_M_1101,
	unimplemented,
	unimplemented,
	ldc_rm_sr_M_1101,
	mac_w_M_0000_N_1101,
	dt_N_1101,
	cmppz_rn_N_1101,
	sts_macl_rn_predec_N_1101,
	stc_gbr_rn_predec_N_1101,
	unimplemented,
	cmppl_rn_N_1101,
	lds_rm_postinc_macl_M_1101,
	ldc_rm_postinc_gbr_M_1101,
	shll8_N_1101,
	shlr8_N_1101,
	lds_macl_M_1101,
	tas_N_1101,
	unimplemented,
	unimplemented,
	ldc_rm_gbr_M_1101,
	mac_w_M_0001_N_1101,
	shal_N_1101,
	shar_N_1101,
	sts_pr_rn_predec_N_1101,
	stc_vbr_rn_predec_N_1101,
	rotcl_N_1101,
	rotcr_N_1101,
	lds_rm_postinc_pr_M_1101,
	ldc_rm_postinc_vbr_M_1101,
	shll16_N_1101,
	shlr16_N_1101,
	lds_pr_M_1101,
	jmp_M_1101,
	unimplemented,
	unimplemented,
	ldc_rm_vbr_M_1101,
	mac_w_M_0010_N_1101,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	mac_w_M_0011_N_1101,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	mac_w_M_0100_N_1101,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	mac_w_M_0101_N_1101,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	mac_w_M_0110_N_1101,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	mac_w_M_0111_N_1101,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	mac_w_M_1000_N_1101,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	mac_w_M_1001_N_1101,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	mac_w_M_1010_N_1101,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	mac_w_M_1011_N_1101,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	mac_w_M_1100_N_1101,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	mac_w_M_1101_N_1101,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	mac_w_M_1110_N_1101,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	mac_w_M_1111_N_1101,
	shll_N_1110,
	shlr_N_1110,
	sts_mach_rn_predec_N_1110,
	stc_sr_rn_predec_N_1110,
	rotl_N_1110,
	rotr_N_1110,
	lds_rm_postinc_mach_M_1110,
	ldc_rm_postinc_sr_M_1110,
	shll2_N_1110,
	shlr2_N_1110,
	lds_mach_M_1110,
	jsr_M_1110,
	unimplemented,
	unimplemented,
	ldc_rm_sr_M_1110,
	mac_w_M_0000_N_1110,
	dt_N_1110,
	cmppz_rn_N_1110,
	sts_macl_rn_predec_N_1110,
	stc_gbr_rn_predec_N_1110,
	unimplemented,
	cmppl_rn_N_1110,
	lds_rm_postinc_macl_M_1110,
	ldc_rm_postinc_gbr_M_1110,
	shll8_N_1110,
	shlr8_N_1110,
	lds_macl_M_1110,
	tas_N_1110,
	unimplemented,
	unimplemented,
	ldc_rm_gbr_M_1110,
	mac_w_M_0001_N_1110,
	shal_N_1110,
	shar_N_1110,
	sts_pr_rn_predec_N_1110,
	stc_vbr_rn_predec_N_1110,
	rotcl_N_1110,
	rotcr_N_1110,
	lds_rm_postinc_pr_M_1110,
	ldc_rm_postinc_vbr_M_1110,
	shll16_N_1110,
	shlr16_N_1110,
	lds_pr_M_1110,
	jmp_M_1110,
	unimplemented,
	unimplemented,
	ldc_rm_vbr_M_1110,
	mac_w_M_0010_N_1110,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	mac_w_M_0011_N_1110,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	mac_w_M_0100_N_1110,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	mac_w_M_0101_N_1110,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	mac_w_M_0110_N_1110,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	mac_w_M_0111_N_1110,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	mac_w_M_1000_N_1110,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	mac_w_M_1001_N_1110,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	mac_w_M_1010_N_1110,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	mac_w_M_1011_N_1110,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	mac_w_M_1100_N_1110,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	mac_w_M_1101_N_1110,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	mac_w_M_1110_N_1110,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	mac_w_M_1111_N_1110,
	shll_N_1111,
	shlr_N_1111,
	sts_mach_rn_predec_N_1111,
	stc_sr_rn_predec_N_1111,
	rotl_N_1111,
	rotr_N_1111,
	lds_rm_postinc_mach_M_1111,
	ldc_rm_postinc_sr_M_1111,
	shll2_N_1111,
	shlr2_N_1111,
	lds_mach_M_1111,
	jsr_M_1111,
	unimplemented,
	unimplemented,
	ldc_rm_sr_M_1111,
	mac_w_M_0000_N_1111,
	dt_N_1111,
	cmppz_rn_N_1111,
	sts_macl_rn_predec_N_1111,
	stc_gbr_rn_predec_N_1111,
	unimplemented,
	cmppl_rn_N_1111,
	lds_rm_postinc_macl_M_1111,
	ldc_rm_postinc_gbr_M_1111,
	shll8_N_1111,
	shlr8_N_1111,
	lds_macl_M_1111,
	tas_N_1111,
	unimplemented,
	unimplemented,
	ldc_rm_gbr_M_1111,
	mac_w_M_0001_N_1111,
	shal_N_1111,
	shar_N_1111,
	sts_pr_rn_predec_N_1111,
	stc_vbr_rn_predec_N_1111,
	rotcl_N_1111,
	rotcr_N_1111,
	lds_rm_postinc_pr_M_1111,
	ldc_rm_postinc_vbr_M_1111,
	shll16_N_1111,
	shlr16_N_1111,
	lds_pr_M_1111,
	jmp_M_1111,
	unimplemented,
	unimplemented,
	ldc_rm_vbr_M_1111,
	mac_w_M_0010_N_1111,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	mac_w_M_0011_N_1111,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	mac_w_M_0100_N_1111,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	mac_w_M_0101_N_1111,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	mac_w_M_0110_N_1111,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	mac_w_M_0111_N_1111,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	mac_w_M_1000_N_1111,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	mac_w_M_1001_N_1111,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	mac_w_M_1010_N_1111,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	mac_w_M_1011_N_1111,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	mac_w_M_1100_N_1111,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	mac_w_M_1101_N_1111,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	mac_w_M_1110_N_1111,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	mac_w_M_1111_N_1111,
	load_disp_rm_rn_l_D_0000_M_0000_N_0000,
	load_disp_rm_rn_l_D_0001_M_0000_N_0000,
	load_disp_rm_rn_l_D_0010_M_0000_N_0000,
	load_disp_rm_rn_l_D_0011_M_0000_N_0000,
	load_disp_rm_rn_l_D_0100_M_0000_N_0000,
	load_disp_rm_rn_l_D_0101_M_0000_N_0000,
	load_disp_rm_rn_l_D_0110_M_0000_N_0000,
	load_disp_rm_rn_l_D_0111_M_0000_N_0000,
	load_disp_rm_rn_l_D_1000_M_0000_N_0000,
	load_disp_rm_rn_l_D_1001_M_0000_N_0000,
	load_disp_rm_rn_l_D_1010_M_0000_N_0000,
	load_disp_rm_rn_l_D_1011_M_0000_N_0000,
	load_disp_rm_rn_l_D_1100_M_0000_N_0000,
	load_disp_rm_rn_l_D_1101_M_0000_N_0000,
	load_disp_rm_rn_l_D_1110_M_0000_N_0000,
	load_disp_rm_rn_l_D_1111_M_0000_N_0000,
	load_disp_rm_rn_l_D_0000_M_0001_N_0000,
	load_disp_rm_rn_l_D_0001_M_0001_N_0000,
	load_disp_rm_rn_l_D_0010_M_0001_N_0000,
	load_disp_rm_rn_l_D_0011_M_0001_N_0000,
	load_disp_rm_rn_l_D_0100_M_0001_N_0000,
	load_disp_rm_rn_l_D_0101_M_0001_N_0000,
	load_disp_rm_rn_l_D_0110_M_0001_N_0000,
	load_disp_rm_rn_l_D_0111_M_0001_N_0000,
	load_disp_rm_rn_l_D_1000_M_0001_N_0000,
	load_disp_rm_rn_l_D_1001_M_0001_N_0000,
	load_disp_rm_rn_l_D_1010_M_0001_N_0000,
	load_disp_rm_rn_l_D_1011_M_0001_N_0000,
	load_disp_rm_rn_l_D_1100_M_0001_N_0000,
	load_disp_rm_rn_l_D_1101_M_0001_N_0000,
	load_disp_rm_rn_l_D_1110_M_0001_N_0000,
	load_disp_rm_rn_l_D_1111_M_0001_N_0000,
	load_disp_rm_rn_l_D_0000_M_0010_N_0000,
	load_disp_rm_rn_l_D_0001_M_0010_N_0000,
	load_disp_rm_rn_l_D_0010_M_0010_N_0000,
	load_disp_rm_rn_l_D_0011_M_0010_N_0000,
	load_disp_rm_rn_l_D_0100_M_0010_N_0000,
	load_disp_rm_rn_l_D_0101_M_0010_N_0000,
	load_disp_rm_rn_l_D_0110_M_0010_N_0000,
	load_disp_rm_rn_l_D_0111_M_0010_N_0000,
	load_disp_rm_rn_l_D_1000_M_0010_N_0000,
	load_disp_rm_rn_l_D_1001_M_0010_N_0000,
	load_disp_rm_rn_l_D_1010_M_0010_N_0000,
	load_disp_rm_rn_l_D_1011_M_0010_N_0000,
	load_disp_rm_rn_l_D_1100_M_0010_N_0000,
	load_disp_rm_rn_l_D_1101_M_0010_N_0000,
	load_disp_rm_rn_l_D_1110_M_0010_N_0000,
	load_disp_rm_rn_l_D_1111_M_0010_N_0000,
	load_disp_rm_rn_l_D_0000_M_0011_N_0000,
	load_disp_rm_rn_l_D_0001_M_0011_N_0000,
	load_disp_rm_rn_l_D_0010_M_0011_N_0000,
	load_disp_rm_rn_l_D_0011_M_0011_N_0000,
	load_disp_rm_rn_l_D_0100_M_0011_N_0000,
	load_disp_rm_rn_l_D_0101_M_0011_N_0000,
	load_disp_rm_rn_l_D_0110_M_0011_N_0000,
	load_disp_rm_rn_l_D_0111_M_0011_N_0000,
	load_disp_rm_rn_l_D_1000_M_0011_N_0000,
	load_disp_rm_rn_l_D_1001_M_0011_N_0000,
	load_disp_rm_rn_l_D_1010_M_0011_N_0000,
	load_disp_rm_rn_l_D_1011_M_0011_N_0000,
	load_disp_rm_rn_l_D_1100_M_0011_N_0000,
	load_disp_rm_rn_l_D_1101_M_0011_N_0000,
	load_disp_rm_rn_l_D_1110_M_0011_N_0000,
	load_disp_rm_rn_l_D_1111_M_0011_N_0000,
	load_disp_rm_rn_l_D_0000_M_0100_N_0000,
	load_disp_rm_rn_l_D_0001_M_0100_N_0000,
	load_disp_rm_rn_l_D_0010_M_0100_N_0000,
	load_disp_rm_rn_l_D_0011_M_0100_N_0000,
	load_disp_rm_rn_l_D_0100_M_0100_N_0000,
	load_disp_rm_rn_l_D_0101_M_0100_N_0000,
	load_disp_rm_rn_l_D_0110_M_0100_N_0000,
	load_disp_rm_rn_l_D_0111_M_0100_N_0000,
	load_disp_rm_rn_l_D_1000_M_0100_N_0000,
	load_disp_rm_rn_l_D_1001_M_0100_N_0000,
	load_disp_rm_rn_l_D_1010_M_0100_N_0000,
	load_disp_rm_rn_l_D_1011_M_0100_N_0000,
	load_disp_rm_rn_l_D_1100_M_0100_N_0000,
	load_disp_rm_rn_l_D_1101_M_0100_N_0000,
	load_disp_rm_rn_l_D_1110_M_0100_N_0000,
	load_disp_rm_rn_l_D_1111_M_0100_N_0000,
	load_disp_rm_rn_l_D_0000_M_0101_N_0000,
	load_disp_rm_rn_l_D_0001_M_0101_N_0000,
	load_disp_rm_rn_l_D_0010_M_0101_N_0000,
	load_disp_rm_rn_l_D_0011_M_0101_N_0000,
	load_disp_rm_rn_l_D_0100_M_0101_N_0000,
	load_disp_rm_rn_l_D_0101_M_0101_N_0000,
	load_disp_rm_rn_l_D_0110_M_0101_N_0000,
	load_disp_rm_rn_l_D_0111_M_0101_N_0000,
	load_disp_rm_rn_l_D_1000_M_0101_N_0000,
	load_disp_rm_rn_l_D_1001_M_0101_N_0000,
	load_disp_rm_rn_l_D_1010_M_0101_N_0000,
	load_disp_rm_rn_l_D_1011_M_0101_N_0000,
	load_disp_rm_rn_l_D_1100_M_0101_N_0000,
	load_disp_rm_rn_l_D_1101_M_0101_N_0000,
	load_disp_rm_rn_l_D_1110_M_0101_N_0000,
	load_disp_rm_rn_l_D_1111_M_0101_N_0000,
	load_disp_rm_rn_l_D_0000_M_0110_N_0000,
	load_disp_rm_rn_l_D_0001_M_0110_N_0000,
	load_disp_rm_rn_l_D_0010_M_0110_N_0000,
	load_disp_rm_rn_l_D_0011_M_0110_N_0000,
	load_disp_rm_rn_l_D_0100_M_0110_N_0000,
	load_disp_rm_rn_l_D_0101_M_0110_N_0000,
	load_disp_rm_rn_l_D_0110_M_0110_N_0000,
	load_disp_rm_rn_l_D_0111_M_0110_N_0000,
	load_disp_rm_rn_l_D_1000_M_0110_N_0000,
	load_disp_rm_rn_l_D_1001_M_0110_N_0000,
	load_disp_rm_rn_l_D_1010_M_0110_N_0000,
	load_disp_rm_rn_l_D_1011_M_0110_N_0000,
	load_disp_rm_rn_l_D_1100_M_0110_N_0000,
	load_disp_rm_rn_l_D_1101_M_0110_N_0000,
	load_disp_rm_rn_l_D_1110_M_0110_N_0000,
	load_disp_rm_rn_l_D_1111_M_0110_N_0000,
	load_disp_rm_rn_l_D_0000_M_0111_N_0000,
	load_disp_rm_rn_l_D_0001_M_0111_N_0000,
	load_disp_rm_rn_l_D_0010_M_0111_N_0000,
	load_disp_rm_rn_l_D_0011_M_0111_N_0000,
	load_disp_rm_rn_l_D_0100_M_0111_N_0000,
	load_disp_rm_rn_l_D_0101_M_0111_N_0000,
	load_disp_rm_rn_l_D_0110_M_0111_N_0000,
	load_disp_rm_rn_l_D_0111_M_0111_N_0000,
	load_disp_rm_rn_l_D_1000_M_0111_N_0000,
	load_disp_rm_rn_l_D_1001_M_0111_N_0000,
	load_disp_rm_rn_l_D_1010_M_0111_N_0000,
	load_disp_rm_rn_l_D_1011_M_0111_N_0000,
	load_disp_rm_rn_l_D_1100_M_0111_N_0000,
	load_disp_rm_rn_l_D_1101_M_0111_N_0000,
	load_disp_rm_rn_l_D_1110_M_0111_N_0000,
	load_disp_rm_rn_l_D_1111_M_0111_N_0000,
	load_disp_rm_rn_l_D_0000_M_1000_N_0000,
	load_disp_rm_rn_l_D_0001_M_1000_N_0000,
	load_disp_rm_rn_l_D_0010_M_1000_N_0000,
	load_disp_rm_rn_l_D_0011_M_1000_N_0000,
	load_disp_rm_rn_l_D_0100_M_1000_N_0000,
	load_disp_rm_rn_l_D_0101_M_1000_N_0000,
	load_disp_rm_rn_l_D_0110_M_1000_N_0000,
	load_disp_rm_rn_l_D_0111_M_1000_N_0000,
	load_disp_rm_rn_l_D_1000_M_1000_N_0000,
	load_disp_rm_rn_l_D_1001_M_1000_N_0000,
	load_disp_rm_rn_l_D_1010_M_1000_N_0000,
	load_disp_rm_rn_l_D_1011_M_1000_N_0000,
	load_disp_rm_rn_l_D_1100_M_1000_N_0000,
	load_disp_rm_rn_l_D_1101_M_1000_N_0000,
	load_disp_rm_rn_l_D_1110_M_1000_N_0000,
	load_disp_rm_rn_l_D_1111_M_1000_N_0000,
	load_disp_rm_rn_l_D_0000_M_1001_N_0000,
	load_disp_rm_rn_l_D_0001_M_1001_N_0000,
	load_disp_rm_rn_l_D_0010_M_1001_N_0000,
	load_disp_rm_rn_l_D_0011_M_1001_N_0000,
	load_disp_rm_rn_l_D_0100_M_1001_N_0000,
	load_disp_rm_rn_l_D_0101_M_1001_N_0000,
	load_disp_rm_rn_l_D_0110_M_1001_N_0000,
	load_disp_rm_rn_l_D_0111_M_1001_N_0000,
	load_disp_rm_rn_l_D_1000_M_1001_N_0000,
	load_disp_rm_rn_l_D_1001_M_1001_N_0000,
	load_disp_rm_rn_l_D_1010_M_1001_N_0000,
	load_disp_rm_rn_l_D_1011_M_1001_N_0000,
	load_disp_rm_rn_l_D_1100_M_1001_N_0000,
	load_disp_rm_rn_l_D_1101_M_1001_N_0000,
	load_disp_rm_rn_l_D_1110_M_1001_N_0000,
	load_disp_rm_rn_l_D_1111_M_1001_N_0000,
	load_disp_rm_rn_l_D_0000_M_1010_N_0000,
	load_disp_rm_rn_l_D_0001_M_1010_N_0000,
	load_disp_rm_rn_l_D_0010_M_1010_N_0000,
	load_disp_rm_rn_l_D_0011_M_1010_N_0000,
	load_disp_rm_rn_l_D_0100_M_1010_N_0000,
	load_disp_rm_rn_l_D_0101_M_1010_N_0000,
	load_disp_rm_rn_l_D_0110_M_1010_N_0000,
	load_disp_rm_rn_l_D_0111_M_1010_N_0000,
	load_disp_rm_rn_l_D_1000_M_1010_N_0000,
	load_disp_rm_rn_l_D_1001_M_1010_N_0000,
	load_disp_rm_rn_l_D_1010_M_1010_N_0000,
	load_disp_rm_rn_l_D_1011_M_1010_N_0000,
	load_disp_rm_rn_l_D_1100_M_1010_N_0000,
	load_disp_rm_rn_l_D_1101_M_1010_N_0000,
	load_disp_rm_rn_l_D_1110_M_1010_N_0000,
	load_disp_rm_rn_l_D_1111_M_1010_N_0000,
	load_disp_rm_rn_l_D_0000_M_1011_N_0000,
	load_disp_rm_rn_l_D_0001_M_1011_N_0000,
	load_disp_rm_rn_l_D_0010_M_1011_N_0000,
	load_disp_rm_rn_l_D_0011_M_1011_N_0000,
	load_disp_rm_rn_l_D_0100_M_1011_N_0000,
	load_disp_rm_rn_l_D_0101_M_1011_N_0000,
	load_disp_rm_rn_l_D_0110_M_1011_N_0000,
	load_disp_rm_rn_l_D_0111_M_1011_N_0000,
	load_disp_rm_rn_l_D_1000_M_1011_N_0000,
	load_disp_rm_rn_l_D_1001_M_1011_N_0000,
	load_disp_rm_rn_l_D_1010_M_1011_N_0000,
	load_disp_rm_rn_l_D_1011_M_1011_N_0000,
	load_disp_rm_rn_l_D_1100_M_1011_N_0000,
	load_disp_rm_rn_l_D_1101_M_1011_N_0000,
	load_disp_rm_rn_l_D_1110_M_1011_N_0000,
	load_disp_rm_rn_l_D_1111_M_1011_N_0000,
	load_disp_rm_rn_l_D_0000_M_1100_N_0000,
	load_disp_rm_rn_l_D_0001_M_1100_N_0000,
	load_disp_rm_rn_l_D_0010_M_1100_N_0000,
	load_disp_rm_rn_l_D_0011_M_1100_N_0000,
	load_disp_rm_rn_l_D_0100_M_1100_N_0000,
	load_disp_rm_rn_l_D_0101_M_1100_N_0000,
	load_disp_rm_rn_l_D_0110_M_1100_N_0000,
	load_disp_rm_rn_l_D_0111_M_1100_N_0000,
	load_disp_rm_rn_l_D_1000_M_1100_N_0000,
	load_disp_rm_rn_l_D_1001_M_1100_N_0000,
	load_disp_rm_rn_l_D_1010_M_1100_N_0000,
	load_disp_rm_rn_l_D_1011_M_1100_N_0000,
	load_disp_rm_rn_l_D_1100_M_1100_N_0000,
	load_disp_rm_rn_l_D_1101_M_1100_N_0000,
	load_disp_rm_rn_l_D_1110_M_1100_N_0000,
	load_disp_rm_rn_l_D_1111_M_1100_N_0000,
	load_disp_rm_rn_l_D_0000_M_1101_N_0000,
	load_disp_rm_rn_l_D_0001_M_1101_N_0000,
	load_disp_rm_rn_l_D_0010_M_1101_N_0000,
	load_disp_rm_rn_l_D_0011_M_1101_N_0000,
	load_disp_rm_rn_l_D_0100_M_1101_N_0000,
	load_disp_rm_rn_l_D_0101_M_1101_N_0000,
	load_disp_rm_rn_l_D_0110_M_1101_N_0000,
	load_disp_rm_rn_l_D_0111_M_1101_N_0000,
	load_disp_rm_rn_l_D_1000_M_1101_N_0000,
	load_disp_rm_rn_l_D_1001_M_1101_N_0000,
	load_disp_rm_rn_l_D_1010_M_1101_N_0000,
	load_disp_rm_rn_l_D_1011_M_1101_N_0000,
	load_disp_rm_rn_l_D_1100_M_1101_N_0000,
	load_disp_rm_rn_l_D_1101_M_1101_N_0000,
	load_disp_rm_rn_l_D_1110_M_1101_N_0000,
	load_disp_rm_rn_l_D_1111_M_1101_N_0000,
	load_disp_rm_rn_l_D_0000_M_1110_N_0000,
	load_disp_rm_rn_l_D_0001_M_1110_N_0000,
	load_disp_rm_rn_l_D_0010_M_1110_N_0000,
	load_disp_rm_rn_l_D_0011_M_1110_N_0000,
	load_disp_rm_rn_l_D_0100_M_1110_N_0000,
	load_disp_rm_rn_l_D_0101_M_1110_N_0000,
	load_disp_rm_rn_l_D_0110_M_1110_N_0000,
	load_disp_rm_rn_l_D_0111_M_1110_N_0000,
	load_disp_rm_rn_l_D_1000_M_1110_N_0000,
	load_disp_rm_rn_l_D_1001_M_1110_N_0000,
	load_disp_rm_rn_l_D_1010_M_1110_N_0000,
	load_disp_rm_rn_l_D_1011_M_1110_N_0000,
	load_disp_rm_rn_l_D_1100_M_1110_N_0000,
	load_disp_rm_rn_l_D_1101_M_1110_N_0000,
	load_disp_rm_rn_l_D_1110_M_1110_N_0000,
	load_disp_rm_rn_l_D_1111_M_1110_N_0000,
	load_disp_rm_rn_l_D_0000_M_1111_N_0000,
	load_disp_rm_rn_l_D_0001_M_1111_N_0000,
	load_disp_rm_rn_l_D_0010_M_1111_N_0000,
	load_disp_rm_rn_l_D_0011_M_1111_N_0000,
	load_disp_rm_rn_l_D_0100_M_1111_N_0000,
	load_disp_rm_rn_l_D_0101_M_1111_N_0000,
	load_disp_rm_rn_l_D_0110_M_1111_N_0000,
	load_disp_rm_rn_l_D_0111_M_1111_N_0000,
	load_disp_rm_rn_l_D_1000_M_1111_N_0000,
	load_disp_rm_rn_l_D_1001_M_1111_N_0000,
	load_disp_rm_rn_l_D_1010_M_1111_N_0000,
	load_disp_rm_rn_l_D_1011_M_1111_N_0000,
	load_disp_rm_rn_l_D_1100_M_1111_N_0000,
	load_disp_rm_rn_l_D_1101_M_1111_N_0000,
	load_disp_rm_rn_l_D_1110_M_1111_N_0000,
	load_disp_rm_rn_l_D_1111_M_1111_N_0000,
	load_disp_rm_rn_l_D_0000_M_0000_N_0001,
	load_disp_rm_rn_l_D_0001_M_0000_N_0001,
	load_disp_rm_rn_l_D_0010_M_0000_N_0001,
	load_disp_rm_rn_l_D_0011_M_0000_N_0001,
	load_disp_rm_rn_l_D_0100_M_0000_N_0001,
	load_disp_rm_rn_l_D_0101_M_0000_N_0001,
	load_disp_rm_rn_l_D_0110_M_0000_N_0001,
	load_disp_rm_rn_l_D_0111_M_0000_N_0001,
	load_disp_rm_rn_l_D_1000_M_0000_N_0001,
	load_disp_rm_rn_l_D_1001_M_0000_N_0001,
	load_disp_rm_rn_l_D_1010_M_0000_N_0001,
	load_disp_rm_rn_l_D_1011_M_0000_N_0001,
	load_disp_rm_rn_l_D_1100_M_0000_N_0001,
	load_disp_rm_rn_l_D_1101_M_0000_N_0001,
	load_disp_rm_rn_l_D_1110_M_0000_N_0001,
	load_disp_rm_rn_l_D_1111_M_0000_N_0001,
	load_disp_rm_rn_l_D_0000_M_0001_N_0001,
	load_disp_rm_rn_l_D_0001_M_0001_N_0001,
	load_disp_rm_rn_l_D_0010_M_0001_N_0001,
	load_disp_rm_rn_l_D_0011_M_0001_N_0001,
	load_disp_rm_rn_l_D_0100_M_0001_N_0001,
	load_disp_rm_rn_l_D_0101_M_0001_N_0001,
	load_disp_rm_rn_l_D_0110_M_0001_N_0001,
	load_disp_rm_rn_l_D_0111_M_0001_N_0001,
	load_disp_rm_rn_l_D_1000_M_0001_N_0001,
	load_disp_rm_rn_l_D_1001_M_0001_N_0001,
	load_disp_rm_rn_l_D_1010_M_0001_N_0001,
	load_disp_rm_rn_l_D_1011_M_0001_N_0001,
	load_disp_rm_rn_l_D_1100_M_0001_N_0001,
	load_disp_rm_rn_l_D_1101_M_0001_N_0001,
	load_disp_rm_rn_l_D_1110_M_0001_N_0001,
	load_disp_rm_rn_l_D_1111_M_0001_N_0001,
	load_disp_rm_rn_l_D_0000_M_0010_N_0001,
	load_disp_rm_rn_l_D_0001_M_0010_N_0001,
	load_disp_rm_rn_l_D_0010_M_0010_N_0001,
	load_disp_rm_rn_l_D_0011_M_0010_N_0001,
	load_disp_rm_rn_l_D_0100_M_0010_N_0001,
	load_disp_rm_rn_l_D_0101_M_0010_N_0001,
	load_disp_rm_rn_l_D_0110_M_0010_N_0001,
	load_disp_rm_rn_l_D_0111_M_0010_N_0001,
	load_disp_rm_rn_l_D_1000_M_0010_N_0001,
	load_disp_rm_rn_l_D_1001_M_0010_N_0001,
	load_disp_rm_rn_l_D_1010_M_0010_N_0001,
	load_disp_rm_rn_l_D_1011_M_0010_N_0001,
	load_disp_rm_rn_l_D_1100_M_0010_N_0001,
	load_disp_rm_rn_l_D_1101_M_0010_N_0001,
	load_disp_rm_rn_l_D_1110_M_0010_N_0001,
	load_disp_rm_rn_l_D_1111_M_0010_N_0001,
	load_disp_rm_rn_l_D_0000_M_0011_N_0001,
	load_disp_rm_rn_l_D_0001_M_0011_N_0001,
	load_disp_rm_rn_l_D_0010_M_0011_N_0001,
	load_disp_rm_rn_l_D_0011_M_0011_N_0001,
	load_disp_rm_rn_l_D_0100_M_0011_N_0001,
	load_disp_rm_rn_l_D_0101_M_0011_N_0001,
	load_disp_rm_rn_l_D_0110_M_0011_N_0001,
	load_disp_rm_rn_l_D_0111_M_0011_N_0001,
	load_disp_rm_rn_l_D_1000_M_0011_N_0001,
	load_disp_rm_rn_l_D_1001_M_0011_N_0001,
	load_disp_rm_rn_l_D_1010_M_0011_N_0001,
	load_disp_rm_rn_l_D_1011_M_0011_N_0001,
	load_disp_rm_rn_l_D_1100_M_0011_N_0001,
	load_disp_rm_rn_l_D_1101_M_0011_N_0001,
	load_disp_rm_rn_l_D_1110_M_0011_N_0001,
	load_disp_rm_rn_l_D_1111_M_0011_N_0001,
	load_disp_rm_rn_l_D_0000_M_0100_N_0001,
	load_disp_rm_rn_l_D_0001_M_0100_N_0001,
	load_disp_rm_rn_l_D_0010_M_0100_N_0001,
	load_disp_rm_rn_l_D_0011_M_0100_N_0001,
	load_disp_rm_rn_l_D_0100_M_0100_N_0001,
	load_disp_rm_rn_l_D_0101_M_0100_N_0001,
	load_disp_rm_rn_l_D_0110_M_0100_N_0001,
	load_disp_rm_rn_l_D_0111_M_0100_N_0001,
	load_disp_rm_rn_l_D_1000_M_0100_N_0001,
	load_disp_rm_rn_l_D_1001_M_0100_N_0001,
	load_disp_rm_rn_l_D_1010_M_0100_N_0001,
	load_disp_rm_rn_l_D_1011_M_0100_N_0001,
	load_disp_rm_rn_l_D_1100_M_0100_N_0001,
	load_disp_rm_rn_l_D_1101_M_0100_N_0001,
	load_disp_rm_rn_l_D_1110_M_0100_N_0001,
	load_disp_rm_rn_l_D_1111_M_0100_N_0001,
	load_disp_rm_rn_l_D_0000_M_0101_N_0001,
	load_disp_rm_rn_l_D_0001_M_0101_N_0001,
	load_disp_rm_rn_l_D_0010_M_0101_N_0001,
	load_disp_rm_rn_l_D_0011_M_0101_N_0001,
	load_disp_rm_rn_l_D_0100_M_0101_N_0001,
	load_disp_rm_rn_l_D_0101_M_0101_N_0001,
	load_disp_rm_rn_l_D_0110_M_0101_N_0001,
	load_disp_rm_rn_l_D_0111_M_0101_N_0001,
	load_disp_rm_rn_l_D_1000_M_0101_N_0001,
	load_disp_rm_rn_l_D_1001_M_0101_N_0001,
	load_disp_rm_rn_l_D_1010_M_0101_N_0001,
	load_disp_rm_rn_l_D_1011_M_0101_N_0001,
	load_disp_rm_rn_l_D_1100_M_0101_N_0001,
	load_disp_rm_rn_l_D_1101_M_0101_N_0001,
	load_disp_rm_rn_l_D_1110_M_0101_N_0001,
	load_disp_rm_rn_l_D_1111_M_0101_N_0001,
	load_disp_rm_rn_l_D_0000_M_0110_N_0001,
	load_disp_rm_rn_l_D_0001_M_0110_N_0001,
	load_disp_rm_rn_l_D_0010_M_0110_N_0001,
	load_disp_rm_rn_l_D_0011_M_0110_N_0001,
	load_disp_rm_rn_l_D_0100_M_0110_N_0001,
	load_disp_rm_rn_l_D_0101_M_0110_N_0001,
	load_disp_rm_rn_l_D_0110_M_0110_N_0001,
	load_disp_rm_rn_l_D_0111_M_0110_N_0001,
	load_disp_rm_rn_l_D_1000_M_0110_N_0001,
	load_disp_rm_rn_l_D_1001_M_0110_N_0001,
	load_disp_rm_rn_l_D_1010_M_0110_N_0001,
	load_disp_rm_rn_l_D_1011_M_0110_N_0001,
	load_disp_rm_rn_l_D_1100_M_0110_N_0001,
	load_disp_rm_rn_l_D_1101_M_0110_N_0001,
	load_disp_rm_rn_l_D_1110_M_0110_N_0001,
	load_disp_rm_rn_l_D_1111_M_0110_N_0001,
	load_disp_rm_rn_l_D_0000_M_0111_N_0001,
	load_disp_rm_rn_l_D_0001_M_0111_N_0001,
	load_disp_rm_rn_l_D_0010_M_0111_N_0001,
	load_disp_rm_rn_l_D_0011_M_0111_N_0001,
	load_disp_rm_rn_l_D_0100_M_0111_N_0001,
	load_disp_rm_rn_l_D_0101_M_0111_N_0001,
	load_disp_rm_rn_l_D_0110_M_0111_N_0001,
	load_disp_rm_rn_l_D_0111_M_0111_N_0001,
	load_disp_rm_rn_l_D_1000_M_0111_N_0001,
	load_disp_rm_rn_l_D_1001_M_0111_N_0001,
	load_disp_rm_rn_l_D_1010_M_0111_N_0001,
	load_disp_rm_rn_l_D_1011_M_0111_N_0001,
	load_disp_rm_rn_l_D_1100_M_0111_N_0001,
	load_disp_rm_rn_l_D_1101_M_0111_N_0001,
	load_disp_rm_rn_l_D_1110_M_0111_N_0001,
	load_disp_rm_rn_l_D_1111_M_0111_N_0001,
	load_disp_rm_rn_l_D_0000_M_1000_N_0001,
	load_disp_rm_rn_l_D_0001_M_1000_N_0001,
	load_disp_rm_rn_l_D_0010_M_1000_N_0001,
	load_disp_rm_rn_l_D_0011_M_1000_N_0001,
	load_disp_rm_rn_l_D_0100_M_1000_N_0001,
	load_disp_rm_rn_l_D_0101_M_1000_N_0001,
	load_disp_rm_rn_l_D_0110_M_1000_N_0001,
	load_disp_rm_rn_l_D_0111_M_1000_N_0001,
	load_disp_rm_rn_l_D_1000_M_1000_N_0001,
	load_disp_rm_rn_l_D_1001_M_1000_N_0001,
	load_disp_rm_rn_l_D_1010_M_1000_N_0001,
	load_disp_rm_rn_l_D_1011_M_1000_N_0001,
	load_disp_rm_rn_l_D_1100_M_1000_N_0001,
	load_disp_rm_rn_l_D_1101_M_1000_N_0001,
	load_disp_rm_rn_l_D_1110_M_1000_N_0001,
	load_disp_rm_rn_l_D_1111_M_1000_N_0001,
	load_disp_rm_rn_l_D_0000_M_1001_N_0001,
	load_disp_rm_rn_l_D_0001_M_1001_N_0001,
	load_disp_rm_rn_l_D_0010_M_1001_N_0001,
	load_disp_rm_rn_l_D_0011_M_1001_N_0001,
	load_disp_rm_rn_l_D_0100_M_1001_N_0001,
	load_disp_rm_rn_l_D_0101_M_1001_N_0001,
	load_disp_rm_rn_l_D_0110_M_1001_N_0001,
	load_disp_rm_rn_l_D_0111_M_1001_N_0001,
	load_disp_rm_rn_l_D_1000_M_1001_N_0001,
	load_disp_rm_rn_l_D_1001_M_1001_N_0001,
	load_disp_rm_rn_l_D_1010_M_1001_N_0001,
	load_disp_rm_rn_l_D_1011_M_1001_N_0001,
	load_disp_rm_rn_l_D_1100_M_1001_N_0001,
	load_disp_rm_rn_l_D_1101_M_1001_N_0001,
	load_disp_rm_rn_l_D_1110_M_1001_N_0001,
	load_disp_rm_rn_l_D_1111_M_1001_N_0001,
	load_disp_rm_rn_l_D_0000_M_1010_N_0001,
	load_disp_rm_rn_l_D_0001_M_1010_N_0001,
	load_disp_rm_rn_l_D_0010_M_1010_N_0001,
	load_disp_rm_rn_l_D_0011_M_1010_N_0001,
	load_disp_rm_rn_l_D_0100_M_1010_N_0001,
	load_disp_rm_rn_l_D_0101_M_1010_N_0001,
	load_disp_rm_rn_l_D_0110_M_1010_N_0001,
	load_disp_rm_rn_l_D_0111_M_1010_N_0001,
	load_disp_rm_rn_l_D_1000_M_1010_N_0001,
	load_disp_rm_rn_l_D_1001_M_1010_N_0001,
	load_disp_rm_rn_l_D_1010_M_1010_N_0001,
	load_disp_rm_rn_l_D_1011_M_1010_N_0001,
	load_disp_rm_rn_l_D_1100_M_1010_N_0001,
	load_disp_rm_rn_l_D_1101_M_1010_N_0001,
	load_disp_rm_rn_l_D_1110_M_1010_N_0001,
	load_disp_rm_rn_l_D_1111_M_1010_N_0001,
	load_disp_rm_rn_l_D_0000_M_1011_N_0001,
	load_disp_rm_rn_l_D_0001_M_1011_N_0001,
	load_disp_rm_rn_l_D_0010_M_1011_N_0001,
	load_disp_rm_rn_l_D_0011_M_1011_N_0001,
	load_disp_rm_rn_l_D_0100_M_1011_N_0001,
	load_disp_rm_rn_l_D_0101_M_1011_N_0001,
	load_disp_rm_rn_l_D_0110_M_1011_N_0001,
	load_disp_rm_rn_l_D_0111_M_1011_N_0001,
	load_disp_rm_rn_l_D_1000_M_1011_N_0001,
	load_disp_rm_rn_l_D_1001_M_1011_N_0001,
	load_disp_rm_rn_l_D_1010_M_1011_N_0001,
	load_disp_rm_rn_l_D_1011_M_1011_N_0001,
	load_disp_rm_rn_l_D_1100_M_1011_N_0001,
	load_disp_rm_rn_l_D_1101_M_1011_N_0001,
	load_disp_rm_rn_l_D_1110_M_1011_N_0001,
	load_disp_rm_rn_l_D_1111_M_1011_N_0001,
	load_disp_rm_rn_l_D_0000_M_1100_N_0001,
	load_disp_rm_rn_l_D_0001_M_1100_N_0001,
	load_disp_rm_rn_l_D_0010_M_1100_N_0001,
	load_disp_rm_rn_l_D_0011_M_1100_N_0001,
	load_disp_rm_rn_l_D_0100_M_1100_N_0001,
	load_disp_rm_rn_l_D_0101_M_1100_N_0001,
	load_disp_rm_rn_l_D_0110_M_1100_N_0001,
	load_disp_rm_rn_l_D_0111_M_1100_N_0001,
	load_disp_rm_rn_l_D_1000_M_1100_N_0001,
	load_disp_rm_rn_l_D_1001_M_1100_N_0001,
	load_disp_rm_rn_l_D_1010_M_1100_N_0001,
	load_disp_rm_rn_l_D_1011_M_1100_N_0001,
	load_disp_rm_rn_l_D_1100_M_1100_N_0001,
	load_disp_rm_rn_l_D_1101_M_1100_N_0001,
	load_disp_rm_rn_l_D_1110_M_1100_N_0001,
	load_disp_rm_rn_l_D_1111_M_1100_N_0001,
	load_disp_rm_rn_l_D_0000_M_1101_N_0001,
	load_disp_rm_rn_l_D_0001_M_1101_N_0001,
	load_disp_rm_rn_l_D_0010_M_1101_N_0001,
	load_disp_rm_rn_l_D_0011_M_1101_N_0001,
	load_disp_rm_rn_l_D_0100_M_1101_N_0001,
	load_disp_rm_rn_l_D_0101_M_1101_N_0001,
	load_disp_rm_rn_l_D_0110_M_1101_N_0001,
	load_disp_rm_rn_l_D_0111_M_1101_N_0001,
	load_disp_rm_rn_l_D_1000_M_1101_N_0001,
	load_disp_rm_rn_l_D_1001_M_1101_N_0001,
	load_disp_rm_rn_l_D_1010_M_1101_N_0001,
	load_disp_rm_rn_l_D_1011_M_1101_N_0001,
	load_disp_rm_rn_l_D_1100_M_1101_N_0001,
	load_disp_rm_rn_l_D_1101_M_1101_N_0001,
	load_disp_rm_rn_l_D_1110_M_1101_N_0001,
	load_disp_rm_rn_l_D_1111_M_1101_N_0001,
	load_disp_rm_rn_l_D_0000_M_1110_N_0001,
	load_disp_rm_rn_l_D_0001_M_1110_N_0001,
	load_disp_rm_rn_l_D_0010_M_1110_N_0001,
	load_disp_rm_rn_l_D_0011_M_1110_N_0001,
	load_disp_rm_rn_l_D_0100_M_1110_N_0001,
	load_disp_rm_rn_l_D_0101_M_1110_N_0001,
	load_disp_rm_rn_l_D_0110_M_1110_N_0001,
	load_disp_rm_rn_l_D_0111_M_1110_N_0001,
	load_disp_rm_rn_l_D_1000_M_1110_N_0001,
	load_disp_rm_rn_l_D_1001_M_1110_N_0001,
	load_disp_rm_rn_l_D_1010_M_1110_N_0001,
	load_disp_rm_rn_l_D_1011_M_1110_N_0001,
	load_disp_rm_rn_l_D_1100_M_1110_N_0001,
	load_disp_rm_rn_l_D_1101_M_1110_N_0001,
	load_disp_rm_rn_l_D_1110_M_1110_N_0001,
	load_disp_rm_rn_l_D_1111_M_1110_N_0001,
	load_disp_rm_rn_l_D_0000_M_1111_N_0001,
	load_disp_rm_rn_l_D_0001_M_1111_N_0001,
	load_disp_rm_rn_l_D_0010_M_1111_N_0001,
	load_disp_rm_rn_l_D_0011_M_1111_N_0001,
	load_disp_rm_rn_l_D_0100_M_1111_N_0001,
	load_disp_rm_rn_l_D_0101_M_1111_N_0001,
	load_disp_rm_rn_l_D_0110_M_1111_N_0001,
	load_disp_rm_rn_l_D_0111_M_1111_N_0001,
	load_disp_rm_rn_l_D_1000_M_1111_N_0001,
	load_disp_rm_rn_l_D_1001_M_1111_N_0001,
	load_disp_rm_rn_l_D_1010_M_1111_N_0001,
	load_disp_rm_rn_l_D_1011_M_1111_N_0001,
	load_disp_rm_rn_l_D_1100_M_1111_N_0001,
	load_disp_rm_rn_l_D_1101_M_1111_N_0001,
	load_disp_rm_rn_l_D_1110_M_1111_N_0001,
	load_disp_rm_rn_l_D_1111_M_1111_N_0001,
	load_disp_rm_rn_l_D_0000_M_0000_N_0010,
	load_disp_rm_rn_l_D_0001_M_0000_N_0010,
	load_disp_rm_rn_l_D_0010_M_0000_N_0010,
	load_disp_rm_rn_l_D_0011_M_0000_N_0010,
	load_disp_rm_rn_l_D_0100_M_0000_N_0010,
	load_disp_rm_rn_l_D_0101_M_0000_N_0010,
	load_disp_rm_rn_l_D_0110_M_0000_N_0010,
	load_disp_rm_rn_l_D_0111_M_0000_N_0010,
	load_disp_rm_rn_l_D_1000_M_0000_N_0010,
	load_disp_rm_rn_l_D_1001_M_0000_N_0010,
	load_disp_rm_rn_l_D_1010_M_0000_N_0010,
	load_disp_rm_rn_l_D_1011_M_0000_N_0010,
	load_disp_rm_rn_l_D_1100_M_0000_N_0010,
	load_disp_rm_rn_l_D_1101_M_0000_N_0010,
	load_disp_rm_rn_l_D_1110_M_0000_N_0010,
	load_disp_rm_rn_l_D_1111_M_0000_N_0010,
	load_disp_rm_rn_l_D_0000_M_0001_N_0010,
	load_disp_rm_rn_l_D_0001_M_0001_N_0010,
	load_disp_rm_rn_l_D_0010_M_0001_N_0010,
	load_disp_rm_rn_l_D_0011_M_0001_N_0010,
	load_disp_rm_rn_l_D_0100_M_0001_N_0010,
	load_disp_rm_rn_l_D_0101_M_0001_N_0010,
	load_disp_rm_rn_l_D_0110_M_0001_N_0010,
	load_disp_rm_rn_l_D_0111_M_0001_N_0010,
	load_disp_rm_rn_l_D_1000_M_0001_N_0010,
	load_disp_rm_rn_l_D_1001_M_0001_N_0010,
	load_disp_rm_rn_l_D_1010_M_0001_N_0010,
	load_disp_rm_rn_l_D_1011_M_0001_N_0010,
	load_disp_rm_rn_l_D_1100_M_0001_N_0010,
	load_disp_rm_rn_l_D_1101_M_0001_N_0010,
	load_disp_rm_rn_l_D_1110_M_0001_N_0010,
	load_disp_rm_rn_l_D_1111_M_0001_N_0010,
	load_disp_rm_rn_l_D_0000_M_0010_N_0010,
	load_disp_rm_rn_l_D_0001_M_0010_N_0010,
	load_disp_rm_rn_l_D_0010_M_0010_N_0010,
	load_disp_rm_rn_l_D_0011_M_0010_N_0010,
	load_disp_rm_rn_l_D_0100_M_0010_N_0010,
	load_disp_rm_rn_l_D_0101_M_0010_N_0010,
	load_disp_rm_rn_l_D_0110_M_0010_N_0010,
	load_disp_rm_rn_l_D_0111_M_0010_N_0010,
	load_disp_rm_rn_l_D_1000_M_0010_N_0010,
	load_disp_rm_rn_l_D_1001_M_0010_N_0010,
	load_disp_rm_rn_l_D_1010_M_0010_N_0010,
	load_disp_rm_rn_l_D_1011_M_0010_N_0010,
	load_disp_rm_rn_l_D_1100_M_0010_N_0010,
	load_disp_rm_rn_l_D_1101_M_0010_N_0010,
	load_disp_rm_rn_l_D_1110_M_0010_N_0010,
	load_disp_rm_rn_l_D_1111_M_0010_N_0010,
	load_disp_rm_rn_l_D_0000_M_0011_N_0010,
	load_disp_rm_rn_l_D_0001_M_0011_N_0010,
	load_disp_rm_rn_l_D_0010_M_0011_N_0010,
	load_disp_rm_rn_l_D_0011_M_0011_N_0010,
	load_disp_rm_rn_l_D_0100_M_0011_N_0010,
	load_disp_rm_rn_l_D_0101_M_0011_N_0010,
	load_disp_rm_rn_l_D_0110_M_0011_N_0010,
	load_disp_rm_rn_l_D_0111_M_0011_N_0010,
	load_disp_rm_rn_l_D_1000_M_0011_N_0010,
	load_disp_rm_rn_l_D_1001_M_0011_N_0010,
	load_disp_rm_rn_l_D_1010_M_0011_N_0010,
	load_disp_rm_rn_l_D_1011_M_0011_N_0010,
	load_disp_rm_rn_l_D_1100_M_0011_N_0010,
	load_disp_rm_rn_l_D_1101_M_0011_N_0010,
	load_disp_rm_rn_l_D_1110_M_0011_N_0010,
	load_disp_rm_rn_l_D_1111_M_0011_N_0010,
	load_disp_rm_rn_l_D_0000_M_0100_N_0010,
	load_disp_rm_rn_l_D_0001_M_0100_N_0010,
	load_disp_rm_rn_l_D_0010_M_0100_N_0010,
	load_disp_rm_rn_l_D_0011_M_0100_N_0010,
	load_disp_rm_rn_l_D_0100_M_0100_N_0010,
	load_disp_rm_rn_l_D_0101_M_0100_N_0010,
	load_disp_rm_rn_l_D_0110_M_0100_N_0010,
	load_disp_rm_rn_l_D_0111_M_0100_N_0010,
	load_disp_rm_rn_l_D_1000_M_0100_N_0010,
	load_disp_rm_rn_l_D_1001_M_0100_N_0010,
	load_disp_rm_rn_l_D_1010_M_0100_N_0010,
	load_disp_rm_rn_l_D_1011_M_0100_N_0010,
	load_disp_rm_rn_l_D_1100_M_0100_N_0010,
	load_disp_rm_rn_l_D_1101_M_0100_N_0010,
	load_disp_rm_rn_l_D_1110_M_0100_N_0010,
	load_disp_rm_rn_l_D_1111_M_0100_N_0010,
	load_disp_rm_rn_l_D_0000_M_0101_N_0010,
	load_disp_rm_rn_l_D_0001_M_0101_N_0010,
	load_disp_rm_rn_l_D_0010_M_0101_N_0010,
	load_disp_rm_rn_l_D_0011_M_0101_N_0010,
	load_disp_rm_rn_l_D_0100_M_0101_N_0010,
	load_disp_rm_rn_l_D_0101_M_0101_N_0010,
	load_disp_rm_rn_l_D_0110_M_0101_N_0010,
	load_disp_rm_rn_l_D_0111_M_0101_N_0010,
	load_disp_rm_rn_l_D_1000_M_0101_N_0010,
	load_disp_rm_rn_l_D_1001_M_0101_N_0010,
	load_disp_rm_rn_l_D_1010_M_0101_N_0010,
	load_disp_rm_rn_l_D_1011_M_0101_N_0010,
	load_disp_rm_rn_l_D_1100_M_0101_N_0010,
	load_disp_rm_rn_l_D_1101_M_0101_N_0010,
	load_disp_rm_rn_l_D_1110_M_0101_N_0010,
	load_disp_rm_rn_l_D_1111_M_0101_N_0010,
	load_disp_rm_rn_l_D_0000_M_0110_N_0010,
	load_disp_rm_rn_l_D_0001_M_0110_N_0010,
	load_disp_rm_rn_l_D_0010_M_0110_N_0010,
	load_disp_rm_rn_l_D_0011_M_0110_N_0010,
	load_disp_rm_rn_l_D_0100_M_0110_N_0010,
	load_disp_rm_rn_l_D_0101_M_0110_N_0010,
	load_disp_rm_rn_l_D_0110_M_0110_N_0010,
	load_disp_rm_rn_l_D_0111_M_0110_N_0010,
	load_disp_rm_rn_l_D_1000_M_0110_N_0010,
	load_disp_rm_rn_l_D_1001_M_0110_N_0010,
	load_disp_rm_rn_l_D_1010_M_0110_N_0010,
	load_disp_rm_rn_l_D_1011_M_0110_N_0010,
	load_disp_rm_rn_l_D_1100_M_0110_N_0010,
	load_disp_rm_rn_l_D_1101_M_0110_N_0010,
	load_disp_rm_rn_l_D_1110_M_0110_N_0010,
	load_disp_rm_rn_l_D_1111_M_0110_N_0010,
	load_disp_rm_rn_l_D_0000_M_0111_N_0010,
	load_disp_rm_rn_l_D_0001_M_0111_N_0010,
	load_disp_rm_rn_l_D_0010_M_0111_N_0010,
	load_disp_rm_rn_l_D_0011_M_0111_N_0010,
	load_disp_rm_rn_l_D_0100_M_0111_N_0010,
	load_disp_rm_rn_l_D_0101_M_0111_N_0010,
	load_disp_rm_rn_l_D_0110_M_0111_N_0010,
	load_disp_rm_rn_l_D_0111_M_0111_N_0010,
	load_disp_rm_rn_l_D_1000_M_0111_N_0010,
	load_disp_rm_rn_l_D_1001_M_0111_N_0010,
	load_disp_rm_rn_l_D_1010_M_0111_N_0010,
	load_disp_rm_rn_l_D_1011_M_0111_N_0010,
	load_disp_rm_rn_l_D_1100_M_0111_N_0010,
	load_disp_rm_rn_l_D_1101_M_0111_N_0010,
	load_disp_rm_rn_l_D_1110_M_0111_N_0010,
	load_disp_rm_rn_l_D_1111_M_0111_N_0010,
	load_disp_rm_rn_l_D_0000_M_1000_N_0010,
	load_disp_rm_rn_l_D_0001_M_1000_N_0010,
	load_disp_rm_rn_l_D_0010_M_1000_N_0010,
	load_disp_rm_rn_l_D_0011_M_1000_N_0010,
	load_disp_rm_rn_l_D_0100_M_1000_N_0010,
	load_disp_rm_rn_l_D_0101_M_1000_N_0010,
	load_disp_rm_rn_l_D_0110_M_1000_N_0010,
	load_disp_rm_rn_l_D_0111_M_1000_N_0010,
	load_disp_rm_rn_l_D_1000_M_1000_N_0010,
	load_disp_rm_rn_l_D_1001_M_1000_N_0010,
	load_disp_rm_rn_l_D_1010_M_1000_N_0010,
	load_disp_rm_rn_l_D_1011_M_1000_N_0010,
	load_disp_rm_rn_l_D_1100_M_1000_N_0010,
	load_disp_rm_rn_l_D_1101_M_1000_N_0010,
	load_disp_rm_rn_l_D_1110_M_1000_N_0010,
	load_disp_rm_rn_l_D_1111_M_1000_N_0010,
	load_disp_rm_rn_l_D_0000_M_1001_N_0010,
	load_disp_rm_rn_l_D_0001_M_1001_N_0010,
	load_disp_rm_rn_l_D_0010_M_1001_N_0010,
	load_disp_rm_rn_l_D_0011_M_1001_N_0010,
	load_disp_rm_rn_l_D_0100_M_1001_N_0010,
	load_disp_rm_rn_l_D_0101_M_1001_N_0010,
	load_disp_rm_rn_l_D_0110_M_1001_N_0010,
	load_disp_rm_rn_l_D_0111_M_1001_N_0010,
	load_disp_rm_rn_l_D_1000_M_1001_N_0010,
	load_disp_rm_rn_l_D_1001_M_1001_N_0010,
	load_disp_rm_rn_l_D_1010_M_1001_N_0010,
	load_disp_rm_rn_l_D_1011_M_1001_N_0010,
	load_disp_rm_rn_l_D_1100_M_1001_N_0010,
	load_disp_rm_rn_l_D_1101_M_1001_N_0010,
	load_disp_rm_rn_l_D_1110_M_1001_N_0010,
	load_disp_rm_rn_l_D_1111_M_1001_N_0010,
	load_disp_rm_rn_l_D_0000_M_1010_N_0010,
	load_disp_rm_rn_l_D_0001_M_1010_N_0010,
	load_disp_rm_rn_l_D_0010_M_1010_N_0010,
	load_disp_rm_rn_l_D_0011_M_1010_N_0010,
	load_disp_rm_rn_l_D_0100_M_1010_N_0010,
	load_disp_rm_rn_l_D_0101_M_1010_N_0010,
	load_disp_rm_rn_l_D_0110_M_1010_N_0010,
	load_disp_rm_rn_l_D_0111_M_1010_N_0010,
	load_disp_rm_rn_l_D_1000_M_1010_N_0010,
	load_disp_rm_rn_l_D_1001_M_1010_N_0010,
	load_disp_rm_rn_l_D_1010_M_1010_N_0010,
	load_disp_rm_rn_l_D_1011_M_1010_N_0010,
	load_disp_rm_rn_l_D_1100_M_1010_N_0010,
	load_disp_rm_rn_l_D_1101_M_1010_N_0010,
	load_disp_rm_rn_l_D_1110_M_1010_N_0010,
	load_disp_rm_rn_l_D_1111_M_1010_N_0010,
	load_disp_rm_rn_l_D_0000_M_1011_N_0010,
	load_disp_rm_rn_l_D_0001_M_1011_N_0010,
	load_disp_rm_rn_l_D_0010_M_1011_N_0010,
	load_disp_rm_rn_l_D_0011_M_1011_N_0010,
	load_disp_rm_rn_l_D_0100_M_1011_N_0010,
	load_disp_rm_rn_l_D_0101_M_1011_N_0010,
	load_disp_rm_rn_l_D_0110_M_1011_N_0010,
	load_disp_rm_rn_l_D_0111_M_1011_N_0010,
	load_disp_rm_rn_l_D_1000_M_1011_N_0010,
	load_disp_rm_rn_l_D_1001_M_1011_N_0010,
	load_disp_rm_rn_l_D_1010_M_1011_N_0010,
	load_disp_rm_rn_l_D_1011_M_1011_N_0010,
	load_disp_rm_rn_l_D_1100_M_1011_N_0010,
	load_disp_rm_rn_l_D_1101_M_1011_N_0010,
	load_disp_rm_rn_l_D_1110_M_1011_N_0010,
	load_disp_rm_rn_l_D_1111_M_1011_N_0010,
	load_disp_rm_rn_l_D_0000_M_1100_N_0010,
	load_disp_rm_rn_l_D_0001_M_1100_N_0010,
	load_disp_rm_rn_l_D_0010_M_1100_N_0010,
	load_disp_rm_rn_l_D_0011_M_1100_N_0010,
	load_disp_rm_rn_l_D_0100_M_1100_N_0010,
	load_disp_rm_rn_l_D_0101_M_1100_N_0010,
	load_disp_rm_rn_l_D_0110_M_1100_N_0010,
	load_disp_rm_rn_l_D_0111_M_1100_N_0010,
	load_disp_rm_rn_l_D_1000_M_1100_N_0010,
	load_disp_rm_rn_l_D_1001_M_1100_N_0010,
	load_disp_rm_rn_l_D_1010_M_1100_N_0010,
	load_disp_rm_rn_l_D_1011_M_1100_N_0010,
	load_disp_rm_rn_l_D_1100_M_1100_N_0010,
	load_disp_rm_rn_l_D_1101_M_1100_N_0010,
	load_disp_rm_rn_l_D_1110_M_1100_N_0010,
	load_disp_rm_rn_l_D_1111_M_1100_N_0010,
	load_disp_rm_rn_l_D_0000_M_1101_N_0010,
	load_disp_rm_rn_l_D_0001_M_1101_N_0010,
	load_disp_rm_rn_l_D_0010_M_1101_N_0010,
	load_disp_rm_rn_l_D_0011_M_1101_N_0010,
	load_disp_rm_rn_l_D_0100_M_1101_N_0010,
	load_disp_rm_rn_l_D_0101_M_1101_N_0010,
	load_disp_rm_rn_l_D_0110_M_1101_N_0010,
	load_disp_rm_rn_l_D_0111_M_1101_N_0010,
	load_disp_rm_rn_l_D_1000_M_1101_N_0010,
	load_disp_rm_rn_l_D_1001_M_1101_N_0010,
	load_disp_rm_rn_l_D_1010_M_1101_N_0010,
	load_disp_rm_rn_l_D_1011_M_1101_N_0010,
	load_disp_rm_rn_l_D_1100_M_1101_N_0010,
	load_disp_rm_rn_l_D_1101_M_1101_N_0010,
	load_disp_rm_rn_l_D_1110_M_1101_N_0010,
	load_disp_rm_rn_l_D_1111_M_1101_N_0010,
	load_disp_rm_rn_l_D_0000_M_1110_N_0010,
	load_disp_rm_rn_l_D_0001_M_1110_N_0010,
	load_disp_rm_rn_l_D_0010_M_1110_N_0010,
	load_disp_rm_rn_l_D_0011_M_1110_N_0010,
	load_disp_rm_rn_l_D_0100_M_1110_N_0010,
	load_disp_rm_rn_l_D_0101_M_1110_N_0010,
	load_disp_rm_rn_l_D_0110_M_1110_N_0010,
	load_disp_rm_rn_l_D_0111_M_1110_N_0010,
	load_disp_rm_rn_l_D_1000_M_1110_N_0010,
	load_disp_rm_rn_l_D_1001_M_1110_N_0010,
	load_disp_rm_rn_l_D_1010_M_1110_N_0010,
	load_disp_rm_rn_l_D_1011_M_1110_N_0010,
	load_disp_rm_rn_l_D_1100_M_1110_N_0010,
	load_disp_rm_rn_l_D_1101_M_1110_N_0010,
	load_disp_rm_rn_l_D_1110_M_1110_N_0010,
	load_disp_rm_rn_l_D_1111_M_1110_N_0010,
	load_disp_rm_rn_l_D_0000_M_1111_N_0010,
	load_disp_rm_rn_l_D_0001_M_1111_N_0010,
	load_disp_rm_rn_l_D_0010_M_1111_N_0010,
	load_disp_rm_rn_l_D_0011_M_1111_N_0010,
	load_disp_rm_rn_l_D_0100_M_1111_N_0010,
	load_disp_rm_rn_l_D_0101_M_1111_N_0010,
	load_disp_rm_rn_l_D_0110_M_1111_N_0010,
	load_disp_rm_rn_l_D_0111_M_1111_N_0010,
	load_disp_rm_rn_l_D_1000_M_1111_N_0010,
	load_disp_rm_rn_l_D_1001_M_1111_N_0010,
	load_disp_rm_rn_l_D_1010_M_1111_N_0010,
	load_disp_rm_rn_l_D_1011_M_1111_N_0010,
	load_disp_rm_rn_l_D_1100_M_1111_N_0010,
	load_disp_rm_rn_l_D_1101_M_1111_N_0010,
	load_disp_rm_rn_l_D_1110_M_1111_N_0010,
	load_disp_rm_rn_l_D_1111_M_1111_N_0010,
	load_disp_rm_rn_l_D_0000_M_0000_N_0011,
	load_disp_rm_rn_l_D_0001_M_0000_N_0011,
	load_disp_rm_rn_l_D_0010_M_0000_N_0011,
	load_disp_rm_rn_l_D_0011_M_0000_N_0011,
	load_disp_rm_rn_l_D_0100_M_0000_N_0011,
	load_disp_rm_rn_l_D_0101_M_0000_N_0011,
	load_disp_rm_rn_l_D_0110_M_0000_N_0011,
	load_disp_rm_rn_l_D_0111_M_0000_N_0011,
	load_disp_rm_rn_l_D_1000_M_0000_N_0011,
	load_disp_rm_rn_l_D_1001_M_0000_N_0011,
	load_disp_rm_rn_l_D_1010_M_0000_N_0011,
	load_disp_rm_rn_l_D_1011_M_0000_N_0011,
	load_disp_rm_rn_l_D_1100_M_0000_N_0011,
	load_disp_rm_rn_l_D_1101_M_0000_N_0011,
	load_disp_rm_rn_l_D_1110_M_0000_N_0011,
	load_disp_rm_rn_l_D_1111_M_0000_N_0011,
	load_disp_rm_rn_l_D_0000_M_0001_N_0011,
	load_disp_rm_rn_l_D_0001_M_0001_N_0011,
	load_disp_rm_rn_l_D_0010_M_0001_N_0011,
	load_disp_rm_rn_l_D_0011_M_0001_N_0011,
	load_disp_rm_rn_l_D_0100_M_0001_N_0011,
	load_disp_rm_rn_l_D_0101_M_0001_N_0011,
	load_disp_rm_rn_l_D_0110_M_0001_N_0011,
	load_disp_rm_rn_l_D_0111_M_0001_N_0011,
	load_disp_rm_rn_l_D_1000_M_0001_N_0011,
	load_disp_rm_rn_l_D_1001_M_0001_N_0011,
	load_disp_rm_rn_l_D_1010_M_0001_N_0011,
	load_disp_rm_rn_l_D_1011_M_0001_N_0011,
	load_disp_rm_rn_l_D_1100_M_0001_N_0011,
	load_disp_rm_rn_l_D_1101_M_0001_N_0011,
	load_disp_rm_rn_l_D_1110_M_0001_N_0011,
	load_disp_rm_rn_l_D_1111_M_0001_N_0011,
	load_disp_rm_rn_l_D_0000_M_0010_N_0011,
	load_disp_rm_rn_l_D_0001_M_0010_N_0011,
	load_disp_rm_rn_l_D_0010_M_0010_N_0011,
	load_disp_rm_rn_l_D_0011_M_0010_N_0011,
	load_disp_rm_rn_l_D_0100_M_0010_N_0011,
	load_disp_rm_rn_l_D_0101_M_0010_N_0011,
	load_disp_rm_rn_l_D_0110_M_0010_N_0011,
	load_disp_rm_rn_l_D_0111_M_0010_N_0011,
	load_disp_rm_rn_l_D_1000_M_0010_N_0011,
	load_disp_rm_rn_l_D_1001_M_0010_N_0011,
	load_disp_rm_rn_l_D_1010_M_0010_N_0011,
	load_disp_rm_rn_l_D_1011_M_0010_N_0011,
	load_disp_rm_rn_l_D_1100_M_0010_N_0011,
	load_disp_rm_rn_l_D_1101_M_0010_N_0011,
	load_disp_rm_rn_l_D_1110_M_0010_N_0011,
	load_disp_rm_rn_l_D_1111_M_0010_N_0011,
	load_disp_rm_rn_l_D_0000_M_0011_N_0011,
	load_disp_rm_rn_l_D_0001_M_0011_N_0011,
	load_disp_rm_rn_l_D_0010_M_0011_N_0011,
	load_disp_rm_rn_l_D_0011_M_0011_N_0011,
	load_disp_rm_rn_l_D_0100_M_0011_N_0011,
	load_disp_rm_rn_l_D_0101_M_0011_N_0011,
	load_disp_rm_rn_l_D_0110_M_0011_N_0011,
	load_disp_rm_rn_l_D_0111_M_0011_N_0011,
	load_disp_rm_rn_l_D_1000_M_0011_N_0011,
	load_disp_rm_rn_l_D_1001_M_0011_N_0011,
	load_disp_rm_rn_l_D_1010_M_0011_N_0011,
	load_disp_rm_rn_l_D_1011_M_0011_N_0011,
	load_disp_rm_rn_l_D_1100_M_0011_N_0011,
	load_disp_rm_rn_l_D_1101_M_0011_N_0011,
	load_disp_rm_rn_l_D_1110_M_0011_N_0011,
	load_disp_rm_rn_l_D_1111_M_0011_N_0011,
	load_disp_rm_rn_l_D_0000_M_0100_N_0011,
	load_disp_rm_rn_l_D_0001_M_0100_N_0011,
	load_disp_rm_rn_l_D_0010_M_0100_N_0011,
	load_disp_rm_rn_l_D_0011_M_0100_N_0011,
	load_disp_rm_rn_l_D_0100_M_0100_N_0011,
	load_disp_rm_rn_l_D_0101_M_0100_N_0011,
	load_disp_rm_rn_l_D_0110_M_0100_N_0011,
	load_disp_rm_rn_l_D_0111_M_0100_N_0011,
	load_disp_rm_rn_l_D_1000_M_0100_N_0011,
	load_disp_rm_rn_l_D_1001_M_0100_N_0011,
	load_disp_rm_rn_l_D_1010_M_0100_N_0011,
	load_disp_rm_rn_l_D_1011_M_0100_N_0011,
	load_disp_rm_rn_l_D_1100_M_0100_N_0011,
	load_disp_rm_rn_l_D_1101_M_0100_N_0011,
	load_disp_rm_rn_l_D_1110_M_0100_N_0011,
	load_disp_rm_rn_l_D_1111_M_0100_N_0011,
	load_disp_rm_rn_l_D_0000_M_0101_N_0011,
	load_disp_rm_rn_l_D_0001_M_0101_N_0011,
	load_disp_rm_rn_l_D_0010_M_0101_N_0011,
	load_disp_rm_rn_l_D_0011_M_0101_N_0011,
	load_disp_rm_rn_l_D_0100_M_0101_N_0011,
	load_disp_rm_rn_l_D_0101_M_0101_N_0011,
	load_disp_rm_rn_l_D_0110_M_0101_N_0011,
	load_disp_rm_rn_l_D_0111_M_0101_N_0011,
	load_disp_rm_rn_l_D_1000_M_0101_N_0011,
	load_disp_rm_rn_l_D_1001_M_0101_N_0011,
	load_disp_rm_rn_l_D_1010_M_0101_N_0011,
	load_disp_rm_rn_l_D_1011_M_0101_N_0011,
	load_disp_rm_rn_l_D_1100_M_0101_N_0011,
	load_disp_rm_rn_l_D_1101_M_0101_N_0011,
	load_disp_rm_rn_l_D_1110_M_0101_N_0011,
	load_disp_rm_rn_l_D_1111_M_0101_N_0011,
	load_disp_rm_rn_l_D_0000_M_0110_N_0011,
	load_disp_rm_rn_l_D_0001_M_0110_N_0011,
	load_disp_rm_rn_l_D_0010_M_0110_N_0011,
	load_disp_rm_rn_l_D_0011_M_0110_N_0011,
	load_disp_rm_rn_l_D_0100_M_0110_N_0011,
	load_disp_rm_rn_l_D_0101_M_0110_N_0011,
	load_disp_rm_rn_l_D_0110_M_0110_N_0011,
	load_disp_rm_rn_l_D_0111_M_0110_N_0011,
	load_disp_rm_rn_l_D_1000_M_0110_N_0011,
	load_disp_rm_rn_l_D_1001_M_0110_N_0011,
	load_disp_rm_rn_l_D_1010_M_0110_N_0011,
	load_disp_rm_rn_l_D_1011_M_0110_N_0011,
	load_disp_rm_rn_l_D_1100_M_0110_N_0011,
	load_disp_rm_rn_l_D_1101_M_0110_N_0011,
	load_disp_rm_rn_l_D_1110_M_0110_N_0011,
	load_disp_rm_rn_l_D_1111_M_0110_N_0011,
	load_disp_rm_rn_l_D_0000_M_0111_N_0011,
	load_disp_rm_rn_l_D_0001_M_0111_N_0011,
	load_disp_rm_rn_l_D_0010_M_0111_N_0011,
	load_disp_rm_rn_l_D_0011_M_0111_N_0011,
	load_disp_rm_rn_l_D_0100_M_0111_N_0011,
	load_disp_rm_rn_l_D_0101_M_0111_N_0011,
	load_disp_rm_rn_l_D_0110_M_0111_N_0011,
	load_disp_rm_rn_l_D_0111_M_0111_N_0011,
	load_disp_rm_rn_l_D_1000_M_0111_N_0011,
	load_disp_rm_rn_l_D_1001_M_0111_N_0011,
	load_disp_rm_rn_l_D_1010_M_0111_N_0011,
	load_disp_rm_rn_l_D_1011_M_0111_N_0011,
	load_disp_rm_rn_l_D_1100_M_0111_N_0011,
	load_disp_rm_rn_l_D_1101_M_0111_N_0011,
	load_disp_rm_rn_l_D_1110_M_0111_N_0011,
	load_disp_rm_rn_l_D_1111_M_0111_N_0011,
	load_disp_rm_rn_l_D_0000_M_1000_N_0011,
	load_disp_rm_rn_l_D_0001_M_1000_N_0011,
	load_disp_rm_rn_l_D_0010_M_1000_N_0011,
	load_disp_rm_rn_l_D_0011_M_1000_N_0011,
	load_disp_rm_rn_l_D_0100_M_1000_N_0011,
	load_disp_rm_rn_l_D_0101_M_1000_N_0011,
	load_disp_rm_rn_l_D_0110_M_1000_N_0011,
	load_disp_rm_rn_l_D_0111_M_1000_N_0011,
	load_disp_rm_rn_l_D_1000_M_1000_N_0011,
	load_disp_rm_rn_l_D_1001_M_1000_N_0011,
	load_disp_rm_rn_l_D_1010_M_1000_N_0011,
	load_disp_rm_rn_l_D_1011_M_1000_N_0011,
	load_disp_rm_rn_l_D_1100_M_1000_N_0011,
	load_disp_rm_rn_l_D_1101_M_1000_N_0011,
	load_disp_rm_rn_l_D_1110_M_1000_N_0011,
	load_disp_rm_rn_l_D_1111_M_1000_N_0011,
	load_disp_rm_rn_l_D_0000_M_1001_N_0011,
	load_disp_rm_rn_l_D_0001_M_1001_N_0011,
	load_disp_rm_rn_l_D_0010_M_1001_N_0011,
	load_disp_rm_rn_l_D_0011_M_1001_N_0011,
	load_disp_rm_rn_l_D_0100_M_1001_N_0011,
	load_disp_rm_rn_l_D_0101_M_1001_N_0011,
	load_disp_rm_rn_l_D_0110_M_1001_N_0011,
	load_disp_rm_rn_l_D_0111_M_1001_N_0011,
	load_disp_rm_rn_l_D_1000_M_1001_N_0011,
	load_disp_rm_rn_l_D_1001_M_1001_N_0011,
	load_disp_rm_rn_l_D_1010_M_1001_N_0011,
	load_disp_rm_rn_l_D_1011_M_1001_N_0011,
	load_disp_rm_rn_l_D_1100_M_1001_N_0011,
	load_disp_rm_rn_l_D_1101_M_1001_N_0011,
	load_disp_rm_rn_l_D_1110_M_1001_N_0011,
	load_disp_rm_rn_l_D_1111_M_1001_N_0011,
	load_disp_rm_rn_l_D_0000_M_1010_N_0011,
	load_disp_rm_rn_l_D_0001_M_1010_N_0011,
	load_disp_rm_rn_l_D_0010_M_1010_N_0011,
	load_disp_rm_rn_l_D_0011_M_1010_N_0011,
	load_disp_rm_rn_l_D_0100_M_1010_N_0011,
	load_disp_rm_rn_l_D_0101_M_1010_N_0011,
	load_disp_rm_rn_l_D_0110_M_1010_N_0011,
	load_disp_rm_rn_l_D_0111_M_1010_N_0011,
	load_disp_rm_rn_l_D_1000_M_1010_N_0011,
	load_disp_rm_rn_l_D_1001_M_1010_N_0011,
	load_disp_rm_rn_l_D_1010_M_1010_N_0011,
	load_disp_rm_rn_l_D_1011_M_1010_N_0011,
	load_disp_rm_rn_l_D_1100_M_1010_N_0011,
	load_disp_rm_rn_l_D_1101_M_1010_N_0011,
	load_disp_rm_rn_l_D_1110_M_1010_N_0011,
	load_disp_rm_rn_l_D_1111_M_1010_N_0011,
	load_disp_rm_rn_l_D_0000_M_1011_N_0011,
	load_disp_rm_rn_l_D_0001_M_1011_N_0011,
	load_disp_rm_rn_l_D_0010_M_1011_N_0011,
	load_disp_rm_rn_l_D_0011_M_1011_N_0011,
	load_disp_rm_rn_l_D_0100_M_1011_N_0011,
	load_disp_rm_rn_l_D_0101_M_1011_N_0011,
	load_disp_rm_rn_l_D_0110_M_1011_N_0011,
	load_disp_rm_rn_l_D_0111_M_1011_N_0011,
	load_disp_rm_rn_l_D_1000_M_1011_N_0011,
	load_disp_rm_rn_l_D_1001_M_1011_N_0011,
	load_disp_rm_rn_l_D_1010_M_1011_N_0011,
	load_disp_rm_rn_l_D_1011_M_1011_N_0011,
	load_disp_rm_rn_l_D_1100_M_1011_N_0011,
	load_disp_rm_rn_l_D_1101_M_1011_N_0011,
	load_disp_rm_rn_l_D_1110_M_1011_N_0011,
	load_disp_rm_rn_l_D_1111_M_1011_N_0011,
	load_disp_rm_rn_l_D_0000_M_1100_N_0011,
	load_disp_rm_rn_l_D_0001_M_1100_N_0011,
	load_disp_rm_rn_l_D_0010_M_1100_N_0011,
	load_disp_rm_rn_l_D_0011_M_1100_N_0011,
	load_disp_rm_rn_l_D_0100_M_1100_N_0011,
	load_disp_rm_rn_l_D_0101_M_1100_N_0011,
	load_disp_rm_rn_l_D_0110_M_1100_N_0011,
	load_disp_rm_rn_l_D_0111_M_1100_N_0011,
	load_disp_rm_rn_l_D_1000_M_1100_N_0011,
	load_disp_rm_rn_l_D_1001_M_1100_N_0011,
	load_disp_rm_rn_l_D_1010_M_1100_N_0011,
	load_disp_rm_rn_l_D_1011_M_1100_N_0011,
	load_disp_rm_rn_l_D_1100_M_1100_N_0011,
	load_disp_rm_rn_l_D_1101_M_1100_N_0011,
	load_disp_rm_rn_l_D_1110_M_1100_N_0011,
	load_disp_rm_rn_l_D_1111_M_1100_N_0011,
	load_disp_rm_rn_l_D_0000_M_1101_N_0011,
	load_disp_rm_rn_l_D_0001_M_1101_N_0011,
	load_disp_rm_rn_l_D_0010_M_1101_N_0011,
	load_disp_rm_rn_l_D_0011_M_1101_N_0011,
	load_disp_rm_rn_l_D_0100_M_1101_N_0011,
	load_disp_rm_rn_l_D_0101_M_1101_N_0011,
	load_disp_rm_rn_l_D_0110_M_1101_N_0011,
	load_disp_rm_rn_l_D_0111_M_1101_N_0011,
	load_disp_rm_rn_l_D_1000_M_1101_N_0011,
	load_disp_rm_rn_l_D_1001_M_1101_N_0011,
	load_disp_rm_rn_l_D_1010_M_1101_N_0011,
	load_disp_rm_rn_l_D_1011_M_1101_N_0011,
	load_disp_rm_rn_l_D_1100_M_1101_N_0011,
	load_disp_rm_rn_l_D_1101_M_1101_N_0011,
	load_disp_rm_rn_l_D_1110_M_1101_N_0011,
	load_disp_rm_rn_l_D_1111_M_1101_N_0011,
	load_disp_rm_rn_l_D_0000_M_1110_N_0011,
	load_disp_rm_rn_l_D_0001_M_1110_N_0011,
	load_disp_rm_rn_l_D_0010_M_1110_N_0011,
	load_disp_rm_rn_l_D_0011_M_1110_N_0011,
	load_disp_rm_rn_l_D_0100_M_1110_N_0011,
	load_disp_rm_rn_l_D_0101_M_1110_N_0011,
	load_disp_rm_rn_l_D_0110_M_1110_N_0011,
	load_disp_rm_rn_l_D_0111_M_1110_N_0011,
	load_disp_rm_rn_l_D_1000_M_1110_N_0011,
	load_disp_rm_rn_l_D_1001_M_1110_N_0011,
	load_disp_rm_rn_l_D_1010_M_1110_N_0011,
	load_disp_rm_rn_l_D_1011_M_1110_N_0011,
	load_disp_rm_rn_l_D_1100_M_1110_N_0011,
	load_disp_rm_rn_l_D_1101_M_1110_N_0011,
	load_disp_rm_rn_l_D_1110_M_1110_N_0011,
	load_disp_rm_rn_l_D_1111_M_1110_N_0011,
	load_disp_rm_rn_l_D_0000_M_1111_N_0011,
	load_disp_rm_rn_l_D_0001_M_1111_N_0011,
	load_disp_rm_rn_l_D_0010_M_1111_N_0011,
	load_disp_rm_rn_l_D_0011_M_1111_N_0011,
	load_disp_rm_rn_l_D_0100_M_1111_N_0011,
	load_disp_rm_rn_l_D_0101_M_1111_N_0011,
	load_disp_rm_rn_l_D_0110_M_1111_N_0011,
	load_disp_rm_rn_l_D_0111_M_1111_N_0011,
	load_disp_rm_rn_l_D_1000_M_1111_N_0011,
	load_disp_rm_rn_l_D_1001_M_1111_N_0011,
	load_disp_rm_rn_l_D_1010_M_1111_N_0011,
	load_disp_rm_rn_l_D_1011_M_1111_N_0011,
	load_disp_rm_rn_l_D_1100_M_1111_N_0011,
	load_disp_rm_rn_l_D_1101_M_1111_N_0011,
	load_disp_rm_rn_l_D_1110_M_1111_N_0011,
	load_disp_rm_rn_l_D_1111_M_1111_N_0011,
	load_disp_rm_rn_l_D_0000_M_0000_N_0100,
	load_disp_rm_rn_l_D_0001_M_0000_N_0100,
	load_disp_rm_rn_l_D_0010_M_0000_N_0100,
	load_disp_rm_rn_l_D_0011_M_0000_N_0100,
	load_disp_rm_rn_l_D_0100_M_0000_N_0100,
	load_disp_rm_rn_l_D_0101_M_0000_N_0100,
	load_disp_rm_rn_l_D_0110_M_0000_N_0100,
	load_disp_rm_rn_l_D_0111_M_0000_N_0100,
	load_disp_rm_rn_l_D_1000_M_0000_N_0100,
	load_disp_rm_rn_l_D_1001_M_0000_N_0100,
	load_disp_rm_rn_l_D_1010_M_0000_N_0100,
	load_disp_rm_rn_l_D_1011_M_0000_N_0100,
	load_disp_rm_rn_l_D_1100_M_0000_N_0100,
	load_disp_rm_rn_l_D_1101_M_0000_N_0100,
	load_disp_rm_rn_l_D_1110_M_0000_N_0100,
	load_disp_rm_rn_l_D_1111_M_0000_N_0100,
	load_disp_rm_rn_l_D_0000_M_0001_N_0100,
	load_disp_rm_rn_l_D_0001_M_0001_N_0100,
	load_disp_rm_rn_l_D_0010_M_0001_N_0100,
	load_disp_rm_rn_l_D_0011_M_0001_N_0100,
	load_disp_rm_rn_l_D_0100_M_0001_N_0100,
	load_disp_rm_rn_l_D_0101_M_0001_N_0100,
	load_disp_rm_rn_l_D_0110_M_0001_N_0100,
	load_disp_rm_rn_l_D_0111_M_0001_N_0100,
	load_disp_rm_rn_l_D_1000_M_0001_N_0100,
	load_disp_rm_rn_l_D_1001_M_0001_N_0100,
	load_disp_rm_rn_l_D_1010_M_0001_N_0100,
	load_disp_rm_rn_l_D_1011_M_0001_N_0100,
	load_disp_rm_rn_l_D_1100_M_0001_N_0100,
	load_disp_rm_rn_l_D_1101_M_0001_N_0100,
	load_disp_rm_rn_l_D_1110_M_0001_N_0100,
	load_disp_rm_rn_l_D_1111_M_0001_N_0100,
	load_disp_rm_rn_l_D_0000_M_0010_N_0100,
	load_disp_rm_rn_l_D_0001_M_0010_N_0100,
	load_disp_rm_rn_l_D_0010_M_0010_N_0100,
	load_disp_rm_rn_l_D_0011_M_0010_N_0100,
	load_disp_rm_rn_l_D_0100_M_0010_N_0100,
	load_disp_rm_rn_l_D_0101_M_0010_N_0100,
	load_disp_rm_rn_l_D_0110_M_0010_N_0100,
	load_disp_rm_rn_l_D_0111_M_0010_N_0100,
	load_disp_rm_rn_l_D_1000_M_0010_N_0100,
	load_disp_rm_rn_l_D_1001_M_0010_N_0100,
	load_disp_rm_rn_l_D_1010_M_0010_N_0100,
	load_disp_rm_rn_l_D_1011_M_0010_N_0100,
	load_disp_rm_rn_l_D_1100_M_0010_N_0100,
	load_disp_rm_rn_l_D_1101_M_0010_N_0100,
	load_disp_rm_rn_l_D_1110_M_0010_N_0100,
	load_disp_rm_rn_l_D_1111_M_0010_N_0100,
	load_disp_rm_rn_l_D_0000_M_0011_N_0100,
	load_disp_rm_rn_l_D_0001_M_0011_N_0100,
	load_disp_rm_rn_l_D_0010_M_0011_N_0100,
	load_disp_rm_rn_l_D_0011_M_0011_N_0100,
	load_disp_rm_rn_l_D_0100_M_0011_N_0100,
	load_disp_rm_rn_l_D_0101_M_0011_N_0100,
	load_disp_rm_rn_l_D_0110_M_0011_N_0100,
	load_disp_rm_rn_l_D_0111_M_0011_N_0100,
	load_disp_rm_rn_l_D_1000_M_0011_N_0100,
	load_disp_rm_rn_l_D_1001_M_0011_N_0100,
	load_disp_rm_rn_l_D_1010_M_0011_N_0100,
	load_disp_rm_rn_l_D_1011_M_0011_N_0100,
	load_disp_rm_rn_l_D_1100_M_0011_N_0100,
	load_disp_rm_rn_l_D_1101_M_0011_N_0100,
	load_disp_rm_rn_l_D_1110_M_0011_N_0100,
	load_disp_rm_rn_l_D_1111_M_0011_N_0100,
	load_disp_rm_rn_l_D_0000_M_0100_N_0100,
	load_disp_rm_rn_l_D_0001_M_0100_N_0100,
	load_disp_rm_rn_l_D_0010_M_0100_N_0100,
	load_disp_rm_rn_l_D_0011_M_0100_N_0100,
	load_disp_rm_rn_l_D_0100_M_0100_N_0100,
	load_disp_rm_rn_l_D_0101_M_0100_N_0100,
	load_disp_rm_rn_l_D_0110_M_0100_N_0100,
	load_disp_rm_rn_l_D_0111_M_0100_N_0100,
	load_disp_rm_rn_l_D_1000_M_0100_N_0100,
	load_disp_rm_rn_l_D_1001_M_0100_N_0100,
	load_disp_rm_rn_l_D_1010_M_0100_N_0100,
	load_disp_rm_rn_l_D_1011_M_0100_N_0100,
	load_disp_rm_rn_l_D_1100_M_0100_N_0100,
	load_disp_rm_rn_l_D_1101_M_0100_N_0100,
	load_disp_rm_rn_l_D_1110_M_0100_N_0100,
	load_disp_rm_rn_l_D_1111_M_0100_N_0100,
	load_disp_rm_rn_l_D_0000_M_0101_N_0100,
	load_disp_rm_rn_l_D_0001_M_0101_N_0100,
	load_disp_rm_rn_l_D_0010_M_0101_N_0100,
	load_disp_rm_rn_l_D_0011_M_0101_N_0100,
	load_disp_rm_rn_l_D_0100_M_0101_N_0100,
	load_disp_rm_rn_l_D_0101_M_0101_N_0100,
	load_disp_rm_rn_l_D_0110_M_0101_N_0100,
	load_disp_rm_rn_l_D_0111_M_0101_N_0100,
	load_disp_rm_rn_l_D_1000_M_0101_N_0100,
	load_disp_rm_rn_l_D_1001_M_0101_N_0100,
	load_disp_rm_rn_l_D_1010_M_0101_N_0100,
	load_disp_rm_rn_l_D_1011_M_0101_N_0100,
	load_disp_rm_rn_l_D_1100_M_0101_N_0100,
	load_disp_rm_rn_l_D_1101_M_0101_N_0100,
	load_disp_rm_rn_l_D_1110_M_0101_N_0100,
	load_disp_rm_rn_l_D_1111_M_0101_N_0100,
	load_disp_rm_rn_l_D_0000_M_0110_N_0100,
	load_disp_rm_rn_l_D_0001_M_0110_N_0100,
	load_disp_rm_rn_l_D_0010_M_0110_N_0100,
	load_disp_rm_rn_l_D_0011_M_0110_N_0100,
	load_disp_rm_rn_l_D_0100_M_0110_N_0100,
	load_disp_rm_rn_l_D_0101_M_0110_N_0100,
	load_disp_rm_rn_l_D_0110_M_0110_N_0100,
	load_disp_rm_rn_l_D_0111_M_0110_N_0100,
	load_disp_rm_rn_l_D_1000_M_0110_N_0100,
	load_disp_rm_rn_l_D_1001_M_0110_N_0100,
	load_disp_rm_rn_l_D_1010_M_0110_N_0100,
	load_disp_rm_rn_l_D_1011_M_0110_N_0100,
	load_disp_rm_rn_l_D_1100_M_0110_N_0100,
	load_disp_rm_rn_l_D_1101_M_0110_N_0100,
	load_disp_rm_rn_l_D_1110_M_0110_N_0100,
	load_disp_rm_rn_l_D_1111_M_0110_N_0100,
	load_disp_rm_rn_l_D_0000_M_0111_N_0100,
	load_disp_rm_rn_l_D_0001_M_0111_N_0100,
	load_disp_rm_rn_l_D_0010_M_0111_N_0100,
	load_disp_rm_rn_l_D_0011_M_0111_N_0100,
	load_disp_rm_rn_l_D_0100_M_0111_N_0100,
	load_disp_rm_rn_l_D_0101_M_0111_N_0100,
	load_disp_rm_rn_l_D_0110_M_0111_N_0100,
	load_disp_rm_rn_l_D_0111_M_0111_N_0100,
	load_disp_rm_rn_l_D_1000_M_0111_N_0100,
	load_disp_rm_rn_l_D_1001_M_0111_N_0100,
	load_disp_rm_rn_l_D_1010_M_0111_N_0100,
	load_disp_rm_rn_l_D_1011_M_0111_N_0100,
	load_disp_rm_rn_l_D_1100_M_0111_N_0100,
	load_disp_rm_rn_l_D_1101_M_0111_N_0100,
	load_disp_rm_rn_l_D_1110_M_0111_N_0100,
	load_disp_rm_rn_l_D_1111_M_0111_N_0100,
	load_disp_rm_rn_l_D_0000_M_1000_N_0100,
	load_disp_rm_rn_l_D_0001_M_1000_N_0100,
	load_disp_rm_rn_l_D_0010_M_1000_N_0100,
	load_disp_rm_rn_l_D_0011_M_1000_N_0100,
	load_disp_rm_rn_l_D_0100_M_1000_N_0100,
	load_disp_rm_rn_l_D_0101_M_1000_N_0100,
	load_disp_rm_rn_l_D_0110_M_1000_N_0100,
	load_disp_rm_rn_l_D_0111_M_1000_N_0100,
	load_disp_rm_rn_l_D_1000_M_1000_N_0100,
	load_disp_rm_rn_l_D_1001_M_1000_N_0100,
	load_disp_rm_rn_l_D_1010_M_1000_N_0100,
	load_disp_rm_rn_l_D_1011_M_1000_N_0100,
	load_disp_rm_rn_l_D_1100_M_1000_N_0100,
	load_disp_rm_rn_l_D_1101_M_1000_N_0100,
	load_disp_rm_rn_l_D_1110_M_1000_N_0100,
	load_disp_rm_rn_l_D_1111_M_1000_N_0100,
	load_disp_rm_rn_l_D_0000_M_1001_N_0100,
	load_disp_rm_rn_l_D_0001_M_1001_N_0100,
	load_disp_rm_rn_l_D_0010_M_1001_N_0100,
	load_disp_rm_rn_l_D_0011_M_1001_N_0100,
	load_disp_rm_rn_l_D_0100_M_1001_N_0100,
	load_disp_rm_rn_l_D_0101_M_1001_N_0100,
	load_disp_rm_rn_l_D_0110_M_1001_N_0100,
	load_disp_rm_rn_l_D_0111_M_1001_N_0100,
	load_disp_rm_rn_l_D_1000_M_1001_N_0100,
	load_disp_rm_rn_l_D_1001_M_1001_N_0100,
	load_disp_rm_rn_l_D_1010_M_1001_N_0100,
	load_disp_rm_rn_l_D_1011_M_1001_N_0100,
	load_disp_rm_rn_l_D_1100_M_1001_N_0100,
	load_disp_rm_rn_l_D_1101_M_1001_N_0100,
	load_disp_rm_rn_l_D_1110_M_1001_N_0100,
	load_disp_rm_rn_l_D_1111_M_1001_N_0100,
	load_disp_rm_rn_l_D_0000_M_1010_N_0100,
	load_disp_rm_rn_l_D_0001_M_1010_N_0100,
	load_disp_rm_rn_l_D_0010_M_1010_N_0100,
	load_disp_rm_rn_l_D_0011_M_1010_N_0100,
	load_disp_rm_rn_l_D_0100_M_1010_N_0100,
	load_disp_rm_rn_l_D_0101_M_1010_N_0100,
	load_disp_rm_rn_l_D_0110_M_1010_N_0100,
	load_disp_rm_rn_l_D_0111_M_1010_N_0100,
	load_disp_rm_rn_l_D_1000_M_1010_N_0100,
	load_disp_rm_rn_l_D_1001_M_1010_N_0100,
	load_disp_rm_rn_l_D_1010_M_1010_N_0100,
	load_disp_rm_rn_l_D_1011_M_1010_N_0100,
	load_disp_rm_rn_l_D_1100_M_1010_N_0100,
	load_disp_rm_rn_l_D_1101_M_1010_N_0100,
	load_disp_rm_rn_l_D_1110_M_1010_N_0100,
	load_disp_rm_rn_l_D_1111_M_1010_N_0100,
	load_disp_rm_rn_l_D_0000_M_1011_N_0100,
	load_disp_rm_rn_l_D_0001_M_1011_N_0100,
	load_disp_rm_rn_l_D_0010_M_1011_N_0100,
	load_disp_rm_rn_l_D_0011_M_1011_N_0100,
	load_disp_rm_rn_l_D_0100_M_1011_N_0100,
	load_disp_rm_rn_l_D_0101_M_1011_N_0100,
	load_disp_rm_rn_l_D_0110_M_1011_N_0100,
	load_disp_rm_rn_l_D_0111_M_1011_N_0100,
	load_disp_rm_rn_l_D_1000_M_1011_N_0100,
	load_disp_rm_rn_l_D_1001_M_1011_N_0100,
	load_disp_rm_rn_l_D_1010_M_1011_N_0100,
	load_disp_rm_rn_l_D_1011_M_1011_N_0100,
	load_disp_rm_rn_l_D_1100_M_1011_N_0100,
	load_disp_rm_rn_l_D_1101_M_1011_N_0100,
	load_disp_rm_rn_l_D_1110_M_1011_N_0100,
	load_disp_rm_rn_l_D_1111_M_1011_N_0100,
	load_disp_rm_rn_l_D_0000_M_1100_N_0100,
	load_disp_rm_rn_l_D_0001_M_1100_N_0100,
	load_disp_rm_rn_l_D_0010_M_1100_N_0100,
	load_disp_rm_rn_l_D_0011_M_1100_N_0100,
	load_disp_rm_rn_l_D_0100_M_1100_N_0100,
	load_disp_rm_rn_l_D_0101_M_1100_N_0100,
	load_disp_rm_rn_l_D_0110_M_1100_N_0100,
	load_disp_rm_rn_l_D_0111_M_1100_N_0100,
	load_disp_rm_rn_l_D_1000_M_1100_N_0100,
	load_disp_rm_rn_l_D_1001_M_1100_N_0100,
	load_disp_rm_rn_l_D_1010_M_1100_N_0100,
	load_disp_rm_rn_l_D_1011_M_1100_N_0100,
	load_disp_rm_rn_l_D_1100_M_1100_N_0100,
	load_disp_rm_rn_l_D_1101_M_1100_N_0100,
	load_disp_rm_rn_l_D_1110_M_1100_N_0100,
	load_disp_rm_rn_l_D_1111_M_1100_N_0100,
	load_disp_rm_rn_l_D_0000_M_1101_N_0100,
	load_disp_rm_rn_l_D_0001_M_1101_N_0100,
	load_disp_rm_rn_l_D_0010_M_1101_N_0100,
	load_disp_rm_rn_l_D_0011_M_1101_N_0100,
	load_disp_rm_rn_l_D_0100_M_1101_N_0100,
	load_disp_rm_rn_l_D_0101_M_1101_N_0100,
	load_disp_rm_rn_l_D_0110_M_1101_N_0100,
	load_disp_rm_rn_l_D_0111_M_1101_N_0100,
	load_disp_rm_rn_l_D_1000_M_1101_N_0100,
	load_disp_rm_rn_l_D_1001_M_1101_N_0100,
	load_disp_rm_rn_l_D_1010_M_1101_N_0100,
	load_disp_rm_rn_l_D_1011_M_1101_N_0100,
	load_disp_rm_rn_l_D_1100_M_1101_N_0100,
	load_disp_rm_rn_l_D_1101_M_1101_N_0100,
	load_disp_rm_rn_l_D_1110_M_1101_N_0100,
	load_disp_rm_rn_l_D_1111_M_1101_N_0100,
	load_disp_rm_rn_l_D_0000_M_1110_N_0100,
	load_disp_rm_rn_l_D_0001_M_1110_N_0100,
	load_disp_rm_rn_l_D_0010_M_1110_N_0100,
	load_disp_rm_rn_l_D_0011_M_1110_N_0100,
	load_disp_rm_rn_l_D_0100_M_1110_N_0100,
	load_disp_rm_rn_l_D_0101_M_1110_N_0100,
	load_disp_rm_rn_l_D_0110_M_1110_N_0100,
	load_disp_rm_rn_l_D_0111_M_1110_N_0100,
	load_disp_rm_rn_l_D_1000_M_1110_N_0100,
	load_disp_rm_rn_l_D_1001_M_1110_N_0100,
	load_disp_rm_rn_l_D_1010_M_1110_N_0100,
	load_disp_rm_rn_l_D_1011_M_1110_N_0100,
	load_disp_rm_rn_l_D_1100_M_1110_N_0100,
	load_disp_rm_rn_l_D_1101_M_1110_N_0100,
	load_disp_rm_rn_l_D_1110_M_1110_N_0100,
	load_disp_rm_rn_l_D_1111_M_1110_N_0100,
	load_disp_rm_rn_l_D_0000_M_1111_N_0100,
	load_disp_rm_rn_l_D_0001_M_1111_N_0100,
	load_disp_rm_rn_l_D_0010_M_1111_N_0100,
	load_disp_rm_rn_l_D_0011_M_1111_N_0100,
	load_disp_rm_rn_l_D_0100_M_1111_N_0100,
	load_disp_rm_rn_l_D_0101_M_1111_N_0100,
	load_disp_rm_rn_l_D_0110_M_1111_N_0100,
	load_disp_rm_rn_l_D_0111_M_1111_N_0100,
	load_disp_rm_rn_l_D_1000_M_1111_N_0100,
	load_disp_rm_rn_l_D_1001_M_1111_N_0100,
	load_disp_rm_rn_l_D_1010_M_1111_N_0100,
	load_disp_rm_rn_l_D_1011_M_1111_N_0100,
	load_disp_rm_rn_l_D_1100_M_1111_N_0100,
	load_disp_rm_rn_l_D_1101_M_1111_N_0100,
	load_disp_rm_rn_l_D_1110_M_1111_N_0100,
	load_disp_rm_rn_l_D_1111_M_1111_N_0100,
	load_disp_rm_rn_l_D_0000_M_0000_N_0101,
	load_disp_rm_rn_l_D_0001_M_0000_N_0101,
	load_disp_rm_rn_l_D_0010_M_0000_N_0101,
	load_disp_rm_rn_l_D_0011_M_0000_N_0101,
	load_disp_rm_rn_l_D_0100_M_0000_N_0101,
	load_disp_rm_rn_l_D_0101_M_0000_N_0101,
	load_disp_rm_rn_l_D_0110_M_0000_N_0101,
	load_disp_rm_rn_l_D_0111_M_0000_N_0101,
	load_disp_rm_rn_l_D_1000_M_0000_N_0101,
	load_disp_rm_rn_l_D_1001_M_0000_N_0101,
	load_disp_rm_rn_l_D_1010_M_0000_N_0101,
	load_disp_rm_rn_l_D_1011_M_0000_N_0101,
	load_disp_rm_rn_l_D_1100_M_0000_N_0101,
	load_disp_rm_rn_l_D_1101_M_0000_N_0101,
	load_disp_rm_rn_l_D_1110_M_0000_N_0101,
	load_disp_rm_rn_l_D_1111_M_0000_N_0101,
	load_disp_rm_rn_l_D_0000_M_0001_N_0101,
	load_disp_rm_rn_l_D_0001_M_0001_N_0101,
	load_disp_rm_rn_l_D_0010_M_0001_N_0101,
	load_disp_rm_rn_l_D_0011_M_0001_N_0101,
	load_disp_rm_rn_l_D_0100_M_0001_N_0101,
	load_disp_rm_rn_l_D_0101_M_0001_N_0101,
	load_disp_rm_rn_l_D_0110_M_0001_N_0101,
	load_disp_rm_rn_l_D_0111_M_0001_N_0101,
	load_disp_rm_rn_l_D_1000_M_0001_N_0101,
	load_disp_rm_rn_l_D_1001_M_0001_N_0101,
	load_disp_rm_rn_l_D_1010_M_0001_N_0101,
	load_disp_rm_rn_l_D_1011_M_0001_N_0101,
	load_disp_rm_rn_l_D_1100_M_0001_N_0101,
	load_disp_rm_rn_l_D_1101_M_0001_N_0101,
	load_disp_rm_rn_l_D_1110_M_0001_N_0101,
	load_disp_rm_rn_l_D_1111_M_0001_N_0101,
	load_disp_rm_rn_l_D_0000_M_0010_N_0101,
	load_disp_rm_rn_l_D_0001_M_0010_N_0101,
	load_disp_rm_rn_l_D_0010_M_0010_N_0101,
	load_disp_rm_rn_l_D_0011_M_0010_N_0101,
	load_disp_rm_rn_l_D_0100_M_0010_N_0101,
	load_disp_rm_rn_l_D_0101_M_0010_N_0101,
	load_disp_rm_rn_l_D_0110_M_0010_N_0101,
	load_disp_rm_rn_l_D_0111_M_0010_N_0101,
	load_disp_rm_rn_l_D_1000_M_0010_N_0101,
	load_disp_rm_rn_l_D_1001_M_0010_N_0101,
	load_disp_rm_rn_l_D_1010_M_0010_N_0101,
	load_disp_rm_rn_l_D_1011_M_0010_N_0101,
	load_disp_rm_rn_l_D_1100_M_0010_N_0101,
	load_disp_rm_rn_l_D_1101_M_0010_N_0101,
	load_disp_rm_rn_l_D_1110_M_0010_N_0101,
	load_disp_rm_rn_l_D_1111_M_0010_N_0101,
	load_disp_rm_rn_l_D_0000_M_0011_N_0101,
	load_disp_rm_rn_l_D_0001_M_0011_N_0101,
	load_disp_rm_rn_l_D_0010_M_0011_N_0101,
	load_disp_rm_rn_l_D_0011_M_0011_N_0101,
	load_disp_rm_rn_l_D_0100_M_0011_N_0101,
	load_disp_rm_rn_l_D_0101_M_0011_N_0101,
	load_disp_rm_rn_l_D_0110_M_0011_N_0101,
	load_disp_rm_rn_l_D_0111_M_0011_N_0101,
	load_disp_rm_rn_l_D_1000_M_0011_N_0101,
	load_disp_rm_rn_l_D_1001_M_0011_N_0101,
	load_disp_rm_rn_l_D_1010_M_0011_N_0101,
	load_disp_rm_rn_l_D_1011_M_0011_N_0101,
	load_disp_rm_rn_l_D_1100_M_0011_N_0101,
	load_disp_rm_rn_l_D_1101_M_0011_N_0101,
	load_disp_rm_rn_l_D_1110_M_0011_N_0101,
	load_disp_rm_rn_l_D_1111_M_0011_N_0101,
	load_disp_rm_rn_l_D_0000_M_0100_N_0101,
	load_disp_rm_rn_l_D_0001_M_0100_N_0101,
	load_disp_rm_rn_l_D_0010_M_0100_N_0101,
	load_disp_rm_rn_l_D_0011_M_0100_N_0101,
	load_disp_rm_rn_l_D_0100_M_0100_N_0101,
	load_disp_rm_rn_l_D_0101_M_0100_N_0101,
	load_disp_rm_rn_l_D_0110_M_0100_N_0101,
	load_disp_rm_rn_l_D_0111_M_0100_N_0101,
	load_disp_rm_rn_l_D_1000_M_0100_N_0101,
	load_disp_rm_rn_l_D_1001_M_0100_N_0101,
	load_disp_rm_rn_l_D_1010_M_0100_N_0101,
	load_disp_rm_rn_l_D_1011_M_0100_N_0101,
	load_disp_rm_rn_l_D_1100_M_0100_N_0101,
	load_disp_rm_rn_l_D_1101_M_0100_N_0101,
	load_disp_rm_rn_l_D_1110_M_0100_N_0101,
	load_disp_rm_rn_l_D_1111_M_0100_N_0101,
	load_disp_rm_rn_l_D_0000_M_0101_N_0101,
	load_disp_rm_rn_l_D_0001_M_0101_N_0101,
	load_disp_rm_rn_l_D_0010_M_0101_N_0101,
	load_disp_rm_rn_l_D_0011_M_0101_N_0101,
	load_disp_rm_rn_l_D_0100_M_0101_N_0101,
	load_disp_rm_rn_l_D_0101_M_0101_N_0101,
	load_disp_rm_rn_l_D_0110_M_0101_N_0101,
	load_disp_rm_rn_l_D_0111_M_0101_N_0101,
	load_disp_rm_rn_l_D_1000_M_0101_N_0101,
	load_disp_rm_rn_l_D_1001_M_0101_N_0101,
	load_disp_rm_rn_l_D_1010_M_0101_N_0101,
	load_disp_rm_rn_l_D_1011_M_0101_N_0101,
	load_disp_rm_rn_l_D_1100_M_0101_N_0101,
	load_disp_rm_rn_l_D_1101_M_0101_N_0101,
	load_disp_rm_rn_l_D_1110_M_0101_N_0101,
	load_disp_rm_rn_l_D_1111_M_0101_N_0101,
	load_disp_rm_rn_l_D_0000_M_0110_N_0101,
	load_disp_rm_rn_l_D_0001_M_0110_N_0101,
	load_disp_rm_rn_l_D_0010_M_0110_N_0101,
	load_disp_rm_rn_l_D_0011_M_0110_N_0101,
	load_disp_rm_rn_l_D_0100_M_0110_N_0101,
	load_disp_rm_rn_l_D_0101_M_0110_N_0101,
	load_disp_rm_rn_l_D_0110_M_0110_N_0101,
	load_disp_rm_rn_l_D_0111_M_0110_N_0101,
	load_disp_rm_rn_l_D_1000_M_0110_N_0101,
	load_disp_rm_rn_l_D_1001_M_0110_N_0101,
	load_disp_rm_rn_l_D_1010_M_0110_N_0101,
	load_disp_rm_rn_l_D_1011_M_0110_N_0101,
	load_disp_rm_rn_l_D_1100_M_0110_N_0101,
	load_disp_rm_rn_l_D_1101_M_0110_N_0101,
	load_disp_rm_rn_l_D_1110_M_0110_N_0101,
	load_disp_rm_rn_l_D_1111_M_0110_N_0101,
	load_disp_rm_rn_l_D_0000_M_0111_N_0101,
	load_disp_rm_rn_l_D_0001_M_0111_N_0101,
	load_disp_rm_rn_l_D_0010_M_0111_N_0101,
	load_disp_rm_rn_l_D_0011_M_0111_N_0101,
	load_disp_rm_rn_l_D_0100_M_0111_N_0101,
	load_disp_rm_rn_l_D_0101_M_0111_N_0101,
	load_disp_rm_rn_l_D_0110_M_0111_N_0101,
	load_disp_rm_rn_l_D_0111_M_0111_N_0101,
	load_disp_rm_rn_l_D_1000_M_0111_N_0101,
	load_disp_rm_rn_l_D_1001_M_0111_N_0101,
	load_disp_rm_rn_l_D_1010_M_0111_N_0101,
	load_disp_rm_rn_l_D_1011_M_0111_N_0101,
	load_disp_rm_rn_l_D_1100_M_0111_N_0101,
	load_disp_rm_rn_l_D_1101_M_0111_N_0101,
	load_disp_rm_rn_l_D_1110_M_0111_N_0101,
	load_disp_rm_rn_l_D_1111_M_0111_N_0101,
	load_disp_rm_rn_l_D_0000_M_1000_N_0101,
	load_disp_rm_rn_l_D_0001_M_1000_N_0101,
	load_disp_rm_rn_l_D_0010_M_1000_N_0101,
	load_disp_rm_rn_l_D_0011_M_1000_N_0101,
	load_disp_rm_rn_l_D_0100_M_1000_N_0101,
	load_disp_rm_rn_l_D_0101_M_1000_N_0101,
	load_disp_rm_rn_l_D_0110_M_1000_N_0101,
	load_disp_rm_rn_l_D_0111_M_1000_N_0101,
	load_disp_rm_rn_l_D_1000_M_1000_N_0101,
	load_disp_rm_rn_l_D_1001_M_1000_N_0101,
	load_disp_rm_rn_l_D_1010_M_1000_N_0101,
	load_disp_rm_rn_l_D_1011_M_1000_N_0101,
	load_disp_rm_rn_l_D_1100_M_1000_N_0101,
	load_disp_rm_rn_l_D_1101_M_1000_N_0101,
	load_disp_rm_rn_l_D_1110_M_1000_N_0101,
	load_disp_rm_rn_l_D_1111_M_1000_N_0101,
	load_disp_rm_rn_l_D_0000_M_1001_N_0101,
	load_disp_rm_rn_l_D_0001_M_1001_N_0101,
	load_disp_rm_rn_l_D_0010_M_1001_N_0101,
	load_disp_rm_rn_l_D_0011_M_1001_N_0101,
	load_disp_rm_rn_l_D_0100_M_1001_N_0101,
	load_disp_rm_rn_l_D_0101_M_1001_N_0101,
	load_disp_rm_rn_l_D_0110_M_1001_N_0101,
	load_disp_rm_rn_l_D_0111_M_1001_N_0101,
	load_disp_rm_rn_l_D_1000_M_1001_N_0101,
	load_disp_rm_rn_l_D_1001_M_1001_N_0101,
	load_disp_rm_rn_l_D_1010_M_1001_N_0101,
	load_disp_rm_rn_l_D_1011_M_1001_N_0101,
	load_disp_rm_rn_l_D_1100_M_1001_N_0101,
	load_disp_rm_rn_l_D_1101_M_1001_N_0101,
	load_disp_rm_rn_l_D_1110_M_1001_N_0101,
	load_disp_rm_rn_l_D_1111_M_1001_N_0101,
	load_disp_rm_rn_l_D_0000_M_1010_N_0101,
	load_disp_rm_rn_l_D_0001_M_1010_N_0101,
	load_disp_rm_rn_l_D_0010_M_1010_N_0101,
	load_disp_rm_rn_l_D_0011_M_1010_N_0101,
	load_disp_rm_rn_l_D_0100_M_1010_N_0101,
	load_disp_rm_rn_l_D_0101_M_1010_N_0101,
	load_disp_rm_rn_l_D_0110_M_1010_N_0101,
	load_disp_rm_rn_l_D_0111_M_1010_N_0101,
	load_disp_rm_rn_l_D_1000_M_1010_N_0101,
	load_disp_rm_rn_l_D_1001_M_1010_N_0101,
	load_disp_rm_rn_l_D_1010_M_1010_N_0101,
	load_disp_rm_rn_l_D_1011_M_1010_N_0101,
	load_disp_rm_rn_l_D_1100_M_1010_N_0101,
	load_disp_rm_rn_l_D_1101_M_1010_N_0101,
	load_disp_rm_rn_l_D_1110_M_1010_N_0101,
	load_disp_rm_rn_l_D_1111_M_1010_N_0101,
	load_disp_rm_rn_l_D_0000_M_1011_N_0101,
	load_disp_rm_rn_l_D_0001_M_1011_N_0101,
	load_disp_rm_rn_l_D_0010_M_1011_N_0101,
	load_disp_rm_rn_l_D_0011_M_1011_N_0101,
	load_disp_rm_rn_l_D_0100_M_1011_N_0101,
	load_disp_rm_rn_l_D_0101_M_1011_N_0101,
	load_disp_rm_rn_l_D_0110_M_1011_N_0101,
	load_disp_rm_rn_l_D_0111_M_1011_N_0101,
	load_disp_rm_rn_l_D_1000_M_1011_N_0101,
	load_disp_rm_rn_l_D_1001_M_1011_N_0101,
	load_disp_rm_rn_l_D_1010_M_1011_N_0101,
	load_disp_rm_rn_l_D_1011_M_1011_N_0101,
	load_disp_rm_rn_l_D_1100_M_1011_N_0101,
	load_disp_rm_rn_l_D_1101_M_1011_N_0101,
	load_disp_rm_rn_l_D_1110_M_1011_N_0101,
	load_disp_rm_rn_l_D_1111_M_1011_N_0101,
	load_disp_rm_rn_l_D_0000_M_1100_N_0101,
	load_disp_rm_rn_l_D_0001_M_1100_N_0101,
	load_disp_rm_rn_l_D_0010_M_1100_N_0101,
	load_disp_rm_rn_l_D_0011_M_1100_N_0101,
	load_disp_rm_rn_l_D_0100_M_1100_N_0101,
	load_disp_rm_rn_l_D_0101_M_1100_N_0101,
	load_disp_rm_rn_l_D_0110_M_1100_N_0101,
	load_disp_rm_rn_l_D_0111_M_1100_N_0101,
	load_disp_rm_rn_l_D_1000_M_1100_N_0101,
	load_disp_rm_rn_l_D_1001_M_1100_N_0101,
	load_disp_rm_rn_l_D_1010_M_1100_N_0101,
	load_disp_rm_rn_l_D_1011_M_1100_N_0101,
	load_disp_rm_rn_l_D_1100_M_1100_N_0101,
	load_disp_rm_rn_l_D_1101_M_1100_N_0101,
	load_disp_rm_rn_l_D_1110_M_1100_N_0101,
	load_disp_rm_rn_l_D_1111_M_1100_N_0101,
	load_disp_rm_rn_l_D_0000_M_1101_N_0101,
	load_disp_rm_rn_l_D_0001_M_1101_N_0101,
	load_disp_rm_rn_l_D_0010_M_1101_N_0101,
	load_disp_rm_rn_l_D_0011_M_1101_N_0101,
	load_disp_rm_rn_l_D_0100_M_1101_N_0101,
	load_disp_rm_rn_l_D_0101_M_1101_N_0101,
	load_disp_rm_rn_l_D_0110_M_1101_N_0101,
	load_disp_rm_rn_l_D_0111_M_1101_N_0101,
	load_disp_rm_rn_l_D_1000_M_1101_N_0101,
	load_disp_rm_rn_l_D_1001_M_1101_N_0101,
	load_disp_rm_rn_l_D_1010_M_1101_N_0101,
	load_disp_rm_rn_l_D_1011_M_1101_N_0101,
	load_disp_rm_rn_l_D_1100_M_1101_N_0101,
	load_disp_rm_rn_l_D_1101_M_1101_N_0101,
	load_disp_rm_rn_l_D_1110_M_1101_N_0101,
	load_disp_rm_rn_l_D_1111_M_1101_N_0101,
	load_disp_rm_rn_l_D_0000_M_1110_N_0101,
	load_disp_rm_rn_l_D_0001_M_1110_N_0101,
	load_disp_rm_rn_l_D_0010_M_1110_N_0101,
	load_disp_rm_rn_l_D_0011_M_1110_N_0101,
	load_disp_rm_rn_l_D_0100_M_1110_N_0101,
	load_disp_rm_rn_l_D_0101_M_1110_N_0101,
	load_disp_rm_rn_l_D_0110_M_1110_N_0101,
	load_disp_rm_rn_l_D_0111_M_1110_N_0101,
	load_disp_rm_rn_l_D_1000_M_1110_N_0101,
	load_disp_rm_rn_l_D_1001_M_1110_N_0101,
	load_disp_rm_rn_l_D_1010_M_1110_N_0101,
	load_disp_rm_rn_l_D_1011_M_1110_N_0101,
	load_disp_rm_rn_l_D_1100_M_1110_N_0101,
	load_disp_rm_rn_l_D_1101_M_1110_N_0101,
	load_disp_rm_rn_l_D_1110_M_1110_N_0101,
	load_disp_rm_rn_l_D_1111_M_1110_N_0101,
	load_disp_rm_rn_l_D_0000_M_1111_N_0101,
	load_disp_rm_rn_l_D_0001_M_1111_N_0101,
	load_disp_rm_rn_l_D_0010_M_1111_N_0101,
	load_disp_rm_rn_l_D_0011_M_1111_N_0101,
	load_disp_rm_rn_l_D_0100_M_1111_N_0101,
	load_disp_rm_rn_l_D_0101_M_1111_N_0101,
	load_disp_rm_rn_l_D_0110_M_1111_N_0101,
	load_disp_rm_rn_l_D_0111_M_1111_N_0101,
	load_disp_rm_rn_l_D_1000_M_1111_N_0101,
	load_disp_rm_rn_l_D_1001_M_1111_N_0101,
	load_disp_rm_rn_l_D_1010_M_1111_N_0101,
	load_disp_rm_rn_l_D_1011_M_1111_N_0101,
	load_disp_rm_rn_l_D_1100_M_1111_N_0101,
	load_disp_rm_rn_l_D_1101_M_1111_N_0101,
	load_disp_rm_rn_l_D_1110_M_1111_N_0101,
	load_disp_rm_rn_l_D_1111_M_1111_N_0101,
	load_disp_rm_rn_l_D_0000_M_0000_N_0110,
	load_disp_rm_rn_l_D_0001_M_0000_N_0110,
	load_disp_rm_rn_l_D_0010_M_0000_N_0110,
	load_disp_rm_rn_l_D_0011_M_0000_N_0110,
	load_disp_rm_rn_l_D_0100_M_0000_N_0110,
	load_disp_rm_rn_l_D_0101_M_0000_N_0110,
	load_disp_rm_rn_l_D_0110_M_0000_N_0110,
	load_disp_rm_rn_l_D_0111_M_0000_N_0110,
	load_disp_rm_rn_l_D_1000_M_0000_N_0110,
	load_disp_rm_rn_l_D_1001_M_0000_N_0110,
	load_disp_rm_rn_l_D_1010_M_0000_N_0110,
	load_disp_rm_rn_l_D_1011_M_0000_N_0110,
	load_disp_rm_rn_l_D_1100_M_0000_N_0110,
	load_disp_rm_rn_l_D_1101_M_0000_N_0110,
	load_disp_rm_rn_l_D_1110_M_0000_N_0110,
	load_disp_rm_rn_l_D_1111_M_0000_N_0110,
	load_disp_rm_rn_l_D_0000_M_0001_N_0110,
	load_disp_rm_rn_l_D_0001_M_0001_N_0110,
	load_disp_rm_rn_l_D_0010_M_0001_N_0110,
	load_disp_rm_rn_l_D_0011_M_0001_N_0110,
	load_disp_rm_rn_l_D_0100_M_0001_N_0110,
	load_disp_rm_rn_l_D_0101_M_0001_N_0110,
	load_disp_rm_rn_l_D_0110_M_0001_N_0110,
	load_disp_rm_rn_l_D_0111_M_0001_N_0110,
	load_disp_rm_rn_l_D_1000_M_0001_N_0110,
	load_disp_rm_rn_l_D_1001_M_0001_N_0110,
	load_disp_rm_rn_l_D_1010_M_0001_N_0110,
	load_disp_rm_rn_l_D_1011_M_0001_N_0110,
	load_disp_rm_rn_l_D_1100_M_0001_N_0110,
	load_disp_rm_rn_l_D_1101_M_0001_N_0110,
	load_disp_rm_rn_l_D_1110_M_0001_N_0110,
	load_disp_rm_rn_l_D_1111_M_0001_N_0110,
	load_disp_rm_rn_l_D_0000_M_0010_N_0110,
	load_disp_rm_rn_l_D_0001_M_0010_N_0110,
	load_disp_rm_rn_l_D_0010_M_0010_N_0110,
	load_disp_rm_rn_l_D_0011_M_0010_N_0110,
	load_disp_rm_rn_l_D_0100_M_0010_N_0110,
	load_disp_rm_rn_l_D_0101_M_0010_N_0110,
	load_disp_rm_rn_l_D_0110_M_0010_N_0110,
	load_disp_rm_rn_l_D_0111_M_0010_N_0110,
	load_disp_rm_rn_l_D_1000_M_0010_N_0110,
	load_disp_rm_rn_l_D_1001_M_0010_N_0110,
	load_disp_rm_rn_l_D_1010_M_0010_N_0110,
	load_disp_rm_rn_l_D_1011_M_0010_N_0110,
	load_disp_rm_rn_l_D_1100_M_0010_N_0110,
	load_disp_rm_rn_l_D_1101_M_0010_N_0110,
	load_disp_rm_rn_l_D_1110_M_0010_N_0110,
	load_disp_rm_rn_l_D_1111_M_0010_N_0110,
	load_disp_rm_rn_l_D_0000_M_0011_N_0110,
	load_disp_rm_rn_l_D_0001_M_0011_N_0110,
	load_disp_rm_rn_l_D_0010_M_0011_N_0110,
	load_disp_rm_rn_l_D_0011_M_0011_N_0110,
	load_disp_rm_rn_l_D_0100_M_0011_N_0110,
	load_disp_rm_rn_l_D_0101_M_0011_N_0110,
	load_disp_rm_rn_l_D_0110_M_0011_N_0110,
	load_disp_rm_rn_l_D_0111_M_0011_N_0110,
	load_disp_rm_rn_l_D_1000_M_0011_N_0110,
	load_disp_rm_rn_l_D_1001_M_0011_N_0110,
	load_disp_rm_rn_l_D_1010_M_0011_N_0110,
	load_disp_rm_rn_l_D_1011_M_0011_N_0110,
	load_disp_rm_rn_l_D_1100_M_0011_N_0110,
	load_disp_rm_rn_l_D_1101_M_0011_N_0110,
	load_disp_rm_rn_l_D_1110_M_0011_N_0110,
	load_disp_rm_rn_l_D_1111_M_0011_N_0110,
	load_disp_rm_rn_l_D_0000_M_0100_N_0110,
	load_disp_rm_rn_l_D_0001_M_0100_N_0110,
	load_disp_rm_rn_l_D_0010_M_0100_N_0110,
	load_disp_rm_rn_l_D_0011_M_0100_N_0110,
	load_disp_rm_rn_l_D_0100_M_0100_N_0110,
	load_disp_rm_rn_l_D_0101_M_0100_N_0110,
	load_disp_rm_rn_l_D_0110_M_0100_N_0110,
	load_disp_rm_rn_l_D_0111_M_0100_N_0110,
	load_disp_rm_rn_l_D_1000_M_0100_N_0110,
	load_disp_rm_rn_l_D_1001_M_0100_N_0110,
	load_disp_rm_rn_l_D_1010_M_0100_N_0110,
	load_disp_rm_rn_l_D_1011_M_0100_N_0110,
	load_disp_rm_rn_l_D_1100_M_0100_N_0110,
	load_disp_rm_rn_l_D_1101_M_0100_N_0110,
	load_disp_rm_rn_l_D_1110_M_0100_N_0110,
	load_disp_rm_rn_l_D_1111_M_0100_N_0110,
	load_disp_rm_rn_l_D_0000_M_0101_N_0110,
	load_disp_rm_rn_l_D_0001_M_0101_N_0110,
	load_disp_rm_rn_l_D_0010_M_0101_N_0110,
	load_disp_rm_rn_l_D_0011_M_0101_N_0110,
	load_disp_rm_rn_l_D_0100_M_0101_N_0110,
	load_disp_rm_rn_l_D_0101_M_0101_N_0110,
	load_disp_rm_rn_l_D_0110_M_0101_N_0110,
	load_disp_rm_rn_l_D_0111_M_0101_N_0110,
	load_disp_rm_rn_l_D_1000_M_0101_N_0110,
	load_disp_rm_rn_l_D_1001_M_0101_N_0110,
	load_disp_rm_rn_l_D_1010_M_0101_N_0110,
	load_disp_rm_rn_l_D_1011_M_0101_N_0110,
	load_disp_rm_rn_l_D_1100_M_0101_N_0110,
	load_disp_rm_rn_l_D_1101_M_0101_N_0110,
	load_disp_rm_rn_l_D_1110_M_0101_N_0110,
	load_disp_rm_rn_l_D_1111_M_0101_N_0110,
	load_disp_rm_rn_l_D_0000_M_0110_N_0110,
	load_disp_rm_rn_l_D_0001_M_0110_N_0110,
	load_disp_rm_rn_l_D_0010_M_0110_N_0110,
	load_disp_rm_rn_l_D_0011_M_0110_N_0110,
	load_disp_rm_rn_l_D_0100_M_0110_N_0110,
	load_disp_rm_rn_l_D_0101_M_0110_N_0110,
	load_disp_rm_rn_l_D_0110_M_0110_N_0110,
	load_disp_rm_rn_l_D_0111_M_0110_N_0110,
	load_disp_rm_rn_l_D_1000_M_0110_N_0110,
	load_disp_rm_rn_l_D_1001_M_0110_N_0110,
	load_disp_rm_rn_l_D_1010_M_0110_N_0110,
	load_disp_rm_rn_l_D_1011_M_0110_N_0110,
	load_disp_rm_rn_l_D_1100_M_0110_N_0110,
	load_disp_rm_rn_l_D_1101_M_0110_N_0110,
	load_disp_rm_rn_l_D_1110_M_0110_N_0110,
	load_disp_rm_rn_l_D_1111_M_0110_N_0110,
	load_disp_rm_rn_l_D_0000_M_0111_N_0110,
	load_disp_rm_rn_l_D_0001_M_0111_N_0110,
	load_disp_rm_rn_l_D_0010_M_0111_N_0110,
	load_disp_rm_rn_l_D_0011_M_0111_N_0110,
	load_disp_rm_rn_l_D_0100_M_0111_N_0110,
	load_disp_rm_rn_l_D_0101_M_0111_N_0110,
	load_disp_rm_rn_l_D_0110_M_0111_N_0110,
	load_disp_rm_rn_l_D_0111_M_0111_N_0110,
	load_disp_rm_rn_l_D_1000_M_0111_N_0110,
	load_disp_rm_rn_l_D_1001_M_0111_N_0110,
	load_disp_rm_rn_l_D_1010_M_0111_N_0110,
	load_disp_rm_rn_l_D_1011_M_0111_N_0110,
	load_disp_rm_rn_l_D_1100_M_0111_N_0110,
	load_disp_rm_rn_l_D_1101_M_0111_N_0110,
	load_disp_rm_rn_l_D_1110_M_0111_N_0110,
	load_disp_rm_rn_l_D_1111_M_0111_N_0110,
	load_disp_rm_rn_l_D_0000_M_1000_N_0110,
	load_disp_rm_rn_l_D_0001_M_1000_N_0110,
	load_disp_rm_rn_l_D_0010_M_1000_N_0110,
	load_disp_rm_rn_l_D_0011_M_1000_N_0110,
	load_disp_rm_rn_l_D_0100_M_1000_N_0110,
	load_disp_rm_rn_l_D_0101_M_1000_N_0110,
	load_disp_rm_rn_l_D_0110_M_1000_N_0110,
	load_disp_rm_rn_l_D_0111_M_1000_N_0110,
	load_disp_rm_rn_l_D_1000_M_1000_N_0110,
	load_disp_rm_rn_l_D_1001_M_1000_N_0110,
	load_disp_rm_rn_l_D_1010_M_1000_N_0110,
	load_disp_rm_rn_l_D_1011_M_1000_N_0110,
	load_disp_rm_rn_l_D_1100_M_1000_N_0110,
	load_disp_rm_rn_l_D_1101_M_1000_N_0110,
	load_disp_rm_rn_l_D_1110_M_1000_N_0110,
	load_disp_rm_rn_l_D_1111_M_1000_N_0110,
	load_disp_rm_rn_l_D_0000_M_1001_N_0110,
	load_disp_rm_rn_l_D_0001_M_1001_N_0110,
	load_disp_rm_rn_l_D_0010_M_1001_N_0110,
	load_disp_rm_rn_l_D_0011_M_1001_N_0110,
	load_disp_rm_rn_l_D_0100_M_1001_N_0110,
	load_disp_rm_rn_l_D_0101_M_1001_N_0110,
	load_disp_rm_rn_l_D_0110_M_1001_N_0110,
	load_disp_rm_rn_l_D_0111_M_1001_N_0110,
	load_disp_rm_rn_l_D_1000_M_1001_N_0110,
	load_disp_rm_rn_l_D_1001_M_1001_N_0110,
	load_disp_rm_rn_l_D_1010_M_1001_N_0110,
	load_disp_rm_rn_l_D_1011_M_1001_N_0110,
	load_disp_rm_rn_l_D_1100_M_1001_N_0110,
	load_disp_rm_rn_l_D_1101_M_1001_N_0110,
	load_disp_rm_rn_l_D_1110_M_1001_N_0110,
	load_disp_rm_rn_l_D_1111_M_1001_N_0110,
	load_disp_rm_rn_l_D_0000_M_1010_N_0110,
	load_disp_rm_rn_l_D_0001_M_1010_N_0110,
	load_disp_rm_rn_l_D_0010_M_1010_N_0110,
	load_disp_rm_rn_l_D_0011_M_1010_N_0110,
	load_disp_rm_rn_l_D_0100_M_1010_N_0110,
	load_disp_rm_rn_l_D_0101_M_1010_N_0110,
	load_disp_rm_rn_l_D_0110_M_1010_N_0110,
	load_disp_rm_rn_l_D_0111_M_1010_N_0110,
	load_disp_rm_rn_l_D_1000_M_1010_N_0110,
	load_disp_rm_rn_l_D_1001_M_1010_N_0110,
	load_disp_rm_rn_l_D_1010_M_1010_N_0110,
	load_disp_rm_rn_l_D_1011_M_1010_N_0110,
	load_disp_rm_rn_l_D_1100_M_1010_N_0110,
	load_disp_rm_rn_l_D_1101_M_1010_N_0110,
	load_disp_rm_rn_l_D_1110_M_1010_N_0110,
	load_disp_rm_rn_l_D_1111_M_1010_N_0110,
	load_disp_rm_rn_l_D_0000_M_1011_N_0110,
	load_disp_rm_rn_l_D_0001_M_1011_N_0110,
	load_disp_rm_rn_l_D_0010_M_1011_N_0110,
	load_disp_rm_rn_l_D_0011_M_1011_N_0110,
	load_disp_rm_rn_l_D_0100_M_1011_N_0110,
	load_disp_rm_rn_l_D_0101_M_1011_N_0110,
	load_disp_rm_rn_l_D_0110_M_1011_N_0110,
	load_disp_rm_rn_l_D_0111_M_1011_N_0110,
	load_disp_rm_rn_l_D_1000_M_1011_N_0110,
	load_disp_rm_rn_l_D_1001_M_1011_N_0110,
	load_disp_rm_rn_l_D_1010_M_1011_N_0110,
	load_disp_rm_rn_l_D_1011_M_1011_N_0110,
	load_disp_rm_rn_l_D_1100_M_1011_N_0110,
	load_disp_rm_rn_l_D_1101_M_1011_N_0110,
	load_disp_rm_rn_l_D_1110_M_1011_N_0110,
	load_disp_rm_rn_l_D_1111_M_1011_N_0110,
	load_disp_rm_rn_l_D_0000_M_1100_N_0110,
	load_disp_rm_rn_l_D_0001_M_1100_N_0110,
	load_disp_rm_rn_l_D_0010_M_1100_N_0110,
	load_disp_rm_rn_l_D_0011_M_1100_N_0110,
	load_disp_rm_rn_l_D_0100_M_1100_N_0110,
	load_disp_rm_rn_l_D_0101_M_1100_N_0110,
	load_disp_rm_rn_l_D_0110_M_1100_N_0110,
	load_disp_rm_rn_l_D_0111_M_1100_N_0110,
	load_disp_rm_rn_l_D_1000_M_1100_N_0110,
	load_disp_rm_rn_l_D_1001_M_1100_N_0110,
	load_disp_rm_rn_l_D_1010_M_1100_N_0110,
	load_disp_rm_rn_l_D_1011_M_1100_N_0110,
	load_disp_rm_rn_l_D_1100_M_1100_N_0110,
	load_disp_rm_rn_l_D_1101_M_1100_N_0110,
	load_disp_rm_rn_l_D_1110_M_1100_N_0110,
	load_disp_rm_rn_l_D_1111_M_1100_N_0110,
	load_disp_rm_rn_l_D_0000_M_1101_N_0110,
	load_disp_rm_rn_l_D_0001_M_1101_N_0110,
	load_disp_rm_rn_l_D_0010_M_1101_N_0110,
	load_disp_rm_rn_l_D_0011_M_1101_N_0110,
	load_disp_rm_rn_l_D_0100_M_1101_N_0110,
	load_disp_rm_rn_l_D_0101_M_1101_N_0110,
	load_disp_rm_rn_l_D_0110_M_1101_N_0110,
	load_disp_rm_rn_l_D_0111_M_1101_N_0110,
	load_disp_rm_rn_l_D_1000_M_1101_N_0110,
	load_disp_rm_rn_l_D_1001_M_1101_N_0110,
	load_disp_rm_rn_l_D_1010_M_1101_N_0110,
	load_disp_rm_rn_l_D_1011_M_1101_N_0110,
	load_disp_rm_rn_l_D_1100_M_1101_N_0110,
	load_disp_rm_rn_l_D_1101_M_1101_N_0110,
	load_disp_rm_rn_l_D_1110_M_1101_N_0110,
	load_disp_rm_rn_l_D_1111_M_1101_N_0110,
	load_disp_rm_rn_l_D_0000_M_1110_N_0110,
	load_disp_rm_rn_l_D_0001_M_1110_N_0110,
	load_disp_rm_rn_l_D_0010_M_1110_N_0110,
	load_disp_rm_rn_l_D_0011_M_1110_N_0110,
	load_disp_rm_rn_l_D_0100_M_1110_N_0110,
	load_disp_rm_rn_l_D_0101_M_1110_N_0110,
	load_disp_rm_rn_l_D_0110_M_1110_N_0110,
	load_disp_rm_rn_l_D_0111_M_1110_N_0110,
	load_disp_rm_rn_l_D_1000_M_1110_N_0110,
	load_disp_rm_rn_l_D_1001_M_1110_N_0110,
	load_disp_rm_rn_l_D_1010_M_1110_N_0110,
	load_disp_rm_rn_l_D_1011_M_1110_N_0110,
	load_disp_rm_rn_l_D_1100_M_1110_N_0110,
	load_disp_rm_rn_l_D_1101_M_1110_N_0110,
	load_disp_rm_rn_l_D_1110_M_1110_N_0110,
	load_disp_rm_rn_l_D_1111_M_1110_N_0110,
	load_disp_rm_rn_l_D_0000_M_1111_N_0110,
	load_disp_rm_rn_l_D_0001_M_1111_N_0110,
	load_disp_rm_rn_l_D_0010_M_1111_N_0110,
	load_disp_rm_rn_l_D_0011_M_1111_N_0110,
	load_disp_rm_rn_l_D_0100_M_1111_N_0110,
	load_disp_rm_rn_l_D_0101_M_1111_N_0110,
	load_disp_rm_rn_l_D_0110_M_1111_N_0110,
	load_disp_rm_rn_l_D_0111_M_1111_N_0110,
	load_disp_rm_rn_l_D_1000_M_1111_N_0110,
	load_disp_rm_rn_l_D_1001_M_1111_N_0110,
	load_disp_rm_rn_l_D_1010_M_1111_N_0110,
	load_disp_rm_rn_l_D_1011_M_1111_N_0110,
	load_disp_rm_rn_l_D_1100_M_1111_N_0110,
	load_disp_rm_rn_l_D_1101_M_1111_N_0110,
	load_disp_rm_rn_l_D_1110_M_1111_N_0110,
	load_disp_rm_rn_l_D_1111_M_1111_N_0110,
	load_disp_rm_rn_l_D_0000_M_0000_N_0111,
	load_disp_rm_rn_l_D_0001_M_0000_N_0111,
	load_disp_rm_rn_l_D_0010_M_0000_N_0111,
	load_disp_rm_rn_l_D_0011_M_0000_N_0111,
	load_disp_rm_rn_l_D_0100_M_0000_N_0111,
	load_disp_rm_rn_l_D_0101_M_0000_N_0111,
	load_disp_rm_rn_l_D_0110_M_0000_N_0111,
	load_disp_rm_rn_l_D_0111_M_0000_N_0111,
	load_disp_rm_rn_l_D_1000_M_0000_N_0111,
	load_disp_rm_rn_l_D_1001_M_0000_N_0111,
	load_disp_rm_rn_l_D_1010_M_0000_N_0111,
	load_disp_rm_rn_l_D_1011_M_0000_N_0111,
	load_disp_rm_rn_l_D_1100_M_0000_N_0111,
	load_disp_rm_rn_l_D_1101_M_0000_N_0111,
	load_disp_rm_rn_l_D_1110_M_0000_N_0111,
	load_disp_rm_rn_l_D_1111_M_0000_N_0111,
	load_disp_rm_rn_l_D_0000_M_0001_N_0111,
	load_disp_rm_rn_l_D_0001_M_0001_N_0111,
	load_disp_rm_rn_l_D_0010_M_0001_N_0111,
	load_disp_rm_rn_l_D_0011_M_0001_N_0111,
	load_disp_rm_rn_l_D_0100_M_0001_N_0111,
	load_disp_rm_rn_l_D_0101_M_0001_N_0111,
	load_disp_rm_rn_l_D_0110_M_0001_N_0111,
	load_disp_rm_rn_l_D_0111_M_0001_N_0111,
	load_disp_rm_rn_l_D_1000_M_0001_N_0111,
	load_disp_rm_rn_l_D_1001_M_0001_N_0111,
	load_disp_rm_rn_l_D_1010_M_0001_N_0111,
	load_disp_rm_rn_l_D_1011_M_0001_N_0111,
	load_disp_rm_rn_l_D_1100_M_0001_N_0111,
	load_disp_rm_rn_l_D_1101_M_0001_N_0111,
	load_disp_rm_rn_l_D_1110_M_0001_N_0111,
	load_disp_rm_rn_l_D_1111_M_0001_N_0111,
	load_disp_rm_rn_l_D_0000_M_0010_N_0111,
	load_disp_rm_rn_l_D_0001_M_0010_N_0111,
	load_disp_rm_rn_l_D_0010_M_0010_N_0111,
	load_disp_rm_rn_l_D_0011_M_0010_N_0111,
	load_disp_rm_rn_l_D_0100_M_0010_N_0111,
	load_disp_rm_rn_l_D_0101_M_0010_N_0111,
	load_disp_rm_rn_l_D_0110_M_0010_N_0111,
	load_disp_rm_rn_l_D_0111_M_0010_N_0111,
	load_disp_rm_rn_l_D_1000_M_0010_N_0111,
	load_disp_rm_rn_l_D_1001_M_0010_N_0111,
	load_disp_rm_rn_l_D_1010_M_0010_N_0111,
	load_disp_rm_rn_l_D_1011_M_0010_N_0111,
	load_disp_rm_rn_l_D_1100_M_0010_N_0111,
	load_disp_rm_rn_l_D_1101_M_0010_N_0111,
	load_disp_rm_rn_l_D_1110_M_0010_N_0111,
	load_disp_rm_rn_l_D_1111_M_0010_N_0111,
	load_disp_rm_rn_l_D_0000_M_0011_N_0111,
	load_disp_rm_rn_l_D_0001_M_0011_N_0111,
	load_disp_rm_rn_l_D_0010_M_0011_N_0111,
	load_disp_rm_rn_l_D_0011_M_0011_N_0111,
	load_disp_rm_rn_l_D_0100_M_0011_N_0111,
	load_disp_rm_rn_l_D_0101_M_0011_N_0111,
	load_disp_rm_rn_l_D_0110_M_0011_N_0111,
	load_disp_rm_rn_l_D_0111_M_0011_N_0111,
	load_disp_rm_rn_l_D_1000_M_0011_N_0111,
	load_disp_rm_rn_l_D_1001_M_0011_N_0111,
	load_disp_rm_rn_l_D_1010_M_0011_N_0111,
	load_disp_rm_rn_l_D_1011_M_0011_N_0111,
	load_disp_rm_rn_l_D_1100_M_0011_N_0111,
	load_disp_rm_rn_l_D_1101_M_0011_N_0111,
	load_disp_rm_rn_l_D_1110_M_0011_N_0111,
	load_disp_rm_rn_l_D_1111_M_0011_N_0111,
	load_disp_rm_rn_l_D_0000_M_0100_N_0111,
	load_disp_rm_rn_l_D_0001_M_0100_N_0111,
	load_disp_rm_rn_l_D_0010_M_0100_N_0111,
	load_disp_rm_rn_l_D_0011_M_0100_N_0111,
	load_disp_rm_rn_l_D_0100_M_0100_N_0111,
	load_disp_rm_rn_l_D_0101_M_0100_N_0111,
	load_disp_rm_rn_l_D_0110_M_0100_N_0111,
	load_disp_rm_rn_l_D_0111_M_0100_N_0111,
	load_disp_rm_rn_l_D_1000_M_0100_N_0111,
	load_disp_rm_rn_l_D_1001_M_0100_N_0111,
	load_disp_rm_rn_l_D_1010_M_0100_N_0111,
	load_disp_rm_rn_l_D_1011_M_0100_N_0111,
	load_disp_rm_rn_l_D_1100_M_0100_N_0111,
	load_disp_rm_rn_l_D_1101_M_0100_N_0111,
	load_disp_rm_rn_l_D_1110_M_0100_N_0111,
	load_disp_rm_rn_l_D_1111_M_0100_N_0111,
	load_disp_rm_rn_l_D_0000_M_0101_N_0111,
	load_disp_rm_rn_l_D_0001_M_0101_N_0111,
	load_disp_rm_rn_l_D_0010_M_0101_N_0111,
	load_disp_rm_rn_l_D_0011_M_0101_N_0111,
	load_disp_rm_rn_l_D_0100_M_0101_N_0111,
	load_disp_rm_rn_l_D_0101_M_0101_N_0111,
	load_disp_rm_rn_l_D_0110_M_0101_N_0111,
	load_disp_rm_rn_l_D_0111_M_0101_N_0111,
	load_disp_rm_rn_l_D_1000_M_0101_N_0111,
	load_disp_rm_rn_l_D_1001_M_0101_N_0111,
	load_disp_rm_rn_l_D_1010_M_0101_N_0111,
	load_disp_rm_rn_l_D_1011_M_0101_N_0111,
	load_disp_rm_rn_l_D_1100_M_0101_N_0111,
	load_disp_rm_rn_l_D_1101_M_0101_N_0111,
	load_disp_rm_rn_l_D_1110_M_0101_N_0111,
	load_disp_rm_rn_l_D_1111_M_0101_N_0111,
	load_disp_rm_rn_l_D_0000_M_0110_N_0111,
	load_disp_rm_rn_l_D_0001_M_0110_N_0111,
	load_disp_rm_rn_l_D_0010_M_0110_N_0111,
	load_disp_rm_rn_l_D_0011_M_0110_N_0111,
	load_disp_rm_rn_l_D_0100_M_0110_N_0111,
	load_disp_rm_rn_l_D_0101_M_0110_N_0111,
	load_disp_rm_rn_l_D_0110_M_0110_N_0111,
	load_disp_rm_rn_l_D_0111_M_0110_N_0111,
	load_disp_rm_rn_l_D_1000_M_0110_N_0111,
	load_disp_rm_rn_l_D_1001_M_0110_N_0111,
	load_disp_rm_rn_l_D_1010_M_0110_N_0111,
	load_disp_rm_rn_l_D_1011_M_0110_N_0111,
	load_disp_rm_rn_l_D_1100_M_0110_N_0111,
	load_disp_rm_rn_l_D_1101_M_0110_N_0111,
	load_disp_rm_rn_l_D_1110_M_0110_N_0111,
	load_disp_rm_rn_l_D_1111_M_0110_N_0111,
	load_disp_rm_rn_l_D_0000_M_0111_N_0111,
	load_disp_rm_rn_l_D_0001_M_0111_N_0111,
	load_disp_rm_rn_l_D_0010_M_0111_N_0111,
	load_disp_rm_rn_l_D_0011_M_0111_N_0111,
	load_disp_rm_rn_l_D_0100_M_0111_N_0111,
	load_disp_rm_rn_l_D_0101_M_0111_N_0111,
	load_disp_rm_rn_l_D_0110_M_0111_N_0111,
	load_disp_rm_rn_l_D_0111_M_0111_N_0111,
	load_disp_rm_rn_l_D_1000_M_0111_N_0111,
	load_disp_rm_rn_l_D_1001_M_0111_N_0111,
	load_disp_rm_rn_l_D_1010_M_0111_N_0111,
	load_disp_rm_rn_l_D_1011_M_0111_N_0111,
	load_disp_rm_rn_l_D_1100_M_0111_N_0111,
	load_disp_rm_rn_l_D_1101_M_0111_N_0111,
	load_disp_rm_rn_l_D_1110_M_0111_N_0111,
	load_disp_rm_rn_l_D_1111_M_0111_N_0111,
	load_disp_rm_rn_l_D_0000_M_1000_N_0111,
	load_disp_rm_rn_l_D_0001_M_1000_N_0111,
	load_disp_rm_rn_l_D_0010_M_1000_N_0111,
	load_disp_rm_rn_l_D_0011_M_1000_N_0111,
	load_disp_rm_rn_l_D_0100_M_1000_N_0111,
	load_disp_rm_rn_l_D_0101_M_1000_N_0111,
	load_disp_rm_rn_l_D_0110_M_1000_N_0111,
	load_disp_rm_rn_l_D_0111_M_1000_N_0111,
	load_disp_rm_rn_l_D_1000_M_1000_N_0111,
	load_disp_rm_rn_l_D_1001_M_1000_N_0111,
	load_disp_rm_rn_l_D_1010_M_1000_N_0111,
	load_disp_rm_rn_l_D_1011_M_1000_N_0111,
	load_disp_rm_rn_l_D_1100_M_1000_N_0111,
	load_disp_rm_rn_l_D_1101_M_1000_N_0111,
	load_disp_rm_rn_l_D_1110_M_1000_N_0111,
	load_disp_rm_rn_l_D_1111_M_1000_N_0111,
	load_disp_rm_rn_l_D_0000_M_1001_N_0111,
	load_disp_rm_rn_l_D_0001_M_1001_N_0111,
	load_disp_rm_rn_l_D_0010_M_1001_N_0111,
	load_disp_rm_rn_l_D_0011_M_1001_N_0111,
	load_disp_rm_rn_l_D_0100_M_1001_N_0111,
	load_disp_rm_rn_l_D_0101_M_1001_N_0111,
	load_disp_rm_rn_l_D_0110_M_1001_N_0111,
	load_disp_rm_rn_l_D_0111_M_1001_N_0111,
	load_disp_rm_rn_l_D_1000_M_1001_N_0111,
	load_disp_rm_rn_l_D_1001_M_1001_N_0111,
	load_disp_rm_rn_l_D_1010_M_1001_N_0111,
	load_disp_rm_rn_l_D_1011_M_1001_N_0111,
	load_disp_rm_rn_l_D_1100_M_1001_N_0111,
	load_disp_rm_rn_l_D_1101_M_1001_N_0111,
	load_disp_rm_rn_l_D_1110_M_1001_N_0111,
	load_disp_rm_rn_l_D_1111_M_1001_N_0111,
	load_disp_rm_rn_l_D_0000_M_1010_N_0111,
	load_disp_rm_rn_l_D_0001_M_1010_N_0111,
	load_disp_rm_rn_l_D_0010_M_1010_N_0111,
	load_disp_rm_rn_l_D_0011_M_1010_N_0111,
	load_disp_rm_rn_l_D_0100_M_1010_N_0111,
	load_disp_rm_rn_l_D_0101_M_1010_N_0111,
	load_disp_rm_rn_l_D_0110_M_1010_N_0111,
	load_disp_rm_rn_l_D_0111_M_1010_N_0111,
	load_disp_rm_rn_l_D_1000_M_1010_N_0111,
	load_disp_rm_rn_l_D_1001_M_1010_N_0111,
	load_disp_rm_rn_l_D_1010_M_1010_N_0111,
	load_disp_rm_rn_l_D_1011_M_1010_N_0111,
	load_disp_rm_rn_l_D_1100_M_1010_N_0111,
	load_disp_rm_rn_l_D_1101_M_1010_N_0111,
	load_disp_rm_rn_l_D_1110_M_1010_N_0111,
	load_disp_rm_rn_l_D_1111_M_1010_N_0111,
	load_disp_rm_rn_l_D_0000_M_1011_N_0111,
	load_disp_rm_rn_l_D_0001_M_1011_N_0111,
	load_disp_rm_rn_l_D_0010_M_1011_N_0111,
	load_disp_rm_rn_l_D_0011_M_1011_N_0111,
	load_disp_rm_rn_l_D_0100_M_1011_N_0111,
	load_disp_rm_rn_l_D_0101_M_1011_N_0111,
	load_disp_rm_rn_l_D_0110_M_1011_N_0111,
	load_disp_rm_rn_l_D_0111_M_1011_N_0111,
	load_disp_rm_rn_l_D_1000_M_1011_N_0111,
	load_disp_rm_rn_l_D_1001_M_1011_N_0111,
	load_disp_rm_rn_l_D_1010_M_1011_N_0111,
	load_disp_rm_rn_l_D_1011_M_1011_N_0111,
	load_disp_rm_rn_l_D_1100_M_1011_N_0111,
	load_disp_rm_rn_l_D_1101_M_1011_N_0111,
	load_disp_rm_rn_l_D_1110_M_1011_N_0111,
	load_disp_rm_rn_l_D_1111_M_1011_N_0111,
	load_disp_rm_rn_l_D_0000_M_1100_N_0111,
	load_disp_rm_rn_l_D_0001_M_1100_N_0111,
	load_disp_rm_rn_l_D_0010_M_1100_N_0111,
	load_disp_rm_rn_l_D_0011_M_1100_N_0111,
	load_disp_rm_rn_l_D_0100_M_1100_N_0111,
	load_disp_rm_rn_l_D_0101_M_1100_N_0111,
	load_disp_rm_rn_l_D_0110_M_1100_N_0111,
	load_disp_rm_rn_l_D_0111_M_1100_N_0111,
	load_disp_rm_rn_l_D_1000_M_1100_N_0111,
	load_disp_rm_rn_l_D_1001_M_1100_N_0111,
	load_disp_rm_rn_l_D_1010_M_1100_N_0111,
	load_disp_rm_rn_l_D_1011_M_1100_N_0111,
	load_disp_rm_rn_l_D_1100_M_1100_N_0111,
	load_disp_rm_rn_l_D_1101_M_1100_N_0111,
	load_disp_rm_rn_l_D_1110_M_1100_N_0111,
	load_disp_rm_rn_l_D_1111_M_1100_N_0111,
	load_disp_rm_rn_l_D_0000_M_1101_N_0111,
	load_disp_rm_rn_l_D_0001_M_1101_N_0111,
	load_disp_rm_rn_l_D_0010_M_1101_N_0111,
	load_disp_rm_rn_l_D_0011_M_1101_N_0111,
	load_disp_rm_rn_l_D_0100_M_1101_N_0111,
	load_disp_rm_rn_l_D_0101_M_1101_N_0111,
	load_disp_rm_rn_l_D_0110_M_1101_N_0111,
	load_disp_rm_rn_l_D_0111_M_1101_N_0111,
	load_disp_rm_rn_l_D_1000_M_1101_N_0111,
	load_disp_rm_rn_l_D_1001_M_1101_N_0111,
	load_disp_rm_rn_l_D_1010_M_1101_N_0111,
	load_disp_rm_rn_l_D_1011_M_1101_N_0111,
	load_disp_rm_rn_l_D_1100_M_1101_N_0111,
	load_disp_rm_rn_l_D_1101_M_1101_N_0111,
	load_disp_rm_rn_l_D_1110_M_1101_N_0111,
	load_disp_rm_rn_l_D_1111_M_1101_N_0111,
	load_disp_rm_rn_l_D_0000_M_1110_N_0111,
	load_disp_rm_rn_l_D_0001_M_1110_N_0111,
	load_disp_rm_rn_l_D_0010_M_1110_N_0111,
	load_disp_rm_rn_l_D_0011_M_1110_N_0111,
	load_disp_rm_rn_l_D_0100_M_1110_N_0111,
	load_disp_rm_rn_l_D_0101_M_1110_N_0111,
	load_disp_rm_rn_l_D_0110_M_1110_N_0111,
	load_disp_rm_rn_l_D_0111_M_1110_N_0111,
	load_disp_rm_rn_l_D_1000_M_1110_N_0111,
	load_disp_rm_rn_l_D_1001_M_1110_N_0111,
	load_disp_rm_rn_l_D_1010_M_1110_N_0111,
	load_disp_rm_rn_l_D_1011_M_1110_N_0111,
	load_disp_rm_rn_l_D_1100_M_1110_N_0111,
	load_disp_rm_rn_l_D_1101_M_1110_N_0111,
	load_disp_rm_rn_l_D_1110_M_1110_N_0111,
	load_disp_rm_rn_l_D_1111_M_1110_N_0111,
	load_disp_rm_rn_l_D_0000_M_1111_N_0111,
	load_disp_rm_rn_l_D_0001_M_1111_N_0111,
	load_disp_rm_rn_l_D_0010_M_1111_N_0111,
	load_disp_rm_rn_l_D_0011_M_1111_N_0111,
	load_disp_rm_rn_l_D_0100_M_1111_N_0111,
	load_disp_rm_rn_l_D_0101_M_1111_N_0111,
	load_disp_rm_rn_l_D_0110_M_1111_N_0111,
	load_disp_rm_rn_l_D_0111_M_1111_N_0111,
	load_disp_rm_rn_l_D_1000_M_1111_N_0111,
	load_disp_rm_rn_l_D_1001_M_1111_N_0111,
	load_disp_rm_rn_l_D_1010_M_1111_N_0111,
	load_disp_rm_rn_l_D_1011_M_1111_N_0111,
	load_disp_rm_rn_l_D_1100_M_1111_N_0111,
	load_disp_rm_rn_l_D_1101_M_1111_N_0111,
	load_disp_rm_rn_l_D_1110_M_1111_N_0111,
	load_disp_rm_rn_l_D_1111_M_1111_N_0111,
	load_disp_rm_rn_l_D_0000_M_0000_N_1000,
	load_disp_rm_rn_l_D_0001_M_0000_N_1000,
	load_disp_rm_rn_l_D_0010_M_0000_N_1000,
	load_disp_rm_rn_l_D_0011_M_0000_N_1000,
	load_disp_rm_rn_l_D_0100_M_0000_N_1000,
	load_disp_rm_rn_l_D_0101_M_0000_N_1000,
	load_disp_rm_rn_l_D_0110_M_0000_N_1000,
	load_disp_rm_rn_l_D_0111_M_0000_N_1000,
	load_disp_rm_rn_l_D_1000_M_0000_N_1000,
	load_disp_rm_rn_l_D_1001_M_0000_N_1000,
	load_disp_rm_rn_l_D_1010_M_0000_N_1000,
	load_disp_rm_rn_l_D_1011_M_0000_N_1000,
	load_disp_rm_rn_l_D_1100_M_0000_N_1000,
	load_disp_rm_rn_l_D_1101_M_0000_N_1000,
	load_disp_rm_rn_l_D_1110_M_0000_N_1000,
	load_disp_rm_rn_l_D_1111_M_0000_N_1000,
	load_disp_rm_rn_l_D_0000_M_0001_N_1000,
	load_disp_rm_rn_l_D_0001_M_0001_N_1000,
	load_disp_rm_rn_l_D_0010_M_0001_N_1000,
	load_disp_rm_rn_l_D_0011_M_0001_N_1000,
	load_disp_rm_rn_l_D_0100_M_0001_N_1000,
	load_disp_rm_rn_l_D_0101_M_0001_N_1000,
	load_disp_rm_rn_l_D_0110_M_0001_N_1000,
	load_disp_rm_rn_l_D_0111_M_0001_N_1000,
	load_disp_rm_rn_l_D_1000_M_0001_N_1000,
	load_disp_rm_rn_l_D_1001_M_0001_N_1000,
	load_disp_rm_rn_l_D_1010_M_0001_N_1000,
	load_disp_rm_rn_l_D_1011_M_0001_N_1000,
	load_disp_rm_rn_l_D_1100_M_0001_N_1000,
	load_disp_rm_rn_l_D_1101_M_0001_N_1000,
	load_disp_rm_rn_l_D_1110_M_0001_N_1000,
	load_disp_rm_rn_l_D_1111_M_0001_N_1000,
	load_disp_rm_rn_l_D_0000_M_0010_N_1000,
	load_disp_rm_rn_l_D_0001_M_0010_N_1000,
	load_disp_rm_rn_l_D_0010_M_0010_N_1000,
	load_disp_rm_rn_l_D_0011_M_0010_N_1000,
	load_disp_rm_rn_l_D_0100_M_0010_N_1000,
	load_disp_rm_rn_l_D_0101_M_0010_N_1000,
	load_disp_rm_rn_l_D_0110_M_0010_N_1000,
	load_disp_rm_rn_l_D_0111_M_0010_N_1000,
	load_disp_rm_rn_l_D_1000_M_0010_N_1000,
	load_disp_rm_rn_l_D_1001_M_0010_N_1000,
	load_disp_rm_rn_l_D_1010_M_0010_N_1000,
	load_disp_rm_rn_l_D_1011_M_0010_N_1000,
	load_disp_rm_rn_l_D_1100_M_0010_N_1000,
	load_disp_rm_rn_l_D_1101_M_0010_N_1000,
	load_disp_rm_rn_l_D_1110_M_0010_N_1000,
	load_disp_rm_rn_l_D_1111_M_0010_N_1000,
	load_disp_rm_rn_l_D_0000_M_0011_N_1000,
	load_disp_rm_rn_l_D_0001_M_0011_N_1000,
	load_disp_rm_rn_l_D_0010_M_0011_N_1000,
	load_disp_rm_rn_l_D_0011_M_0011_N_1000,
	load_disp_rm_rn_l_D_0100_M_0011_N_1000,
	load_disp_rm_rn_l_D_0101_M_0011_N_1000,
	load_disp_rm_rn_l_D_0110_M_0011_N_1000,
	load_disp_rm_rn_l_D_0111_M_0011_N_1000,
	load_disp_rm_rn_l_D_1000_M_0011_N_1000,
	load_disp_rm_rn_l_D_1001_M_0011_N_1000,
	load_disp_rm_rn_l_D_1010_M_0011_N_1000,
	load_disp_rm_rn_l_D_1011_M_0011_N_1000,
	load_disp_rm_rn_l_D_1100_M_0011_N_1000,
	load_disp_rm_rn_l_D_1101_M_0011_N_1000,
	load_disp_rm_rn_l_D_1110_M_0011_N_1000,
	load_disp_rm_rn_l_D_1111_M_0011_N_1000,
	load_disp_rm_rn_l_D_0000_M_0100_N_1000,
	load_disp_rm_rn_l_D_0001_M_0100_N_1000,
	load_disp_rm_rn_l_D_0010_M_0100_N_1000,
	load_disp_rm_rn_l_D_0011_M_0100_N_1000,
	load_disp_rm_rn_l_D_0100_M_0100_N_1000,
	load_disp_rm_rn_l_D_0101_M_0100_N_1000,
	load_disp_rm_rn_l_D_0110_M_0100_N_1000,
	load_disp_rm_rn_l_D_0111_M_0100_N_1000,
	load_disp_rm_rn_l_D_1000_M_0100_N_1000,
	load_disp_rm_rn_l_D_1001_M_0100_N_1000,
	load_disp_rm_rn_l_D_1010_M_0100_N_1000,
	load_disp_rm_rn_l_D_1011_M_0100_N_1000,
	load_disp_rm_rn_l_D_1100_M_0100_N_1000,
	load_disp_rm_rn_l_D_1101_M_0100_N_1000,
	load_disp_rm_rn_l_D_1110_M_0100_N_1000,
	load_disp_rm_rn_l_D_1111_M_0100_N_1000,
	load_disp_rm_rn_l_D_0000_M_0101_N_1000,
	load_disp_rm_rn_l_D_0001_M_0101_N_1000,
	load_disp_rm_rn_l_D_0010_M_0101_N_1000,
	load_disp_rm_rn_l_D_0011_M_0101_N_1000,
	load_disp_rm_rn_l_D_0100_M_0101_N_1000,
	load_disp_rm_rn_l_D_0101_M_0101_N_1000,
	load_disp_rm_rn_l_D_0110_M_0101_N_1000,
	load_disp_rm_rn_l_D_0111_M_0101_N_1000,
	load_disp_rm_rn_l_D_1000_M_0101_N_1000,
	load_disp_rm_rn_l_D_1001_M_0101_N_1000,
	load_disp_rm_rn_l_D_1010_M_0101_N_1000,
	load_disp_rm_rn_l_D_1011_M_0101_N_1000,
	load_disp_rm_rn_l_D_1100_M_0101_N_1000,
	load_disp_rm_rn_l_D_1101_M_0101_N_1000,
	load_disp_rm_rn_l_D_1110_M_0101_N_1000,
	load_disp_rm_rn_l_D_1111_M_0101_N_1000,
	load_disp_rm_rn_l_D_0000_M_0110_N_1000,
	load_disp_rm_rn_l_D_0001_M_0110_N_1000,
	load_disp_rm_rn_l_D_0010_M_0110_N_1000,
	load_disp_rm_rn_l_D_0011_M_0110_N_1000,
	load_disp_rm_rn_l_D_0100_M_0110_N_1000,
	load_disp_rm_rn_l_D_0101_M_0110_N_1000,
	load_disp_rm_rn_l_D_0110_M_0110_N_1000,
	load_disp_rm_rn_l_D_0111_M_0110_N_1000,
	load_disp_rm_rn_l_D_1000_M_0110_N_1000,
	load_disp_rm_rn_l_D_1001_M_0110_N_1000,
	load_disp_rm_rn_l_D_1010_M_0110_N_1000,
	load_disp_rm_rn_l_D_1011_M_0110_N_1000,
	load_disp_rm_rn_l_D_1100_M_0110_N_1000,
	load_disp_rm_rn_l_D_1101_M_0110_N_1000,
	load_disp_rm_rn_l_D_1110_M_0110_N_1000,
	load_disp_rm_rn_l_D_1111_M_0110_N_1000,
	load_disp_rm_rn_l_D_0000_M_0111_N_1000,
	load_disp_rm_rn_l_D_0001_M_0111_N_1000,
	load_disp_rm_rn_l_D_0010_M_0111_N_1000,
	load_disp_rm_rn_l_D_0011_M_0111_N_1000,
	load_disp_rm_rn_l_D_0100_M_0111_N_1000,
	load_disp_rm_rn_l_D_0101_M_0111_N_1000,
	load_disp_rm_rn_l_D_0110_M_0111_N_1000,
	load_disp_rm_rn_l_D_0111_M_0111_N_1000,
	load_disp_rm_rn_l_D_1000_M_0111_N_1000,
	load_disp_rm_rn_l_D_1001_M_0111_N_1000,
	load_disp_rm_rn_l_D_1010_M_0111_N_1000,
	load_disp_rm_rn_l_D_1011_M_0111_N_1000,
	load_disp_rm_rn_l_D_1100_M_0111_N_1000,
	load_disp_rm_rn_l_D_1101_M_0111_N_1000,
	load_disp_rm_rn_l_D_1110_M_0111_N_1000,
	load_disp_rm_rn_l_D_1111_M_0111_N_1000,
	load_disp_rm_rn_l_D_0000_M_1000_N_1000,
	load_disp_rm_rn_l_D_0001_M_1000_N_1000,
	load_disp_rm_rn_l_D_0010_M_1000_N_1000,
	load_disp_rm_rn_l_D_0011_M_1000_N_1000,
	load_disp_rm_rn_l_D_0100_M_1000_N_1000,
	load_disp_rm_rn_l_D_0101_M_1000_N_1000,
	load_disp_rm_rn_l_D_0110_M_1000_N_1000,
	load_disp_rm_rn_l_D_0111_M_1000_N_1000,
	load_disp_rm_rn_l_D_1000_M_1000_N_1000,
	load_disp_rm_rn_l_D_1001_M_1000_N_1000,
	load_disp_rm_rn_l_D_1010_M_1000_N_1000,
	load_disp_rm_rn_l_D_1011_M_1000_N_1000,
	load_disp_rm_rn_l_D_1100_M_1000_N_1000,
	load_disp_rm_rn_l_D_1101_M_1000_N_1000,
	load_disp_rm_rn_l_D_1110_M_1000_N_1000,
	load_disp_rm_rn_l_D_1111_M_1000_N_1000,
	load_disp_rm_rn_l_D_0000_M_1001_N_1000,
	load_disp_rm_rn_l_D_0001_M_1001_N_1000,
	load_disp_rm_rn_l_D_0010_M_1001_N_1000,
	load_disp_rm_rn_l_D_0011_M_1001_N_1000,
	load_disp_rm_rn_l_D_0100_M_1001_N_1000,
	load_disp_rm_rn_l_D_0101_M_1001_N_1000,
	load_disp_rm_rn_l_D_0110_M_1001_N_1000,
	load_disp_rm_rn_l_D_0111_M_1001_N_1000,
	load_disp_rm_rn_l_D_1000_M_1001_N_1000,
	load_disp_rm_rn_l_D_1001_M_1001_N_1000,
	load_disp_rm_rn_l_D_1010_M_1001_N_1000,
	load_disp_rm_rn_l_D_1011_M_1001_N_1000,
	load_disp_rm_rn_l_D_1100_M_1001_N_1000,
	load_disp_rm_rn_l_D_1101_M_1001_N_1000,
	load_disp_rm_rn_l_D_1110_M_1001_N_1000,
	load_disp_rm_rn_l_D_1111_M_1001_N_1000,
	load_disp_rm_rn_l_D_0000_M_1010_N_1000,
	load_disp_rm_rn_l_D_0001_M_1010_N_1000,
	load_disp_rm_rn_l_D_0010_M_1010_N_1000,
	load_disp_rm_rn_l_D_0011_M_1010_N_1000,
	load_disp_rm_rn_l_D_0100_M_1010_N_1000,
	load_disp_rm_rn_l_D_0101_M_1010_N_1000,
	load_disp_rm_rn_l_D_0110_M_1010_N_1000,
	load_disp_rm_rn_l_D_0111_M_1010_N_1000,
	load_disp_rm_rn_l_D_1000_M_1010_N_1000,
	load_disp_rm_rn_l_D_1001_M_1010_N_1000,
	load_disp_rm_rn_l_D_1010_M_1010_N_1000,
	load_disp_rm_rn_l_D_1011_M_1010_N_1000,
	load_disp_rm_rn_l_D_1100_M_1010_N_1000,
	load_disp_rm_rn_l_D_1101_M_1010_N_1000,
	load_disp_rm_rn_l_D_1110_M_1010_N_1000,
	load_disp_rm_rn_l_D_1111_M_1010_N_1000,
	load_disp_rm_rn_l_D_0000_M_1011_N_1000,
	load_disp_rm_rn_l_D_0001_M_1011_N_1000,
	load_disp_rm_rn_l_D_0010_M_1011_N_1000,
	load_disp_rm_rn_l_D_0011_M_1011_N_1000,
	load_disp_rm_rn_l_D_0100_M_1011_N_1000,
	load_disp_rm_rn_l_D_0101_M_1011_N_1000,
	load_disp_rm_rn_l_D_0110_M_1011_N_1000,
	load_disp_rm_rn_l_D_0111_M_1011_N_1000,
	load_disp_rm_rn_l_D_1000_M_1011_N_1000,
	load_disp_rm_rn_l_D_1001_M_1011_N_1000,
	load_disp_rm_rn_l_D_1010_M_1011_N_1000,
	load_disp_rm_rn_l_D_1011_M_1011_N_1000,
	load_disp_rm_rn_l_D_1100_M_1011_N_1000,
	load_disp_rm_rn_l_D_1101_M_1011_N_1000,
	load_disp_rm_rn_l_D_1110_M_1011_N_1000,
	load_disp_rm_rn_l_D_1111_M_1011_N_1000,
	load_disp_rm_rn_l_D_0000_M_1100_N_1000,
	load_disp_rm_rn_l_D_0001_M_1100_N_1000,
	load_disp_rm_rn_l_D_0010_M_1100_N_1000,
	load_disp_rm_rn_l_D_0011_M_1100_N_1000,
	load_disp_rm_rn_l_D_0100_M_1100_N_1000,
	load_disp_rm_rn_l_D_0101_M_1100_N_1000,
	load_disp_rm_rn_l_D_0110_M_1100_N_1000,
	load_disp_rm_rn_l_D_0111_M_1100_N_1000,
	load_disp_rm_rn_l_D_1000_M_1100_N_1000,
	load_disp_rm_rn_l_D_1001_M_1100_N_1000,
	load_disp_rm_rn_l_D_1010_M_1100_N_1000,
	load_disp_rm_rn_l_D_1011_M_1100_N_1000,
	load_disp_rm_rn_l_D_1100_M_1100_N_1000,
	load_disp_rm_rn_l_D_1101_M_1100_N_1000,
	load_disp_rm_rn_l_D_1110_M_1100_N_1000,
	load_disp_rm_rn_l_D_1111_M_1100_N_1000,
	load_disp_rm_rn_l_D_0000_M_1101_N_1000,
	load_disp_rm_rn_l_D_0001_M_1101_N_1000,
	load_disp_rm_rn_l_D_0010_M_1101_N_1000,
	load_disp_rm_rn_l_D_0011_M_1101_N_1000,
	load_disp_rm_rn_l_D_0100_M_1101_N_1000,
	load_disp_rm_rn_l_D_0101_M_1101_N_1000,
	load_disp_rm_rn_l_D_0110_M_1101_N_1000,
	load_disp_rm_rn_l_D_0111_M_1101_N_1000,
	load_disp_rm_rn_l_D_1000_M_1101_N_1000,
	load_disp_rm_rn_l_D_1001_M_1101_N_1000,
	load_disp_rm_rn_l_D_1010_M_1101_N_1000,
	load_disp_rm_rn_l_D_1011_M_1101_N_1000,
	load_disp_rm_rn_l_D_1100_M_1101_N_1000,
	load_disp_rm_rn_l_D_1101_M_1101_N_1000,
	load_disp_rm_rn_l_D_1110_M_1101_N_1000,
	load_disp_rm_rn_l_D_1111_M_1101_N_1000,
	load_disp_rm_rn_l_D_0000_M_1110_N_1000,
	load_disp_rm_rn_l_D_0001_M_1110_N_1000,
	load_disp_rm_rn_l_D_0010_M_1110_N_1000,
	load_disp_rm_rn_l_D_0011_M_1110_N_1000,
	load_disp_rm_rn_l_D_0100_M_1110_N_1000,
	load_disp_rm_rn_l_D_0101_M_1110_N_1000,
	load_disp_rm_rn_l_D_0110_M_1110_N_1000,
	load_disp_rm_rn_l_D_0111_M_1110_N_1000,
	load_disp_rm_rn_l_D_1000_M_1110_N_1000,
	load_disp_rm_rn_l_D_1001_M_1110_N_1000,
	load_disp_rm_rn_l_D_1010_M_1110_N_1000,
	load_disp_rm_rn_l_D_1011_M_1110_N_1000,
	load_disp_rm_rn_l_D_1100_M_1110_N_1000,
	load_disp_rm_rn_l_D_1101_M_1110_N_1000,
	load_disp_rm_rn_l_D_1110_M_1110_N_1000,
	load_disp_rm_rn_l_D_1111_M_1110_N_1000,
	load_disp_rm_rn_l_D_0000_M_1111_N_1000,
	load_disp_rm_rn_l_D_0001_M_1111_N_1000,
	load_disp_rm_rn_l_D_0010_M_1111_N_1000,
	load_disp_rm_rn_l_D_0011_M_1111_N_1000,
	load_disp_rm_rn_l_D_0100_M_1111_N_1000,
	load_disp_rm_rn_l_D_0101_M_1111_N_1000,
	load_disp_rm_rn_l_D_0110_M_1111_N_1000,
	load_disp_rm_rn_l_D_0111_M_1111_N_1000,
	load_disp_rm_rn_l_D_1000_M_1111_N_1000,
	load_disp_rm_rn_l_D_1001_M_1111_N_1000,
	load_disp_rm_rn_l_D_1010_M_1111_N_1000,
	load_disp_rm_rn_l_D_1011_M_1111_N_1000,
	load_disp_rm_rn_l_D_1100_M_1111_N_1000,
	load_disp_rm_rn_l_D_1101_M_1111_N_1000,
	load_disp_rm_rn_l_D_1110_M_1111_N_1000,
	load_disp_rm_rn_l_D_1111_M_1111_N_1000,
	load_disp_rm_rn_l_D_0000_M_0000_N_1001,
	load_disp_rm_rn_l_D_0001_M_0000_N_1001,
	load_disp_rm_rn_l_D_0010_M_0000_N_1001,
	load_disp_rm_rn_l_D_0011_M_0000_N_1001,
	load_disp_rm_rn_l_D_0100_M_0000_N_1001,
	load_disp_rm_rn_l_D_0101_M_0000_N_1001,
	load_disp_rm_rn_l_D_0110_M_0000_N_1001,
	load_disp_rm_rn_l_D_0111_M_0000_N_1001,
	load_disp_rm_rn_l_D_1000_M_0000_N_1001,
	load_disp_rm_rn_l_D_1001_M_0000_N_1001,
	load_disp_rm_rn_l_D_1010_M_0000_N_1001,
	load_disp_rm_rn_l_D_1011_M_0000_N_1001,
	load_disp_rm_rn_l_D_1100_M_0000_N_1001,
	load_disp_rm_rn_l_D_1101_M_0000_N_1001,
	load_disp_rm_rn_l_D_1110_M_0000_N_1001,
	load_disp_rm_rn_l_D_1111_M_0000_N_1001,
	load_disp_rm_rn_l_D_0000_M_0001_N_1001,
	load_disp_rm_rn_l_D_0001_M_0001_N_1001,
	load_disp_rm_rn_l_D_0010_M_0001_N_1001,
	load_disp_rm_rn_l_D_0011_M_0001_N_1001,
	load_disp_rm_rn_l_D_0100_M_0001_N_1001,
	load_disp_rm_rn_l_D_0101_M_0001_N_1001,
	load_disp_rm_rn_l_D_0110_M_0001_N_1001,
	load_disp_rm_rn_l_D_0111_M_0001_N_1001,
	load_disp_rm_rn_l_D_1000_M_0001_N_1001,
	load_disp_rm_rn_l_D_1001_M_0001_N_1001,
	load_disp_rm_rn_l_D_1010_M_0001_N_1001,
	load_disp_rm_rn_l_D_1011_M_0001_N_1001,
	load_disp_rm_rn_l_D_1100_M_0001_N_1001,
	load_disp_rm_rn_l_D_1101_M_0001_N_1001,
	load_disp_rm_rn_l_D_1110_M_0001_N_1001,
	load_disp_rm_rn_l_D_1111_M_0001_N_1001,
	load_disp_rm_rn_l_D_0000_M_0010_N_1001,
	load_disp_rm_rn_l_D_0001_M_0010_N_1001,
	load_disp_rm_rn_l_D_0010_M_0010_N_1001,
	load_disp_rm_rn_l_D_0011_M_0010_N_1001,
	load_disp_rm_rn_l_D_0100_M_0010_N_1001,
	load_disp_rm_rn_l_D_0101_M_0010_N_1001,
	load_disp_rm_rn_l_D_0110_M_0010_N_1001,
	load_disp_rm_rn_l_D_0111_M_0010_N_1001,
	load_disp_rm_rn_l_D_1000_M_0010_N_1001,
	load_disp_rm_rn_l_D_1001_M_0010_N_1001,
	load_disp_rm_rn_l_D_1010_M_0010_N_1001,
	load_disp_rm_rn_l_D_1011_M_0010_N_1001,
	load_disp_rm_rn_l_D_1100_M_0010_N_1001,
	load_disp_rm_rn_l_D_1101_M_0010_N_1001,
	load_disp_rm_rn_l_D_1110_M_0010_N_1001,
	load_disp_rm_rn_l_D_1111_M_0010_N_1001,
	load_disp_rm_rn_l_D_0000_M_0011_N_1001,
	load_disp_rm_rn_l_D_0001_M_0011_N_1001,
	load_disp_rm_rn_l_D_0010_M_0011_N_1001,
	load_disp_rm_rn_l_D_0011_M_0011_N_1001,
	load_disp_rm_rn_l_D_0100_M_0011_N_1001,
	load_disp_rm_rn_l_D_0101_M_0011_N_1001,
	load_disp_rm_rn_l_D_0110_M_0011_N_1001,
	load_disp_rm_rn_l_D_0111_M_0011_N_1001,
	load_disp_rm_rn_l_D_1000_M_0011_N_1001,
	load_disp_rm_rn_l_D_1001_M_0011_N_1001,
	load_disp_rm_rn_l_D_1010_M_0011_N_1001,
	load_disp_rm_rn_l_D_1011_M_0011_N_1001,
	load_disp_rm_rn_l_D_1100_M_0011_N_1001,
	load_disp_rm_rn_l_D_1101_M_0011_N_1001,
	load_disp_rm_rn_l_D_1110_M_0011_N_1001,
	load_disp_rm_rn_l_D_1111_M_0011_N_1001,
	load_disp_rm_rn_l_D_0000_M_0100_N_1001,
	load_disp_rm_rn_l_D_0001_M_0100_N_1001,
	load_disp_rm_rn_l_D_0010_M_0100_N_1001,
	load_disp_rm_rn_l_D_0011_M_0100_N_1001,
	load_disp_rm_rn_l_D_0100_M_0100_N_1001,
	load_disp_rm_rn_l_D_0101_M_0100_N_1001,
	load_disp_rm_rn_l_D_0110_M_0100_N_1001,
	load_disp_rm_rn_l_D_0111_M_0100_N_1001,
	load_disp_rm_rn_l_D_1000_M_0100_N_1001,
	load_disp_rm_rn_l_D_1001_M_0100_N_1001,
	load_disp_rm_rn_l_D_1010_M_0100_N_1001,
	load_disp_rm_rn_l_D_1011_M_0100_N_1001,
	load_disp_rm_rn_l_D_1100_M_0100_N_1001,
	load_disp_rm_rn_l_D_1101_M_0100_N_1001,
	load_disp_rm_rn_l_D_1110_M_0100_N_1001,
	load_disp_rm_rn_l_D_1111_M_0100_N_1001,
	load_disp_rm_rn_l_D_0000_M_0101_N_1001,
	load_disp_rm_rn_l_D_0001_M_0101_N_1001,
	load_disp_rm_rn_l_D_0010_M_0101_N_1001,
	load_disp_rm_rn_l_D_0011_M_0101_N_1001,
	load_disp_rm_rn_l_D_0100_M_0101_N_1001,
	load_disp_rm_rn_l_D_0101_M_0101_N_1001,
	load_disp_rm_rn_l_D_0110_M_0101_N_1001,
	load_disp_rm_rn_l_D_0111_M_0101_N_1001,
	load_disp_rm_rn_l_D_1000_M_0101_N_1001,
	load_disp_rm_rn_l_D_1001_M_0101_N_1001,
	load_disp_rm_rn_l_D_1010_M_0101_N_1001,
	load_disp_rm_rn_l_D_1011_M_0101_N_1001,
	load_disp_rm_rn_l_D_1100_M_0101_N_1001,
	load_disp_rm_rn_l_D_1101_M_0101_N_1001,
	load_disp_rm_rn_l_D_1110_M_0101_N_1001,
	load_disp_rm_rn_l_D_1111_M_0101_N_1001,
	load_disp_rm_rn_l_D_0000_M_0110_N_1001,
	load_disp_rm_rn_l_D_0001_M_0110_N_1001,
	load_disp_rm_rn_l_D_0010_M_0110_N_1001,
	load_disp_rm_rn_l_D_0011_M_0110_N_1001,
	load_disp_rm_rn_l_D_0100_M_0110_N_1001,
	load_disp_rm_rn_l_D_0101_M_0110_N_1001,
	load_disp_rm_rn_l_D_0110_M_0110_N_1001,
	load_disp_rm_rn_l_D_0111_M_0110_N_1001,
	load_disp_rm_rn_l_D_1000_M_0110_N_1001,
	load_disp_rm_rn_l_D_1001_M_0110_N_1001,
	load_disp_rm_rn_l_D_1010_M_0110_N_1001,
	load_disp_rm_rn_l_D_1011_M_0110_N_1001,
	load_disp_rm_rn_l_D_1100_M_0110_N_1001,
	load_disp_rm_rn_l_D_1101_M_0110_N_1001,
	load_disp_rm_rn_l_D_1110_M_0110_N_1001,
	load_disp_rm_rn_l_D_1111_M_0110_N_1001,
	load_disp_rm_rn_l_D_0000_M_0111_N_1001,
	load_disp_rm_rn_l_D_0001_M_0111_N_1001,
	load_disp_rm_rn_l_D_0010_M_0111_N_1001,
	load_disp_rm_rn_l_D_0011_M_0111_N_1001,
	load_disp_rm_rn_l_D_0100_M_0111_N_1001,
	load_disp_rm_rn_l_D_0101_M_0111_N_1001,
	load_disp_rm_rn_l_D_0110_M_0111_N_1001,
	load_disp_rm_rn_l_D_0111_M_0111_N_1001,
	load_disp_rm_rn_l_D_1000_M_0111_N_1001,
	load_disp_rm_rn_l_D_1001_M_0111_N_1001,
	load_disp_rm_rn_l_D_1010_M_0111_N_1001,
	load_disp_rm_rn_l_D_1011_M_0111_N_1001,
	load_disp_rm_rn_l_D_1100_M_0111_N_1001,
	load_disp_rm_rn_l_D_1101_M_0111_N_1001,
	load_disp_rm_rn_l_D_1110_M_0111_N_1001,
	load_disp_rm_rn_l_D_1111_M_0111_N_1001,
	load_disp_rm_rn_l_D_0000_M_1000_N_1001,
	load_disp_rm_rn_l_D_0001_M_1000_N_1001,
	load_disp_rm_rn_l_D_0010_M_1000_N_1001,
	load_disp_rm_rn_l_D_0011_M_1000_N_1001,
	load_disp_rm_rn_l_D_0100_M_1000_N_1001,
	load_disp_rm_rn_l_D_0101_M_1000_N_1001,
	load_disp_rm_rn_l_D_0110_M_1000_N_1001,
	load_disp_rm_rn_l_D_0111_M_1000_N_1001,
	load_disp_rm_rn_l_D_1000_M_1000_N_1001,
	load_disp_rm_rn_l_D_1001_M_1000_N_1001,
	load_disp_rm_rn_l_D_1010_M_1000_N_1001,
	load_disp_rm_rn_l_D_1011_M_1000_N_1001,
	load_disp_rm_rn_l_D_1100_M_1000_N_1001,
	load_disp_rm_rn_l_D_1101_M_1000_N_1001,
	load_disp_rm_rn_l_D_1110_M_1000_N_1001,
	load_disp_rm_rn_l_D_1111_M_1000_N_1001,
	load_disp_rm_rn_l_D_0000_M_1001_N_1001,
	load_disp_rm_rn_l_D_0001_M_1001_N_1001,
	load_disp_rm_rn_l_D_0010_M_1001_N_1001,
	load_disp_rm_rn_l_D_0011_M_1001_N_1001,
	load_disp_rm_rn_l_D_0100_M_1001_N_1001,
	load_disp_rm_rn_l_D_0101_M_1001_N_1001,
	load_disp_rm_rn_l_D_0110_M_1001_N_1001,
	load_disp_rm_rn_l_D_0111_M_1001_N_1001,
	load_disp_rm_rn_l_D_1000_M_1001_N_1001,
	load_disp_rm_rn_l_D_1001_M_1001_N_1001,
	load_disp_rm_rn_l_D_1010_M_1001_N_1001,
	load_disp_rm_rn_l_D_1011_M_1001_N_1001,
	load_disp_rm_rn_l_D_1100_M_1001_N_1001,
	load_disp_rm_rn_l_D_1101_M_1001_N_1001,
	load_disp_rm_rn_l_D_1110_M_1001_N_1001,
	load_disp_rm_rn_l_D_1111_M_1001_N_1001,
	load_disp_rm_rn_l_D_0000_M_1010_N_1001,
	load_disp_rm_rn_l_D_0001_M_1010_N_1001,
	load_disp_rm_rn_l_D_0010_M_1010_N_1001,
	load_disp_rm_rn_l_D_0011_M_1010_N_1001,
	load_disp_rm_rn_l_D_0100_M_1010_N_1001,
	load_disp_rm_rn_l_D_0101_M_1010_N_1001,
	load_disp_rm_rn_l_D_0110_M_1010_N_1001,
	load_disp_rm_rn_l_D_0111_M_1010_N_1001,
	load_disp_rm_rn_l_D_1000_M_1010_N_1001,
	load_disp_rm_rn_l_D_1001_M_1010_N_1001,
	load_disp_rm_rn_l_D_1010_M_1010_N_1001,
	load_disp_rm_rn_l_D_1011_M_1010_N_1001,
	load_disp_rm_rn_l_D_1100_M_1010_N_1001,
	load_disp_rm_rn_l_D_1101_M_1010_N_1001,
	load_disp_rm_rn_l_D_1110_M_1010_N_1001,
	load_disp_rm_rn_l_D_1111_M_1010_N_1001,
	load_disp_rm_rn_l_D_0000_M_1011_N_1001,
	load_disp_rm_rn_l_D_0001_M_1011_N_1001,
	load_disp_rm_rn_l_D_0010_M_1011_N_1001,
	load_disp_rm_rn_l_D_0011_M_1011_N_1001,
	load_disp_rm_rn_l_D_0100_M_1011_N_1001,
	load_disp_rm_rn_l_D_0101_M_1011_N_1001,
	load_disp_rm_rn_l_D_0110_M_1011_N_1001,
	load_disp_rm_rn_l_D_0111_M_1011_N_1001,
	load_disp_rm_rn_l_D_1000_M_1011_N_1001,
	load_disp_rm_rn_l_D_1001_M_1011_N_1001,
	load_disp_rm_rn_l_D_1010_M_1011_N_1001,
	load_disp_rm_rn_l_D_1011_M_1011_N_1001,
	load_disp_rm_rn_l_D_1100_M_1011_N_1001,
	load_disp_rm_rn_l_D_1101_M_1011_N_1001,
	load_disp_rm_rn_l_D_1110_M_1011_N_1001,
	load_disp_rm_rn_l_D_1111_M_1011_N_1001,
	load_disp_rm_rn_l_D_0000_M_1100_N_1001,
	load_disp_rm_rn_l_D_0001_M_1100_N_1001,
	load_disp_rm_rn_l_D_0010_M_1100_N_1001,
	load_disp_rm_rn_l_D_0011_M_1100_N_1001,
	load_disp_rm_rn_l_D_0100_M_1100_N_1001,
	load_disp_rm_rn_l_D_0101_M_1100_N_1001,
	load_disp_rm_rn_l_D_0110_M_1100_N_1001,
	load_disp_rm_rn_l_D_0111_M_1100_N_1001,
	load_disp_rm_rn_l_D_1000_M_1100_N_1001,
	load_disp_rm_rn_l_D_1001_M_1100_N_1001,
	load_disp_rm_rn_l_D_1010_M_1100_N_1001,
	load_disp_rm_rn_l_D_1011_M_1100_N_1001,
	load_disp_rm_rn_l_D_1100_M_1100_N_1001,
	load_disp_rm_rn_l_D_1101_M_1100_N_1001,
	load_disp_rm_rn_l_D_1110_M_1100_N_1001,
	load_disp_rm_rn_l_D_1111_M_1100_N_1001,
	load_disp_rm_rn_l_D_0000_M_1101_N_1001,
	load_disp_rm_rn_l_D_0001_M_1101_N_1001,
	load_disp_rm_rn_l_D_0010_M_1101_N_1001,
	load_disp_rm_rn_l_D_0011_M_1101_N_1001,
	load_disp_rm_rn_l_D_0100_M_1101_N_1001,
	load_disp_rm_rn_l_D_0101_M_1101_N_1001,
	load_disp_rm_rn_l_D_0110_M_1101_N_1001,
	load_disp_rm_rn_l_D_0111_M_1101_N_1001,
	load_disp_rm_rn_l_D_1000_M_1101_N_1001,
	load_disp_rm_rn_l_D_1001_M_1101_N_1001,
	load_disp_rm_rn_l_D_1010_M_1101_N_1001,
	load_disp_rm_rn_l_D_1011_M_1101_N_1001,
	load_disp_rm_rn_l_D_1100_M_1101_N_1001,
	load_disp_rm_rn_l_D_1101_M_1101_N_1001,
	load_disp_rm_rn_l_D_1110_M_1101_N_1001,
	load_disp_rm_rn_l_D_1111_M_1101_N_1001,
	load_disp_rm_rn_l_D_0000_M_1110_N_1001,
	load_disp_rm_rn_l_D_0001_M_1110_N_1001,
	load_disp_rm_rn_l_D_0010_M_1110_N_1001,
	load_disp_rm_rn_l_D_0011_M_1110_N_1001,
	load_disp_rm_rn_l_D_0100_M_1110_N_1001,
	load_disp_rm_rn_l_D_0101_M_1110_N_1001,
	load_disp_rm_rn_l_D_0110_M_1110_N_1001,
	load_disp_rm_rn_l_D_0111_M_1110_N_1001,
	load_disp_rm_rn_l_D_1000_M_1110_N_1001,
	load_disp_rm_rn_l_D_1001_M_1110_N_1001,
	load_disp_rm_rn_l_D_1010_M_1110_N_1001,
	load_disp_rm_rn_l_D_1011_M_1110_N_1001,
	load_disp_rm_rn_l_D_1100_M_1110_N_1001,
	load_disp_rm_rn_l_D_1101_M_1110_N_1001,
	load_disp_rm_rn_l_D_1110_M_1110_N_1001,
	load_disp_rm_rn_l_D_1111_M_1110_N_1001,
	load_disp_rm_rn_l_D_0000_M_1111_N_1001,
	load_disp_rm_rn_l_D_0001_M_1111_N_1001,
	load_disp_rm_rn_l_D_0010_M_1111_N_1001,
	load_disp_rm_rn_l_D_0011_M_1111_N_1001,
	load_disp_rm_rn_l_D_0100_M_1111_N_1001,
	load_disp_rm_rn_l_D_0101_M_1111_N_1001,
	load_disp_rm_rn_l_D_0110_M_1111_N_1001,
	load_disp_rm_rn_l_D_0111_M_1111_N_1001,
	load_disp_rm_rn_l_D_1000_M_1111_N_1001,
	load_disp_rm_rn_l_D_1001_M_1111_N_1001,
	load_disp_rm_rn_l_D_1010_M_1111_N_1001,
	load_disp_rm_rn_l_D_1011_M_1111_N_1001,
	load_disp_rm_rn_l_D_1100_M_1111_N_1001,
	load_disp_rm_rn_l_D_1101_M_1111_N_1001,
	load_disp_rm_rn_l_D_1110_M_1111_N_1001,
	load_disp_rm_rn_l_D_1111_M_1111_N_1001,
	load_disp_rm_rn_l_D_0000_M_0000_N_1010,
	load_disp_rm_rn_l_D_0001_M_0000_N_1010,
	load_disp_rm_rn_l_D_0010_M_0000_N_1010,
	load_disp_rm_rn_l_D_0011_M_0000_N_1010,
	load_disp_rm_rn_l_D_0100_M_0000_N_1010,
	load_disp_rm_rn_l_D_0101_M_0000_N_1010,
	load_disp_rm_rn_l_D_0110_M_0000_N_1010,
	load_disp_rm_rn_l_D_0111_M_0000_N_1010,
	load_disp_rm_rn_l_D_1000_M_0000_N_1010,
	load_disp_rm_rn_l_D_1001_M_0000_N_1010,
	load_disp_rm_rn_l_D_1010_M_0000_N_1010,
	load_disp_rm_rn_l_D_1011_M_0000_N_1010,
	load_disp_rm_rn_l_D_1100_M_0000_N_1010,
	load_disp_rm_rn_l_D_1101_M_0000_N_1010,
	load_disp_rm_rn_l_D_1110_M_0000_N_1010,
	load_disp_rm_rn_l_D_1111_M_0000_N_1010,
	load_disp_rm_rn_l_D_0000_M_0001_N_1010,
	load_disp_rm_rn_l_D_0001_M_0001_N_1010,
	load_disp_rm_rn_l_D_0010_M_0001_N_1010,
	load_disp_rm_rn_l_D_0011_M_0001_N_1010,
	load_disp_rm_rn_l_D_0100_M_0001_N_1010,
	load_disp_rm_rn_l_D_0101_M_0001_N_1010,
	load_disp_rm_rn_l_D_0110_M_0001_N_1010,
	load_disp_rm_rn_l_D_0111_M_0001_N_1010,
	load_disp_rm_rn_l_D_1000_M_0001_N_1010,
	load_disp_rm_rn_l_D_1001_M_0001_N_1010,
	load_disp_rm_rn_l_D_1010_M_0001_N_1010,
	load_disp_rm_rn_l_D_1011_M_0001_N_1010,
	load_disp_rm_rn_l_D_1100_M_0001_N_1010,
	load_disp_rm_rn_l_D_1101_M_0001_N_1010,
	load_disp_rm_rn_l_D_1110_M_0001_N_1010,
	load_disp_rm_rn_l_D_1111_M_0001_N_1010,
	load_disp_rm_rn_l_D_0000_M_0010_N_1010,
	load_disp_rm_rn_l_D_0001_M_0010_N_1010,
	load_disp_rm_rn_l_D_0010_M_0010_N_1010,
	load_disp_rm_rn_l_D_0011_M_0010_N_1010,
	load_disp_rm_rn_l_D_0100_M_0010_N_1010,
	load_disp_rm_rn_l_D_0101_M_0010_N_1010,
	load_disp_rm_rn_l_D_0110_M_0010_N_1010,
	load_disp_rm_rn_l_D_0111_M_0010_N_1010,
	load_disp_rm_rn_l_D_1000_M_0010_N_1010,
	load_disp_rm_rn_l_D_1001_M_0010_N_1010,
	load_disp_rm_rn_l_D_1010_M_0010_N_1010,
	load_disp_rm_rn_l_D_1011_M_0010_N_1010,
	load_disp_rm_rn_l_D_1100_M_0010_N_1010,
	load_disp_rm_rn_l_D_1101_M_0010_N_1010,
	load_disp_rm_rn_l_D_1110_M_0010_N_1010,
	load_disp_rm_rn_l_D_1111_M_0010_N_1010,
	load_disp_rm_rn_l_D_0000_M_0011_N_1010,
	load_disp_rm_rn_l_D_0001_M_0011_N_1010,
	load_disp_rm_rn_l_D_0010_M_0011_N_1010,
	load_disp_rm_rn_l_D_0011_M_0011_N_1010,
	load_disp_rm_rn_l_D_0100_M_0011_N_1010,
	load_disp_rm_rn_l_D_0101_M_0011_N_1010,
	load_disp_rm_rn_l_D_0110_M_0011_N_1010,
	load_disp_rm_rn_l_D_0111_M_0011_N_1010,
	load_disp_rm_rn_l_D_1000_M_0011_N_1010,
	load_disp_rm_rn_l_D_1001_M_0011_N_1010,
	load_disp_rm_rn_l_D_1010_M_0011_N_1010,
	load_disp_rm_rn_l_D_1011_M_0011_N_1010,
	load_disp_rm_rn_l_D_1100_M_0011_N_1010,
	load_disp_rm_rn_l_D_1101_M_0011_N_1010,
	load_disp_rm_rn_l_D_1110_M_0011_N_1010,
	load_disp_rm_rn_l_D_1111_M_0011_N_1010,
	load_disp_rm_rn_l_D_0000_M_0100_N_1010,
	load_disp_rm_rn_l_D_0001_M_0100_N_1010,
	load_disp_rm_rn_l_D_0010_M_0100_N_1010,
	load_disp_rm_rn_l_D_0011_M_0100_N_1010,
	load_disp_rm_rn_l_D_0100_M_0100_N_1010,
	load_disp_rm_rn_l_D_0101_M_0100_N_1010,
	load_disp_rm_rn_l_D_0110_M_0100_N_1010,
	load_disp_rm_rn_l_D_0111_M_0100_N_1010,
	load_disp_rm_rn_l_D_1000_M_0100_N_1010,
	load_disp_rm_rn_l_D_1001_M_0100_N_1010,
	load_disp_rm_rn_l_D_1010_M_0100_N_1010,
	load_disp_rm_rn_l_D_1011_M_0100_N_1010,
	load_disp_rm_rn_l_D_1100_M_0100_N_1010,
	load_disp_rm_rn_l_D_1101_M_0100_N_1010,
	load_disp_rm_rn_l_D_1110_M_0100_N_1010,
	load_disp_rm_rn_l_D_1111_M_0100_N_1010,
	load_disp_rm_rn_l_D_0000_M_0101_N_1010,
	load_disp_rm_rn_l_D_0001_M_0101_N_1010,
	load_disp_rm_rn_l_D_0010_M_0101_N_1010,
	load_disp_rm_rn_l_D_0011_M_0101_N_1010,
	load_disp_rm_rn_l_D_0100_M_0101_N_1010,
	load_disp_rm_rn_l_D_0101_M_0101_N_1010,
	load_disp_rm_rn_l_D_0110_M_0101_N_1010,
	load_disp_rm_rn_l_D_0111_M_0101_N_1010,
	load_disp_rm_rn_l_D_1000_M_0101_N_1010,
	load_disp_rm_rn_l_D_1001_M_0101_N_1010,
	load_disp_rm_rn_l_D_1010_M_0101_N_1010,
	load_disp_rm_rn_l_D_1011_M_0101_N_1010,
	load_disp_rm_rn_l_D_1100_M_0101_N_1010,
	load_disp_rm_rn_l_D_1101_M_0101_N_1010,
	load_disp_rm_rn_l_D_1110_M_0101_N_1010,
	load_disp_rm_rn_l_D_1111_M_0101_N_1010,
	load_disp_rm_rn_l_D_0000_M_0110_N_1010,
	load_disp_rm_rn_l_D_0001_M_0110_N_1010,
	load_disp_rm_rn_l_D_0010_M_0110_N_1010,
	load_disp_rm_rn_l_D_0011_M_0110_N_1010,
	load_disp_rm_rn_l_D_0100_M_0110_N_1010,
	load_disp_rm_rn_l_D_0101_M_0110_N_1010,
	load_disp_rm_rn_l_D_0110_M_0110_N_1010,
	load_disp_rm_rn_l_D_0111_M_0110_N_1010,
	load_disp_rm_rn_l_D_1000_M_0110_N_1010,
	load_disp_rm_rn_l_D_1001_M_0110_N_1010,
	load_disp_rm_rn_l_D_1010_M_0110_N_1010,
	load_disp_rm_rn_l_D_1011_M_0110_N_1010,
	load_disp_rm_rn_l_D_1100_M_0110_N_1010,
	load_disp_rm_rn_l_D_1101_M_0110_N_1010,
	load_disp_rm_rn_l_D_1110_M_0110_N_1010,
	load_disp_rm_rn_l_D_1111_M_0110_N_1010,
	load_disp_rm_rn_l_D_0000_M_0111_N_1010,
	load_disp_rm_rn_l_D_0001_M_0111_N_1010,
	load_disp_rm_rn_l_D_0010_M_0111_N_1010,
	load_disp_rm_rn_l_D_0011_M_0111_N_1010,
	load_disp_rm_rn_l_D_0100_M_0111_N_1010,
	load_disp_rm_rn_l_D_0101_M_0111_N_1010,
	load_disp_rm_rn_l_D_0110_M_0111_N_1010,
	load_disp_rm_rn_l_D_0111_M_0111_N_1010,
	load_disp_rm_rn_l_D_1000_M_0111_N_1010,
	load_disp_rm_rn_l_D_1001_M_0111_N_1010,
	load_disp_rm_rn_l_D_1010_M_0111_N_1010,
	load_disp_rm_rn_l_D_1011_M_0111_N_1010,
	load_disp_rm_rn_l_D_1100_M_0111_N_1010,
	load_disp_rm_rn_l_D_1101_M_0111_N_1010,
	load_disp_rm_rn_l_D_1110_M_0111_N_1010,
	load_disp_rm_rn_l_D_1111_M_0111_N_1010,
	load_disp_rm_rn_l_D_0000_M_1000_N_1010,
	load_disp_rm_rn_l_D_0001_M_1000_N_1010,
	load_disp_rm_rn_l_D_0010_M_1000_N_1010,
	load_disp_rm_rn_l_D_0011_M_1000_N_1010,
	load_disp_rm_rn_l_D_0100_M_1000_N_1010,
	load_disp_rm_rn_l_D_0101_M_1000_N_1010,
	load_disp_rm_rn_l_D_0110_M_1000_N_1010,
	load_disp_rm_rn_l_D_0111_M_1000_N_1010,
	load_disp_rm_rn_l_D_1000_M_1000_N_1010,
	load_disp_rm_rn_l_D_1001_M_1000_N_1010,
	load_disp_rm_rn_l_D_1010_M_1000_N_1010,
	load_disp_rm_rn_l_D_1011_M_1000_N_1010,
	load_disp_rm_rn_l_D_1100_M_1000_N_1010,
	load_disp_rm_rn_l_D_1101_M_1000_N_1010,
	load_disp_rm_rn_l_D_1110_M_1000_N_1010,
	load_disp_rm_rn_l_D_1111_M_1000_N_1010,
	load_disp_rm_rn_l_D_0000_M_1001_N_1010,
	load_disp_rm_rn_l_D_0001_M_1001_N_1010,
	load_disp_rm_rn_l_D_0010_M_1001_N_1010,
	load_disp_rm_rn_l_D_0011_M_1001_N_1010,
	load_disp_rm_rn_l_D_0100_M_1001_N_1010,
	load_disp_rm_rn_l_D_0101_M_1001_N_1010,
	load_disp_rm_rn_l_D_0110_M_1001_N_1010,
	load_disp_rm_rn_l_D_0111_M_1001_N_1010,
	load_disp_rm_rn_l_D_1000_M_1001_N_1010,
	load_disp_rm_rn_l_D_1001_M_1001_N_1010,
	load_disp_rm_rn_l_D_1010_M_1001_N_1010,
	load_disp_rm_rn_l_D_1011_M_1001_N_1010,
	load_disp_rm_rn_l_D_1100_M_1001_N_1010,
	load_disp_rm_rn_l_D_1101_M_1001_N_1010,
	load_disp_rm_rn_l_D_1110_M_1001_N_1010,
	load_disp_rm_rn_l_D_1111_M_1001_N_1010,
	load_disp_rm_rn_l_D_0000_M_1010_N_1010,
	load_disp_rm_rn_l_D_0001_M_1010_N_1010,
	load_disp_rm_rn_l_D_0010_M_1010_N_1010,
	load_disp_rm_rn_l_D_0011_M_1010_N_1010,
	load_disp_rm_rn_l_D_0100_M_1010_N_1010,
	load_disp_rm_rn_l_D_0101_M_1010_N_1010,
	load_disp_rm_rn_l_D_0110_M_1010_N_1010,
	load_disp_rm_rn_l_D_0111_M_1010_N_1010,
	load_disp_rm_rn_l_D_1000_M_1010_N_1010,
	load_disp_rm_rn_l_D_1001_M_1010_N_1010,
	load_disp_rm_rn_l_D_1010_M_1010_N_1010,
	load_disp_rm_rn_l_D_1011_M_1010_N_1010,
	load_disp_rm_rn_l_D_1100_M_1010_N_1010,
	load_disp_rm_rn_l_D_1101_M_1010_N_1010,
	load_disp_rm_rn_l_D_1110_M_1010_N_1010,
	load_disp_rm_rn_l_D_1111_M_1010_N_1010,
	load_disp_rm_rn_l_D_0000_M_1011_N_1010,
	load_disp_rm_rn_l_D_0001_M_1011_N_1010,
	load_disp_rm_rn_l_D_0010_M_1011_N_1010,
	load_disp_rm_rn_l_D_0011_M_1011_N_1010,
	load_disp_rm_rn_l_D_0100_M_1011_N_1010,
	load_disp_rm_rn_l_D_0101_M_1011_N_1010,
	load_disp_rm_rn_l_D_0110_M_1011_N_1010,
	load_disp_rm_rn_l_D_0111_M_1011_N_1010,
	load_disp_rm_rn_l_D_1000_M_1011_N_1010,
	load_disp_rm_rn_l_D_1001_M_1011_N_1010,
	load_disp_rm_rn_l_D_1010_M_1011_N_1010,
	load_disp_rm_rn_l_D_1011_M_1011_N_1010,
	load_disp_rm_rn_l_D_1100_M_1011_N_1010,
	load_disp_rm_rn_l_D_1101_M_1011_N_1010,
	load_disp_rm_rn_l_D_1110_M_1011_N_1010,
	load_disp_rm_rn_l_D_1111_M_1011_N_1010,
	load_disp_rm_rn_l_D_0000_M_1100_N_1010,
	load_disp_rm_rn_l_D_0001_M_1100_N_1010,
	load_disp_rm_rn_l_D_0010_M_1100_N_1010,
	load_disp_rm_rn_l_D_0011_M_1100_N_1010,
	load_disp_rm_rn_l_D_0100_M_1100_N_1010,
	load_disp_rm_rn_l_D_0101_M_1100_N_1010,
	load_disp_rm_rn_l_D_0110_M_1100_N_1010,
	load_disp_rm_rn_l_D_0111_M_1100_N_1010,
	load_disp_rm_rn_l_D_1000_M_1100_N_1010,
	load_disp_rm_rn_l_D_1001_M_1100_N_1010,
	load_disp_rm_rn_l_D_1010_M_1100_N_1010,
	load_disp_rm_rn_l_D_1011_M_1100_N_1010,
	load_disp_rm_rn_l_D_1100_M_1100_N_1010,
	load_disp_rm_rn_l_D_1101_M_1100_N_1010,
	load_disp_rm_rn_l_D_1110_M_1100_N_1010,
	load_disp_rm_rn_l_D_1111_M_1100_N_1010,
	load_disp_rm_rn_l_D_0000_M_1101_N_1010,
	load_disp_rm_rn_l_D_0001_M_1101_N_1010,
	load_disp_rm_rn_l_D_0010_M_1101_N_1010,
	load_disp_rm_rn_l_D_0011_M_1101_N_1010,
	load_disp_rm_rn_l_D_0100_M_1101_N_1010,
	load_disp_rm_rn_l_D_0101_M_1101_N_1010,
	load_disp_rm_rn_l_D_0110_M_1101_N_1010,
	load_disp_rm_rn_l_D_0111_M_1101_N_1010,
	load_disp_rm_rn_l_D_1000_M_1101_N_1010,
	load_disp_rm_rn_l_D_1001_M_1101_N_1010,
	load_disp_rm_rn_l_D_1010_M_1101_N_1010,
	load_disp_rm_rn_l_D_1011_M_1101_N_1010,
	load_disp_rm_rn_l_D_1100_M_1101_N_1010,
	load_disp_rm_rn_l_D_1101_M_1101_N_1010,
	load_disp_rm_rn_l_D_1110_M_1101_N_1010,
	load_disp_rm_rn_l_D_1111_M_1101_N_1010,
	load_disp_rm_rn_l_D_0000_M_1110_N_1010,
	load_disp_rm_rn_l_D_0001_M_1110_N_1010,
	load_disp_rm_rn_l_D_0010_M_1110_N_1010,
	load_disp_rm_rn_l_D_0011_M_1110_N_1010,
	load_disp_rm_rn_l_D_0100_M_1110_N_1010,
	load_disp_rm_rn_l_D_0101_M_1110_N_1010,
	load_disp_rm_rn_l_D_0110_M_1110_N_1010,
	load_disp_rm_rn_l_D_0111_M_1110_N_1010,
	load_disp_rm_rn_l_D_1000_M_1110_N_1010,
	load_disp_rm_rn_l_D_1001_M_1110_N_1010,
	load_disp_rm_rn_l_D_1010_M_1110_N_1010,
	load_disp_rm_rn_l_D_1011_M_1110_N_1010,
	load_disp_rm_rn_l_D_1100_M_1110_N_1010,
	load_disp_rm_rn_l_D_1101_M_1110_N_1010,
	load_disp_rm_rn_l_D_1110_M_1110_N_1010,
	load_disp_rm_rn_l_D_1111_M_1110_N_1010,
	load_disp_rm_rn_l_D_0000_M_1111_N_1010,
	load_disp_rm_rn_l_D_0001_M_1111_N_1010,
	load_disp_rm_rn_l_D_0010_M_1111_N_1010,
	load_disp_rm_rn_l_D_0011_M_1111_N_1010,
	load_disp_rm_rn_l_D_0100_M_1111_N_1010,
	load_disp_rm_rn_l_D_0101_M_1111_N_1010,
	load_disp_rm_rn_l_D_0110_M_1111_N_1010,
	load_disp_rm_rn_l_D_0111_M_1111_N_1010,
	load_disp_rm_rn_l_D_1000_M_1111_N_1010,
	load_disp_rm_rn_l_D_1001_M_1111_N_1010,
	load_disp_rm_rn_l_D_1010_M_1111_N_1010,
	load_disp_rm_rn_l_D_1011_M_1111_N_1010,
	load_disp_rm_rn_l_D_1100_M_1111_N_1010,
	load_disp_rm_rn_l_D_1101_M_1111_N_1010,
	load_disp_rm_rn_l_D_1110_M_1111_N_1010,
	load_disp_rm_rn_l_D_1111_M_1111_N_1010,
	load_disp_rm_rn_l_D_0000_M_0000_N_1011,
	load_disp_rm_rn_l_D_0001_M_0000_N_1011,
	load_disp_rm_rn_l_D_0010_M_0000_N_1011,
	load_disp_rm_rn_l_D_0011_M_0000_N_1011,
	load_disp_rm_rn_l_D_0100_M_0000_N_1011,
	load_disp_rm_rn_l_D_0101_M_0000_N_1011,
	load_disp_rm_rn_l_D_0110_M_0000_N_1011,
	load_disp_rm_rn_l_D_0111_M_0000_N_1011,
	load_disp_rm_rn_l_D_1000_M_0000_N_1011,
	load_disp_rm_rn_l_D_1001_M_0000_N_1011,
	load_disp_rm_rn_l_D_1010_M_0000_N_1011,
	load_disp_rm_rn_l_D_1011_M_0000_N_1011,
	load_disp_rm_rn_l_D_1100_M_0000_N_1011,
	load_disp_rm_rn_l_D_1101_M_0000_N_1011,
	load_disp_rm_rn_l_D_1110_M_0000_N_1011,
	load_disp_rm_rn_l_D_1111_M_0000_N_1011,
	load_disp_rm_rn_l_D_0000_M_0001_N_1011,
	load_disp_rm_rn_l_D_0001_M_0001_N_1011,
	load_disp_rm_rn_l_D_0010_M_0001_N_1011,
	load_disp_rm_rn_l_D_0011_M_0001_N_1011,
	load_disp_rm_rn_l_D_0100_M_0001_N_1011,
	load_disp_rm_rn_l_D_0101_M_0001_N_1011,
	load_disp_rm_rn_l_D_0110_M_0001_N_1011,
	load_disp_rm_rn_l_D_0111_M_0001_N_1011,
	load_disp_rm_rn_l_D_1000_M_0001_N_1011,
	load_disp_rm_rn_l_D_1001_M_0001_N_1011,
	load_disp_rm_rn_l_D_1010_M_0001_N_1011,
	load_disp_rm_rn_l_D_1011_M_0001_N_1011,
	load_disp_rm_rn_l_D_1100_M_0001_N_1011,
	load_disp_rm_rn_l_D_1101_M_0001_N_1011,
	load_disp_rm_rn_l_D_1110_M_0001_N_1011,
	load_disp_rm_rn_l_D_1111_M_0001_N_1011,
	load_disp_rm_rn_l_D_0000_M_0010_N_1011,
	load_disp_rm_rn_l_D_0001_M_0010_N_1011,
	load_disp_rm_rn_l_D_0010_M_0010_N_1011,
	load_disp_rm_rn_l_D_0011_M_0010_N_1011,
	load_disp_rm_rn_l_D_0100_M_0010_N_1011,
	load_disp_rm_rn_l_D_0101_M_0010_N_1011,
	load_disp_rm_rn_l_D_0110_M_0010_N_1011,
	load_disp_rm_rn_l_D_0111_M_0010_N_1011,
	load_disp_rm_rn_l_D_1000_M_0010_N_1011,
	load_disp_rm_rn_l_D_1001_M_0010_N_1011,
	load_disp_rm_rn_l_D_1010_M_0010_N_1011,
	load_disp_rm_rn_l_D_1011_M_0010_N_1011,
	load_disp_rm_rn_l_D_1100_M_0010_N_1011,
	load_disp_rm_rn_l_D_1101_M_0010_N_1011,
	load_disp_rm_rn_l_D_1110_M_0010_N_1011,
	load_disp_rm_rn_l_D_1111_M_0010_N_1011,
	load_disp_rm_rn_l_D_0000_M_0011_N_1011,
	load_disp_rm_rn_l_D_0001_M_0011_N_1011,
	load_disp_rm_rn_l_D_0010_M_0011_N_1011,
	load_disp_rm_rn_l_D_0011_M_0011_N_1011,
	load_disp_rm_rn_l_D_0100_M_0011_N_1011,
	load_disp_rm_rn_l_D_0101_M_0011_N_1011,
	load_disp_rm_rn_l_D_0110_M_0011_N_1011,
	load_disp_rm_rn_l_D_0111_M_0011_N_1011,
	load_disp_rm_rn_l_D_1000_M_0011_N_1011,
	load_disp_rm_rn_l_D_1001_M_0011_N_1011,
	load_disp_rm_rn_l_D_1010_M_0011_N_1011,
	load_disp_rm_rn_l_D_1011_M_0011_N_1011,
	load_disp_rm_rn_l_D_1100_M_0011_N_1011,
	load_disp_rm_rn_l_D_1101_M_0011_N_1011,
	load_disp_rm_rn_l_D_1110_M_0011_N_1011,
	load_disp_rm_rn_l_D_1111_M_0011_N_1011,
	load_disp_rm_rn_l_D_0000_M_0100_N_1011,
	load_disp_rm_rn_l_D_0001_M_0100_N_1011,
	load_disp_rm_rn_l_D_0010_M_0100_N_1011,
	load_disp_rm_rn_l_D_0011_M_0100_N_1011,
	load_disp_rm_rn_l_D_0100_M_0100_N_1011,
	load_disp_rm_rn_l_D_0101_M_0100_N_1011,
	load_disp_rm_rn_l_D_0110_M_0100_N_1011,
	load_disp_rm_rn_l_D_0111_M_0100_N_1011,
	load_disp_rm_rn_l_D_1000_M_0100_N_1011,
	load_disp_rm_rn_l_D_1001_M_0100_N_1011,
	load_disp_rm_rn_l_D_1010_M_0100_N_1011,
	load_disp_rm_rn_l_D_1011_M_0100_N_1011,
	load_disp_rm_rn_l_D_1100_M_0100_N_1011,
	load_disp_rm_rn_l_D_1101_M_0100_N_1011,
	load_disp_rm_rn_l_D_1110_M_0100_N_1011,
	load_disp_rm_rn_l_D_1111_M_0100_N_1011,
	load_disp_rm_rn_l_D_0000_M_0101_N_1011,
	load_disp_rm_rn_l_D_0001_M_0101_N_1011,
	load_disp_rm_rn_l_D_0010_M_0101_N_1011,
	load_disp_rm_rn_l_D_0011_M_0101_N_1011,
	load_disp_rm_rn_l_D_0100_M_0101_N_1011,
	load_disp_rm_rn_l_D_0101_M_0101_N_1011,
	load_disp_rm_rn_l_D_0110_M_0101_N_1011,
	load_disp_rm_rn_l_D_0111_M_0101_N_1011,
	load_disp_rm_rn_l_D_1000_M_0101_N_1011,
	load_disp_rm_rn_l_D_1001_M_0101_N_1011,
	load_disp_rm_rn_l_D_1010_M_0101_N_1011,
	load_disp_rm_rn_l_D_1011_M_0101_N_1011,
	load_disp_rm_rn_l_D_1100_M_0101_N_1011,
	load_disp_rm_rn_l_D_1101_M_0101_N_1011,
	load_disp_rm_rn_l_D_1110_M_0101_N_1011,
	load_disp_rm_rn_l_D_1111_M_0101_N_1011,
	load_disp_rm_rn_l_D_0000_M_0110_N_1011,
	load_disp_rm_rn_l_D_0001_M_0110_N_1011,
	load_disp_rm_rn_l_D_0010_M_0110_N_1011,
	load_disp_rm_rn_l_D_0011_M_0110_N_1011,
	load_disp_rm_rn_l_D_0100_M_0110_N_1011,
	load_disp_rm_rn_l_D_0101_M_0110_N_1011,
	load_disp_rm_rn_l_D_0110_M_0110_N_1011,
	load_disp_rm_rn_l_D_0111_M_0110_N_1011,
	load_disp_rm_rn_l_D_1000_M_0110_N_1011,
	load_disp_rm_rn_l_D_1001_M_0110_N_1011,
	load_disp_rm_rn_l_D_1010_M_0110_N_1011,
	load_disp_rm_rn_l_D_1011_M_0110_N_1011,
	load_disp_rm_rn_l_D_1100_M_0110_N_1011,
	load_disp_rm_rn_l_D_1101_M_0110_N_1011,
	load_disp_rm_rn_l_D_1110_M_0110_N_1011,
	load_disp_rm_rn_l_D_1111_M_0110_N_1011,
	load_disp_rm_rn_l_D_0000_M_0111_N_1011,
	load_disp_rm_rn_l_D_0001_M_0111_N_1011,
	load_disp_rm_rn_l_D_0010_M_0111_N_1011,
	load_disp_rm_rn_l_D_0011_M_0111_N_1011,
	load_disp_rm_rn_l_D_0100_M_0111_N_1011,
	load_disp_rm_rn_l_D_0101_M_0111_N_1011,
	load_disp_rm_rn_l_D_0110_M_0111_N_1011,
	load_disp_rm_rn_l_D_0111_M_0111_N_1011,
	load_disp_rm_rn_l_D_1000_M_0111_N_1011,
	load_disp_rm_rn_l_D_1001_M_0111_N_1011,
	load_disp_rm_rn_l_D_1010_M_0111_N_1011,
	load_disp_rm_rn_l_D_1011_M_0111_N_1011,
	load_disp_rm_rn_l_D_1100_M_0111_N_1011,
	load_disp_rm_rn_l_D_1101_M_0111_N_1011,
	load_disp_rm_rn_l_D_1110_M_0111_N_1011,
	load_disp_rm_rn_l_D_1111_M_0111_N_1011,
	load_disp_rm_rn_l_D_0000_M_1000_N_1011,
	load_disp_rm_rn_l_D_0001_M_1000_N_1011,
	load_disp_rm_rn_l_D_0010_M_1000_N_1011,
	load_disp_rm_rn_l_D_0011_M_1000_N_1011,
	load_disp_rm_rn_l_D_0100_M_1000_N_1011,
	load_disp_rm_rn_l_D_0101_M_1000_N_1011,
	load_disp_rm_rn_l_D_0110_M_1000_N_1011,
	load_disp_rm_rn_l_D_0111_M_1000_N_1011,
	load_disp_rm_rn_l_D_1000_M_1000_N_1011,
	load_disp_rm_rn_l_D_1001_M_1000_N_1011,
	load_disp_rm_rn_l_D_1010_M_1000_N_1011,
	load_disp_rm_rn_l_D_1011_M_1000_N_1011,
	load_disp_rm_rn_l_D_1100_M_1000_N_1011,
	load_disp_rm_rn_l_D_1101_M_1000_N_1011,
	load_disp_rm_rn_l_D_1110_M_1000_N_1011,
	load_disp_rm_rn_l_D_1111_M_1000_N_1011,
	load_disp_rm_rn_l_D_0000_M_1001_N_1011,
	load_disp_rm_rn_l_D_0001_M_1001_N_1011,
	load_disp_rm_rn_l_D_0010_M_1001_N_1011,
	load_disp_rm_rn_l_D_0011_M_1001_N_1011,
	load_disp_rm_rn_l_D_0100_M_1001_N_1011,
	load_disp_rm_rn_l_D_0101_M_1001_N_1011,
	load_disp_rm_rn_l_D_0110_M_1001_N_1011,
	load_disp_rm_rn_l_D_0111_M_1001_N_1011,
	load_disp_rm_rn_l_D_1000_M_1001_N_1011,
	load_disp_rm_rn_l_D_1001_M_1001_N_1011,
	load_disp_rm_rn_l_D_1010_M_1001_N_1011,
	load_disp_rm_rn_l_D_1011_M_1001_N_1011,
	load_disp_rm_rn_l_D_1100_M_1001_N_1011,
	load_disp_rm_rn_l_D_1101_M_1001_N_1011,
	load_disp_rm_rn_l_D_1110_M_1001_N_1011,
	load_disp_rm_rn_l_D_1111_M_1001_N_1011,
	load_disp_rm_rn_l_D_0000_M_1010_N_1011,
	load_disp_rm_rn_l_D_0001_M_1010_N_1011,
	load_disp_rm_rn_l_D_0010_M_1010_N_1011,
	load_disp_rm_rn_l_D_0011_M_1010_N_1011,
	load_disp_rm_rn_l_D_0100_M_1010_N_1011,
	load_disp_rm_rn_l_D_0101_M_1010_N_1011,
	load_disp_rm_rn_l_D_0110_M_1010_N_1011,
	load_disp_rm_rn_l_D_0111_M_1010_N_1011,
	load_disp_rm_rn_l_D_1000_M_1010_N_1011,
	load_disp_rm_rn_l_D_1001_M_1010_N_1011,
	load_disp_rm_rn_l_D_1010_M_1010_N_1011,
	load_disp_rm_rn_l_D_1011_M_1010_N_1011,
	load_disp_rm_rn_l_D_1100_M_1010_N_1011,
	load_disp_rm_rn_l_D_1101_M_1010_N_1011,
	load_disp_rm_rn_l_D_1110_M_1010_N_1011,
	load_disp_rm_rn_l_D_1111_M_1010_N_1011,
	load_disp_rm_rn_l_D_0000_M_1011_N_1011,
	load_disp_rm_rn_l_D_0001_M_1011_N_1011,
	load_disp_rm_rn_l_D_0010_M_1011_N_1011,
	load_disp_rm_rn_l_D_0011_M_1011_N_1011,
	load_disp_rm_rn_l_D_0100_M_1011_N_1011,
	load_disp_rm_rn_l_D_0101_M_1011_N_1011,
	load_disp_rm_rn_l_D_0110_M_1011_N_1011,
	load_disp_rm_rn_l_D_0111_M_1011_N_1011,
	load_disp_rm_rn_l_D_1000_M_1011_N_1011,
	load_disp_rm_rn_l_D_1001_M_1011_N_1011,
	load_disp_rm_rn_l_D_1010_M_1011_N_1011,
	load_disp_rm_rn_l_D_1011_M_1011_N_1011,
	load_disp_rm_rn_l_D_1100_M_1011_N_1011,
	load_disp_rm_rn_l_D_1101_M_1011_N_1011,
	load_disp_rm_rn_l_D_1110_M_1011_N_1011,
	load_disp_rm_rn_l_D_1111_M_1011_N_1011,
	load_disp_rm_rn_l_D_0000_M_1100_N_1011,
	load_disp_rm_rn_l_D_0001_M_1100_N_1011,
	load_disp_rm_rn_l_D_0010_M_1100_N_1011,
	load_disp_rm_rn_l_D_0011_M_1100_N_1011,
	load_disp_rm_rn_l_D_0100_M_1100_N_1011,
	load_disp_rm_rn_l_D_0101_M_1100_N_1011,
	load_disp_rm_rn_l_D_0110_M_1100_N_1011,
	load_disp_rm_rn_l_D_0111_M_1100_N_1011,
	load_disp_rm_rn_l_D_1000_M_1100_N_1011,
	load_disp_rm_rn_l_D_1001_M_1100_N_1011,
	load_disp_rm_rn_l_D_1010_M_1100_N_1011,
	load_disp_rm_rn_l_D_1011_M_1100_N_1011,
	load_disp_rm_rn_l_D_1100_M_1100_N_1011,
	load_disp_rm_rn_l_D_1101_M_1100_N_1011,
	load_disp_rm_rn_l_D_1110_M_1100_N_1011,
	load_disp_rm_rn_l_D_1111_M_1100_N_1011,
	load_disp_rm_rn_l_D_0000_M_1101_N_1011,
	load_disp_rm_rn_l_D_0001_M_1101_N_1011,
	load_disp_rm_rn_l_D_0010_M_1101_N_1011,
	load_disp_rm_rn_l_D_0011_M_1101_N_1011,
	load_disp_rm_rn_l_D_0100_M_1101_N_1011,
	load_disp_rm_rn_l_D_0101_M_1101_N_1011,
	load_disp_rm_rn_l_D_0110_M_1101_N_1011,
	load_disp_rm_rn_l_D_0111_M_1101_N_1011,
	load_disp_rm_rn_l_D_1000_M_1101_N_1011,
	load_disp_rm_rn_l_D_1001_M_1101_N_1011,
	load_disp_rm_rn_l_D_1010_M_1101_N_1011,
	load_disp_rm_rn_l_D_1011_M_1101_N_1011,
	load_disp_rm_rn_l_D_1100_M_1101_N_1011,
	load_disp_rm_rn_l_D_1101_M_1101_N_1011,
	load_disp_rm_rn_l_D_1110_M_1101_N_1011,
	load_disp_rm_rn_l_D_1111_M_1101_N_1011,
	load_disp_rm_rn_l_D_0000_M_1110_N_1011,
	load_disp_rm_rn_l_D_0001_M_1110_N_1011,
	load_disp_rm_rn_l_D_0010_M_1110_N_1011,
	load_disp_rm_rn_l_D_0011_M_1110_N_1011,
	load_disp_rm_rn_l_D_0100_M_1110_N_1011,
	load_disp_rm_rn_l_D_0101_M_1110_N_1011,
	load_disp_rm_rn_l_D_0110_M_1110_N_1011,
	load_disp_rm_rn_l_D_0111_M_1110_N_1011,
	load_disp_rm_rn_l_D_1000_M_1110_N_1011,
	load_disp_rm_rn_l_D_1001_M_1110_N_1011,
	load_disp_rm_rn_l_D_1010_M_1110_N_1011,
	load_disp_rm_rn_l_D_1011_M_1110_N_1011,
	load_disp_rm_rn_l_D_1100_M_1110_N_1011,
	load_disp_rm_rn_l_D_1101_M_1110_N_1011,
	load_disp_rm_rn_l_D_1110_M_1110_N_1011,
	load_disp_rm_rn_l_D_1111_M_1110_N_1011,
	load_disp_rm_rn_l_D_0000_M_1111_N_1011,
	load_disp_rm_rn_l_D_0001_M_1111_N_1011,
	load_disp_rm_rn_l_D_0010_M_1111_N_1011,
	load_disp_rm_rn_l_D_0011_M_1111_N_1011,
	load_disp_rm_rn_l_D_0100_M_1111_N_1011,
	load_disp_rm_rn_l_D_0101_M_1111_N_1011,
	load_disp_rm_rn_l_D_0110_M_1111_N_1011,
	load_disp_rm_rn_l_D_0111_M_1111_N_1011,
	load_disp_rm_rn_l_D_1000_M_1111_N_1011,
	load_disp_rm_rn_l_D_1001_M_1111_N_1011,
	load_disp_rm_rn_l_D_1010_M_1111_N_1011,
	load_disp_rm_rn_l_D_1011_M_1111_N_1011,
	load_disp_rm_rn_l_D_1100_M_1111_N_1011,
	load_disp_rm_rn_l_D_1101_M_1111_N_1011,
	load_disp_rm_rn_l_D_1110_M_1111_N_1011,
	load_disp_rm_rn_l_D_1111_M_1111_N_1011,
	load_disp_rm_rn_l_D_0000_M_0000_N_1100,
	load_disp_rm_rn_l_D_0001_M_0000_N_1100,
	load_disp_rm_rn_l_D_0010_M_0000_N_1100,
	load_disp_rm_rn_l_D_0011_M_0000_N_1100,
	load_disp_rm_rn_l_D_0100_M_0000_N_1100,
	load_disp_rm_rn_l_D_0101_M_0000_N_1100,
	load_disp_rm_rn_l_D_0110_M_0000_N_1100,
	load_disp_rm_rn_l_D_0111_M_0000_N_1100,
	load_disp_rm_rn_l_D_1000_M_0000_N_1100,
	load_disp_rm_rn_l_D_1001_M_0000_N_1100,
	load_disp_rm_rn_l_D_1010_M_0000_N_1100,
	load_disp_rm_rn_l_D_1011_M_0000_N_1100,
	load_disp_rm_rn_l_D_1100_M_0000_N_1100,
	load_disp_rm_rn_l_D_1101_M_0000_N_1100,
	load_disp_rm_rn_l_D_1110_M_0000_N_1100,
	load_disp_rm_rn_l_D_1111_M_0000_N_1100,
	load_disp_rm_rn_l_D_0000_M_0001_N_1100,
	load_disp_rm_rn_l_D_0001_M_0001_N_1100,
	load_disp_rm_rn_l_D_0010_M_0001_N_1100,
	load_disp_rm_rn_l_D_0011_M_0001_N_1100,
	load_disp_rm_rn_l_D_0100_M_0001_N_1100,
	load_disp_rm_rn_l_D_0101_M_0001_N_1100,
	load_disp_rm_rn_l_D_0110_M_0001_N_1100,
	load_disp_rm_rn_l_D_0111_M_0001_N_1100,
	load_disp_rm_rn_l_D_1000_M_0001_N_1100,
	load_disp_rm_rn_l_D_1001_M_0001_N_1100,
	load_disp_rm_rn_l_D_1010_M_0001_N_1100,
	load_disp_rm_rn_l_D_1011_M_0001_N_1100,
	load_disp_rm_rn_l_D_1100_M_0001_N_1100,
	load_disp_rm_rn_l_D_1101_M_0001_N_1100,
	load_disp_rm_rn_l_D_1110_M_0001_N_1100,
	load_disp_rm_rn_l_D_1111_M_0001_N_1100,
	load_disp_rm_rn_l_D_0000_M_0010_N_1100,
	load_disp_rm_rn_l_D_0001_M_0010_N_1100,
	load_disp_rm_rn_l_D_0010_M_0010_N_1100,
	load_disp_rm_rn_l_D_0011_M_0010_N_1100,
	load_disp_rm_rn_l_D_0100_M_0010_N_1100,
	load_disp_rm_rn_l_D_0101_M_0010_N_1100,
	load_disp_rm_rn_l_D_0110_M_0010_N_1100,
	load_disp_rm_rn_l_D_0111_M_0010_N_1100,
	load_disp_rm_rn_l_D_1000_M_0010_N_1100,
	load_disp_rm_rn_l_D_1001_M_0010_N_1100,
	load_disp_rm_rn_l_D_1010_M_0010_N_1100,
	load_disp_rm_rn_l_D_1011_M_0010_N_1100,
	load_disp_rm_rn_l_D_1100_M_0010_N_1100,
	load_disp_rm_rn_l_D_1101_M_0010_N_1100,
	load_disp_rm_rn_l_D_1110_M_0010_N_1100,
	load_disp_rm_rn_l_D_1111_M_0010_N_1100,
	load_disp_rm_rn_l_D_0000_M_0011_N_1100,
	load_disp_rm_rn_l_D_0001_M_0011_N_1100,
	load_disp_rm_rn_l_D_0010_M_0011_N_1100,
	load_disp_rm_rn_l_D_0011_M_0011_N_1100,
	load_disp_rm_rn_l_D_0100_M_0011_N_1100,
	load_disp_rm_rn_l_D_0101_M_0011_N_1100,
	load_disp_rm_rn_l_D_0110_M_0011_N_1100,
	load_disp_rm_rn_l_D_0111_M_0011_N_1100,
	load_disp_rm_rn_l_D_1000_M_0011_N_1100,
	load_disp_rm_rn_l_D_1001_M_0011_N_1100,
	load_disp_rm_rn_l_D_1010_M_0011_N_1100,
	load_disp_rm_rn_l_D_1011_M_0011_N_1100,
	load_disp_rm_rn_l_D_1100_M_0011_N_1100,
	load_disp_rm_rn_l_D_1101_M_0011_N_1100,
	load_disp_rm_rn_l_D_1110_M_0011_N_1100,
	load_disp_rm_rn_l_D_1111_M_0011_N_1100,
	load_disp_rm_rn_l_D_0000_M_0100_N_1100,
	load_disp_rm_rn_l_D_0001_M_0100_N_1100,
	load_disp_rm_rn_l_D_0010_M_0100_N_1100,
	load_disp_rm_rn_l_D_0011_M_0100_N_1100,
	load_disp_rm_rn_l_D_0100_M_0100_N_1100,
	load_disp_rm_rn_l_D_0101_M_0100_N_1100,
	load_disp_rm_rn_l_D_0110_M_0100_N_1100,
	load_disp_rm_rn_l_D_0111_M_0100_N_1100,
	load_disp_rm_rn_l_D_1000_M_0100_N_1100,
	load_disp_rm_rn_l_D_1001_M_0100_N_1100,
	load_disp_rm_rn_l_D_1010_M_0100_N_1100,
	load_disp_rm_rn_l_D_1011_M_0100_N_1100,
	load_disp_rm_rn_l_D_1100_M_0100_N_1100,
	load_disp_rm_rn_l_D_1101_M_0100_N_1100,
	load_disp_rm_rn_l_D_1110_M_0100_N_1100,
	load_disp_rm_rn_l_D_1111_M_0100_N_1100,
	load_disp_rm_rn_l_D_0000_M_0101_N_1100,
	load_disp_rm_rn_l_D_0001_M_0101_N_1100,
	load_disp_rm_rn_l_D_0010_M_0101_N_1100,
	load_disp_rm_rn_l_D_0011_M_0101_N_1100,
	load_disp_rm_rn_l_D_0100_M_0101_N_1100,
	load_disp_rm_rn_l_D_0101_M_0101_N_1100,
	load_disp_rm_rn_l_D_0110_M_0101_N_1100,
	load_disp_rm_rn_l_D_0111_M_0101_N_1100,
	load_disp_rm_rn_l_D_1000_M_0101_N_1100,
	load_disp_rm_rn_l_D_1001_M_0101_N_1100,
	load_disp_rm_rn_l_D_1010_M_0101_N_1100,
	load_disp_rm_rn_l_D_1011_M_0101_N_1100,
	load_disp_rm_rn_l_D_1100_M_0101_N_1100,
	load_disp_rm_rn_l_D_1101_M_0101_N_1100,
	load_disp_rm_rn_l_D_1110_M_0101_N_1100,
	load_disp_rm_rn_l_D_1111_M_0101_N_1100,
	load_disp_rm_rn_l_D_0000_M_0110_N_1100,
	load_disp_rm_rn_l_D_0001_M_0110_N_1100,
	load_disp_rm_rn_l_D_0010_M_0110_N_1100,
	load_disp_rm_rn_l_D_0011_M_0110_N_1100,
	load_disp_rm_rn_l_D_0100_M_0110_N_1100,
	load_disp_rm_rn_l_D_0101_M_0110_N_1100,
	load_disp_rm_rn_l_D_0110_M_0110_N_1100,
	load_disp_rm_rn_l_D_0111_M_0110_N_1100,
	load_disp_rm_rn_l_D_1000_M_0110_N_1100,
	load_disp_rm_rn_l_D_1001_M_0110_N_1100,
	load_disp_rm_rn_l_D_1010_M_0110_N_1100,
	load_disp_rm_rn_l_D_1011_M_0110_N_1100,
	load_disp_rm_rn_l_D_1100_M_0110_N_1100,
	load_disp_rm_rn_l_D_1101_M_0110_N_1100,
	load_disp_rm_rn_l_D_1110_M_0110_N_1100,
	load_disp_rm_rn_l_D_1111_M_0110_N_1100,
	load_disp_rm_rn_l_D_0000_M_0111_N_1100,
	load_disp_rm_rn_l_D_0001_M_0111_N_1100,
	load_disp_rm_rn_l_D_0010_M_0111_N_1100,
	load_disp_rm_rn_l_D_0011_M_0111_N_1100,
	load_disp_rm_rn_l_D_0100_M_0111_N_1100,
	load_disp_rm_rn_l_D_0101_M_0111_N_1100,
	load_disp_rm_rn_l_D_0110_M_0111_N_1100,
	load_disp_rm_rn_l_D_0111_M_0111_N_1100,
	load_disp_rm_rn_l_D_1000_M_0111_N_1100,
	load_disp_rm_rn_l_D_1001_M_0111_N_1100,
	load_disp_rm_rn_l_D_1010_M_0111_N_1100,
	load_disp_rm_rn_l_D_1011_M_0111_N_1100,
	load_disp_rm_rn_l_D_1100_M_0111_N_1100,
	load_disp_rm_rn_l_D_1101_M_0111_N_1100,
	load_disp_rm_rn_l_D_1110_M_0111_N_1100,
	load_disp_rm_rn_l_D_1111_M_0111_N_1100,
	load_disp_rm_rn_l_D_0000_M_1000_N_1100,
	load_disp_rm_rn_l_D_0001_M_1000_N_1100,
	load_disp_rm_rn_l_D_0010_M_1000_N_1100,
	load_disp_rm_rn_l_D_0011_M_1000_N_1100,
	load_disp_rm_rn_l_D_0100_M_1000_N_1100,
	load_disp_rm_rn_l_D_0101_M_1000_N_1100,
	load_disp_rm_rn_l_D_0110_M_1000_N_1100,
	load_disp_rm_rn_l_D_0111_M_1000_N_1100,
	load_disp_rm_rn_l_D_1000_M_1000_N_1100,
	load_disp_rm_rn_l_D_1001_M_1000_N_1100,
	load_disp_rm_rn_l_D_1010_M_1000_N_1100,
	load_disp_rm_rn_l_D_1011_M_1000_N_1100,
	load_disp_rm_rn_l_D_1100_M_1000_N_1100,
	load_disp_rm_rn_l_D_1101_M_1000_N_1100,
	load_disp_rm_rn_l_D_1110_M_1000_N_1100,
	load_disp_rm_rn_l_D_1111_M_1000_N_1100,
	load_disp_rm_rn_l_D_0000_M_1001_N_1100,
	load_disp_rm_rn_l_D_0001_M_1001_N_1100,
	load_disp_rm_rn_l_D_0010_M_1001_N_1100,
	load_disp_rm_rn_l_D_0011_M_1001_N_1100,
	load_disp_rm_rn_l_D_0100_M_1001_N_1100,
	load_disp_rm_rn_l_D_0101_M_1001_N_1100,
	load_disp_rm_rn_l_D_0110_M_1001_N_1100,
	load_disp_rm_rn_l_D_0111_M_1001_N_1100,
	load_disp_rm_rn_l_D_1000_M_1001_N_1100,
	load_disp_rm_rn_l_D_1001_M_1001_N_1100,
	load_disp_rm_rn_l_D_1010_M_1001_N_1100,
	load_disp_rm_rn_l_D_1011_M_1001_N_1100,
	load_disp_rm_rn_l_D_1100_M_1001_N_1100,
	load_disp_rm_rn_l_D_1101_M_1001_N_1100,
	load_disp_rm_rn_l_D_1110_M_1001_N_1100,
	load_disp_rm_rn_l_D_1111_M_1001_N_1100,
	load_disp_rm_rn_l_D_0000_M_1010_N_1100,
	load_disp_rm_rn_l_D_0001_M_1010_N_1100,
	load_disp_rm_rn_l_D_0010_M_1010_N_1100,
	load_disp_rm_rn_l_D_0011_M_1010_N_1100,
	load_disp_rm_rn_l_D_0100_M_1010_N_1100,
	load_disp_rm_rn_l_D_0101_M_1010_N_1100,
	load_disp_rm_rn_l_D_0110_M_1010_N_1100,
	load_disp_rm_rn_l_D_0111_M_1010_N_1100,
	load_disp_rm_rn_l_D_1000_M_1010_N_1100,
	load_disp_rm_rn_l_D_1001_M_1010_N_1100,
	load_disp_rm_rn_l_D_1010_M_1010_N_1100,
	load_disp_rm_rn_l_D_1011_M_1010_N_1100,
	load_disp_rm_rn_l_D_1100_M_1010_N_1100,
	load_disp_rm_rn_l_D_1101_M_1010_N_1100,
	load_disp_rm_rn_l_D_1110_M_1010_N_1100,
	load_disp_rm_rn_l_D_1111_M_1010_N_1100,
	load_disp_rm_rn_l_D_0000_M_1011_N_1100,
	load_disp_rm_rn_l_D_0001_M_1011_N_1100,
	load_disp_rm_rn_l_D_0010_M_1011_N_1100,
	load_disp_rm_rn_l_D_0011_M_1011_N_1100,
	load_disp_rm_rn_l_D_0100_M_1011_N_1100,
	load_disp_rm_rn_l_D_0101_M_1011_N_1100,
	load_disp_rm_rn_l_D_0110_M_1011_N_1100,
	load_disp_rm_rn_l_D_0111_M_1011_N_1100,
	load_disp_rm_rn_l_D_1000_M_1011_N_1100,
	load_disp_rm_rn_l_D_1001_M_1011_N_1100,
	load_disp_rm_rn_l_D_1010_M_1011_N_1100,
	load_disp_rm_rn_l_D_1011_M_1011_N_1100,
	load_disp_rm_rn_l_D_1100_M_1011_N_1100,
	load_disp_rm_rn_l_D_1101_M_1011_N_1100,
	load_disp_rm_rn_l_D_1110_M_1011_N_1100,
	load_disp_rm_rn_l_D_1111_M_1011_N_1100,
	load_disp_rm_rn_l_D_0000_M_1100_N_1100,
	load_disp_rm_rn_l_D_0001_M_1100_N_1100,
	load_disp_rm_rn_l_D_0010_M_1100_N_1100,
	load_disp_rm_rn_l_D_0011_M_1100_N_1100,
	load_disp_rm_rn_l_D_0100_M_1100_N_1100,
	load_disp_rm_rn_l_D_0101_M_1100_N_1100,
	load_disp_rm_rn_l_D_0110_M_1100_N_1100,
	load_disp_rm_rn_l_D_0111_M_1100_N_1100,
	load_disp_rm_rn_l_D_1000_M_1100_N_1100,
	load_disp_rm_rn_l_D_1001_M_1100_N_1100,
	load_disp_rm_rn_l_D_1010_M_1100_N_1100,
	load_disp_rm_rn_l_D_1011_M_1100_N_1100,
	load_disp_rm_rn_l_D_1100_M_1100_N_1100,
	load_disp_rm_rn_l_D_1101_M_1100_N_1100,
	load_disp_rm_rn_l_D_1110_M_1100_N_1100,
	load_disp_rm_rn_l_D_1111_M_1100_N_1100,
	load_disp_rm_rn_l_D_0000_M_1101_N_1100,
	load_disp_rm_rn_l_D_0001_M_1101_N_1100,
	load_disp_rm_rn_l_D_0010_M_1101_N_1100,
	load_disp_rm_rn_l_D_0011_M_1101_N_1100,
	load_disp_rm_rn_l_D_0100_M_1101_N_1100,
	load_disp_rm_rn_l_D_0101_M_1101_N_1100,
	load_disp_rm_rn_l_D_0110_M_1101_N_1100,
	load_disp_rm_rn_l_D_0111_M_1101_N_1100,
	load_disp_rm_rn_l_D_1000_M_1101_N_1100,
	load_disp_rm_rn_l_D_1001_M_1101_N_1100,
	load_disp_rm_rn_l_D_1010_M_1101_N_1100,
	load_disp_rm_rn_l_D_1011_M_1101_N_1100,
	load_disp_rm_rn_l_D_1100_M_1101_N_1100,
	load_disp_rm_rn_l_D_1101_M_1101_N_1100,
	load_disp_rm_rn_l_D_1110_M_1101_N_1100,
	load_disp_rm_rn_l_D_1111_M_1101_N_1100,
	load_disp_rm_rn_l_D_0000_M_1110_N_1100,
	load_disp_rm_rn_l_D_0001_M_1110_N_1100,
	load_disp_rm_rn_l_D_0010_M_1110_N_1100,
	load_disp_rm_rn_l_D_0011_M_1110_N_1100,
	load_disp_rm_rn_l_D_0100_M_1110_N_1100,
	load_disp_rm_rn_l_D_0101_M_1110_N_1100,
	load_disp_rm_rn_l_D_0110_M_1110_N_1100,
	load_disp_rm_rn_l_D_0111_M_1110_N_1100,
	load_disp_rm_rn_l_D_1000_M_1110_N_1100,
	load_disp_rm_rn_l_D_1001_M_1110_N_1100,
	load_disp_rm_rn_l_D_1010_M_1110_N_1100,
	load_disp_rm_rn_l_D_1011_M_1110_N_1100,
	load_disp_rm_rn_l_D_1100_M_1110_N_1100,
	load_disp_rm_rn_l_D_1101_M_1110_N_1100,
	load_disp_rm_rn_l_D_1110_M_1110_N_1100,
	load_disp_rm_rn_l_D_1111_M_1110_N_1100,
	load_disp_rm_rn_l_D_0000_M_1111_N_1100,
	load_disp_rm_rn_l_D_0001_M_1111_N_1100,
	load_disp_rm_rn_l_D_0010_M_1111_N_1100,
	load_disp_rm_rn_l_D_0011_M_1111_N_1100,
	load_disp_rm_rn_l_D_0100_M_1111_N_1100,
	load_disp_rm_rn_l_D_0101_M_1111_N_1100,
	load_disp_rm_rn_l_D_0110_M_1111_N_1100,
	load_disp_rm_rn_l_D_0111_M_1111_N_1100,
	load_disp_rm_rn_l_D_1000_M_1111_N_1100,
	load_disp_rm_rn_l_D_1001_M_1111_N_1100,
	load_disp_rm_rn_l_D_1010_M_1111_N_1100,
	load_disp_rm_rn_l_D_1011_M_1111_N_1100,
	load_disp_rm_rn_l_D_1100_M_1111_N_1100,
	load_disp_rm_rn_l_D_1101_M_1111_N_1100,
	load_disp_rm_rn_l_D_1110_M_1111_N_1100,
	load_disp_rm_rn_l_D_1111_M_1111_N_1100,
	load_disp_rm_rn_l_D_0000_M_0000_N_1101,
	load_disp_rm_rn_l_D_0001_M_0000_N_1101,
	load_disp_rm_rn_l_D_0010_M_0000_N_1101,
	load_disp_rm_rn_l_D_0011_M_0000_N_1101,
	load_disp_rm_rn_l_D_0100_M_0000_N_1101,
	load_disp_rm_rn_l_D_0101_M_0000_N_1101,
	load_disp_rm_rn_l_D_0110_M_0000_N_1101,
	load_disp_rm_rn_l_D_0111_M_0000_N_1101,
	load_disp_rm_rn_l_D_1000_M_0000_N_1101,
	load_disp_rm_rn_l_D_1001_M_0000_N_1101,
	load_disp_rm_rn_l_D_1010_M_0000_N_1101,
	load_disp_rm_rn_l_D_1011_M_0000_N_1101,
	load_disp_rm_rn_l_D_1100_M_0000_N_1101,
	load_disp_rm_rn_l_D_1101_M_0000_N_1101,
	load_disp_rm_rn_l_D_1110_M_0000_N_1101,
	load_disp_rm_rn_l_D_1111_M_0000_N_1101,
	load_disp_rm_rn_l_D_0000_M_0001_N_1101,
	load_disp_rm_rn_l_D_0001_M_0001_N_1101,
	load_disp_rm_rn_l_D_0010_M_0001_N_1101,
	load_disp_rm_rn_l_D_0011_M_0001_N_1101,
	load_disp_rm_rn_l_D_0100_M_0001_N_1101,
	load_disp_rm_rn_l_D_0101_M_0001_N_1101,
	load_disp_rm_rn_l_D_0110_M_0001_N_1101,
	load_disp_rm_rn_l_D_0111_M_0001_N_1101,
	load_disp_rm_rn_l_D_1000_M_0001_N_1101,
	load_disp_rm_rn_l_D_1001_M_0001_N_1101,
	load_disp_rm_rn_l_D_1010_M_0001_N_1101,
	load_disp_rm_rn_l_D_1011_M_0001_N_1101,
	load_disp_rm_rn_l_D_1100_M_0001_N_1101,
	load_disp_rm_rn_l_D_1101_M_0001_N_1101,
	load_disp_rm_rn_l_D_1110_M_0001_N_1101,
	load_disp_rm_rn_l_D_1111_M_0001_N_1101,
	load_disp_rm_rn_l_D_0000_M_0010_N_1101,
	load_disp_rm_rn_l_D_0001_M_0010_N_1101,
	load_disp_rm_rn_l_D_0010_M_0010_N_1101,
	load_disp_rm_rn_l_D_0011_M_0010_N_1101,
	load_disp_rm_rn_l_D_0100_M_0010_N_1101,
	load_disp_rm_rn_l_D_0101_M_0010_N_1101,
	load_disp_rm_rn_l_D_0110_M_0010_N_1101,
	load_disp_rm_rn_l_D_0111_M_0010_N_1101,
	load_disp_rm_rn_l_D_1000_M_0010_N_1101,
	load_disp_rm_rn_l_D_1001_M_0010_N_1101,
	load_disp_rm_rn_l_D_1010_M_0010_N_1101,
	load_disp_rm_rn_l_D_1011_M_0010_N_1101,
	load_disp_rm_rn_l_D_1100_M_0010_N_1101,
	load_disp_rm_rn_l_D_1101_M_0010_N_1101,
	load_disp_rm_rn_l_D_1110_M_0010_N_1101,
	load_disp_rm_rn_l_D_1111_M_0010_N_1101,
	load_disp_rm_rn_l_D_0000_M_0011_N_1101,
	load_disp_rm_rn_l_D_0001_M_0011_N_1101,
	load_disp_rm_rn_l_D_0010_M_0011_N_1101,
	load_disp_rm_rn_l_D_0011_M_0011_N_1101,
	load_disp_rm_rn_l_D_0100_M_0011_N_1101,
	load_disp_rm_rn_l_D_0101_M_0011_N_1101,
	load_disp_rm_rn_l_D_0110_M_0011_N_1101,
	load_disp_rm_rn_l_D_0111_M_0011_N_1101,
	load_disp_rm_rn_l_D_1000_M_0011_N_1101,
	load_disp_rm_rn_l_D_1001_M_0011_N_1101,
	load_disp_rm_rn_l_D_1010_M_0011_N_1101,
	load_disp_rm_rn_l_D_1011_M_0011_N_1101,
	load_disp_rm_rn_l_D_1100_M_0011_N_1101,
	load_disp_rm_rn_l_D_1101_M_0011_N_1101,
	load_disp_rm_rn_l_D_1110_M_0011_N_1101,
	load_disp_rm_rn_l_D_1111_M_0011_N_1101,
	load_disp_rm_rn_l_D_0000_M_0100_N_1101,
	load_disp_rm_rn_l_D_0001_M_0100_N_1101,
	load_disp_rm_rn_l_D_0010_M_0100_N_1101,
	load_disp_rm_rn_l_D_0011_M_0100_N_1101,
	load_disp_rm_rn_l_D_0100_M_0100_N_1101,
	load_disp_rm_rn_l_D_0101_M_0100_N_1101,
	load_disp_rm_rn_l_D_0110_M_0100_N_1101,
	load_disp_rm_rn_l_D_0111_M_0100_N_1101,
	load_disp_rm_rn_l_D_1000_M_0100_N_1101,
	load_disp_rm_rn_l_D_1001_M_0100_N_1101,
	load_disp_rm_rn_l_D_1010_M_0100_N_1101,
	load_disp_rm_rn_l_D_1011_M_0100_N_1101,
	load_disp_rm_rn_l_D_1100_M_0100_N_1101,
	load_disp_rm_rn_l_D_1101_M_0100_N_1101,
	load_disp_rm_rn_l_D_1110_M_0100_N_1101,
	load_disp_rm_rn_l_D_1111_M_0100_N_1101,
	load_disp_rm_rn_l_D_0000_M_0101_N_1101,
	load_disp_rm_rn_l_D_0001_M_0101_N_1101,
	load_disp_rm_rn_l_D_0010_M_0101_N_1101,
	load_disp_rm_rn_l_D_0011_M_0101_N_1101,
	load_disp_rm_rn_l_D_0100_M_0101_N_1101,
	load_disp_rm_rn_l_D_0101_M_0101_N_1101,
	load_disp_rm_rn_l_D_0110_M_0101_N_1101,
	load_disp_rm_rn_l_D_0111_M_0101_N_1101,
	load_disp_rm_rn_l_D_1000_M_0101_N_1101,
	load_disp_rm_rn_l_D_1001_M_0101_N_1101,
	load_disp_rm_rn_l_D_1010_M_0101_N_1101,
	load_disp_rm_rn_l_D_1011_M_0101_N_1101,
	load_disp_rm_rn_l_D_1100_M_0101_N_1101,
	load_disp_rm_rn_l_D_1101_M_0101_N_1101,
	load_disp_rm_rn_l_D_1110_M_0101_N_1101,
	load_disp_rm_rn_l_D_1111_M_0101_N_1101,
	load_disp_rm_rn_l_D_0000_M_0110_N_1101,
	load_disp_rm_rn_l_D_0001_M_0110_N_1101,
	load_disp_rm_rn_l_D_0010_M_0110_N_1101,
	load_disp_rm_rn_l_D_0011_M_0110_N_1101,
	load_disp_rm_rn_l_D_0100_M_0110_N_1101,
	load_disp_rm_rn_l_D_0101_M_0110_N_1101,
	load_disp_rm_rn_l_D_0110_M_0110_N_1101,
	load_disp_rm_rn_l_D_0111_M_0110_N_1101,
	load_disp_rm_rn_l_D_1000_M_0110_N_1101,
	load_disp_rm_rn_l_D_1001_M_0110_N_1101,
	load_disp_rm_rn_l_D_1010_M_0110_N_1101,
	load_disp_rm_rn_l_D_1011_M_0110_N_1101,
	load_disp_rm_rn_l_D_1100_M_0110_N_1101,
	load_disp_rm_rn_l_D_1101_M_0110_N_1101,
	load_disp_rm_rn_l_D_1110_M_0110_N_1101,
	load_disp_rm_rn_l_D_1111_M_0110_N_1101,
	load_disp_rm_rn_l_D_0000_M_0111_N_1101,
	load_disp_rm_rn_l_D_0001_M_0111_N_1101,
	load_disp_rm_rn_l_D_0010_M_0111_N_1101,
	load_disp_rm_rn_l_D_0011_M_0111_N_1101,
	load_disp_rm_rn_l_D_0100_M_0111_N_1101,
	load_disp_rm_rn_l_D_0101_M_0111_N_1101,
	load_disp_rm_rn_l_D_0110_M_0111_N_1101,
	load_disp_rm_rn_l_D_0111_M_0111_N_1101,
	load_disp_rm_rn_l_D_1000_M_0111_N_1101,
	load_disp_rm_rn_l_D_1001_M_0111_N_1101,
	load_disp_rm_rn_l_D_1010_M_0111_N_1101,
	load_disp_rm_rn_l_D_1011_M_0111_N_1101,
	load_disp_rm_rn_l_D_1100_M_0111_N_1101,
	load_disp_rm_rn_l_D_1101_M_0111_N_1101,
	load_disp_rm_rn_l_D_1110_M_0111_N_1101,
	load_disp_rm_rn_l_D_1111_M_0111_N_1101,
	load_disp_rm_rn_l_D_0000_M_1000_N_1101,
	load_disp_rm_rn_l_D_0001_M_1000_N_1101,
	load_disp_rm_rn_l_D_0010_M_1000_N_1101,
	load_disp_rm_rn_l_D_0011_M_1000_N_1101,
	load_disp_rm_rn_l_D_0100_M_1000_N_1101,
	load_disp_rm_rn_l_D_0101_M_1000_N_1101,
	load_disp_rm_rn_l_D_0110_M_1000_N_1101,
	load_disp_rm_rn_l_D_0111_M_1000_N_1101,
	load_disp_rm_rn_l_D_1000_M_1000_N_1101,
	load_disp_rm_rn_l_D_1001_M_1000_N_1101,
	load_disp_rm_rn_l_D_1010_M_1000_N_1101,
	load_disp_rm_rn_l_D_1011_M_1000_N_1101,
	load_disp_rm_rn_l_D_1100_M_1000_N_1101,
	load_disp_rm_rn_l_D_1101_M_1000_N_1101,
	load_disp_rm_rn_l_D_1110_M_1000_N_1101,
	load_disp_rm_rn_l_D_1111_M_1000_N_1101,
	load_disp_rm_rn_l_D_0000_M_1001_N_1101,
	load_disp_rm_rn_l_D_0001_M_1001_N_1101,
	load_disp_rm_rn_l_D_0010_M_1001_N_1101,
	load_disp_rm_rn_l_D_0011_M_1001_N_1101,
	load_disp_rm_rn_l_D_0100_M_1001_N_1101,
	load_disp_rm_rn_l_D_0101_M_1001_N_1101,
	load_disp_rm_rn_l_D_0110_M_1001_N_1101,
	load_disp_rm_rn_l_D_0111_M_1001_N_1101,
	load_disp_rm_rn_l_D_1000_M_1001_N_1101,
	load_disp_rm_rn_l_D_1001_M_1001_N_1101,
	load_disp_rm_rn_l_D_1010_M_1001_N_1101,
	load_disp_rm_rn_l_D_1011_M_1001_N_1101,
	load_disp_rm_rn_l_D_1100_M_1001_N_1101,
	load_disp_rm_rn_l_D_1101_M_1001_N_1101,
	load_disp_rm_rn_l_D_1110_M_1001_N_1101,
	load_disp_rm_rn_l_D_1111_M_1001_N_1101,
	load_disp_rm_rn_l_D_0000_M_1010_N_1101,
	load_disp_rm_rn_l_D_0001_M_1010_N_1101,
	load_disp_rm_rn_l_D_0010_M_1010_N_1101,
	load_disp_rm_rn_l_D_0011_M_1010_N_1101,
	load_disp_rm_rn_l_D_0100_M_1010_N_1101,
	load_disp_rm_rn_l_D_0101_M_1010_N_1101,
	load_disp_rm_rn_l_D_0110_M_1010_N_1101,
	load_disp_rm_rn_l_D_0111_M_1010_N_1101,
	load_disp_rm_rn_l_D_1000_M_1010_N_1101,
	load_disp_rm_rn_l_D_1001_M_1010_N_1101,
	load_disp_rm_rn_l_D_1010_M_1010_N_1101,
	load_disp_rm_rn_l_D_1011_M_1010_N_1101,
	load_disp_rm_rn_l_D_1100_M_1010_N_1101,
	load_disp_rm_rn_l_D_1101_M_1010_N_1101,
	load_disp_rm_rn_l_D_1110_M_1010_N_1101,
	load_disp_rm_rn_l_D_1111_M_1010_N_1101,
	load_disp_rm_rn_l_D_0000_M_1011_N_1101,
	load_disp_rm_rn_l_D_0001_M_1011_N_1101,
	load_disp_rm_rn_l_D_0010_M_1011_N_1101,
	load_disp_rm_rn_l_D_0011_M_1011_N_1101,
	load_disp_rm_rn_l_D_0100_M_1011_N_1101,
	load_disp_rm_rn_l_D_0101_M_1011_N_1101,
	load_disp_rm_rn_l_D_0110_M_1011_N_1101,
	load_disp_rm_rn_l_D_0111_M_1011_N_1101,
	load_disp_rm_rn_l_D_1000_M_1011_N_1101,
	load_disp_rm_rn_l_D_1001_M_1011_N_1101,
	load_disp_rm_rn_l_D_1010_M_1011_N_1101,
	load_disp_rm_rn_l_D_1011_M_1011_N_1101,
	load_disp_rm_rn_l_D_1100_M_1011_N_1101,
	load_disp_rm_rn_l_D_1101_M_1011_N_1101,
	load_disp_rm_rn_l_D_1110_M_1011_N_1101,
	load_disp_rm_rn_l_D_1111_M_1011_N_1101,
	load_disp_rm_rn_l_D_0000_M_1100_N_1101,
	load_disp_rm_rn_l_D_0001_M_1100_N_1101,
	load_disp_rm_rn_l_D_0010_M_1100_N_1101,
	load_disp_rm_rn_l_D_0011_M_1100_N_1101,
	load_disp_rm_rn_l_D_0100_M_1100_N_1101,
	load_disp_rm_rn_l_D_0101_M_1100_N_1101,
	load_disp_rm_rn_l_D_0110_M_1100_N_1101,
	load_disp_rm_rn_l_D_0111_M_1100_N_1101,
	load_disp_rm_rn_l_D_1000_M_1100_N_1101,
	load_disp_rm_rn_l_D_1001_M_1100_N_1101,
	load_disp_rm_rn_l_D_1010_M_1100_N_1101,
	load_disp_rm_rn_l_D_1011_M_1100_N_1101,
	load_disp_rm_rn_l_D_1100_M_1100_N_1101,
	load_disp_rm_rn_l_D_1101_M_1100_N_1101,
	load_disp_rm_rn_l_D_1110_M_1100_N_1101,
	load_disp_rm_rn_l_D_1111_M_1100_N_1101,
	load_disp_rm_rn_l_D_0000_M_1101_N_1101,
	load_disp_rm_rn_l_D_0001_M_1101_N_1101,
	load_disp_rm_rn_l_D_0010_M_1101_N_1101,
	load_disp_rm_rn_l_D_0011_M_1101_N_1101,
	load_disp_rm_rn_l_D_0100_M_1101_N_1101,
	load_disp_rm_rn_l_D_0101_M_1101_N_1101,
	load_disp_rm_rn_l_D_0110_M_1101_N_1101,
	load_disp_rm_rn_l_D_0111_M_1101_N_1101,
	load_disp_rm_rn_l_D_1000_M_1101_N_1101,
	load_disp_rm_rn_l_D_1001_M_1101_N_1101,
	load_disp_rm_rn_l_D_1010_M_1101_N_1101,
	load_disp_rm_rn_l_D_1011_M_1101_N_1101,
	load_disp_rm_rn_l_D_1100_M_1101_N_1101,
	load_disp_rm_rn_l_D_1101_M_1101_N_1101,
	load_disp_rm_rn_l_D_1110_M_1101_N_1101,
	load_disp_rm_rn_l_D_1111_M_1101_N_1101,
	load_disp_rm_rn_l_D_0000_M_1110_N_1101,
	load_disp_rm_rn_l_D_0001_M_1110_N_1101,
	load_disp_rm_rn_l_D_0010_M_1110_N_1101,
	load_disp_rm_rn_l_D_0011_M_1110_N_1101,
	load_disp_rm_rn_l_D_0100_M_1110_N_1101,
	load_disp_rm_rn_l_D_0101_M_1110_N_1101,
	load_disp_rm_rn_l_D_0110_M_1110_N_1101,
	load_disp_rm_rn_l_D_0111_M_1110_N_1101,
	load_disp_rm_rn_l_D_1000_M_1110_N_1101,
	load_disp_rm_rn_l_D_1001_M_1110_N_1101,
	load_disp_rm_rn_l_D_1010_M_1110_N_1101,
	load_disp_rm_rn_l_D_1011_M_1110_N_1101,
	load_disp_rm_rn_l_D_1100_M_1110_N_1101,
	load_disp_rm_rn_l_D_1101_M_1110_N_1101,
	load_disp_rm_rn_l_D_1110_M_1110_N_1101,
	load_disp_rm_rn_l_D_1111_M_1110_N_1101,
	load_disp_rm_rn_l_D_0000_M_1111_N_1101,
	load_disp_rm_rn_l_D_0001_M_1111_N_1101,
	load_disp_rm_rn_l_D_0010_M_1111_N_1101,
	load_disp_rm_rn_l_D_0011_M_1111_N_1101,
	load_disp_rm_rn_l_D_0100_M_1111_N_1101,
	load_disp_rm_rn_l_D_0101_M_1111_N_1101,
	load_disp_rm_rn_l_D_0110_M_1111_N_1101,
	load_disp_rm_rn_l_D_0111_M_1111_N_1101,
	load_disp_rm_rn_l_D_1000_M_1111_N_1101,
	load_disp_rm_rn_l_D_1001_M_1111_N_1101,
	load_disp_rm_rn_l_D_1010_M_1111_N_1101,
	load_disp_rm_rn_l_D_1011_M_1111_N_1101,
	load_disp_rm_rn_l_D_1100_M_1111_N_1101,
	load_disp_rm_rn_l_D_1101_M_1111_N_1101,
	load_disp_rm_rn_l_D_1110_M_1111_N_1101,
	load_disp_rm_rn_l_D_1111_M_1111_N_1101,
	load_disp_rm_rn_l_D_0000_M_0000_N_1110,
	load_disp_rm_rn_l_D_0001_M_0000_N_1110,
	load_disp_rm_rn_l_D_0010_M_0000_N_1110,
	load_disp_rm_rn_l_D_0011_M_0000_N_1110,
	load_disp_rm_rn_l_D_0100_M_0000_N_1110,
	load_disp_rm_rn_l_D_0101_M_0000_N_1110,
	load_disp_rm_rn_l_D_0110_M_0000_N_1110,
	load_disp_rm_rn_l_D_0111_M_0000_N_1110,
	load_disp_rm_rn_l_D_1000_M_0000_N_1110,
	load_disp_rm_rn_l_D_1001_M_0000_N_1110,
	load_disp_rm_rn_l_D_1010_M_0000_N_1110,
	load_disp_rm_rn_l_D_1011_M_0000_N_1110,
	load_disp_rm_rn_l_D_1100_M_0000_N_1110,
	load_disp_rm_rn_l_D_1101_M_0000_N_1110,
	load_disp_rm_rn_l_D_1110_M_0000_N_1110,
	load_disp_rm_rn_l_D_1111_M_0000_N_1110,
	load_disp_rm_rn_l_D_0000_M_0001_N_1110,
	load_disp_rm_rn_l_D_0001_M_0001_N_1110,
	load_disp_rm_rn_l_D_0010_M_0001_N_1110,
	load_disp_rm_rn_l_D_0011_M_0001_N_1110,
	load_disp_rm_rn_l_D_0100_M_0001_N_1110,
	load_disp_rm_rn_l_D_0101_M_0001_N_1110,
	load_disp_rm_rn_l_D_0110_M_0001_N_1110,
	load_disp_rm_rn_l_D_0111_M_0001_N_1110,
	load_disp_rm_rn_l_D_1000_M_0001_N_1110,
	load_disp_rm_rn_l_D_1001_M_0001_N_1110,
	load_disp_rm_rn_l_D_1010_M_0001_N_1110,
	load_disp_rm_rn_l_D_1011_M_0001_N_1110,
	load_disp_rm_rn_l_D_1100_M_0001_N_1110,
	load_disp_rm_rn_l_D_1101_M_0001_N_1110,
	load_disp_rm_rn_l_D_1110_M_0001_N_1110,
	load_disp_rm_rn_l_D_1111_M_0001_N_1110,
	load_disp_rm_rn_l_D_0000_M_0010_N_1110,
	load_disp_rm_rn_l_D_0001_M_0010_N_1110,
	load_disp_rm_rn_l_D_0010_M_0010_N_1110,
	load_disp_rm_rn_l_D_0011_M_0010_N_1110,
	load_disp_rm_rn_l_D_0100_M_0010_N_1110,
	load_disp_rm_rn_l_D_0101_M_0010_N_1110,
	load_disp_rm_rn_l_D_0110_M_0010_N_1110,
	load_disp_rm_rn_l_D_0111_M_0010_N_1110,
	load_disp_rm_rn_l_D_1000_M_0010_N_1110,
	load_disp_rm_rn_l_D_1001_M_0010_N_1110,
	load_disp_rm_rn_l_D_1010_M_0010_N_1110,
	load_disp_rm_rn_l_D_1011_M_0010_N_1110,
	load_disp_rm_rn_l_D_1100_M_0010_N_1110,
	load_disp_rm_rn_l_D_1101_M_0010_N_1110,
	load_disp_rm_rn_l_D_1110_M_0010_N_1110,
	load_disp_rm_rn_l_D_1111_M_0010_N_1110,
	load_disp_rm_rn_l_D_0000_M_0011_N_1110,
	load_disp_rm_rn_l_D_0001_M_0011_N_1110,
	load_disp_rm_rn_l_D_0010_M_0011_N_1110,
	load_disp_rm_rn_l_D_0011_M_0011_N_1110,
	load_disp_rm_rn_l_D_0100_M_0011_N_1110,
	load_disp_rm_rn_l_D_0101_M_0011_N_1110,
	load_disp_rm_rn_l_D_0110_M_0011_N_1110,
	load_disp_rm_rn_l_D_0111_M_0011_N_1110,
	load_disp_rm_rn_l_D_1000_M_0011_N_1110,
	load_disp_rm_rn_l_D_1001_M_0011_N_1110,
	load_disp_rm_rn_l_D_1010_M_0011_N_1110,
	load_disp_rm_rn_l_D_1011_M_0011_N_1110,
	load_disp_rm_rn_l_D_1100_M_0011_N_1110,
	load_disp_rm_rn_l_D_1101_M_0011_N_1110,
	load_disp_rm_rn_l_D_1110_M_0011_N_1110,
	load_disp_rm_rn_l_D_1111_M_0011_N_1110,
	load_disp_rm_rn_l_D_0000_M_0100_N_1110,
	load_disp_rm_rn_l_D_0001_M_0100_N_1110,
	load_disp_rm_rn_l_D_0010_M_0100_N_1110,
	load_disp_rm_rn_l_D_0011_M_0100_N_1110,
	load_disp_rm_rn_l_D_0100_M_0100_N_1110,
	load_disp_rm_rn_l_D_0101_M_0100_N_1110,
	load_disp_rm_rn_l_D_0110_M_0100_N_1110,
	load_disp_rm_rn_l_D_0111_M_0100_N_1110,
	load_disp_rm_rn_l_D_1000_M_0100_N_1110,
	load_disp_rm_rn_l_D_1001_M_0100_N_1110,
	load_disp_rm_rn_l_D_1010_M_0100_N_1110,
	load_disp_rm_rn_l_D_1011_M_0100_N_1110,
	load_disp_rm_rn_l_D_1100_M_0100_N_1110,
	load_disp_rm_rn_l_D_1101_M_0100_N_1110,
	load_disp_rm_rn_l_D_1110_M_0100_N_1110,
	load_disp_rm_rn_l_D_1111_M_0100_N_1110,
	load_disp_rm_rn_l_D_0000_M_0101_N_1110,
	load_disp_rm_rn_l_D_0001_M_0101_N_1110,
	load_disp_rm_rn_l_D_0010_M_0101_N_1110,
	load_disp_rm_rn_l_D_0011_M_0101_N_1110,
	load_disp_rm_rn_l_D_0100_M_0101_N_1110,
	load_disp_rm_rn_l_D_0101_M_0101_N_1110,
	load_disp_rm_rn_l_D_0110_M_0101_N_1110,
	load_disp_rm_rn_l_D_0111_M_0101_N_1110,
	load_disp_rm_rn_l_D_1000_M_0101_N_1110,
	load_disp_rm_rn_l_D_1001_M_0101_N_1110,
	load_disp_rm_rn_l_D_1010_M_0101_N_1110,
	load_disp_rm_rn_l_D_1011_M_0101_N_1110,
	load_disp_rm_rn_l_D_1100_M_0101_N_1110,
	load_disp_rm_rn_l_D_1101_M_0101_N_1110,
	load_disp_rm_rn_l_D_1110_M_0101_N_1110,
	load_disp_rm_rn_l_D_1111_M_0101_N_1110,
	load_disp_rm_rn_l_D_0000_M_0110_N_1110,
	load_disp_rm_rn_l_D_0001_M_0110_N_1110,
	load_disp_rm_rn_l_D_0010_M_0110_N_1110,
	load_disp_rm_rn_l_D_0011_M_0110_N_1110,
	load_disp_rm_rn_l_D_0100_M_0110_N_1110,
	load_disp_rm_rn_l_D_0101_M_0110_N_1110,
	load_disp_rm_rn_l_D_0110_M_0110_N_1110,
	load_disp_rm_rn_l_D_0111_M_0110_N_1110,
	load_disp_rm_rn_l_D_1000_M_0110_N_1110,
	load_disp_rm_rn_l_D_1001_M_0110_N_1110,
	load_disp_rm_rn_l_D_1010_M_0110_N_1110,
	load_disp_rm_rn_l_D_1011_M_0110_N_1110,
	load_disp_rm_rn_l_D_1100_M_0110_N_1110,
	load_disp_rm_rn_l_D_1101_M_0110_N_1110,
	load_disp_rm_rn_l_D_1110_M_0110_N_1110,
	load_disp_rm_rn_l_D_1111_M_0110_N_1110,
	load_disp_rm_rn_l_D_0000_M_0111_N_1110,
	load_disp_rm_rn_l_D_0001_M_0111_N_1110,
	load_disp_rm_rn_l_D_0010_M_0111_N_1110,
	load_disp_rm_rn_l_D_0011_M_0111_N_1110,
	load_disp_rm_rn_l_D_0100_M_0111_N_1110,
	load_disp_rm_rn_l_D_0101_M_0111_N_1110,
	load_disp_rm_rn_l_D_0110_M_0111_N_1110,
	load_disp_rm_rn_l_D_0111_M_0111_N_1110,
	load_disp_rm_rn_l_D_1000_M_0111_N_1110,
	load_disp_rm_rn_l_D_1001_M_0111_N_1110,
	load_disp_rm_rn_l_D_1010_M_0111_N_1110,
	load_disp_rm_rn_l_D_1011_M_0111_N_1110,
	load_disp_rm_rn_l_D_1100_M_0111_N_1110,
	load_disp_rm_rn_l_D_1101_M_0111_N_1110,
	load_disp_rm_rn_l_D_1110_M_0111_N_1110,
	load_disp_rm_rn_l_D_1111_M_0111_N_1110,
	load_disp_rm_rn_l_D_0000_M_1000_N_1110,
	load_disp_rm_rn_l_D_0001_M_1000_N_1110,
	load_disp_rm_rn_l_D_0010_M_1000_N_1110,
	load_disp_rm_rn_l_D_0011_M_1000_N_1110,
	load_disp_rm_rn_l_D_0100_M_1000_N_1110,
	load_disp_rm_rn_l_D_0101_M_1000_N_1110,
	load_disp_rm_rn_l_D_0110_M_1000_N_1110,
	load_disp_rm_rn_l_D_0111_M_1000_N_1110,
	load_disp_rm_rn_l_D_1000_M_1000_N_1110,
	load_disp_rm_rn_l_D_1001_M_1000_N_1110,
	load_disp_rm_rn_l_D_1010_M_1000_N_1110,
	load_disp_rm_rn_l_D_1011_M_1000_N_1110,
	load_disp_rm_rn_l_D_1100_M_1000_N_1110,
	load_disp_rm_rn_l_D_1101_M_1000_N_1110,
	load_disp_rm_rn_l_D_1110_M_1000_N_1110,
	load_disp_rm_rn_l_D_1111_M_1000_N_1110,
	load_disp_rm_rn_l_D_0000_M_1001_N_1110,
	load_disp_rm_rn_l_D_0001_M_1001_N_1110,
	load_disp_rm_rn_l_D_0010_M_1001_N_1110,
	load_disp_rm_rn_l_D_0011_M_1001_N_1110,
	load_disp_rm_rn_l_D_0100_M_1001_N_1110,
	load_disp_rm_rn_l_D_0101_M_1001_N_1110,
	load_disp_rm_rn_l_D_0110_M_1001_N_1110,
	load_disp_rm_rn_l_D_0111_M_1001_N_1110,
	load_disp_rm_rn_l_D_1000_M_1001_N_1110,
	load_disp_rm_rn_l_D_1001_M_1001_N_1110,
	load_disp_rm_rn_l_D_1010_M_1001_N_1110,
	load_disp_rm_rn_l_D_1011_M_1001_N_1110,
	load_disp_rm_rn_l_D_1100_M_1001_N_1110,
	load_disp_rm_rn_l_D_1101_M_1001_N_1110,
	load_disp_rm_rn_l_D_1110_M_1001_N_1110,
	load_disp_rm_rn_l_D_1111_M_1001_N_1110,
	load_disp_rm_rn_l_D_0000_M_1010_N_1110,
	load_disp_rm_rn_l_D_0001_M_1010_N_1110,
	load_disp_rm_rn_l_D_0010_M_1010_N_1110,
	load_disp_rm_rn_l_D_0011_M_1010_N_1110,
	load_disp_rm_rn_l_D_0100_M_1010_N_1110,
	load_disp_rm_rn_l_D_0101_M_1010_N_1110,
	load_disp_rm_rn_l_D_0110_M_1010_N_1110,
	load_disp_rm_rn_l_D_0111_M_1010_N_1110,
	load_disp_rm_rn_l_D_1000_M_1010_N_1110,
	load_disp_rm_rn_l_D_1001_M_1010_N_1110,
	load_disp_rm_rn_l_D_1010_M_1010_N_1110,
	load_disp_rm_rn_l_D_1011_M_1010_N_1110,
	load_disp_rm_rn_l_D_1100_M_1010_N_1110,
	load_disp_rm_rn_l_D_1101_M_1010_N_1110,
	load_disp_rm_rn_l_D_1110_M_1010_N_1110,
	load_disp_rm_rn_l_D_1111_M_1010_N_1110,
	load_disp_rm_rn_l_D_0000_M_1011_N_1110,
	load_disp_rm_rn_l_D_0001_M_1011_N_1110,
	load_disp_rm_rn_l_D_0010_M_1011_N_1110,
	load_disp_rm_rn_l_D_0011_M_1011_N_1110,
	load_disp_rm_rn_l_D_0100_M_1011_N_1110,
	load_disp_rm_rn_l_D_0101_M_1011_N_1110,
	load_disp_rm_rn_l_D_0110_M_1011_N_1110,
	load_disp_rm_rn_l_D_0111_M_1011_N_1110,
	load_disp_rm_rn_l_D_1000_M_1011_N_1110,
	load_disp_rm_rn_l_D_1001_M_1011_N_1110,
	load_disp_rm_rn_l_D_1010_M_1011_N_1110,
	load_disp_rm_rn_l_D_1011_M_1011_N_1110,
	load_disp_rm_rn_l_D_1100_M_1011_N_1110,
	load_disp_rm_rn_l_D_1101_M_1011_N_1110,
	load_disp_rm_rn_l_D_1110_M_1011_N_1110,
	load_disp_rm_rn_l_D_1111_M_1011_N_1110,
	load_disp_rm_rn_l_D_0000_M_1100_N_1110,
	load_disp_rm_rn_l_D_0001_M_1100_N_1110,
	load_disp_rm_rn_l_D_0010_M_1100_N_1110,
	load_disp_rm_rn_l_D_0011_M_1100_N_1110,
	load_disp_rm_rn_l_D_0100_M_1100_N_1110,
	load_disp_rm_rn_l_D_0101_M_1100_N_1110,
	load_disp_rm_rn_l_D_0110_M_1100_N_1110,
	load_disp_rm_rn_l_D_0111_M_1100_N_1110,
	load_disp_rm_rn_l_D_1000_M_1100_N_1110,
	load_disp_rm_rn_l_D_1001_M_1100_N_1110,
	load_disp_rm_rn_l_D_1010_M_1100_N_1110,
	load_disp_rm_rn_l_D_1011_M_1100_N_1110,
	load_disp_rm_rn_l_D_1100_M_1100_N_1110,
	load_disp_rm_rn_l_D_1101_M_1100_N_1110,
	load_disp_rm_rn_l_D_1110_M_1100_N_1110,
	load_disp_rm_rn_l_D_1111_M_1100_N_1110,
	load_disp_rm_rn_l_D_0000_M_1101_N_1110,
	load_disp_rm_rn_l_D_0001_M_1101_N_1110,
	load_disp_rm_rn_l_D_0010_M_1101_N_1110,
	load_disp_rm_rn_l_D_0011_M_1101_N_1110,
	load_disp_rm_rn_l_D_0100_M_1101_N_1110,
	load_disp_rm_rn_l_D_0101_M_1101_N_1110,
	load_disp_rm_rn_l_D_0110_M_1101_N_1110,
	load_disp_rm_rn_l_D_0111_M_1101_N_1110,
	load_disp_rm_rn_l_D_1000_M_1101_N_1110,
	load_disp_rm_rn_l_D_1001_M_1101_N_1110,
	load_disp_rm_rn_l_D_1010_M_1101_N_1110,
	load_disp_rm_rn_l_D_1011_M_1101_N_1110,
	load_disp_rm_rn_l_D_1100_M_1101_N_1110,
	load_disp_rm_rn_l_D_1101_M_1101_N_1110,
	load_disp_rm_rn_l_D_1110_M_1101_N_1110,
	load_disp_rm_rn_l_D_1111_M_1101_N_1110,
	load_disp_rm_rn_l_D_0000_M_1110_N_1110,
	load_disp_rm_rn_l_D_0001_M_1110_N_1110,
	load_disp_rm_rn_l_D_0010_M_1110_N_1110,
	load_disp_rm_rn_l_D_0011_M_1110_N_1110,
	load_disp_rm_rn_l_D_0100_M_1110_N_1110,
	load_disp_rm_rn_l_D_0101_M_1110_N_1110,
	load_disp_rm_rn_l_D_0110_M_1110_N_1110,
	load_disp_rm_rn_l_D_0111_M_1110_N_1110,
	load_disp_rm_rn_l_D_1000_M_1110_N_1110,
	load_disp_rm_rn_l_D_1001_M_1110_N_1110,
	load_disp_rm_rn_l_D_1010_M_1110_N_1110,
	load_disp_rm_rn_l_D_1011_M_1110_N_1110,
	load_disp_rm_rn_l_D_1100_M_1110_N_1110,
	load_disp_rm_rn_l_D_1101_M_1110_N_1110,
	load_disp_rm_rn_l_D_1110_M_1110_N_1110,
	load_disp_rm_rn_l_D_1111_M_1110_N_1110,
	load_disp_rm_rn_l_D_0000_M_1111_N_1110,
	load_disp_rm_rn_l_D_0001_M_1111_N_1110,
	load_disp_rm_rn_l_D_0010_M_1111_N_1110,
	load_disp_rm_rn_l_D_0011_M_1111_N_1110,
	load_disp_rm_rn_l_D_0100_M_1111_N_1110,
	load_disp_rm_rn_l_D_0101_M_1111_N_1110,
	load_disp_rm_rn_l_D_0110_M_1111_N_1110,
	load_disp_rm_rn_l_D_0111_M_1111_N_1110,
	load_disp_rm_rn_l_D_1000_M_1111_N_1110,
	load_disp_rm_rn_l_D_1001_M_1111_N_1110,
	load_disp_rm_rn_l_D_1010_M_1111_N_1110,
	load_disp_rm_rn_l_D_1011_M_1111_N_1110,
	load_disp_rm_rn_l_D_1100_M_1111_N_1110,
	load_disp_rm_rn_l_D_1101_M_1111_N_1110,
	load_disp_rm_rn_l_D_1110_M_1111_N_1110,
	load_disp_rm_rn_l_D_1111_M_1111_N_1110,
	load_disp_rm_rn_l_D_0000_M_0000_N_1111,
	load_disp_rm_rn_l_D_0001_M_0000_N_1111,
	load_disp_rm_rn_l_D_0010_M_0000_N_1111,
	load_disp_rm_rn_l_D_0011_M_0000_N_1111,
	load_disp_rm_rn_l_D_0100_M_0000_N_1111,
	load_disp_rm_rn_l_D_0101_M_0000_N_1111,
	load_disp_rm_rn_l_D_0110_M_0000_N_1111,
	load_disp_rm_rn_l_D_0111_M_0000_N_1111,
	load_disp_rm_rn_l_D_1000_M_0000_N_1111,
	load_disp_rm_rn_l_D_1001_M_0000_N_1111,
	load_disp_rm_rn_l_D_1010_M_0000_N_1111,
	load_disp_rm_rn_l_D_1011_M_0000_N_1111,
	load_disp_rm_rn_l_D_1100_M_0000_N_1111,
	load_disp_rm_rn_l_D_1101_M_0000_N_1111,
	load_disp_rm_rn_l_D_1110_M_0000_N_1111,
	load_disp_rm_rn_l_D_1111_M_0000_N_1111,
	load_disp_rm_rn_l_D_0000_M_0001_N_1111,
	load_disp_rm_rn_l_D_0001_M_0001_N_1111,
	load_disp_rm_rn_l_D_0010_M_0001_N_1111,
	load_disp_rm_rn_l_D_0011_M_0001_N_1111,
	load_disp_rm_rn_l_D_0100_M_0001_N_1111,
	load_disp_rm_rn_l_D_0101_M_0001_N_1111,
	load_disp_rm_rn_l_D_0110_M_0001_N_1111,
	load_disp_rm_rn_l_D_0111_M_0001_N_1111,
	load_disp_rm_rn_l_D_1000_M_0001_N_1111,
	load_disp_rm_rn_l_D_1001_M_0001_N_1111,
	load_disp_rm_rn_l_D_1010_M_0001_N_1111,
	load_disp_rm_rn_l_D_1011_M_0001_N_1111,
	load_disp_rm_rn_l_D_1100_M_0001_N_1111,
	load_disp_rm_rn_l_D_1101_M_0001_N_1111,
	load_disp_rm_rn_l_D_1110_M_0001_N_1111,
	load_disp_rm_rn_l_D_1111_M_0001_N_1111,
	load_disp_rm_rn_l_D_0000_M_0010_N_1111,
	load_disp_rm_rn_l_D_0001_M_0010_N_1111,
	load_disp_rm_rn_l_D_0010_M_0010_N_1111,
	load_disp_rm_rn_l_D_0011_M_0010_N_1111,
	load_disp_rm_rn_l_D_0100_M_0010_N_1111,
	load_disp_rm_rn_l_D_0101_M_0010_N_1111,
	load_disp_rm_rn_l_D_0110_M_0010_N_1111,
	load_disp_rm_rn_l_D_0111_M_0010_N_1111,
	load_disp_rm_rn_l_D_1000_M_0010_N_1111,
	load_disp_rm_rn_l_D_1001_M_0010_N_1111,
	load_disp_rm_rn_l_D_1010_M_0010_N_1111,
	load_disp_rm_rn_l_D_1011_M_0010_N_1111,
	load_disp_rm_rn_l_D_1100_M_0010_N_1111,
	load_disp_rm_rn_l_D_1101_M_0010_N_1111,
	load_disp_rm_rn_l_D_1110_M_0010_N_1111,
	load_disp_rm_rn_l_D_1111_M_0010_N_1111,
	load_disp_rm_rn_l_D_0000_M_0011_N_1111,
	load_disp_rm_rn_l_D_0001_M_0011_N_1111,
	load_disp_rm_rn_l_D_0010_M_0011_N_1111,
	load_disp_rm_rn_l_D_0011_M_0011_N_1111,
	load_disp_rm_rn_l_D_0100_M_0011_N_1111,
	load_disp_rm_rn_l_D_0101_M_0011_N_1111,
	load_disp_rm_rn_l_D_0110_M_0011_N_1111,
	load_disp_rm_rn_l_D_0111_M_0011_N_1111,
	load_disp_rm_rn_l_D_1000_M_0011_N_1111,
	load_disp_rm_rn_l_D_1001_M_0011_N_1111,
	load_disp_rm_rn_l_D_1010_M_0011_N_1111,
	load_disp_rm_rn_l_D_1011_M_0011_N_1111,
	load_disp_rm_rn_l_D_1100_M_0011_N_1111,
	load_disp_rm_rn_l_D_1101_M_0011_N_1111,
	load_disp_rm_rn_l_D_1110_M_0011_N_1111,
	load_disp_rm_rn_l_D_1111_M_0011_N_1111,
	load_disp_rm_rn_l_D_0000_M_0100_N_1111,
	load_disp_rm_rn_l_D_0001_M_0100_N_1111,
	load_disp_rm_rn_l_D_0010_M_0100_N_1111,
	load_disp_rm_rn_l_D_0011_M_0100_N_1111,
	load_disp_rm_rn_l_D_0100_M_0100_N_1111,
	load_disp_rm_rn_l_D_0101_M_0100_N_1111,
	load_disp_rm_rn_l_D_0110_M_0100_N_1111,
	load_disp_rm_rn_l_D_0111_M_0100_N_1111,
	load_disp_rm_rn_l_D_1000_M_0100_N_1111,
	load_disp_rm_rn_l_D_1001_M_0100_N_1111,
	load_disp_rm_rn_l_D_1010_M_0100_N_1111,
	load_disp_rm_rn_l_D_1011_M_0100_N_1111,
	load_disp_rm_rn_l_D_1100_M_0100_N_1111,
	load_disp_rm_rn_l_D_1101_M_0100_N_1111,
	load_disp_rm_rn_l_D_1110_M_0100_N_1111,
	load_disp_rm_rn_l_D_1111_M_0100_N_1111,
	load_disp_rm_rn_l_D_0000_M_0101_N_1111,
	load_disp_rm_rn_l_D_0001_M_0101_N_1111,
	load_disp_rm_rn_l_D_0010_M_0101_N_1111,
	load_disp_rm_rn_l_D_0011_M_0101_N_1111,
	load_disp_rm_rn_l_D_0100_M_0101_N_1111,
	load_disp_rm_rn_l_D_0101_M_0101_N_1111,
	load_disp_rm_rn_l_D_0110_M_0101_N_1111,
	load_disp_rm_rn_l_D_0111_M_0101_N_1111,
	load_disp_rm_rn_l_D_1000_M_0101_N_1111,
	load_disp_rm_rn_l_D_1001_M_0101_N_1111,
	load_disp_rm_rn_l_D_1010_M_0101_N_1111,
	load_disp_rm_rn_l_D_1011_M_0101_N_1111,
	load_disp_rm_rn_l_D_1100_M_0101_N_1111,
	load_disp_rm_rn_l_D_1101_M_0101_N_1111,
	load_disp_rm_rn_l_D_1110_M_0101_N_1111,
	load_disp_rm_rn_l_D_1111_M_0101_N_1111,
	load_disp_rm_rn_l_D_0000_M_0110_N_1111,
	load_disp_rm_rn_l_D_0001_M_0110_N_1111,
	load_disp_rm_rn_l_D_0010_M_0110_N_1111,
	load_disp_rm_rn_l_D_0011_M_0110_N_1111,
	load_disp_rm_rn_l_D_0100_M_0110_N_1111,
	load_disp_rm_rn_l_D_0101_M_0110_N_1111,
	load_disp_rm_rn_l_D_0110_M_0110_N_1111,
	load_disp_rm_rn_l_D_0111_M_0110_N_1111,
	load_disp_rm_rn_l_D_1000_M_0110_N_1111,
	load_disp_rm_rn_l_D_1001_M_0110_N_1111,
	load_disp_rm_rn_l_D_1010_M_0110_N_1111,
	load_disp_rm_rn_l_D_1011_M_0110_N_1111,
	load_disp_rm_rn_l_D_1100_M_0110_N_1111,
	load_disp_rm_rn_l_D_1101_M_0110_N_1111,
	load_disp_rm_rn_l_D_1110_M_0110_N_1111,
	load_disp_rm_rn_l_D_1111_M_0110_N_1111,
	load_disp_rm_rn_l_D_0000_M_0111_N_1111,
	load_disp_rm_rn_l_D_0001_M_0111_N_1111,
	load_disp_rm_rn_l_D_0010_M_0111_N_1111,
	load_disp_rm_rn_l_D_0011_M_0111_N_1111,
	load_disp_rm_rn_l_D_0100_M_0111_N_1111,
	load_disp_rm_rn_l_D_0101_M_0111_N_1111,
	load_disp_rm_rn_l_D_0110_M_0111_N_1111,
	load_disp_rm_rn_l_D_0111_M_0111_N_1111,
	load_disp_rm_rn_l_D_1000_M_0111_N_1111,
	load_disp_rm_rn_l_D_1001_M_0111_N_1111,
	load_disp_rm_rn_l_D_1010_M_0111_N_1111,
	load_disp_rm_rn_l_D_1011_M_0111_N_1111,
	load_disp_rm_rn_l_D_1100_M_0111_N_1111,
	load_disp_rm_rn_l_D_1101_M_0111_N_1111,
	load_disp_rm_rn_l_D_1110_M_0111_N_1111,
	load_disp_rm_rn_l_D_1111_M_0111_N_1111,
	load_disp_rm_rn_l_D_0000_M_1000_N_1111,
	load_disp_rm_rn_l_D_0001_M_1000_N_1111,
	load_disp_rm_rn_l_D_0010_M_1000_N_1111,
	load_disp_rm_rn_l_D_0011_M_1000_N_1111,
	load_disp_rm_rn_l_D_0100_M_1000_N_1111,
	load_disp_rm_rn_l_D_0101_M_1000_N_1111,
	load_disp_rm_rn_l_D_0110_M_1000_N_1111,
	load_disp_rm_rn_l_D_0111_M_1000_N_1111,
	load_disp_rm_rn_l_D_1000_M_1000_N_1111,
	load_disp_rm_rn_l_D_1001_M_1000_N_1111,
	load_disp_rm_rn_l_D_1010_M_1000_N_1111,
	load_disp_rm_rn_l_D_1011_M_1000_N_1111,
	load_disp_rm_rn_l_D_1100_M_1000_N_1111,
	load_disp_rm_rn_l_D_1101_M_1000_N_1111,
	load_disp_rm_rn_l_D_1110_M_1000_N_1111,
	load_disp_rm_rn_l_D_1111_M_1000_N_1111,
	load_disp_rm_rn_l_D_0000_M_1001_N_1111,
	load_disp_rm_rn_l_D_0001_M_1001_N_1111,
	load_disp_rm_rn_l_D_0010_M_1001_N_1111,
	load_disp_rm_rn_l_D_0011_M_1001_N_1111,
	load_disp_rm_rn_l_D_0100_M_1001_N_1111,
	load_disp_rm_rn_l_D_0101_M_1001_N_1111,
	load_disp_rm_rn_l_D_0110_M_1001_N_1111,
	load_disp_rm_rn_l_D_0111_M_1001_N_1111,
	load_disp_rm_rn_l_D_1000_M_1001_N_1111,
	load_disp_rm_rn_l_D_1001_M_1001_N_1111,
	load_disp_rm_rn_l_D_1010_M_1001_N_1111,
	load_disp_rm_rn_l_D_1011_M_1001_N_1111,
	load_disp_rm_rn_l_D_1100_M_1001_N_1111,
	load_disp_rm_rn_l_D_1101_M_1001_N_1111,
	load_disp_rm_rn_l_D_1110_M_1001_N_1111,
	load_disp_rm_rn_l_D_1111_M_1001_N_1111,
	load_disp_rm_rn_l_D_0000_M_1010_N_1111,
	load_disp_rm_rn_l_D_0001_M_1010_N_1111,
	load_disp_rm_rn_l_D_0010_M_1010_N_1111,
	load_disp_rm_rn_l_D_0011_M_1010_N_1111,
	load_disp_rm_rn_l_D_0100_M_1010_N_1111,
	load_disp_rm_rn_l_D_0101_M_1010_N_1111,
	load_disp_rm_rn_l_D_0110_M_1010_N_1111,
	load_disp_rm_rn_l_D_0111_M_1010_N_1111,
	load_disp_rm_rn_l_D_1000_M_1010_N_1111,
	load_disp_rm_rn_l_D_1001_M_1010_N_1111,
	load_disp_rm_rn_l_D_1010_M_1010_N_1111,
	load_disp_rm_rn_l_D_1011_M_1010_N_1111,
	load_disp_rm_rn_l_D_1100_M_1010_N_1111,
	load_disp_rm_rn_l_D_1101_M_1010_N_1111,
	load_disp_rm_rn_l_D_1110_M_1010_N_1111,
	load_disp_rm_rn_l_D_1111_M_1010_N_1111,
	load_disp_rm_rn_l_D_0000_M_1011_N_1111,
	load_disp_rm_rn_l_D_0001_M_1011_N_1111,
	load_disp_rm_rn_l_D_0010_M_1011_N_1111,
	load_disp_rm_rn_l_D_0011_M_1011_N_1111,
	load_disp_rm_rn_l_D_0100_M_1011_N_1111,
	load_disp_rm_rn_l_D_0101_M_1011_N_1111,
	load_disp_rm_rn_l_D_0110_M_1011_N_1111,
	load_disp_rm_rn_l_D_0111_M_1011_N_1111,
	load_disp_rm_rn_l_D_1000_M_1011_N_1111,
	load_disp_rm_rn_l_D_1001_M_1011_N_1111,
	load_disp_rm_rn_l_D_1010_M_1011_N_1111,
	load_disp_rm_rn_l_D_1011_M_1011_N_1111,
	load_disp_rm_rn_l_D_1100_M_1011_N_1111,
	load_disp_rm_rn_l_D_1101_M_1011_N_1111,
	load_disp_rm_rn_l_D_1110_M_1011_N_1111,
	load_disp_rm_rn_l_D_1111_M_1011_N_1111,
	load_disp_rm_rn_l_D_0000_M_1100_N_1111,
	load_disp_rm_rn_l_D_0001_M_1100_N_1111,
	load_disp_rm_rn_l_D_0010_M_1100_N_1111,
	load_disp_rm_rn_l_D_0011_M_1100_N_1111,
	load_disp_rm_rn_l_D_0100_M_1100_N_1111,
	load_disp_rm_rn_l_D_0101_M_1100_N_1111,
	load_disp_rm_rn_l_D_0110_M_1100_N_1111,
	load_disp_rm_rn_l_D_0111_M_1100_N_1111,
	load_disp_rm_rn_l_D_1000_M_1100_N_1111,
	load_disp_rm_rn_l_D_1001_M_1100_N_1111,
	load_disp_rm_rn_l_D_1010_M_1100_N_1111,
	load_disp_rm_rn_l_D_1011_M_1100_N_1111,
	load_disp_rm_rn_l_D_1100_M_1100_N_1111,
	load_disp_rm_rn_l_D_1101_M_1100_N_1111,
	load_disp_rm_rn_l_D_1110_M_1100_N_1111,
	load_disp_rm_rn_l_D_1111_M_1100_N_1111,
	load_disp_rm_rn_l_D_0000_M_1101_N_1111,
	load_disp_rm_rn_l_D_0001_M_1101_N_1111,
	load_disp_rm_rn_l_D_0010_M_1101_N_1111,
	load_disp_rm_rn_l_D_0011_M_1101_N_1111,
	load_disp_rm_rn_l_D_0100_M_1101_N_1111,
	load_disp_rm_rn_l_D_0101_M_1101_N_1111,
	load_disp_rm_rn_l_D_0110_M_1101_N_1111,
	load_disp_rm_rn_l_D_0111_M_1101_N_1111,
	load_disp_rm_rn_l_D_1000_M_1101_N_1111,
	load_disp_rm_rn_l_D_1001_M_1101_N_1111,
	load_disp_rm_rn_l_D_1010_M_1101_N_1111,
	load_disp_rm_rn_l_D_1011_M_1101_N_1111,
	load_disp_rm_rn_l_D_1100_M_1101_N_1111,
	load_disp_rm_rn_l_D_1101_M_1101_N_1111,
	load_disp_rm_rn_l_D_1110_M_1101_N_1111,
	load_disp_rm_rn_l_D_1111_M_1101_N_1111,
	load_disp_rm_rn_l_D_0000_M_1110_N_1111,
	load_disp_rm_rn_l_D_0001_M_1110_N_1111,
	load_disp_rm_rn_l_D_0010_M_1110_N_1111,
	load_disp_rm_rn_l_D_0011_M_1110_N_1111,
	load_disp_rm_rn_l_D_0100_M_1110_N_1111,
	load_disp_rm_rn_l_D_0101_M_1110_N_1111,
	load_disp_rm_rn_l_D_0110_M_1110_N_1111,
	load_disp_rm_rn_l_D_0111_M_1110_N_1111,
	load_disp_rm_rn_l_D_1000_M_1110_N_1111,
	load_disp_rm_rn_l_D_1001_M_1110_N_1111,
	load_disp_rm_rn_l_D_1010_M_1110_N_1111,
	load_disp_rm_rn_l_D_1011_M_1110_N_1111,
	load_disp_rm_rn_l_D_1100_M_1110_N_1111,
	load_disp_rm_rn_l_D_1101_M_1110_N_1111,
	load_disp_rm_rn_l_D_1110_M_1110_N_1111,
	load_disp_rm_rn_l_D_1111_M_1110_N_1111,
	load_disp_rm_rn_l_D_0000_M_1111_N_1111,
	load_disp_rm_rn_l_D_0001_M_1111_N_1111,
	load_disp_rm_rn_l_D_0010_M_1111_N_1111,
	load_disp_rm_rn_l_D_0011_M_1111_N_1111,
	load_disp_rm_rn_l_D_0100_M_1111_N_1111,
	load_disp_rm_rn_l_D_0101_M_1111_N_1111,
	load_disp_rm_rn_l_D_0110_M_1111_N_1111,
	load_disp_rm_rn_l_D_0111_M_1111_N_1111,
	load_disp_rm_rn_l_D_1000_M_1111_N_1111,
	load_disp_rm_rn_l_D_1001_M_1111_N_1111,
	load_disp_rm_rn_l_D_1010_M_1111_N_1111,
	load_disp_rm_rn_l_D_1011_M_1111_N_1111,
	load_disp_rm_rn_l_D_1100_M_1111_N_1111,
	load_disp_rm_rn_l_D_1101_M_1111_N_1111,
	load_disp_rm_rn_l_D_1110_M_1111_N_1111,
	load_disp_rm_rn_l_D_1111_M_1111_N_1111,
	load_rm_rn_b_M_0000_N_0000,
	load_rm_rn_w_M_0000_N_0000,
	load_rm_rn_l_M_0000_N_0000,
	mov_rm_rn_M_0000_N_0000,
	load_postinc_rm_rn_b_M_0000_N_0000,
	load_postinc_rm_rn_w_M_0000_N_0000,
	load_postinc_rm_rn_l_M_0000_N_0000,
	not_M_0000_N_0000,
	swap_b_M_0000_N_0000,
	swap_w_M_0000_N_0000,
	negc_M_0000_N_0000,
	neg_M_0000_N_0000,
	extu_b_M_0000_N_0000,
	extu_w_M_0000_N_0000,
	exts_b_M_0000_N_0000,
	exts_w_M_0000_N_0000,
	load_rm_rn_b_M_0001_N_0000,
	load_rm_rn_w_M_0001_N_0000,
	load_rm_rn_l_M_0001_N_0000,
	mov_rm_rn_M_0001_N_0000,
	load_postinc_rm_rn_b_M_0001_N_0000,
	load_postinc_rm_rn_w_M_0001_N_0000,
	load_postinc_rm_rn_l_M_0001_N_0000,
	not_M_0001_N_0000,
	swap_b_M_0001_N_0000,
	swap_w_M_0001_N_0000,
	negc_M_0001_N_0000,
	neg_M_0001_N_0000,
	extu_b_M_0001_N_0000,
	extu_w_M_0001_N_0000,
	exts_b_M_0001_N_0000,
	exts_w_M_0001_N_0000,
	load_rm_rn_b_M_0010_N_0000,
	load_rm_rn_w_M_0010_N_0000,
	load_rm_rn_l_M_0010_N_0000,
	mov_rm_rn_M_0010_N_0000,
	load_postinc_rm_rn_b_M_0010_N_0000,
	load_postinc_rm_rn_w_M_0010_N_0000,
	load_postinc_rm_rn_l_M_0010_N_0000,
	not_M_0010_N_0000,
	swap_b_M_0010_N_0000,
	swap_w_M_0010_N_0000,
	negc_M_0010_N_0000,
	neg_M_0010_N_0000,
	extu_b_M_0010_N_0000,
	extu_w_M_0010_N_0000,
	exts_b_M_0010_N_0000,
	exts_w_M_0010_N_0000,
	load_rm_rn_b_M_0011_N_0000,
	load_rm_rn_w_M_0011_N_0000,
	load_rm_rn_l_M_0011_N_0000,
	mov_rm_rn_M_0011_N_0000,
	load_postinc_rm_rn_b_M_0011_N_0000,
	load_postinc_rm_rn_w_M_0011_N_0000,
	load_postinc_rm_rn_l_M_0011_N_0000,
	not_M_0011_N_0000,
	swap_b_M_0011_N_0000,
	swap_w_M_0011_N_0000,
	negc_M_0011_N_0000,
	neg_M_0011_N_0000,
	extu_b_M_0011_N_0000,
	extu_w_M_0011_N_0000,
	exts_b_M_0011_N_0000,
	exts_w_M_0011_N_0000,
	load_rm_rn_b_M_0100_N_0000,
	load_rm_rn_w_M_0100_N_0000,
	load_rm_rn_l_M_0100_N_0000,
	mov_rm_rn_M_0100_N_0000,
	load_postinc_rm_rn_b_M_0100_N_0000,
	load_postinc_rm_rn_w_M_0100_N_0000,
	load_postinc_rm_rn_l_M_0100_N_0000,
	not_M_0100_N_0000,
	swap_b_M_0100_N_0000,
	swap_w_M_0100_N_0000,
	negc_M_0100_N_0000,
	neg_M_0100_N_0000,
	extu_b_M_0100_N_0000,
	extu_w_M_0100_N_0000,
	exts_b_M_0100_N_0000,
	exts_w_M_0100_N_0000,
	load_rm_rn_b_M_0101_N_0000,
	load_rm_rn_w_M_0101_N_0000,
	load_rm_rn_l_M_0101_N_0000,
	mov_rm_rn_M_0101_N_0000,
	load_postinc_rm_rn_b_M_0101_N_0000,
	load_postinc_rm_rn_w_M_0101_N_0000,
	load_postinc_rm_rn_l_M_0101_N_0000,
	not_M_0101_N_0000,
	swap_b_M_0101_N_0000,
	swap_w_M_0101_N_0000,
	negc_M_0101_N_0000,
	neg_M_0101_N_0000,
	extu_b_M_0101_N_0000,
	extu_w_M_0101_N_0000,
	exts_b_M_0101_N_0000,
	exts_w_M_0101_N_0000,
	load_rm_rn_b_M_0110_N_0000,
	load_rm_rn_w_M_0110_N_0000,
	load_rm_rn_l_M_0110_N_0000,
	mov_rm_rn_M_0110_N_0000,
	load_postinc_rm_rn_b_M_0110_N_0000,
	load_postinc_rm_rn_w_M_0110_N_0000,
	load_postinc_rm_rn_l_M_0110_N_0000,
	not_M_0110_N_0000,
	swap_b_M_0110_N_0000,
	swap_w_M_0110_N_0000,
	negc_M_0110_N_0000,
	neg_M_0110_N_0000,
	extu_b_M_0110_N_0000,
	extu_w_M_0110_N_0000,
	exts_b_M_0110_N_0000,
	exts_w_M_0110_N_0000,
	load_rm_rn_b_M_0111_N_0000,
	load_rm_rn_w_M_0111_N_0000,
	load_rm_rn_l_M_0111_N_0000,
	mov_rm_rn_M_0111_N_0000,
	load_postinc_rm_rn_b_M_0111_N_0000,
	load_postinc_rm_rn_w_M_0111_N_0000,
	load_postinc_rm_rn_l_M_0111_N_0000,
	not_M_0111_N_0000,
	swap_b_M_0111_N_0000,
	swap_w_M_0111_N_0000,
	negc_M_0111_N_0000,
	neg_M_0111_N_0000,
	extu_b_M_0111_N_0000,
	extu_w_M_0111_N_0000,
	exts_b_M_0111_N_0000,
	exts_w_M_0111_N_0000,
	load_rm_rn_b_M_1000_N_0000,
	load_rm_rn_w_M_1000_N_0000,
	load_rm_rn_l_M_1000_N_0000,
	mov_rm_rn_M_1000_N_0000,
	load_postinc_rm_rn_b_M_1000_N_0000,
	load_postinc_rm_rn_w_M_1000_N_0000,
	load_postinc_rm_rn_l_M_1000_N_0000,
	not_M_1000_N_0000,
	swap_b_M_1000_N_0000,
	swap_w_M_1000_N_0000,
	negc_M_1000_N_0000,
	neg_M_1000_N_0000,
	extu_b_M_1000_N_0000,
	extu_w_M_1000_N_0000,
	exts_b_M_1000_N_0000,
	exts_w_M_1000_N_0000,
	load_rm_rn_b_M_1001_N_0000,
	load_rm_rn_w_M_1001_N_0000,
	load_rm_rn_l_M_1001_N_0000,
	mov_rm_rn_M_1001_N_0000,
	load_postinc_rm_rn_b_M_1001_N_0000,
	load_postinc_rm_rn_w_M_1001_N_0000,
	load_postinc_rm_rn_l_M_1001_N_0000,
	not_M_1001_N_0000,
	swap_b_M_1001_N_0000,
	swap_w_M_1001_N_0000,
	negc_M_1001_N_0000,
	neg_M_1001_N_0000,
	extu_b_M_1001_N_0000,
	extu_w_M_1001_N_0000,
	exts_b_M_1001_N_0000,
	exts_w_M_1001_N_0000,
	load_rm_rn_b_M_1010_N_0000,
	load_rm_rn_w_M_1010_N_0000,
	load_rm_rn_l_M_1010_N_0000,
	mov_rm_rn_M_1010_N_0000,
	load_postinc_rm_rn_b_M_1010_N_0000,
	load_postinc_rm_rn_w_M_1010_N_0000,
	load_postinc_rm_rn_l_M_1010_N_0000,
	not_M_1010_N_0000,
	swap_b_M_1010_N_0000,
	swap_w_M_1010_N_0000,
	negc_M_1010_N_0000,
	neg_M_1010_N_0000,
	extu_b_M_1010_N_0000,
	extu_w_M_1010_N_0000,
	exts_b_M_1010_N_0000,
	exts_w_M_1010_N_0000,
	load_rm_rn_b_M_1011_N_0000,
	load_rm_rn_w_M_1011_N_0000,
	load_rm_rn_l_M_1011_N_0000,
	mov_rm_rn_M_1011_N_0000,
	load_postinc_rm_rn_b_M_1011_N_0000,
	load_postinc_rm_rn_w_M_1011_N_0000,
	load_postinc_rm_rn_l_M_1011_N_0000,
	not_M_1011_N_0000,
	swap_b_M_1011_N_0000,
	swap_w_M_1011_N_0000,
	negc_M_1011_N_0000,
	neg_M_1011_N_0000,
	extu_b_M_1011_N_0000,
	extu_w_M_1011_N_0000,
	exts_b_M_1011_N_0000,
	exts_w_M_1011_N_0000,
	load_rm_rn_b_M_1100_N_0000,
	load_rm_rn_w_M_1100_N_0000,
	load_rm_rn_l_M_1100_N_0000,
	mov_rm_rn_M_1100_N_0000,
	load_postinc_rm_rn_b_M_1100_N_0000,
	load_postinc_rm_rn_w_M_1100_N_0000,
	load_postinc_rm_rn_l_M_1100_N_0000,
	not_M_1100_N_0000,
	swap_b_M_1100_N_0000,
	swap_w_M_1100_N_0000,
	negc_M_1100_N_0000,
	neg_M_1100_N_0000,
	extu_b_M_1100_N_0000,
	extu_w_M_1100_N_0000,
	exts_b_M_1100_N_0000,
	exts_w_M_1100_N_0000,
	load_rm_rn_b_M_1101_N_0000,
	load_rm_rn_w_M_1101_N_0000,
	load_rm_rn_l_M_1101_N_0000,
	mov_rm_rn_M_1101_N_0000,
	load_postinc_rm_rn_b_M_1101_N_0000,
	load_postinc_rm_rn_w_M_1101_N_0000,
	load_postinc_rm_rn_l_M_1101_N_0000,
	not_M_1101_N_0000,
	swap_b_M_1101_N_0000,
	swap_w_M_1101_N_0000,
	negc_M_1101_N_0000,
	neg_M_1101_N_0000,
	extu_b_M_1101_N_0000,
	extu_w_M_1101_N_0000,
	exts_b_M_1101_N_0000,
	exts_w_M_1101_N_0000,
	load_rm_rn_b_M_1110_N_0000,
	load_rm_rn_w_M_1110_N_0000,
	load_rm_rn_l_M_1110_N_0000,
	mov_rm_rn_M_1110_N_0000,
	load_postinc_rm_rn_b_M_1110_N_0000,
	load_postinc_rm_rn_w_M_1110_N_0000,
	load_postinc_rm_rn_l_M_1110_N_0000,
	not_M_1110_N_0000,
	swap_b_M_1110_N_0000,
	swap_w_M_1110_N_0000,
	negc_M_1110_N_0000,
	neg_M_1110_N_0000,
	extu_b_M_1110_N_0000,
	extu_w_M_1110_N_0000,
	exts_b_M_1110_N_0000,
	exts_w_M_1110_N_0000,
	load_rm_rn_b_M_1111_N_0000,
	load_rm_rn_w_M_1111_N_0000,
	load_rm_rn_l_M_1111_N_0000,
	mov_rm_rn_M_1111_N_0000,
	load_postinc_rm_rn_b_M_1111_N_0000,
	load_postinc_rm_rn_w_M_1111_N_0000,
	load_postinc_rm_rn_l_M_1111_N_0000,
	not_M_1111_N_0000,
	swap_b_M_1111_N_0000,
	swap_w_M_1111_N_0000,
	negc_M_1111_N_0000,
	neg_M_1111_N_0000,
	extu_b_M_1111_N_0000,
	extu_w_M_1111_N_0000,
	exts_b_M_1111_N_0000,
	exts_w_M_1111_N_0000,
	load_rm_rn_b_M_0000_N_0001,
	load_rm_rn_w_M_0000_N_0001,
	load_rm_rn_l_M_0000_N_0001,
	mov_rm_rn_M_0000_N_0001,
	load_postinc_rm_rn_b_M_0000_N_0001,
	load_postinc_rm_rn_w_M_0000_N_0001,
	load_postinc_rm_rn_l_M_0000_N_0001,
	not_M_0000_N_0001,
	swap_b_M_0000_N_0001,
	swap_w_M_0000_N_0001,
	negc_M_0000_N_0001,
	neg_M_0000_N_0001,
	extu_b_M_0000_N_0001,
	extu_w_M_0000_N_0001,
	exts_b_M_0000_N_0001,
	exts_w_M_0000_N_0001,
	load_rm_rn_b_M_0001_N_0001,
	load_rm_rn_w_M_0001_N_0001,
	load_rm_rn_l_M_0001_N_0001,
	mov_rm_rn_M_0001_N_0001,
	load_postinc_rm_rn_b_M_0001_N_0001,
	load_postinc_rm_rn_w_M_0001_N_0001,
	load_postinc_rm_rn_l_M_0001_N_0001,
	not_M_0001_N_0001,
	swap_b_M_0001_N_0001,
	swap_w_M_0001_N_0001,
	negc_M_0001_N_0001,
	neg_M_0001_N_0001,
	extu_b_M_0001_N_0001,
	extu_w_M_0001_N_0001,
	exts_b_M_0001_N_0001,
	exts_w_M_0001_N_0001,
	load_rm_rn_b_M_0010_N_0001,
	load_rm_rn_w_M_0010_N_0001,
	load_rm_rn_l_M_0010_N_0001,
	mov_rm_rn_M_0010_N_0001,
	load_postinc_rm_rn_b_M_0010_N_0001,
	load_postinc_rm_rn_w_M_0010_N_0001,
	load_postinc_rm_rn_l_M_0010_N_0001,
	not_M_0010_N_0001,
	swap_b_M_0010_N_0001,
	swap_w_M_0010_N_0001,
	negc_M_0010_N_0001,
	neg_M_0010_N_0001,
	extu_b_M_0010_N_0001,
	extu_w_M_0010_N_0001,
	exts_b_M_0010_N_0001,
	exts_w_M_0010_N_0001,
	load_rm_rn_b_M_0011_N_0001,
	load_rm_rn_w_M_0011_N_0001,
	load_rm_rn_l_M_0011_N_0001,
	mov_rm_rn_M_0011_N_0001,
	load_postinc_rm_rn_b_M_0011_N_0001,
	load_postinc_rm_rn_w_M_0011_N_0001,
	load_postinc_rm_rn_l_M_0011_N_0001,
	not_M_0011_N_0001,
	swap_b_M_0011_N_0001,
	swap_w_M_0011_N_0001,
	negc_M_0011_N_0001,
	neg_M_0011_N_0001,
	extu_b_M_0011_N_0001,
	extu_w_M_0011_N_0001,
	exts_b_M_0011_N_0001,
	exts_w_M_0011_N_0001,
	load_rm_rn_b_M_0100_N_0001,
	load_rm_rn_w_M_0100_N_0001,
	load_rm_rn_l_M_0100_N_0001,
	mov_rm_rn_M_0100_N_0001,
	load_postinc_rm_rn_b_M_0100_N_0001,
	load_postinc_rm_rn_w_M_0100_N_0001,
	load_postinc_rm_rn_l_M_0100_N_0001,
	not_M_0100_N_0001,
	swap_b_M_0100_N_0001,
	swap_w_M_0100_N_0001,
	negc_M_0100_N_0001,
	neg_M_0100_N_0001,
	extu_b_M_0100_N_0001,
	extu_w_M_0100_N_0001,
	exts_b_M_0100_N_0001,
	exts_w_M_0100_N_0001,
	load_rm_rn_b_M_0101_N_0001,
	load_rm_rn_w_M_0101_N_0001,
	load_rm_rn_l_M_0101_N_0001,
	mov_rm_rn_M_0101_N_0001,
	load_postinc_rm_rn_b_M_0101_N_0001,
	load_postinc_rm_rn_w_M_0101_N_0001,
	load_postinc_rm_rn_l_M_0101_N_0001,
	not_M_0101_N_0001,
	swap_b_M_0101_N_0001,
	swap_w_M_0101_N_0001,
	negc_M_0101_N_0001,
	neg_M_0101_N_0001,
	extu_b_M_0101_N_0001,
	extu_w_M_0101_N_0001,
	exts_b_M_0101_N_0001,
	exts_w_M_0101_N_0001,
	load_rm_rn_b_M_0110_N_0001,
	load_rm_rn_w_M_0110_N_0001,
	load_rm_rn_l_M_0110_N_0001,
	mov_rm_rn_M_0110_N_0001,
	load_postinc_rm_rn_b_M_0110_N_0001,
	load_postinc_rm_rn_w_M_0110_N_0001,
	load_postinc_rm_rn_l_M_0110_N_0001,
	not_M_0110_N_0001,
	swap_b_M_0110_N_0001,
	swap_w_M_0110_N_0001,
	negc_M_0110_N_0001,
	neg_M_0110_N_0001,
	extu_b_M_0110_N_0001,
	extu_w_M_0110_N_0001,
	exts_b_M_0110_N_0001,
	exts_w_M_0110_N_0001,
	load_rm_rn_b_M_0111_N_0001,
	load_rm_rn_w_M_0111_N_0001,
	load_rm_rn_l_M_0111_N_0001,
	mov_rm_rn_M_0111_N_0001,
	load_postinc_rm_rn_b_M_0111_N_0001,
	load_postinc_rm_rn_w_M_0111_N_0001,
	load_postinc_rm_rn_l_M_0111_N_0001,
	not_M_0111_N_0001,
	swap_b_M_0111_N_0001,
	swap_w_M_0111_N_0001,
	negc_M_0111_N_0001,
	neg_M_0111_N_0001,
	extu_b_M_0111_N_0001,
	extu_w_M_0111_N_0001,
	exts_b_M_0111_N_0001,
	exts_w_M_0111_N_0001,
	load_rm_rn_b_M_1000_N_0001,
	load_rm_rn_w_M_1000_N_0001,
	load_rm_rn_l_M_1000_N_0001,
	mov_rm_rn_M_1000_N_0001,
	load_postinc_rm_rn_b_M_1000_N_0001,
	load_postinc_rm_rn_w_M_1000_N_0001,
	load_postinc_rm_rn_l_M_1000_N_0001,
	not_M_1000_N_0001,
	swap_b_M_1000_N_0001,
	swap_w_M_1000_N_0001,
	negc_M_1000_N_0001,
	neg_M_1000_N_0001,
	extu_b_M_1000_N_0001,
	extu_w_M_1000_N_0001,
	exts_b_M_1000_N_0001,
	exts_w_M_1000_N_0001,
	load_rm_rn_b_M_1001_N_0001,
	load_rm_rn_w_M_1001_N_0001,
	load_rm_rn_l_M_1001_N_0001,
	mov_rm_rn_M_1001_N_0001,
	load_postinc_rm_rn_b_M_1001_N_0001,
	load_postinc_rm_rn_w_M_1001_N_0001,
	load_postinc_rm_rn_l_M_1001_N_0001,
	not_M_1001_N_0001,
	swap_b_M_1001_N_0001,
	swap_w_M_1001_N_0001,
	negc_M_1001_N_0001,
	neg_M_1001_N_0001,
	extu_b_M_1001_N_0001,
	extu_w_M_1001_N_0001,
	exts_b_M_1001_N_0001,
	exts_w_M_1001_N_0001,
	load_rm_rn_b_M_1010_N_0001,
	load_rm_rn_w_M_1010_N_0001,
	load_rm_rn_l_M_1010_N_0001,
	mov_rm_rn_M_1010_N_0001,
	load_postinc_rm_rn_b_M_1010_N_0001,
	load_postinc_rm_rn_w_M_1010_N_0001,
	load_postinc_rm_rn_l_M_1010_N_0001,
	not_M_1010_N_0001,
	swap_b_M_1010_N_0001,
	swap_w_M_1010_N_0001,
	negc_M_1010_N_0001,
	neg_M_1010_N_0001,
	extu_b_M_1010_N_0001,
	extu_w_M_1010_N_0001,
	exts_b_M_1010_N_0001,
	exts_w_M_1010_N_0001,
	load_rm_rn_b_M_1011_N_0001,
	load_rm_rn_w_M_1011_N_0001,
	load_rm_rn_l_M_1011_N_0001,
	mov_rm_rn_M_1011_N_0001,
	load_postinc_rm_rn_b_M_1011_N_0001,
	load_postinc_rm_rn_w_M_1011_N_0001,
	load_postinc_rm_rn_l_M_1011_N_0001,
	not_M_1011_N_0001,
	swap_b_M_1011_N_0001,
	swap_w_M_1011_N_0001,
	negc_M_1011_N_0001,
	neg_M_1011_N_0001,
	extu_b_M_1011_N_0001,
	extu_w_M_1011_N_0001,
	exts_b_M_1011_N_0001,
	exts_w_M_1011_N_0001,
	load_rm_rn_b_M_1100_N_0001,
	load_rm_rn_w_M_1100_N_0001,
	load_rm_rn_l_M_1100_N_0001,
	mov_rm_rn_M_1100_N_0001,
	load_postinc_rm_rn_b_M_1100_N_0001,
	load_postinc_rm_rn_w_M_1100_N_0001,
	load_postinc_rm_rn_l_M_1100_N_0001,
	not_M_1100_N_0001,
	swap_b_M_1100_N_0001,
	swap_w_M_1100_N_0001,
	negc_M_1100_N_0001,
	neg_M_1100_N_0001,
	extu_b_M_1100_N_0001,
	extu_w_M_1100_N_0001,
	exts_b_M_1100_N_0001,
	exts_w_M_1100_N_0001,
	load_rm_rn_b_M_1101_N_0001,
	load_rm_rn_w_M_1101_N_0001,
	load_rm_rn_l_M_1101_N_0001,
	mov_rm_rn_M_1101_N_0001,
	load_postinc_rm_rn_b_M_1101_N_0001,
	load_postinc_rm_rn_w_M_1101_N_0001,
	load_postinc_rm_rn_l_M_1101_N_0001,
	not_M_1101_N_0001,
	swap_b_M_1101_N_0001,
	swap_w_M_1101_N_0001,
	negc_M_1101_N_0001,
	neg_M_1101_N_0001,
	extu_b_M_1101_N_0001,
	extu_w_M_1101_N_0001,
	exts_b_M_1101_N_0001,
	exts_w_M_1101_N_0001,
	load_rm_rn_b_M_1110_N_0001,
	load_rm_rn_w_M_1110_N_0001,
	load_rm_rn_l_M_1110_N_0001,
	mov_rm_rn_M_1110_N_0001,
	load_postinc_rm_rn_b_M_1110_N_0001,
	load_postinc_rm_rn_w_M_1110_N_0001,
	load_postinc_rm_rn_l_M_1110_N_0001,
	not_M_1110_N_0001,
	swap_b_M_1110_N_0001,
	swap_w_M_1110_N_0001,
	negc_M_1110_N_0001,
	neg_M_1110_N_0001,
	extu_b_M_1110_N_0001,
	extu_w_M_1110_N_0001,
	exts_b_M_1110_N_0001,
	exts_w_M_1110_N_0001,
	load_rm_rn_b_M_1111_N_0001,
	load_rm_rn_w_M_1111_N_0001,
	load_rm_rn_l_M_1111_N_0001,
	mov_rm_rn_M_1111_N_0001,
	load_postinc_rm_rn_b_M_1111_N_0001,
	load_postinc_rm_rn_w_M_1111_N_0001,
	load_postinc_rm_rn_l_M_1111_N_0001,
	not_M_1111_N_0001,
	swap_b_M_1111_N_0001,
	swap_w_M_1111_N_0001,
	negc_M_1111_N_0001,
	neg_M_1111_N_0001,
	extu_b_M_1111_N_0001,
	extu_w_M_1111_N_0001,
	exts_b_M_1111_N_0001,
	exts_w_M_1111_N_0001,
	load_rm_rn_b_M_0000_N_0010,
	load_rm_rn_w_M_0000_N_0010,
	load_rm_rn_l_M_0000_N_0010,
	mov_rm_rn_M_0000_N_0010,
	load_postinc_rm_rn_b_M_0000_N_0010,
	load_postinc_rm_rn_w_M_0000_N_0010,
	load_postinc_rm_rn_l_M_0000_N_0010,
	not_M_0000_N_0010,
	swap_b_M_0000_N_0010,
	swap_w_M_0000_N_0010,
	negc_M_0000_N_0010,
	neg_M_0000_N_0010,
	extu_b_M_0000_N_0010,
	extu_w_M_0000_N_0010,
	exts_b_M_0000_N_0010,
	exts_w_M_0000_N_0010,
	load_rm_rn_b_M_0001_N_0010,
	load_rm_rn_w_M_0001_N_0010,
	load_rm_rn_l_M_0001_N_0010,
	mov_rm_rn_M_0001_N_0010,
	load_postinc_rm_rn_b_M_0001_N_0010,
	load_postinc_rm_rn_w_M_0001_N_0010,
	load_postinc_rm_rn_l_M_0001_N_0010,
	not_M_0001_N_0010,
	swap_b_M_0001_N_0010,
	swap_w_M_0001_N_0010,
	negc_M_0001_N_0010,
	neg_M_0001_N_0010,
	extu_b_M_0001_N_0010,
	extu_w_M_0001_N_0010,
	exts_b_M_0001_N_0010,
	exts_w_M_0001_N_0010,
	load_rm_rn_b_M_0010_N_0010,
	load_rm_rn_w_M_0010_N_0010,
	load_rm_rn_l_M_0010_N_0010,
	mov_rm_rn_M_0010_N_0010,
	load_postinc_rm_rn_b_M_0010_N_0010,
	load_postinc_rm_rn_w_M_0010_N_0010,
	load_postinc_rm_rn_l_M_0010_N_0010,
	not_M_0010_N_0010,
	swap_b_M_0010_N_0010,
	swap_w_M_0010_N_0010,
	negc_M_0010_N_0010,
	neg_M_0010_N_0010,
	extu_b_M_0010_N_0010,
	extu_w_M_0010_N_0010,
	exts_b_M_0010_N_0010,
	exts_w_M_0010_N_0010,
	load_rm_rn_b_M_0011_N_0010,
	load_rm_rn_w_M_0011_N_0010,
	load_rm_rn_l_M_0011_N_0010,
	mov_rm_rn_M_0011_N_0010,
	load_postinc_rm_rn_b_M_0011_N_0010,
	load_postinc_rm_rn_w_M_0011_N_0010,
	load_postinc_rm_rn_l_M_0011_N_0010,
	not_M_0011_N_0010,
	swap_b_M_0011_N_0010,
	swap_w_M_0011_N_0010,
	negc_M_0011_N_0010,
	neg_M_0011_N_0010,
	extu_b_M_0011_N_0010,
	extu_w_M_0011_N_0010,
	exts_b_M_0011_N_0010,
	exts_w_M_0011_N_0010,
	load_rm_rn_b_M_0100_N_0010,
	load_rm_rn_w_M_0100_N_0010,
	load_rm_rn_l_M_0100_N_0010,
	mov_rm_rn_M_0100_N_0010,
	load_postinc_rm_rn_b_M_0100_N_0010,
	load_postinc_rm_rn_w_M_0100_N_0010,
	load_postinc_rm_rn_l_M_0100_N_0010,
	not_M_0100_N_0010,
	swap_b_M_0100_N_0010,
	swap_w_M_0100_N_0010,
	negc_M_0100_N_0010,
	neg_M_0100_N_0010,
	extu_b_M_0100_N_0010,
	extu_w_M_0100_N_0010,
	exts_b_M_0100_N_0010,
	exts_w_M_0100_N_0010,
	load_rm_rn_b_M_0101_N_0010,
	load_rm_rn_w_M_0101_N_0010,
	load_rm_rn_l_M_0101_N_0010,
	mov_rm_rn_M_0101_N_0010,
	load_postinc_rm_rn_b_M_0101_N_0010,
	load_postinc_rm_rn_w_M_0101_N_0010,
	load_postinc_rm_rn_l_M_0101_N_0010,
	not_M_0101_N_0010,
	swap_b_M_0101_N_0010,
	swap_w_M_0101_N_0010,
	negc_M_0101_N_0010,
	neg_M_0101_N_0010,
	extu_b_M_0101_N_0010,
	extu_w_M_0101_N_0010,
	exts_b_M_0101_N_0010,
	exts_w_M_0101_N_0010,
	load_rm_rn_b_M_0110_N_0010,
	load_rm_rn_w_M_0110_N_0010,
	load_rm_rn_l_M_0110_N_0010,
	mov_rm_rn_M_0110_N_0010,
	load_postinc_rm_rn_b_M_0110_N_0010,
	load_postinc_rm_rn_w_M_0110_N_0010,
	load_postinc_rm_rn_l_M_0110_N_0010,
	not_M_0110_N_0010,
	swap_b_M_0110_N_0010,
	swap_w_M_0110_N_0010,
	negc_M_0110_N_0010,
	neg_M_0110_N_0010,
	extu_b_M_0110_N_0010,
	extu_w_M_0110_N_0010,
	exts_b_M_0110_N_0010,
	exts_w_M_0110_N_0010,
	load_rm_rn_b_M_0111_N_0010,
	load_rm_rn_w_M_0111_N_0010,
	load_rm_rn_l_M_0111_N_0010,
	mov_rm_rn_M_0111_N_0010,
	load_postinc_rm_rn_b_M_0111_N_0010,
	load_postinc_rm_rn_w_M_0111_N_0010,
	load_postinc_rm_rn_l_M_0111_N_0010,
	not_M_0111_N_0010,
	swap_b_M_0111_N_0010,
	swap_w_M_0111_N_0010,
	negc_M_0111_N_0010,
	neg_M_0111_N_0010,
	extu_b_M_0111_N_0010,
	extu_w_M_0111_N_0010,
	exts_b_M_0111_N_0010,
	exts_w_M_0111_N_0010,
	load_rm_rn_b_M_1000_N_0010,
	load_rm_rn_w_M_1000_N_0010,
	load_rm_rn_l_M_1000_N_0010,
	mov_rm_rn_M_1000_N_0010,
	load_postinc_rm_rn_b_M_1000_N_0010,
	load_postinc_rm_rn_w_M_1000_N_0010,
	load_postinc_rm_rn_l_M_1000_N_0010,
	not_M_1000_N_0010,
	swap_b_M_1000_N_0010,
	swap_w_M_1000_N_0010,
	negc_M_1000_N_0010,
	neg_M_1000_N_0010,
	extu_b_M_1000_N_0010,
	extu_w_M_1000_N_0010,
	exts_b_M_1000_N_0010,
	exts_w_M_1000_N_0010,
	load_rm_rn_b_M_1001_N_0010,
	load_rm_rn_w_M_1001_N_0010,
	load_rm_rn_l_M_1001_N_0010,
	mov_rm_rn_M_1001_N_0010,
	load_postinc_rm_rn_b_M_1001_N_0010,
	load_postinc_rm_rn_w_M_1001_N_0010,
	load_postinc_rm_rn_l_M_1001_N_0010,
	not_M_1001_N_0010,
	swap_b_M_1001_N_0010,
	swap_w_M_1001_N_0010,
	negc_M_1001_N_0010,
	neg_M_1001_N_0010,
	extu_b_M_1001_N_0010,
	extu_w_M_1001_N_0010,
	exts_b_M_1001_N_0010,
	exts_w_M_1001_N_0010,
	load_rm_rn_b_M_1010_N_0010,
	load_rm_rn_w_M_1010_N_0010,
	load_rm_rn_l_M_1010_N_0010,
	mov_rm_rn_M_1010_N_0010,
	load_postinc_rm_rn_b_M_1010_N_0010,
	load_postinc_rm_rn_w_M_1010_N_0010,
	load_postinc_rm_rn_l_M_1010_N_0010,
	not_M_1010_N_0010,
	swap_b_M_1010_N_0010,
	swap_w_M_1010_N_0010,
	negc_M_1010_N_0010,
	neg_M_1010_N_0010,
	extu_b_M_1010_N_0010,
	extu_w_M_1010_N_0010,
	exts_b_M_1010_N_0010,
	exts_w_M_1010_N_0010,
	load_rm_rn_b_M_1011_N_0010,
	load_rm_rn_w_M_1011_N_0010,
	load_rm_rn_l_M_1011_N_0010,
	mov_rm_rn_M_1011_N_0010,
	load_postinc_rm_rn_b_M_1011_N_0010,
	load_postinc_rm_rn_w_M_1011_N_0010,
	load_postinc_rm_rn_l_M_1011_N_0010,
	not_M_1011_N_0010,
	swap_b_M_1011_N_0010,
	swap_w_M_1011_N_0010,
	negc_M_1011_N_0010,
	neg_M_1011_N_0010,
	extu_b_M_1011_N_0010,
	extu_w_M_1011_N_0010,
	exts_b_M_1011_N_0010,
	exts_w_M_1011_N_0010,
	load_rm_rn_b_M_1100_N_0010,
	load_rm_rn_w_M_1100_N_0010,
	load_rm_rn_l_M_1100_N_0010,
	mov_rm_rn_M_1100_N_0010,
	load_postinc_rm_rn_b_M_1100_N_0010,
	load_postinc_rm_rn_w_M_1100_N_0010,
	load_postinc_rm_rn_l_M_1100_N_0010,
	not_M_1100_N_0010,
	swap_b_M_1100_N_0010,
	swap_w_M_1100_N_0010,
	negc_M_1100_N_0010,
	neg_M_1100_N_0010,
	extu_b_M_1100_N_0010,
	extu_w_M_1100_N_0010,
	exts_b_M_1100_N_0010,
	exts_w_M_1100_N_0010,
	load_rm_rn_b_M_1101_N_0010,
	load_rm_rn_w_M_1101_N_0010,
	load_rm_rn_l_M_1101_N_0010,
	mov_rm_rn_M_1101_N_0010,
	load_postinc_rm_rn_b_M_1101_N_0010,
	load_postinc_rm_rn_w_M_1101_N_0010,
	load_postinc_rm_rn_l_M_1101_N_0010,
	not_M_1101_N_0010,
	swap_b_M_1101_N_0010,
	swap_w_M_1101_N_0010,
	negc_M_1101_N_0010,
	neg_M_1101_N_0010,
	extu_b_M_1101_N_0010,
	extu_w_M_1101_N_0010,
	exts_b_M_1101_N_0010,
	exts_w_M_1101_N_0010,
	load_rm_rn_b_M_1110_N_0010,
	load_rm_rn_w_M_1110_N_0010,
	load_rm_rn_l_M_1110_N_0010,
	mov_rm_rn_M_1110_N_0010,
	load_postinc_rm_rn_b_M_1110_N_0010,
	load_postinc_rm_rn_w_M_1110_N_0010,
	load_postinc_rm_rn_l_M_1110_N_0010,
	not_M_1110_N_0010,
	swap_b_M_1110_N_0010,
	swap_w_M_1110_N_0010,
	negc_M_1110_N_0010,
	neg_M_1110_N_0010,
	extu_b_M_1110_N_0010,
	extu_w_M_1110_N_0010,
	exts_b_M_1110_N_0010,
	exts_w_M_1110_N_0010,
	load_rm_rn_b_M_1111_N_0010,
	load_rm_rn_w_M_1111_N_0010,
	load_rm_rn_l_M_1111_N_0010,
	mov_rm_rn_M_1111_N_0010,
	load_postinc_rm_rn_b_M_1111_N_0010,
	load_postinc_rm_rn_w_M_1111_N_0010,
	load_postinc_rm_rn_l_M_1111_N_0010,
	not_M_1111_N_0010,
	swap_b_M_1111_N_0010,
	swap_w_M_1111_N_0010,
	negc_M_1111_N_0010,
	neg_M_1111_N_0010,
	extu_b_M_1111_N_0010,
	extu_w_M_1111_N_0010,
	exts_b_M_1111_N_0010,
	exts_w_M_1111_N_0010,
	load_rm_rn_b_M_0000_N_0011,
	load_rm_rn_w_M_0000_N_0011,
	load_rm_rn_l_M_0000_N_0011,
	mov_rm_rn_M_0000_N_0011,
	load_postinc_rm_rn_b_M_0000_N_0011,
	load_postinc_rm_rn_w_M_0000_N_0011,
	load_postinc_rm_rn_l_M_0000_N_0011,
	not_M_0000_N_0011,
	swap_b_M_0000_N_0011,
	swap_w_M_0000_N_0011,
	negc_M_0000_N_0011,
	neg_M_0000_N_0011,
	extu_b_M_0000_N_0011,
	extu_w_M_0000_N_0011,
	exts_b_M_0000_N_0011,
	exts_w_M_0000_N_0011,
	load_rm_rn_b_M_0001_N_0011,
	load_rm_rn_w_M_0001_N_0011,
	load_rm_rn_l_M_0001_N_0011,
	mov_rm_rn_M_0001_N_0011,
	load_postinc_rm_rn_b_M_0001_N_0011,
	load_postinc_rm_rn_w_M_0001_N_0011,
	load_postinc_rm_rn_l_M_0001_N_0011,
	not_M_0001_N_0011,
	swap_b_M_0001_N_0011,
	swap_w_M_0001_N_0011,
	negc_M_0001_N_0011,
	neg_M_0001_N_0011,
	extu_b_M_0001_N_0011,
	extu_w_M_0001_N_0011,
	exts_b_M_0001_N_0011,
	exts_w_M_0001_N_0011,
	load_rm_rn_b_M_0010_N_0011,
	load_rm_rn_w_M_0010_N_0011,
	load_rm_rn_l_M_0010_N_0011,
	mov_rm_rn_M_0010_N_0011,
	load_postinc_rm_rn_b_M_0010_N_0011,
	load_postinc_rm_rn_w_M_0010_N_0011,
	load_postinc_rm_rn_l_M_0010_N_0011,
	not_M_0010_N_0011,
	swap_b_M_0010_N_0011,
	swap_w_M_0010_N_0011,
	negc_M_0010_N_0011,
	neg_M_0010_N_0011,
	extu_b_M_0010_N_0011,
	extu_w_M_0010_N_0011,
	exts_b_M_0010_N_0011,
	exts_w_M_0010_N_0011,
	load_rm_rn_b_M_0011_N_0011,
	load_rm_rn_w_M_0011_N_0011,
	load_rm_rn_l_M_0011_N_0011,
	mov_rm_rn_M_0011_N_0011,
	load_postinc_rm_rn_b_M_0011_N_0011,
	load_postinc_rm_rn_w_M_0011_N_0011,
	load_postinc_rm_rn_l_M_0011_N_0011,
	not_M_0011_N_0011,
	swap_b_M_0011_N_0011,
	swap_w_M_0011_N_0011,
	negc_M_0011_N_0011,
	neg_M_0011_N_0011,
	extu_b_M_0011_N_0011,
	extu_w_M_0011_N_0011,
	exts_b_M_0011_N_0011,
	exts_w_M_0011_N_0011,
	load_rm_rn_b_M_0100_N_0011,
	load_rm_rn_w_M_0100_N_0011,
	load_rm_rn_l_M_0100_N_0011,
	mov_rm_rn_M_0100_N_0011,
	load_postinc_rm_rn_b_M_0100_N_0011,
	load_postinc_rm_rn_w_M_0100_N_0011,
	load_postinc_rm_rn_l_M_0100_N_0011,
	not_M_0100_N_0011,
	swap_b_M_0100_N_0011,
	swap_w_M_0100_N_0011,
	negc_M_0100_N_0011,
	neg_M_0100_N_0011,
	extu_b_M_0100_N_0011,
	extu_w_M_0100_N_0011,
	exts_b_M_0100_N_0011,
	exts_w_M_0100_N_0011,
	load_rm_rn_b_M_0101_N_0011,
	load_rm_rn_w_M_0101_N_0011,
	load_rm_rn_l_M_0101_N_0011,
	mov_rm_rn_M_0101_N_0011,
	load_postinc_rm_rn_b_M_0101_N_0011,
	load_postinc_rm_rn_w_M_0101_N_0011,
	load_postinc_rm_rn_l_M_0101_N_0011,
	not_M_0101_N_0011,
	swap_b_M_0101_N_0011,
	swap_w_M_0101_N_0011,
	negc_M_0101_N_0011,
	neg_M_0101_N_0011,
	extu_b_M_0101_N_0011,
	extu_w_M_0101_N_0011,
	exts_b_M_0101_N_0011,
	exts_w_M_0101_N_0011,
	load_rm_rn_b_M_0110_N_0011,
	load_rm_rn_w_M_0110_N_0011,
	load_rm_rn_l_M_0110_N_0011,
	mov_rm_rn_M_0110_N_0011,
	load_postinc_rm_rn_b_M_0110_N_0011,
	load_postinc_rm_rn_w_M_0110_N_0011,
	load_postinc_rm_rn_l_M_0110_N_0011,
	not_M_0110_N_0011,
	swap_b_M_0110_N_0011,
	swap_w_M_0110_N_0011,
	negc_M_0110_N_0011,
	neg_M_0110_N_0011,
	extu_b_M_0110_N_0011,
	extu_w_M_0110_N_0011,
	exts_b_M_0110_N_0011,
	exts_w_M_0110_N_0011,
	load_rm_rn_b_M_0111_N_0011,
	load_rm_rn_w_M_0111_N_0011,
	load_rm_rn_l_M_0111_N_0011,
	mov_rm_rn_M_0111_N_0011,
	load_postinc_rm_rn_b_M_0111_N_0011,
	load_postinc_rm_rn_w_M_0111_N_0011,
	load_postinc_rm_rn_l_M_0111_N_0011,
	not_M_0111_N_0011,
	swap_b_M_0111_N_0011,
	swap_w_M_0111_N_0011,
	negc_M_0111_N_0011,
	neg_M_0111_N_0011,
	extu_b_M_0111_N_0011,
	extu_w_M_0111_N_0011,
	exts_b_M_0111_N_0011,
	exts_w_M_0111_N_0011,
	load_rm_rn_b_M_1000_N_0011,
	load_rm_rn_w_M_1000_N_0011,
	load_rm_rn_l_M_1000_N_0011,
	mov_rm_rn_M_1000_N_0011,
	load_postinc_rm_rn_b_M_1000_N_0011,
	load_postinc_rm_rn_w_M_1000_N_0011,
	load_postinc_rm_rn_l_M_1000_N_0011,
	not_M_1000_N_0011,
	swap_b_M_1000_N_0011,
	swap_w_M_1000_N_0011,
	negc_M_1000_N_0011,
	neg_M_1000_N_0011,
	extu_b_M_1000_N_0011,
	extu_w_M_1000_N_0011,
	exts_b_M_1000_N_0011,
	exts_w_M_1000_N_0011,
	load_rm_rn_b_M_1001_N_0011,
	load_rm_rn_w_M_1001_N_0011,
	load_rm_rn_l_M_1001_N_0011,
	mov_rm_rn_M_1001_N_0011,
	load_postinc_rm_rn_b_M_1001_N_0011,
	load_postinc_rm_rn_w_M_1001_N_0011,
	load_postinc_rm_rn_l_M_1001_N_0011,
	not_M_1001_N_0011,
	swap_b_M_1001_N_0011,
	swap_w_M_1001_N_0011,
	negc_M_1001_N_0011,
	neg_M_1001_N_0011,
	extu_b_M_1001_N_0011,
	extu_w_M_1001_N_0011,
	exts_b_M_1001_N_0011,
	exts_w_M_1001_N_0011,
	load_rm_rn_b_M_1010_N_0011,
	load_rm_rn_w_M_1010_N_0011,
	load_rm_rn_l_M_1010_N_0011,
	mov_rm_rn_M_1010_N_0011,
	load_postinc_rm_rn_b_M_1010_N_0011,
	load_postinc_rm_rn_w_M_1010_N_0011,
	load_postinc_rm_rn_l_M_1010_N_0011,
	not_M_1010_N_0011,
	swap_b_M_1010_N_0011,
	swap_w_M_1010_N_0011,
	negc_M_1010_N_0011,
	neg_M_1010_N_0011,
	extu_b_M_1010_N_0011,
	extu_w_M_1010_N_0011,
	exts_b_M_1010_N_0011,
	exts_w_M_1010_N_0011,
	load_rm_rn_b_M_1011_N_0011,
	load_rm_rn_w_M_1011_N_0011,
	load_rm_rn_l_M_1011_N_0011,
	mov_rm_rn_M_1011_N_0011,
	load_postinc_rm_rn_b_M_1011_N_0011,
	load_postinc_rm_rn_w_M_1011_N_0011,
	load_postinc_rm_rn_l_M_1011_N_0011,
	not_M_1011_N_0011,
	swap_b_M_1011_N_0011,
	swap_w_M_1011_N_0011,
	negc_M_1011_N_0011,
	neg_M_1011_N_0011,
	extu_b_M_1011_N_0011,
	extu_w_M_1011_N_0011,
	exts_b_M_1011_N_0011,
	exts_w_M_1011_N_0011,
	load_rm_rn_b_M_1100_N_0011,
	load_rm_rn_w_M_1100_N_0011,
	load_rm_rn_l_M_1100_N_0011,
	mov_rm_rn_M_1100_N_0011,
	load_postinc_rm_rn_b_M_1100_N_0011,
	load_postinc_rm_rn_w_M_1100_N_0011,
	load_postinc_rm_rn_l_M_1100_N_0011,
	not_M_1100_N_0011,
	swap_b_M_1100_N_0011,
	swap_w_M_1100_N_0011,
	negc_M_1100_N_0011,
	neg_M_1100_N_0011,
	extu_b_M_1100_N_0011,
	extu_w_M_1100_N_0011,
	exts_b_M_1100_N_0011,
	exts_w_M_1100_N_0011,
	load_rm_rn_b_M_1101_N_0011,
	load_rm_rn_w_M_1101_N_0011,
	load_rm_rn_l_M_1101_N_0011,
	mov_rm_rn_M_1101_N_0011,
	load_postinc_rm_rn_b_M_1101_N_0011,
	load_postinc_rm_rn_w_M_1101_N_0011,
	load_postinc_rm_rn_l_M_1101_N_0011,
	not_M_1101_N_0011,
	swap_b_M_1101_N_0011,
	swap_w_M_1101_N_0011,
	negc_M_1101_N_0011,
	neg_M_1101_N_0011,
	extu_b_M_1101_N_0011,
	extu_w_M_1101_N_0011,
	exts_b_M_1101_N_0011,
	exts_w_M_1101_N_0011,
	load_rm_rn_b_M_1110_N_0011,
	load_rm_rn_w_M_1110_N_0011,
	load_rm_rn_l_M_1110_N_0011,
	mov_rm_rn_M_1110_N_0011,
	load_postinc_rm_rn_b_M_1110_N_0011,
	load_postinc_rm_rn_w_M_1110_N_0011,
	load_postinc_rm_rn_l_M_1110_N_0011,
	not_M_1110_N_0011,
	swap_b_M_1110_N_0011,
	swap_w_M_1110_N_0011,
	negc_M_1110_N_0011,
	neg_M_1110_N_0011,
	extu_b_M_1110_N_0011,
	extu_w_M_1110_N_0011,
	exts_b_M_1110_N_0011,
	exts_w_M_1110_N_0011,
	load_rm_rn_b_M_1111_N_0011,
	load_rm_rn_w_M_1111_N_0011,
	load_rm_rn_l_M_1111_N_0011,
	mov_rm_rn_M_1111_N_0011,
	load_postinc_rm_rn_b_M_1111_N_0011,
	load_postinc_rm_rn_w_M_1111_N_0011,
	load_postinc_rm_rn_l_M_1111_N_0011,
	not_M_1111_N_0011,
	swap_b_M_1111_N_0011,
	swap_w_M_1111_N_0011,
	negc_M_1111_N_0011,
	neg_M_1111_N_0011,
	extu_b_M_1111_N_0011,
	extu_w_M_1111_N_0011,
	exts_b_M_1111_N_0011,
	exts_w_M_1111_N_0011,
	load_rm_rn_b_M_0000_N_0100,
	load_rm_rn_w_M_0000_N_0100,
	load_rm_rn_l_M_0000_N_0100,
	mov_rm_rn_M_0000_N_0100,
	load_postinc_rm_rn_b_M_0000_N_0100,
	load_postinc_rm_rn_w_M_0000_N_0100,
	load_postinc_rm_rn_l_M_0000_N_0100,
	not_M_0000_N_0100,
	swap_b_M_0000_N_0100,
	swap_w_M_0000_N_0100,
	negc_M_0000_N_0100,
	neg_M_0000_N_0100,
	extu_b_M_0000_N_0100,
	extu_w_M_0000_N_0100,
	exts_b_M_0000_N_0100,
	exts_w_M_0000_N_0100,
	load_rm_rn_b_M_0001_N_0100,
	load_rm_rn_w_M_0001_N_0100,
	load_rm_rn_l_M_0001_N_0100,
	mov_rm_rn_M_0001_N_0100,
	load_postinc_rm_rn_b_M_0001_N_0100,
	load_postinc_rm_rn_w_M_0001_N_0100,
	load_postinc_rm_rn_l_M_0001_N_0100,
	not_M_0001_N_0100,
	swap_b_M_0001_N_0100,
	swap_w_M_0001_N_0100,
	negc_M_0001_N_0100,
	neg_M_0001_N_0100,
	extu_b_M_0001_N_0100,
	extu_w_M_0001_N_0100,
	exts_b_M_0001_N_0100,
	exts_w_M_0001_N_0100,
	load_rm_rn_b_M_0010_N_0100,
	load_rm_rn_w_M_0010_N_0100,
	load_rm_rn_l_M_0010_N_0100,
	mov_rm_rn_M_0010_N_0100,
	load_postinc_rm_rn_b_M_0010_N_0100,
	load_postinc_rm_rn_w_M_0010_N_0100,
	load_postinc_rm_rn_l_M_0010_N_0100,
	not_M_0010_N_0100,
	swap_b_M_0010_N_0100,
	swap_w_M_0010_N_0100,
	negc_M_0010_N_0100,
	neg_M_0010_N_0100,
	extu_b_M_0010_N_0100,
	extu_w_M_0010_N_0100,
	exts_b_M_0010_N_0100,
	exts_w_M_0010_N_0100,
	load_rm_rn_b_M_0011_N_0100,
	load_rm_rn_w_M_0011_N_0100,
	load_rm_rn_l_M_0011_N_0100,
	mov_rm_rn_M_0011_N_0100,
	load_postinc_rm_rn_b_M_0011_N_0100,
	load_postinc_rm_rn_w_M_0011_N_0100,
	load_postinc_rm_rn_l_M_0011_N_0100,
	not_M_0011_N_0100,
	swap_b_M_0011_N_0100,
	swap_w_M_0011_N_0100,
	negc_M_0011_N_0100,
	neg_M_0011_N_0100,
	extu_b_M_0011_N_0100,
	extu_w_M_0011_N_0100,
	exts_b_M_0011_N_0100,
	exts_w_M_0011_N_0100,
	load_rm_rn_b_M_0100_N_0100,
	load_rm_rn_w_M_0100_N_0100,
	load_rm_rn_l_M_0100_N_0100,
	mov_rm_rn_M_0100_N_0100,
	load_postinc_rm_rn_b_M_0100_N_0100,
	load_postinc_rm_rn_w_M_0100_N_0100,
	load_postinc_rm_rn_l_M_0100_N_0100,
	not_M_0100_N_0100,
	swap_b_M_0100_N_0100,
	swap_w_M_0100_N_0100,
	negc_M_0100_N_0100,
	neg_M_0100_N_0100,
	extu_b_M_0100_N_0100,
	extu_w_M_0100_N_0100,
	exts_b_M_0100_N_0100,
	exts_w_M_0100_N_0100,
	load_rm_rn_b_M_0101_N_0100,
	load_rm_rn_w_M_0101_N_0100,
	load_rm_rn_l_M_0101_N_0100,
	mov_rm_rn_M_0101_N_0100,
	load_postinc_rm_rn_b_M_0101_N_0100,
	load_postinc_rm_rn_w_M_0101_N_0100,
	load_postinc_rm_rn_l_M_0101_N_0100,
	not_M_0101_N_0100,
	swap_b_M_0101_N_0100,
	swap_w_M_0101_N_0100,
	negc_M_0101_N_0100,
	neg_M_0101_N_0100,
	extu_b_M_0101_N_0100,
	extu_w_M_0101_N_0100,
	exts_b_M_0101_N_0100,
	exts_w_M_0101_N_0100,
	load_rm_rn_b_M_0110_N_0100,
	load_rm_rn_w_M_0110_N_0100,
	load_rm_rn_l_M_0110_N_0100,
	mov_rm_rn_M_0110_N_0100,
	load_postinc_rm_rn_b_M_0110_N_0100,
	load_postinc_rm_rn_w_M_0110_N_0100,
	load_postinc_rm_rn_l_M_0110_N_0100,
	not_M_0110_N_0100,
	swap_b_M_0110_N_0100,
	swap_w_M_0110_N_0100,
	negc_M_0110_N_0100,
	neg_M_0110_N_0100,
	extu_b_M_0110_N_0100,
	extu_w_M_0110_N_0100,
	exts_b_M_0110_N_0100,
	exts_w_M_0110_N_0100,
	load_rm_rn_b_M_0111_N_0100,
	load_rm_rn_w_M_0111_N_0100,
	load_rm_rn_l_M_0111_N_0100,
	mov_rm_rn_M_0111_N_0100,
	load_postinc_rm_rn_b_M_0111_N_0100,
	load_postinc_rm_rn_w_M_0111_N_0100,
	load_postinc_rm_rn_l_M_0111_N_0100,
	not_M_0111_N_0100,
	swap_b_M_0111_N_0100,
	swap_w_M_0111_N_0100,
	negc_M_0111_N_0100,
	neg_M_0111_N_0100,
	extu_b_M_0111_N_0100,
	extu_w_M_0111_N_0100,
	exts_b_M_0111_N_0100,
	exts_w_M_0111_N_0100,
	load_rm_rn_b_M_1000_N_0100,
	load_rm_rn_w_M_1000_N_0100,
	load_rm_rn_l_M_1000_N_0100,
	mov_rm_rn_M_1000_N_0100,
	load_postinc_rm_rn_b_M_1000_N_0100,
	load_postinc_rm_rn_w_M_1000_N_0100,
	load_postinc_rm_rn_l_M_1000_N_0100,
	not_M_1000_N_0100,
	swap_b_M_1000_N_0100,
	swap_w_M_1000_N_0100,
	negc_M_1000_N_0100,
	neg_M_1000_N_0100,
	extu_b_M_1000_N_0100,
	extu_w_M_1000_N_0100,
	exts_b_M_1000_N_0100,
	exts_w_M_1000_N_0100,
	load_rm_rn_b_M_1001_N_0100,
	load_rm_rn_w_M_1001_N_0100,
	load_rm_rn_l_M_1001_N_0100,
	mov_rm_rn_M_1001_N_0100,
	load_postinc_rm_rn_b_M_1001_N_0100,
	load_postinc_rm_rn_w_M_1001_N_0100,
	load_postinc_rm_rn_l_M_1001_N_0100,
	not_M_1001_N_0100,
	swap_b_M_1001_N_0100,
	swap_w_M_1001_N_0100,
	negc_M_1001_N_0100,
	neg_M_1001_N_0100,
	extu_b_M_1001_N_0100,
	extu_w_M_1001_N_0100,
	exts_b_M_1001_N_0100,
	exts_w_M_1001_N_0100,
	load_rm_rn_b_M_1010_N_0100,
	load_rm_rn_w_M_1010_N_0100,
	load_rm_rn_l_M_1010_N_0100,
	mov_rm_rn_M_1010_N_0100,
	load_postinc_rm_rn_b_M_1010_N_0100,
	load_postinc_rm_rn_w_M_1010_N_0100,
	load_postinc_rm_rn_l_M_1010_N_0100,
	not_M_1010_N_0100,
	swap_b_M_1010_N_0100,
	swap_w_M_1010_N_0100,
	negc_M_1010_N_0100,
	neg_M_1010_N_0100,
	extu_b_M_1010_N_0100,
	extu_w_M_1010_N_0100,
	exts_b_M_1010_N_0100,
	exts_w_M_1010_N_0100,
	load_rm_rn_b_M_1011_N_0100,
	load_rm_rn_w_M_1011_N_0100,
	load_rm_rn_l_M_1011_N_0100,
	mov_rm_rn_M_1011_N_0100,
	load_postinc_rm_rn_b_M_1011_N_0100,
	load_postinc_rm_rn_w_M_1011_N_0100,
	load_postinc_rm_rn_l_M_1011_N_0100,
	not_M_1011_N_0100,
	swap_b_M_1011_N_0100,
	swap_w_M_1011_N_0100,
	negc_M_1011_N_0100,
	neg_M_1011_N_0100,
	extu_b_M_1011_N_0100,
	extu_w_M_1011_N_0100,
	exts_b_M_1011_N_0100,
	exts_w_M_1011_N_0100,
	load_rm_rn_b_M_1100_N_0100,
	load_rm_rn_w_M_1100_N_0100,
	load_rm_rn_l_M_1100_N_0100,
	mov_rm_rn_M_1100_N_0100,
	load_postinc_rm_rn_b_M_1100_N_0100,
	load_postinc_rm_rn_w_M_1100_N_0100,
	load_postinc_rm_rn_l_M_1100_N_0100,
	not_M_1100_N_0100,
	swap_b_M_1100_N_0100,
	swap_w_M_1100_N_0100,
	negc_M_1100_N_0100,
	neg_M_1100_N_0100,
	extu_b_M_1100_N_0100,
	extu_w_M_1100_N_0100,
	exts_b_M_1100_N_0100,
	exts_w_M_1100_N_0100,
	load_rm_rn_b_M_1101_N_0100,
	load_rm_rn_w_M_1101_N_0100,
	load_rm_rn_l_M_1101_N_0100,
	mov_rm_rn_M_1101_N_0100,
	load_postinc_rm_rn_b_M_1101_N_0100,
	load_postinc_rm_rn_w_M_1101_N_0100,
	load_postinc_rm_rn_l_M_1101_N_0100,
	not_M_1101_N_0100,
	swap_b_M_1101_N_0100,
	swap_w_M_1101_N_0100,
	negc_M_1101_N_0100,
	neg_M_1101_N_0100,
	extu_b_M_1101_N_0100,
	extu_w_M_1101_N_0100,
	exts_b_M_1101_N_0100,
	exts_w_M_1101_N_0100,
	load_rm_rn_b_M_1110_N_0100,
	load_rm_rn_w_M_1110_N_0100,
	load_rm_rn_l_M_1110_N_0100,
	mov_rm_rn_M_1110_N_0100,
	load_postinc_rm_rn_b_M_1110_N_0100,
	load_postinc_rm_rn_w_M_1110_N_0100,
	load_postinc_rm_rn_l_M_1110_N_0100,
	not_M_1110_N_0100,
	swap_b_M_1110_N_0100,
	swap_w_M_1110_N_0100,
	negc_M_1110_N_0100,
	neg_M_1110_N_0100,
	extu_b_M_1110_N_0100,
	extu_w_M_1110_N_0100,
	exts_b_M_1110_N_0100,
	exts_w_M_1110_N_0100,
	load_rm_rn_b_M_1111_N_0100,
	load_rm_rn_w_M_1111_N_0100,
	load_rm_rn_l_M_1111_N_0100,
	mov_rm_rn_M_1111_N_0100,
	load_postinc_rm_rn_b_M_1111_N_0100,
	load_postinc_rm_rn_w_M_1111_N_0100,
	load_postinc_rm_rn_l_M_1111_N_0100,
	not_M_1111_N_0100,
	swap_b_M_1111_N_0100,
	swap_w_M_1111_N_0100,
	negc_M_1111_N_0100,
	neg_M_1111_N_0100,
	extu_b_M_1111_N_0100,
	extu_w_M_1111_N_0100,
	exts_b_M_1111_N_0100,
	exts_w_M_1111_N_0100,
	load_rm_rn_b_M_0000_N_0101,
	load_rm_rn_w_M_0000_N_0101,
	load_rm_rn_l_M_0000_N_0101,
	mov_rm_rn_M_0000_N_0101,
	load_postinc_rm_rn_b_M_0000_N_0101,
	load_postinc_rm_rn_w_M_0000_N_0101,
	load_postinc_rm_rn_l_M_0000_N_0101,
	not_M_0000_N_0101,
	swap_b_M_0000_N_0101,
	swap_w_M_0000_N_0101,
	negc_M_0000_N_0101,
	neg_M_0000_N_0101,
	extu_b_M_0000_N_0101,
	extu_w_M_0000_N_0101,
	exts_b_M_0000_N_0101,
	exts_w_M_0000_N_0101,
	load_rm_rn_b_M_0001_N_0101,
	load_rm_rn_w_M_0001_N_0101,
	load_rm_rn_l_M_0001_N_0101,
	mov_rm_rn_M_0001_N_0101,
	load_postinc_rm_rn_b_M_0001_N_0101,
	load_postinc_rm_rn_w_M_0001_N_0101,
	load_postinc_rm_rn_l_M_0001_N_0101,
	not_M_0001_N_0101,
	swap_b_M_0001_N_0101,
	swap_w_M_0001_N_0101,
	negc_M_0001_N_0101,
	neg_M_0001_N_0101,
	extu_b_M_0001_N_0101,
	extu_w_M_0001_N_0101,
	exts_b_M_0001_N_0101,
	exts_w_M_0001_N_0101,
	load_rm_rn_b_M_0010_N_0101,
	load_rm_rn_w_M_0010_N_0101,
	load_rm_rn_l_M_0010_N_0101,
	mov_rm_rn_M_0010_N_0101,
	load_postinc_rm_rn_b_M_0010_N_0101,
	load_postinc_rm_rn_w_M_0010_N_0101,
	load_postinc_rm_rn_l_M_0010_N_0101,
	not_M_0010_N_0101,
	swap_b_M_0010_N_0101,
	swap_w_M_0010_N_0101,
	negc_M_0010_N_0101,
	neg_M_0010_N_0101,
	extu_b_M_0010_N_0101,
	extu_w_M_0010_N_0101,
	exts_b_M_0010_N_0101,
	exts_w_M_0010_N_0101,
	load_rm_rn_b_M_0011_N_0101,
	load_rm_rn_w_M_0011_N_0101,
	load_rm_rn_l_M_0011_N_0101,
	mov_rm_rn_M_0011_N_0101,
	load_postinc_rm_rn_b_M_0011_N_0101,
	load_postinc_rm_rn_w_M_0011_N_0101,
	load_postinc_rm_rn_l_M_0011_N_0101,
	not_M_0011_N_0101,
	swap_b_M_0011_N_0101,
	swap_w_M_0011_N_0101,
	negc_M_0011_N_0101,
	neg_M_0011_N_0101,
	extu_b_M_0011_N_0101,
	extu_w_M_0011_N_0101,
	exts_b_M_0011_N_0101,
	exts_w_M_0011_N_0101,
	load_rm_rn_b_M_0100_N_0101,
	load_rm_rn_w_M_0100_N_0101,
	load_rm_rn_l_M_0100_N_0101,
	mov_rm_rn_M_0100_N_0101,
	load_postinc_rm_rn_b_M_0100_N_0101,
	load_postinc_rm_rn_w_M_0100_N_0101,
	load_postinc_rm_rn_l_M_0100_N_0101,
	not_M_0100_N_0101,
	swap_b_M_0100_N_0101,
	swap_w_M_0100_N_0101,
	negc_M_0100_N_0101,
	neg_M_0100_N_0101,
	extu_b_M_0100_N_0101,
	extu_w_M_0100_N_0101,
	exts_b_M_0100_N_0101,
	exts_w_M_0100_N_0101,
	load_rm_rn_b_M_0101_N_0101,
	load_rm_rn_w_M_0101_N_0101,
	load_rm_rn_l_M_0101_N_0101,
	mov_rm_rn_M_0101_N_0101,
	load_postinc_rm_rn_b_M_0101_N_0101,
	load_postinc_rm_rn_w_M_0101_N_0101,
	load_postinc_rm_rn_l_M_0101_N_0101,
	not_M_0101_N_0101,
	swap_b_M_0101_N_0101,
	swap_w_M_0101_N_0101,
	negc_M_0101_N_0101,
	neg_M_0101_N_0101,
	extu_b_M_0101_N_0101,
	extu_w_M_0101_N_0101,
	exts_b_M_0101_N_0101,
	exts_w_M_0101_N_0101,
	load_rm_rn_b_M_0110_N_0101,
	load_rm_rn_w_M_0110_N_0101,
	load_rm_rn_l_M_0110_N_0101,
	mov_rm_rn_M_0110_N_0101,
	load_postinc_rm_rn_b_M_0110_N_0101,
	load_postinc_rm_rn_w_M_0110_N_0101,
	load_postinc_rm_rn_l_M_0110_N_0101,
	not_M_0110_N_0101,
	swap_b_M_0110_N_0101,
	swap_w_M_0110_N_0101,
	negc_M_0110_N_0101,
	neg_M_0110_N_0101,
	extu_b_M_0110_N_0101,
	extu_w_M_0110_N_0101,
	exts_b_M_0110_N_0101,
	exts_w_M_0110_N_0101,
	load_rm_rn_b_M_0111_N_0101,
	load_rm_rn_w_M_0111_N_0101,
	load_rm_rn_l_M_0111_N_0101,
	mov_rm_rn_M_0111_N_0101,
	load_postinc_rm_rn_b_M_0111_N_0101,
	load_postinc_rm_rn_w_M_0111_N_0101,
	load_postinc_rm_rn_l_M_0111_N_0101,
	not_M_0111_N_0101,
	swap_b_M_0111_N_0101,
	swap_w_M_0111_N_0101,
	negc_M_0111_N_0101,
	neg_M_0111_N_0101,
	extu_b_M_0111_N_0101,
	extu_w_M_0111_N_0101,
	exts_b_M_0111_N_0101,
	exts_w_M_0111_N_0101,
	load_rm_rn_b_M_1000_N_0101,
	load_rm_rn_w_M_1000_N_0101,
	load_rm_rn_l_M_1000_N_0101,
	mov_rm_rn_M_1000_N_0101,
	load_postinc_rm_rn_b_M_1000_N_0101,
	load_postinc_rm_rn_w_M_1000_N_0101,
	load_postinc_rm_rn_l_M_1000_N_0101,
	not_M_1000_N_0101,
	swap_b_M_1000_N_0101,
	swap_w_M_1000_N_0101,
	negc_M_1000_N_0101,
	neg_M_1000_N_0101,
	extu_b_M_1000_N_0101,
	extu_w_M_1000_N_0101,
	exts_b_M_1000_N_0101,
	exts_w_M_1000_N_0101,
	load_rm_rn_b_M_1001_N_0101,
	load_rm_rn_w_M_1001_N_0101,
	load_rm_rn_l_M_1001_N_0101,
	mov_rm_rn_M_1001_N_0101,
	load_postinc_rm_rn_b_M_1001_N_0101,
	load_postinc_rm_rn_w_M_1001_N_0101,
	load_postinc_rm_rn_l_M_1001_N_0101,
	not_M_1001_N_0101,
	swap_b_M_1001_N_0101,
	swap_w_M_1001_N_0101,
	negc_M_1001_N_0101,
	neg_M_1001_N_0101,
	extu_b_M_1001_N_0101,
	extu_w_M_1001_N_0101,
	exts_b_M_1001_N_0101,
	exts_w_M_1001_N_0101,
	load_rm_rn_b_M_1010_N_0101,
	load_rm_rn_w_M_1010_N_0101,
	load_rm_rn_l_M_1010_N_0101,
	mov_rm_rn_M_1010_N_0101,
	load_postinc_rm_rn_b_M_1010_N_0101,
	load_postinc_rm_rn_w_M_1010_N_0101,
	load_postinc_rm_rn_l_M_1010_N_0101,
	not_M_1010_N_0101,
	swap_b_M_1010_N_0101,
	swap_w_M_1010_N_0101,
	negc_M_1010_N_0101,
	neg_M_1010_N_0101,
	extu_b_M_1010_N_0101,
	extu_w_M_1010_N_0101,
	exts_b_M_1010_N_0101,
	exts_w_M_1010_N_0101,
	load_rm_rn_b_M_1011_N_0101,
	load_rm_rn_w_M_1011_N_0101,
	load_rm_rn_l_M_1011_N_0101,
	mov_rm_rn_M_1011_N_0101,
	load_postinc_rm_rn_b_M_1011_N_0101,
	load_postinc_rm_rn_w_M_1011_N_0101,
	load_postinc_rm_rn_l_M_1011_N_0101,
	not_M_1011_N_0101,
	swap_b_M_1011_N_0101,
	swap_w_M_1011_N_0101,
	negc_M_1011_N_0101,
	neg_M_1011_N_0101,
	extu_b_M_1011_N_0101,
	extu_w_M_1011_N_0101,
	exts_b_M_1011_N_0101,
	exts_w_M_1011_N_0101,
	load_rm_rn_b_M_1100_N_0101,
	load_rm_rn_w_M_1100_N_0101,
	load_rm_rn_l_M_1100_N_0101,
	mov_rm_rn_M_1100_N_0101,
	load_postinc_rm_rn_b_M_1100_N_0101,
	load_postinc_rm_rn_w_M_1100_N_0101,
	load_postinc_rm_rn_l_M_1100_N_0101,
	not_M_1100_N_0101,
	swap_b_M_1100_N_0101,
	swap_w_M_1100_N_0101,
	negc_M_1100_N_0101,
	neg_M_1100_N_0101,
	extu_b_M_1100_N_0101,
	extu_w_M_1100_N_0101,
	exts_b_M_1100_N_0101,
	exts_w_M_1100_N_0101,
	load_rm_rn_b_M_1101_N_0101,
	load_rm_rn_w_M_1101_N_0101,
	load_rm_rn_l_M_1101_N_0101,
	mov_rm_rn_M_1101_N_0101,
	load_postinc_rm_rn_b_M_1101_N_0101,
	load_postinc_rm_rn_w_M_1101_N_0101,
	load_postinc_rm_rn_l_M_1101_N_0101,
	not_M_1101_N_0101,
	swap_b_M_1101_N_0101,
	swap_w_M_1101_N_0101,
	negc_M_1101_N_0101,
	neg_M_1101_N_0101,
	extu_b_M_1101_N_0101,
	extu_w_M_1101_N_0101,
	exts_b_M_1101_N_0101,
	exts_w_M_1101_N_0101,
	load_rm_rn_b_M_1110_N_0101,
	load_rm_rn_w_M_1110_N_0101,
	load_rm_rn_l_M_1110_N_0101,
	mov_rm_rn_M_1110_N_0101,
	load_postinc_rm_rn_b_M_1110_N_0101,
	load_postinc_rm_rn_w_M_1110_N_0101,
	load_postinc_rm_rn_l_M_1110_N_0101,
	not_M_1110_N_0101,
	swap_b_M_1110_N_0101,
	swap_w_M_1110_N_0101,
	negc_M_1110_N_0101,
	neg_M_1110_N_0101,
	extu_b_M_1110_N_0101,
	extu_w_M_1110_N_0101,
	exts_b_M_1110_N_0101,
	exts_w_M_1110_N_0101,
	load_rm_rn_b_M_1111_N_0101,
	load_rm_rn_w_M_1111_N_0101,
	load_rm_rn_l_M_1111_N_0101,
	mov_rm_rn_M_1111_N_0101,
	load_postinc_rm_rn_b_M_1111_N_0101,
	load_postinc_rm_rn_w_M_1111_N_0101,
	load_postinc_rm_rn_l_M_1111_N_0101,
	not_M_1111_N_0101,
	swap_b_M_1111_N_0101,
	swap_w_M_1111_N_0101,
	negc_M_1111_N_0101,
	neg_M_1111_N_0101,
	extu_b_M_1111_N_0101,
	extu_w_M_1111_N_0101,
	exts_b_M_1111_N_0101,
	exts_w_M_1111_N_0101,
	load_rm_rn_b_M_0000_N_0110,
	load_rm_rn_w_M_0000_N_0110,
	load_rm_rn_l_M_0000_N_0110,
	mov_rm_rn_M_0000_N_0110,
	load_postinc_rm_rn_b_M_0000_N_0110,
	load_postinc_rm_rn_w_M_0000_N_0110,
	load_postinc_rm_rn_l_M_0000_N_0110,
	not_M_0000_N_0110,
	swap_b_M_0000_N_0110,
	swap_w_M_0000_N_0110,
	negc_M_0000_N_0110,
	neg_M_0000_N_0110,
	extu_b_M_0000_N_0110,
	extu_w_M_0000_N_0110,
	exts_b_M_0000_N_0110,
	exts_w_M_0000_N_0110,
	load_rm_rn_b_M_0001_N_0110,
	load_rm_rn_w_M_0001_N_0110,
	load_rm_rn_l_M_0001_N_0110,
	mov_rm_rn_M_0001_N_0110,
	load_postinc_rm_rn_b_M_0001_N_0110,
	load_postinc_rm_rn_w_M_0001_N_0110,
	load_postinc_rm_rn_l_M_0001_N_0110,
	not_M_0001_N_0110,
	swap_b_M_0001_N_0110,
	swap_w_M_0001_N_0110,
	negc_M_0001_N_0110,
	neg_M_0001_N_0110,
	extu_b_M_0001_N_0110,
	extu_w_M_0001_N_0110,
	exts_b_M_0001_N_0110,
	exts_w_M_0001_N_0110,
	load_rm_rn_b_M_0010_N_0110,
	load_rm_rn_w_M_0010_N_0110,
	load_rm_rn_l_M_0010_N_0110,
	mov_rm_rn_M_0010_N_0110,
	load_postinc_rm_rn_b_M_0010_N_0110,
	load_postinc_rm_rn_w_M_0010_N_0110,
	load_postinc_rm_rn_l_M_0010_N_0110,
	not_M_0010_N_0110,
	swap_b_M_0010_N_0110,
	swap_w_M_0010_N_0110,
	negc_M_0010_N_0110,
	neg_M_0010_N_0110,
	extu_b_M_0010_N_0110,
	extu_w_M_0010_N_0110,
	exts_b_M_0010_N_0110,
	exts_w_M_0010_N_0110,
	load_rm_rn_b_M_0011_N_0110,
	load_rm_rn_w_M_0011_N_0110,
	load_rm_rn_l_M_0011_N_0110,
	mov_rm_rn_M_0011_N_0110,
	load_postinc_rm_rn_b_M_0011_N_0110,
	load_postinc_rm_rn_w_M_0011_N_0110,
	load_postinc_rm_rn_l_M_0011_N_0110,
	not_M_0011_N_0110,
	swap_b_M_0011_N_0110,
	swap_w_M_0011_N_0110,
	negc_M_0011_N_0110,
	neg_M_0011_N_0110,
	extu_b_M_0011_N_0110,
	extu_w_M_0011_N_0110,
	exts_b_M_0011_N_0110,
	exts_w_M_0011_N_0110,
	load_rm_rn_b_M_0100_N_0110,
	load_rm_rn_w_M_0100_N_0110,
	load_rm_rn_l_M_0100_N_0110,
	mov_rm_rn_M_0100_N_0110,
	load_postinc_rm_rn_b_M_0100_N_0110,
	load_postinc_rm_rn_w_M_0100_N_0110,
	load_postinc_rm_rn_l_M_0100_N_0110,
	not_M_0100_N_0110,
	swap_b_M_0100_N_0110,
	swap_w_M_0100_N_0110,
	negc_M_0100_N_0110,
	neg_M_0100_N_0110,
	extu_b_M_0100_N_0110,
	extu_w_M_0100_N_0110,
	exts_b_M_0100_N_0110,
	exts_w_M_0100_N_0110,
	load_rm_rn_b_M_0101_N_0110,
	load_rm_rn_w_M_0101_N_0110,
	load_rm_rn_l_M_0101_N_0110,
	mov_rm_rn_M_0101_N_0110,
	load_postinc_rm_rn_b_M_0101_N_0110,
	load_postinc_rm_rn_w_M_0101_N_0110,
	load_postinc_rm_rn_l_M_0101_N_0110,
	not_M_0101_N_0110,
	swap_b_M_0101_N_0110,
	swap_w_M_0101_N_0110,
	negc_M_0101_N_0110,
	neg_M_0101_N_0110,
	extu_b_M_0101_N_0110,
	extu_w_M_0101_N_0110,
	exts_b_M_0101_N_0110,
	exts_w_M_0101_N_0110,
	load_rm_rn_b_M_0110_N_0110,
	load_rm_rn_w_M_0110_N_0110,
	load_rm_rn_l_M_0110_N_0110,
	mov_rm_rn_M_0110_N_0110,
	load_postinc_rm_rn_b_M_0110_N_0110,
	load_postinc_rm_rn_w_M_0110_N_0110,
	load_postinc_rm_rn_l_M_0110_N_0110,
	not_M_0110_N_0110,
	swap_b_M_0110_N_0110,
	swap_w_M_0110_N_0110,
	negc_M_0110_N_0110,
	neg_M_0110_N_0110,
	extu_b_M_0110_N_0110,
	extu_w_M_0110_N_0110,
	exts_b_M_0110_N_0110,
	exts_w_M_0110_N_0110,
	load_rm_rn_b_M_0111_N_0110,
	load_rm_rn_w_M_0111_N_0110,
	load_rm_rn_l_M_0111_N_0110,
	mov_rm_rn_M_0111_N_0110,
	load_postinc_rm_rn_b_M_0111_N_0110,
	load_postinc_rm_rn_w_M_0111_N_0110,
	load_postinc_rm_rn_l_M_0111_N_0110,
	not_M_0111_N_0110,
	swap_b_M_0111_N_0110,
	swap_w_M_0111_N_0110,
	negc_M_0111_N_0110,
	neg_M_0111_N_0110,
	extu_b_M_0111_N_0110,
	extu_w_M_0111_N_0110,
	exts_b_M_0111_N_0110,
	exts_w_M_0111_N_0110,
	load_rm_rn_b_M_1000_N_0110,
	load_rm_rn_w_M_1000_N_0110,
	load_rm_rn_l_M_1000_N_0110,
	mov_rm_rn_M_1000_N_0110,
	load_postinc_rm_rn_b_M_1000_N_0110,
	load_postinc_rm_rn_w_M_1000_N_0110,
	load_postinc_rm_rn_l_M_1000_N_0110,
	not_M_1000_N_0110,
	swap_b_M_1000_N_0110,
	swap_w_M_1000_N_0110,
	negc_M_1000_N_0110,
	neg_M_1000_N_0110,
	extu_b_M_1000_N_0110,
	extu_w_M_1000_N_0110,
	exts_b_M_1000_N_0110,
	exts_w_M_1000_N_0110,
	load_rm_rn_b_M_1001_N_0110,
	load_rm_rn_w_M_1001_N_0110,
	load_rm_rn_l_M_1001_N_0110,
	mov_rm_rn_M_1001_N_0110,
	load_postinc_rm_rn_b_M_1001_N_0110,
	load_postinc_rm_rn_w_M_1001_N_0110,
	load_postinc_rm_rn_l_M_1001_N_0110,
	not_M_1001_N_0110,
	swap_b_M_1001_N_0110,
	swap_w_M_1001_N_0110,
	negc_M_1001_N_0110,
	neg_M_1001_N_0110,
	extu_b_M_1001_N_0110,
	extu_w_M_1001_N_0110,
	exts_b_M_1001_N_0110,
	exts_w_M_1001_N_0110,
	load_rm_rn_b_M_1010_N_0110,
	load_rm_rn_w_M_1010_N_0110,
	load_rm_rn_l_M_1010_N_0110,
	mov_rm_rn_M_1010_N_0110,
	load_postinc_rm_rn_b_M_1010_N_0110,
	load_postinc_rm_rn_w_M_1010_N_0110,
	load_postinc_rm_rn_l_M_1010_N_0110,
	not_M_1010_N_0110,
	swap_b_M_1010_N_0110,
	swap_w_M_1010_N_0110,
	negc_M_1010_N_0110,
	neg_M_1010_N_0110,
	extu_b_M_1010_N_0110,
	extu_w_M_1010_N_0110,
	exts_b_M_1010_N_0110,
	exts_w_M_1010_N_0110,
	load_rm_rn_b_M_1011_N_0110,
	load_rm_rn_w_M_1011_N_0110,
	load_rm_rn_l_M_1011_N_0110,
	mov_rm_rn_M_1011_N_0110,
	load_postinc_rm_rn_b_M_1011_N_0110,
	load_postinc_rm_rn_w_M_1011_N_0110,
	load_postinc_rm_rn_l_M_1011_N_0110,
	not_M_1011_N_0110,
	swap_b_M_1011_N_0110,
	swap_w_M_1011_N_0110,
	negc_M_1011_N_0110,
	neg_M_1011_N_0110,
	extu_b_M_1011_N_0110,
	extu_w_M_1011_N_0110,
	exts_b_M_1011_N_0110,
	exts_w_M_1011_N_0110,
	load_rm_rn_b_M_1100_N_0110,
	load_rm_rn_w_M_1100_N_0110,
	load_rm_rn_l_M_1100_N_0110,
	mov_rm_rn_M_1100_N_0110,
	load_postinc_rm_rn_b_M_1100_N_0110,
	load_postinc_rm_rn_w_M_1100_N_0110,
	load_postinc_rm_rn_l_M_1100_N_0110,
	not_M_1100_N_0110,
	swap_b_M_1100_N_0110,
	swap_w_M_1100_N_0110,
	negc_M_1100_N_0110,
	neg_M_1100_N_0110,
	extu_b_M_1100_N_0110,
	extu_w_M_1100_N_0110,
	exts_b_M_1100_N_0110,
	exts_w_M_1100_N_0110,
	load_rm_rn_b_M_1101_N_0110,
	load_rm_rn_w_M_1101_N_0110,
	load_rm_rn_l_M_1101_N_0110,
	mov_rm_rn_M_1101_N_0110,
	load_postinc_rm_rn_b_M_1101_N_0110,
	load_postinc_rm_rn_w_M_1101_N_0110,
	load_postinc_rm_rn_l_M_1101_N_0110,
	not_M_1101_N_0110,
	swap_b_M_1101_N_0110,
	swap_w_M_1101_N_0110,
	negc_M_1101_N_0110,
	neg_M_1101_N_0110,
	extu_b_M_1101_N_0110,
	extu_w_M_1101_N_0110,
	exts_b_M_1101_N_0110,
	exts_w_M_1101_N_0110,
	load_rm_rn_b_M_1110_N_0110,
	load_rm_rn_w_M_1110_N_0110,
	load_rm_rn_l_M_1110_N_0110,
	mov_rm_rn_M_1110_N_0110,
	load_postinc_rm_rn_b_M_1110_N_0110,
	load_postinc_rm_rn_w_M_1110_N_0110,
	load_postinc_rm_rn_l_M_1110_N_0110,
	not_M_1110_N_0110,
	swap_b_M_1110_N_0110,
	swap_w_M_1110_N_0110,
	negc_M_1110_N_0110,
	neg_M_1110_N_0110,
	extu_b_M_1110_N_0110,
	extu_w_M_1110_N_0110,
	exts_b_M_1110_N_0110,
	exts_w_M_1110_N_0110,
	load_rm_rn_b_M_1111_N_0110,
	load_rm_rn_w_M_1111_N_0110,
	load_rm_rn_l_M_1111_N_0110,
	mov_rm_rn_M_1111_N_0110,
	load_postinc_rm_rn_b_M_1111_N_0110,
	load_postinc_rm_rn_w_M_1111_N_0110,
	load_postinc_rm_rn_l_M_1111_N_0110,
	not_M_1111_N_0110,
	swap_b_M_1111_N_0110,
	swap_w_M_1111_N_0110,
	negc_M_1111_N_0110,
	neg_M_1111_N_0110,
	extu_b_M_1111_N_0110,
	extu_w_M_1111_N_0110,
	exts_b_M_1111_N_0110,
	exts_w_M_1111_N_0110,
	load_rm_rn_b_M_0000_N_0111,
	load_rm_rn_w_M_0000_N_0111,
	load_rm_rn_l_M_0000_N_0111,
	mov_rm_rn_M_0000_N_0111,
	load_postinc_rm_rn_b_M_0000_N_0111,
	load_postinc_rm_rn_w_M_0000_N_0111,
	load_postinc_rm_rn_l_M_0000_N_0111,
	not_M_0000_N_0111,
	swap_b_M_0000_N_0111,
	swap_w_M_0000_N_0111,
	negc_M_0000_N_0111,
	neg_M_0000_N_0111,
	extu_b_M_0000_N_0111,
	extu_w_M_0000_N_0111,
	exts_b_M_0000_N_0111,
	exts_w_M_0000_N_0111,
	load_rm_rn_b_M_0001_N_0111,
	load_rm_rn_w_M_0001_N_0111,
	load_rm_rn_l_M_0001_N_0111,
	mov_rm_rn_M_0001_N_0111,
	load_postinc_rm_rn_b_M_0001_N_0111,
	load_postinc_rm_rn_w_M_0001_N_0111,
	load_postinc_rm_rn_l_M_0001_N_0111,
	not_M_0001_N_0111,
	swap_b_M_0001_N_0111,
	swap_w_M_0001_N_0111,
	negc_M_0001_N_0111,
	neg_M_0001_N_0111,
	extu_b_M_0001_N_0111,
	extu_w_M_0001_N_0111,
	exts_b_M_0001_N_0111,
	exts_w_M_0001_N_0111,
	load_rm_rn_b_M_0010_N_0111,
	load_rm_rn_w_M_0010_N_0111,
	load_rm_rn_l_M_0010_N_0111,
	mov_rm_rn_M_0010_N_0111,
	load_postinc_rm_rn_b_M_0010_N_0111,
	load_postinc_rm_rn_w_M_0010_N_0111,
	load_postinc_rm_rn_l_M_0010_N_0111,
	not_M_0010_N_0111,
	swap_b_M_0010_N_0111,
	swap_w_M_0010_N_0111,
	negc_M_0010_N_0111,
	neg_M_0010_N_0111,
	extu_b_M_0010_N_0111,
	extu_w_M_0010_N_0111,
	exts_b_M_0010_N_0111,
	exts_w_M_0010_N_0111,
	load_rm_rn_b_M_0011_N_0111,
	load_rm_rn_w_M_0011_N_0111,
	load_rm_rn_l_M_0011_N_0111,
	mov_rm_rn_M_0011_N_0111,
	load_postinc_rm_rn_b_M_0011_N_0111,
	load_postinc_rm_rn_w_M_0011_N_0111,
	load_postinc_rm_rn_l_M_0011_N_0111,
	not_M_0011_N_0111,
	swap_b_M_0011_N_0111,
	swap_w_M_0011_N_0111,
	negc_M_0011_N_0111,
	neg_M_0011_N_0111,
	extu_b_M_0011_N_0111,
	extu_w_M_0011_N_0111,
	exts_b_M_0011_N_0111,
	exts_w_M_0011_N_0111,
	load_rm_rn_b_M_0100_N_0111,
	load_rm_rn_w_M_0100_N_0111,
	load_rm_rn_l_M_0100_N_0111,
	mov_rm_rn_M_0100_N_0111,
	load_postinc_rm_rn_b_M_0100_N_0111,
	load_postinc_rm_rn_w_M_0100_N_0111,
	load_postinc_rm_rn_l_M_0100_N_0111,
	not_M_0100_N_0111,
	swap_b_M_0100_N_0111,
	swap_w_M_0100_N_0111,
	negc_M_0100_N_0111,
	neg_M_0100_N_0111,
	extu_b_M_0100_N_0111,
	extu_w_M_0100_N_0111,
	exts_b_M_0100_N_0111,
	exts_w_M_0100_N_0111,
	load_rm_rn_b_M_0101_N_0111,
	load_rm_rn_w_M_0101_N_0111,
	load_rm_rn_l_M_0101_N_0111,
	mov_rm_rn_M_0101_N_0111,
	load_postinc_rm_rn_b_M_0101_N_0111,
	load_postinc_rm_rn_w_M_0101_N_0111,
	load_postinc_rm_rn_l_M_0101_N_0111,
	not_M_0101_N_0111,
	swap_b_M_0101_N_0111,
	swap_w_M_0101_N_0111,
	negc_M_0101_N_0111,
	neg_M_0101_N_0111,
	extu_b_M_0101_N_0111,
	extu_w_M_0101_N_0111,
	exts_b_M_0101_N_0111,
	exts_w_M_0101_N_0111,
	load_rm_rn_b_M_0110_N_0111,
	load_rm_rn_w_M_0110_N_0111,
	load_rm_rn_l_M_0110_N_0111,
	mov_rm_rn_M_0110_N_0111,
	load_postinc_rm_rn_b_M_0110_N_0111,
	load_postinc_rm_rn_w_M_0110_N_0111,
	load_postinc_rm_rn_l_M_0110_N_0111,
	not_M_0110_N_0111,
	swap_b_M_0110_N_0111,
	swap_w_M_0110_N_0111,
	negc_M_0110_N_0111,
	neg_M_0110_N_0111,
	extu_b_M_0110_N_0111,
	extu_w_M_0110_N_0111,
	exts_b_M_0110_N_0111,
	exts_w_M_0110_N_0111,
	load_rm_rn_b_M_0111_N_0111,
	load_rm_rn_w_M_0111_N_0111,
	load_rm_rn_l_M_0111_N_0111,
	mov_rm_rn_M_0111_N_0111,
	load_postinc_rm_rn_b_M_0111_N_0111,
	load_postinc_rm_rn_w_M_0111_N_0111,
	load_postinc_rm_rn_l_M_0111_N_0111,
	not_M_0111_N_0111,
	swap_b_M_0111_N_0111,
	swap_w_M_0111_N_0111,
	negc_M_0111_N_0111,
	neg_M_0111_N_0111,
	extu_b_M_0111_N_0111,
	extu_w_M_0111_N_0111,
	exts_b_M_0111_N_0111,
	exts_w_M_0111_N_0111,
	load_rm_rn_b_M_1000_N_0111,
	load_rm_rn_w_M_1000_N_0111,
	load_rm_rn_l_M_1000_N_0111,
	mov_rm_rn_M_1000_N_0111,
	load_postinc_rm_rn_b_M_1000_N_0111,
	load_postinc_rm_rn_w_M_1000_N_0111,
	load_postinc_rm_rn_l_M_1000_N_0111,
	not_M_1000_N_0111,
	swap_b_M_1000_N_0111,
	swap_w_M_1000_N_0111,
	negc_M_1000_N_0111,
	neg_M_1000_N_0111,
	extu_b_M_1000_N_0111,
	extu_w_M_1000_N_0111,
	exts_b_M_1000_N_0111,
	exts_w_M_1000_N_0111,
	load_rm_rn_b_M_1001_N_0111,
	load_rm_rn_w_M_1001_N_0111,
	load_rm_rn_l_M_1001_N_0111,
	mov_rm_rn_M_1001_N_0111,
	load_postinc_rm_rn_b_M_1001_N_0111,
	load_postinc_rm_rn_w_M_1001_N_0111,
	load_postinc_rm_rn_l_M_1001_N_0111,
	not_M_1001_N_0111,
	swap_b_M_1001_N_0111,
	swap_w_M_1001_N_0111,
	negc_M_1001_N_0111,
	neg_M_1001_N_0111,
	extu_b_M_1001_N_0111,
	extu_w_M_1001_N_0111,
	exts_b_M_1001_N_0111,
	exts_w_M_1001_N_0111,
	load_rm_rn_b_M_1010_N_0111,
	load_rm_rn_w_M_1010_N_0111,
	load_rm_rn_l_M_1010_N_0111,
	mov_rm_rn_M_1010_N_0111,
	load_postinc_rm_rn_b_M_1010_N_0111,
	load_postinc_rm_rn_w_M_1010_N_0111,
	load_postinc_rm_rn_l_M_1010_N_0111,
	not_M_1010_N_0111,
	swap_b_M_1010_N_0111,
	swap_w_M_1010_N_0111,
	negc_M_1010_N_0111,
	neg_M_1010_N_0111,
	extu_b_M_1010_N_0111,
	extu_w_M_1010_N_0111,
	exts_b_M_1010_N_0111,
	exts_w_M_1010_N_0111,
	load_rm_rn_b_M_1011_N_0111,
	load_rm_rn_w_M_1011_N_0111,
	load_rm_rn_l_M_1011_N_0111,
	mov_rm_rn_M_1011_N_0111,
	load_postinc_rm_rn_b_M_1011_N_0111,
	load_postinc_rm_rn_w_M_1011_N_0111,
	load_postinc_rm_rn_l_M_1011_N_0111,
	not_M_1011_N_0111,
	swap_b_M_1011_N_0111,
	swap_w_M_1011_N_0111,
	negc_M_1011_N_0111,
	neg_M_1011_N_0111,
	extu_b_M_1011_N_0111,
	extu_w_M_1011_N_0111,
	exts_b_M_1011_N_0111,
	exts_w_M_1011_N_0111,
	load_rm_rn_b_M_1100_N_0111,
	load_rm_rn_w_M_1100_N_0111,
	load_rm_rn_l_M_1100_N_0111,
	mov_rm_rn_M_1100_N_0111,
	load_postinc_rm_rn_b_M_1100_N_0111,
	load_postinc_rm_rn_w_M_1100_N_0111,
	load_postinc_rm_rn_l_M_1100_N_0111,
	not_M_1100_N_0111,
	swap_b_M_1100_N_0111,
	swap_w_M_1100_N_0111,
	negc_M_1100_N_0111,
	neg_M_1100_N_0111,
	extu_b_M_1100_N_0111,
	extu_w_M_1100_N_0111,
	exts_b_M_1100_N_0111,
	exts_w_M_1100_N_0111,
	load_rm_rn_b_M_1101_N_0111,
	load_rm_rn_w_M_1101_N_0111,
	load_rm_rn_l_M_1101_N_0111,
	mov_rm_rn_M_1101_N_0111,
	load_postinc_rm_rn_b_M_1101_N_0111,
	load_postinc_rm_rn_w_M_1101_N_0111,
	load_postinc_rm_rn_l_M_1101_N_0111,
	not_M_1101_N_0111,
	swap_b_M_1101_N_0111,
	swap_w_M_1101_N_0111,
	negc_M_1101_N_0111,
	neg_M_1101_N_0111,
	extu_b_M_1101_N_0111,
	extu_w_M_1101_N_0111,
	exts_b_M_1101_N_0111,
	exts_w_M_1101_N_0111,
	load_rm_rn_b_M_1110_N_0111,
	load_rm_rn_w_M_1110_N_0111,
	load_rm_rn_l_M_1110_N_0111,
	mov_rm_rn_M_1110_N_0111,
	load_postinc_rm_rn_b_M_1110_N_0111,
	load_postinc_rm_rn_w_M_1110_N_0111,
	load_postinc_rm_rn_l_M_1110_N_0111,
	not_M_1110_N_0111,
	swap_b_M_1110_N_0111,
	swap_w_M_1110_N_0111,
	negc_M_1110_N_0111,
	neg_M_1110_N_0111,
	extu_b_M_1110_N_0111,
	extu_w_M_1110_N_0111,
	exts_b_M_1110_N_0111,
	exts_w_M_1110_N_0111,
	load_rm_rn_b_M_1111_N_0111,
	load_rm_rn_w_M_1111_N_0111,
	load_rm_rn_l_M_1111_N_0111,
	mov_rm_rn_M_1111_N_0111,
	load_postinc_rm_rn_b_M_1111_N_0111,
	load_postinc_rm_rn_w_M_1111_N_0111,
	load_postinc_rm_rn_l_M_1111_N_0111,
	not_M_1111_N_0111,
	swap_b_M_1111_N_0111,
	swap_w_M_1111_N_0111,
	negc_M_1111_N_0111,
	neg_M_1111_N_0111,
	extu_b_M_1111_N_0111,
	extu_w_M_1111_N_0111,
	exts_b_M_1111_N_0111,
	exts_w_M_1111_N_0111,
	load_rm_rn_b_M_0000_N_1000,
	load_rm_rn_w_M_0000_N_1000,
	load_rm_rn_l_M_0000_N_1000,
	mov_rm_rn_M_0000_N_1000,
	load_postinc_rm_rn_b_M_0000_N_1000,
	load_postinc_rm_rn_w_M_0000_N_1000,
	load_postinc_rm_rn_l_M_0000_N_1000,
	not_M_0000_N_1000,
	swap_b_M_0000_N_1000,
	swap_w_M_0000_N_1000,
	negc_M_0000_N_1000,
	neg_M_0000_N_1000,
	extu_b_M_0000_N_1000,
	extu_w_M_0000_N_1000,
	exts_b_M_0000_N_1000,
	exts_w_M_0000_N_1000,
	load_rm_rn_b_M_0001_N_1000,
	load_rm_rn_w_M_0001_N_1000,
	load_rm_rn_l_M_0001_N_1000,
	mov_rm_rn_M_0001_N_1000,
	load_postinc_rm_rn_b_M_0001_N_1000,
	load_postinc_rm_rn_w_M_0001_N_1000,
	load_postinc_rm_rn_l_M_0001_N_1000,
	not_M_0001_N_1000,
	swap_b_M_0001_N_1000,
	swap_w_M_0001_N_1000,
	negc_M_0001_N_1000,
	neg_M_0001_N_1000,
	extu_b_M_0001_N_1000,
	extu_w_M_0001_N_1000,
	exts_b_M_0001_N_1000,
	exts_w_M_0001_N_1000,
	load_rm_rn_b_M_0010_N_1000,
	load_rm_rn_w_M_0010_N_1000,
	load_rm_rn_l_M_0010_N_1000,
	mov_rm_rn_M_0010_N_1000,
	load_postinc_rm_rn_b_M_0010_N_1000,
	load_postinc_rm_rn_w_M_0010_N_1000,
	load_postinc_rm_rn_l_M_0010_N_1000,
	not_M_0010_N_1000,
	swap_b_M_0010_N_1000,
	swap_w_M_0010_N_1000,
	negc_M_0010_N_1000,
	neg_M_0010_N_1000,
	extu_b_M_0010_N_1000,
	extu_w_M_0010_N_1000,
	exts_b_M_0010_N_1000,
	exts_w_M_0010_N_1000,
	load_rm_rn_b_M_0011_N_1000,
	load_rm_rn_w_M_0011_N_1000,
	load_rm_rn_l_M_0011_N_1000,
	mov_rm_rn_M_0011_N_1000,
	load_postinc_rm_rn_b_M_0011_N_1000,
	load_postinc_rm_rn_w_M_0011_N_1000,
	load_postinc_rm_rn_l_M_0011_N_1000,
	not_M_0011_N_1000,
	swap_b_M_0011_N_1000,
	swap_w_M_0011_N_1000,
	negc_M_0011_N_1000,
	neg_M_0011_N_1000,
	extu_b_M_0011_N_1000,
	extu_w_M_0011_N_1000,
	exts_b_M_0011_N_1000,
	exts_w_M_0011_N_1000,
	load_rm_rn_b_M_0100_N_1000,
	load_rm_rn_w_M_0100_N_1000,
	load_rm_rn_l_M_0100_N_1000,
	mov_rm_rn_M_0100_N_1000,
	load_postinc_rm_rn_b_M_0100_N_1000,
	load_postinc_rm_rn_w_M_0100_N_1000,
	load_postinc_rm_rn_l_M_0100_N_1000,
	not_M_0100_N_1000,
	swap_b_M_0100_N_1000,
	swap_w_M_0100_N_1000,
	negc_M_0100_N_1000,
	neg_M_0100_N_1000,
	extu_b_M_0100_N_1000,
	extu_w_M_0100_N_1000,
	exts_b_M_0100_N_1000,
	exts_w_M_0100_N_1000,
	load_rm_rn_b_M_0101_N_1000,
	load_rm_rn_w_M_0101_N_1000,
	load_rm_rn_l_M_0101_N_1000,
	mov_rm_rn_M_0101_N_1000,
	load_postinc_rm_rn_b_M_0101_N_1000,
	load_postinc_rm_rn_w_M_0101_N_1000,
	load_postinc_rm_rn_l_M_0101_N_1000,
	not_M_0101_N_1000,
	swap_b_M_0101_N_1000,
	swap_w_M_0101_N_1000,
	negc_M_0101_N_1000,
	neg_M_0101_N_1000,
	extu_b_M_0101_N_1000,
	extu_w_M_0101_N_1000,
	exts_b_M_0101_N_1000,
	exts_w_M_0101_N_1000,
	load_rm_rn_b_M_0110_N_1000,
	load_rm_rn_w_M_0110_N_1000,
	load_rm_rn_l_M_0110_N_1000,
	mov_rm_rn_M_0110_N_1000,
	load_postinc_rm_rn_b_M_0110_N_1000,
	load_postinc_rm_rn_w_M_0110_N_1000,
	load_postinc_rm_rn_l_M_0110_N_1000,
	not_M_0110_N_1000,
	swap_b_M_0110_N_1000,
	swap_w_M_0110_N_1000,
	negc_M_0110_N_1000,
	neg_M_0110_N_1000,
	extu_b_M_0110_N_1000,
	extu_w_M_0110_N_1000,
	exts_b_M_0110_N_1000,
	exts_w_M_0110_N_1000,
	load_rm_rn_b_M_0111_N_1000,
	load_rm_rn_w_M_0111_N_1000,
	load_rm_rn_l_M_0111_N_1000,
	mov_rm_rn_M_0111_N_1000,
	load_postinc_rm_rn_b_M_0111_N_1000,
	load_postinc_rm_rn_w_M_0111_N_1000,
	load_postinc_rm_rn_l_M_0111_N_1000,
	not_M_0111_N_1000,
	swap_b_M_0111_N_1000,
	swap_w_M_0111_N_1000,
	negc_M_0111_N_1000,
	neg_M_0111_N_1000,
	extu_b_M_0111_N_1000,
	extu_w_M_0111_N_1000,
	exts_b_M_0111_N_1000,
	exts_w_M_0111_N_1000,
	load_rm_rn_b_M_1000_N_1000,
	load_rm_rn_w_M_1000_N_1000,
	load_rm_rn_l_M_1000_N_1000,
	mov_rm_rn_M_1000_N_1000,
	load_postinc_rm_rn_b_M_1000_N_1000,
	load_postinc_rm_rn_w_M_1000_N_1000,
	load_postinc_rm_rn_l_M_1000_N_1000,
	not_M_1000_N_1000,
	swap_b_M_1000_N_1000,
	swap_w_M_1000_N_1000,
	negc_M_1000_N_1000,
	neg_M_1000_N_1000,
	extu_b_M_1000_N_1000,
	extu_w_M_1000_N_1000,
	exts_b_M_1000_N_1000,
	exts_w_M_1000_N_1000,
	load_rm_rn_b_M_1001_N_1000,
	load_rm_rn_w_M_1001_N_1000,
	load_rm_rn_l_M_1001_N_1000,
	mov_rm_rn_M_1001_N_1000,
	load_postinc_rm_rn_b_M_1001_N_1000,
	load_postinc_rm_rn_w_M_1001_N_1000,
	load_postinc_rm_rn_l_M_1001_N_1000,
	not_M_1001_N_1000,
	swap_b_M_1001_N_1000,
	swap_w_M_1001_N_1000,
	negc_M_1001_N_1000,
	neg_M_1001_N_1000,
	extu_b_M_1001_N_1000,
	extu_w_M_1001_N_1000,
	exts_b_M_1001_N_1000,
	exts_w_M_1001_N_1000,
	load_rm_rn_b_M_1010_N_1000,
	load_rm_rn_w_M_1010_N_1000,
	load_rm_rn_l_M_1010_N_1000,
	mov_rm_rn_M_1010_N_1000,
	load_postinc_rm_rn_b_M_1010_N_1000,
	load_postinc_rm_rn_w_M_1010_N_1000,
	load_postinc_rm_rn_l_M_1010_N_1000,
	not_M_1010_N_1000,
	swap_b_M_1010_N_1000,
	swap_w_M_1010_N_1000,
	negc_M_1010_N_1000,
	neg_M_1010_N_1000,
	extu_b_M_1010_N_1000,
	extu_w_M_1010_N_1000,
	exts_b_M_1010_N_1000,
	exts_w_M_1010_N_1000,
	load_rm_rn_b_M_1011_N_1000,
	load_rm_rn_w_M_1011_N_1000,
	load_rm_rn_l_M_1011_N_1000,
	mov_rm_rn_M_1011_N_1000,
	load_postinc_rm_rn_b_M_1011_N_1000,
	load_postinc_rm_rn_w_M_1011_N_1000,
	load_postinc_rm_rn_l_M_1011_N_1000,
	not_M_1011_N_1000,
	swap_b_M_1011_N_1000,
	swap_w_M_1011_N_1000,
	negc_M_1011_N_1000,
	neg_M_1011_N_1000,
	extu_b_M_1011_N_1000,
	extu_w_M_1011_N_1000,
	exts_b_M_1011_N_1000,
	exts_w_M_1011_N_1000,
	load_rm_rn_b_M_1100_N_1000,
	load_rm_rn_w_M_1100_N_1000,
	load_rm_rn_l_M_1100_N_1000,
	mov_rm_rn_M_1100_N_1000,
	load_postinc_rm_rn_b_M_1100_N_1000,
	load_postinc_rm_rn_w_M_1100_N_1000,
	load_postinc_rm_rn_l_M_1100_N_1000,
	not_M_1100_N_1000,
	swap_b_M_1100_N_1000,
	swap_w_M_1100_N_1000,
	negc_M_1100_N_1000,
	neg_M_1100_N_1000,
	extu_b_M_1100_N_1000,
	extu_w_M_1100_N_1000,
	exts_b_M_1100_N_1000,
	exts_w_M_1100_N_1000,
	load_rm_rn_b_M_1101_N_1000,
	load_rm_rn_w_M_1101_N_1000,
	load_rm_rn_l_M_1101_N_1000,
	mov_rm_rn_M_1101_N_1000,
	load_postinc_rm_rn_b_M_1101_N_1000,
	load_postinc_rm_rn_w_M_1101_N_1000,
	load_postinc_rm_rn_l_M_1101_N_1000,
	not_M_1101_N_1000,
	swap_b_M_1101_N_1000,
	swap_w_M_1101_N_1000,
	negc_M_1101_N_1000,
	neg_M_1101_N_1000,
	extu_b_M_1101_N_1000,
	extu_w_M_1101_N_1000,
	exts_b_M_1101_N_1000,
	exts_w_M_1101_N_1000,
	load_rm_rn_b_M_1110_N_1000,
	load_rm_rn_w_M_1110_N_1000,
	load_rm_rn_l_M_1110_N_1000,
	mov_rm_rn_M_1110_N_1000,
	load_postinc_rm_rn_b_M_1110_N_1000,
	load_postinc_rm_rn_w_M_1110_N_1000,
	load_postinc_rm_rn_l_M_1110_N_1000,
	not_M_1110_N_1000,
	swap_b_M_1110_N_1000,
	swap_w_M_1110_N_1000,
	negc_M_1110_N_1000,
	neg_M_1110_N_1000,
	extu_b_M_1110_N_1000,
	extu_w_M_1110_N_1000,
	exts_b_M_1110_N_1000,
	exts_w_M_1110_N_1000,
	load_rm_rn_b_M_1111_N_1000,
	load_rm_rn_w_M_1111_N_1000,
	load_rm_rn_l_M_1111_N_1000,
	mov_rm_rn_M_1111_N_1000,
	load_postinc_rm_rn_b_M_1111_N_1000,
	load_postinc_rm_rn_w_M_1111_N_1000,
	load_postinc_rm_rn_l_M_1111_N_1000,
	not_M_1111_N_1000,
	swap_b_M_1111_N_1000,
	swap_w_M_1111_N_1000,
	negc_M_1111_N_1000,
	neg_M_1111_N_1000,
	extu_b_M_1111_N_1000,
	extu_w_M_1111_N_1000,
	exts_b_M_1111_N_1000,
	exts_w_M_1111_N_1000,
	load_rm_rn_b_M_0000_N_1001,
	load_rm_rn_w_M_0000_N_1001,
	load_rm_rn_l_M_0000_N_1001,
	mov_rm_rn_M_0000_N_1001,
	load_postinc_rm_rn_b_M_0000_N_1001,
	load_postinc_rm_rn_w_M_0000_N_1001,
	load_postinc_rm_rn_l_M_0000_N_1001,
	not_M_0000_N_1001,
	swap_b_M_0000_N_1001,
	swap_w_M_0000_N_1001,
	negc_M_0000_N_1001,
	neg_M_0000_N_1001,
	extu_b_M_0000_N_1001,
	extu_w_M_0000_N_1001,
	exts_b_M_0000_N_1001,
	exts_w_M_0000_N_1001,
	load_rm_rn_b_M_0001_N_1001,
	load_rm_rn_w_M_0001_N_1001,
	load_rm_rn_l_M_0001_N_1001,
	mov_rm_rn_M_0001_N_1001,
	load_postinc_rm_rn_b_M_0001_N_1001,
	load_postinc_rm_rn_w_M_0001_N_1001,
	load_postinc_rm_rn_l_M_0001_N_1001,
	not_M_0001_N_1001,
	swap_b_M_0001_N_1001,
	swap_w_M_0001_N_1001,
	negc_M_0001_N_1001,
	neg_M_0001_N_1001,
	extu_b_M_0001_N_1001,
	extu_w_M_0001_N_1001,
	exts_b_M_0001_N_1001,
	exts_w_M_0001_N_1001,
	load_rm_rn_b_M_0010_N_1001,
	load_rm_rn_w_M_0010_N_1001,
	load_rm_rn_l_M_0010_N_1001,
	mov_rm_rn_M_0010_N_1001,
	load_postinc_rm_rn_b_M_0010_N_1001,
	load_postinc_rm_rn_w_M_0010_N_1001,
	load_postinc_rm_rn_l_M_0010_N_1001,
	not_M_0010_N_1001,
	swap_b_M_0010_N_1001,
	swap_w_M_0010_N_1001,
	negc_M_0010_N_1001,
	neg_M_0010_N_1001,
	extu_b_M_0010_N_1001,
	extu_w_M_0010_N_1001,
	exts_b_M_0010_N_1001,
	exts_w_M_0010_N_1001,
	load_rm_rn_b_M_0011_N_1001,
	load_rm_rn_w_M_0011_N_1001,
	load_rm_rn_l_M_0011_N_1001,
	mov_rm_rn_M_0011_N_1001,
	load_postinc_rm_rn_b_M_0011_N_1001,
	load_postinc_rm_rn_w_M_0011_N_1001,
	load_postinc_rm_rn_l_M_0011_N_1001,
	not_M_0011_N_1001,
	swap_b_M_0011_N_1001,
	swap_w_M_0011_N_1001,
	negc_M_0011_N_1001,
	neg_M_0011_N_1001,
	extu_b_M_0011_N_1001,
	extu_w_M_0011_N_1001,
	exts_b_M_0011_N_1001,
	exts_w_M_0011_N_1001,
	load_rm_rn_b_M_0100_N_1001,
	load_rm_rn_w_M_0100_N_1001,
	load_rm_rn_l_M_0100_N_1001,
	mov_rm_rn_M_0100_N_1001,
	load_postinc_rm_rn_b_M_0100_N_1001,
	load_postinc_rm_rn_w_M_0100_N_1001,
	load_postinc_rm_rn_l_M_0100_N_1001,
	not_M_0100_N_1001,
	swap_b_M_0100_N_1001,
	swap_w_M_0100_N_1001,
	negc_M_0100_N_1001,
	neg_M_0100_N_1001,
	extu_b_M_0100_N_1001,
	extu_w_M_0100_N_1001,
	exts_b_M_0100_N_1001,
	exts_w_M_0100_N_1001,
	load_rm_rn_b_M_0101_N_1001,
	load_rm_rn_w_M_0101_N_1001,
	load_rm_rn_l_M_0101_N_1001,
	mov_rm_rn_M_0101_N_1001,
	load_postinc_rm_rn_b_M_0101_N_1001,
	load_postinc_rm_rn_w_M_0101_N_1001,
	load_postinc_rm_rn_l_M_0101_N_1001,
	not_M_0101_N_1001,
	swap_b_M_0101_N_1001,
	swap_w_M_0101_N_1001,
	negc_M_0101_N_1001,
	neg_M_0101_N_1001,
	extu_b_M_0101_N_1001,
	extu_w_M_0101_N_1001,
	exts_b_M_0101_N_1001,
	exts_w_M_0101_N_1001,
	load_rm_rn_b_M_0110_N_1001,
	load_rm_rn_w_M_0110_N_1001,
	load_rm_rn_l_M_0110_N_1001,
	mov_rm_rn_M_0110_N_1001,
	load_postinc_rm_rn_b_M_0110_N_1001,
	load_postinc_rm_rn_w_M_0110_N_1001,
	load_postinc_rm_rn_l_M_0110_N_1001,
	not_M_0110_N_1001,
	swap_b_M_0110_N_1001,
	swap_w_M_0110_N_1001,
	negc_M_0110_N_1001,
	neg_M_0110_N_1001,
	extu_b_M_0110_N_1001,
	extu_w_M_0110_N_1001,
	exts_b_M_0110_N_1001,
	exts_w_M_0110_N_1001,
	load_rm_rn_b_M_0111_N_1001,
	load_rm_rn_w_M_0111_N_1001,
	load_rm_rn_l_M_0111_N_1001,
	mov_rm_rn_M_0111_N_1001,
	load_postinc_rm_rn_b_M_0111_N_1001,
	load_postinc_rm_rn_w_M_0111_N_1001,
	load_postinc_rm_rn_l_M_0111_N_1001,
	not_M_0111_N_1001,
	swap_b_M_0111_N_1001,
	swap_w_M_0111_N_1001,
	negc_M_0111_N_1001,
	neg_M_0111_N_1001,
	extu_b_M_0111_N_1001,
	extu_w_M_0111_N_1001,
	exts_b_M_0111_N_1001,
	exts_w_M_0111_N_1001,
	load_rm_rn_b_M_1000_N_1001,
	load_rm_rn_w_M_1000_N_1001,
	load_rm_rn_l_M_1000_N_1001,
	mov_rm_rn_M_1000_N_1001,
	load_postinc_rm_rn_b_M_1000_N_1001,
	load_postinc_rm_rn_w_M_1000_N_1001,
	load_postinc_rm_rn_l_M_1000_N_1001,
	not_M_1000_N_1001,
	swap_b_M_1000_N_1001,
	swap_w_M_1000_N_1001,
	negc_M_1000_N_1001,
	neg_M_1000_N_1001,
	extu_b_M_1000_N_1001,
	extu_w_M_1000_N_1001,
	exts_b_M_1000_N_1001,
	exts_w_M_1000_N_1001,
	load_rm_rn_b_M_1001_N_1001,
	load_rm_rn_w_M_1001_N_1001,
	load_rm_rn_l_M_1001_N_1001,
	mov_rm_rn_M_1001_N_1001,
	load_postinc_rm_rn_b_M_1001_N_1001,
	load_postinc_rm_rn_w_M_1001_N_1001,
	load_postinc_rm_rn_l_M_1001_N_1001,
	not_M_1001_N_1001,
	swap_b_M_1001_N_1001,
	swap_w_M_1001_N_1001,
	negc_M_1001_N_1001,
	neg_M_1001_N_1001,
	extu_b_M_1001_N_1001,
	extu_w_M_1001_N_1001,
	exts_b_M_1001_N_1001,
	exts_w_M_1001_N_1001,
	load_rm_rn_b_M_1010_N_1001,
	load_rm_rn_w_M_1010_N_1001,
	load_rm_rn_l_M_1010_N_1001,
	mov_rm_rn_M_1010_N_1001,
	load_postinc_rm_rn_b_M_1010_N_1001,
	load_postinc_rm_rn_w_M_1010_N_1001,
	load_postinc_rm_rn_l_M_1010_N_1001,
	not_M_1010_N_1001,
	swap_b_M_1010_N_1001,
	swap_w_M_1010_N_1001,
	negc_M_1010_N_1001,
	neg_M_1010_N_1001,
	extu_b_M_1010_N_1001,
	extu_w_M_1010_N_1001,
	exts_b_M_1010_N_1001,
	exts_w_M_1010_N_1001,
	load_rm_rn_b_M_1011_N_1001,
	load_rm_rn_w_M_1011_N_1001,
	load_rm_rn_l_M_1011_N_1001,
	mov_rm_rn_M_1011_N_1001,
	load_postinc_rm_rn_b_M_1011_N_1001,
	load_postinc_rm_rn_w_M_1011_N_1001,
	load_postinc_rm_rn_l_M_1011_N_1001,
	not_M_1011_N_1001,
	swap_b_M_1011_N_1001,
	swap_w_M_1011_N_1001,
	negc_M_1011_N_1001,
	neg_M_1011_N_1001,
	extu_b_M_1011_N_1001,
	extu_w_M_1011_N_1001,
	exts_b_M_1011_N_1001,
	exts_w_M_1011_N_1001,
	load_rm_rn_b_M_1100_N_1001,
	load_rm_rn_w_M_1100_N_1001,
	load_rm_rn_l_M_1100_N_1001,
	mov_rm_rn_M_1100_N_1001,
	load_postinc_rm_rn_b_M_1100_N_1001,
	load_postinc_rm_rn_w_M_1100_N_1001,
	load_postinc_rm_rn_l_M_1100_N_1001,
	not_M_1100_N_1001,
	swap_b_M_1100_N_1001,
	swap_w_M_1100_N_1001,
	negc_M_1100_N_1001,
	neg_M_1100_N_1001,
	extu_b_M_1100_N_1001,
	extu_w_M_1100_N_1001,
	exts_b_M_1100_N_1001,
	exts_w_M_1100_N_1001,
	load_rm_rn_b_M_1101_N_1001,
	load_rm_rn_w_M_1101_N_1001,
	load_rm_rn_l_M_1101_N_1001,
	mov_rm_rn_M_1101_N_1001,
	load_postinc_rm_rn_b_M_1101_N_1001,
	load_postinc_rm_rn_w_M_1101_N_1001,
	load_postinc_rm_rn_l_M_1101_N_1001,
	not_M_1101_N_1001,
	swap_b_M_1101_N_1001,
	swap_w_M_1101_N_1001,
	negc_M_1101_N_1001,
	neg_M_1101_N_1001,
	extu_b_M_1101_N_1001,
	extu_w_M_1101_N_1001,
	exts_b_M_1101_N_1001,
	exts_w_M_1101_N_1001,
	load_rm_rn_b_M_1110_N_1001,
	load_rm_rn_w_M_1110_N_1001,
	load_rm_rn_l_M_1110_N_1001,
	mov_rm_rn_M_1110_N_1001,
	load_postinc_rm_rn_b_M_1110_N_1001,
	load_postinc_rm_rn_w_M_1110_N_1001,
	load_postinc_rm_rn_l_M_1110_N_1001,
	not_M_1110_N_1001,
	swap_b_M_1110_N_1001,
	swap_w_M_1110_N_1001,
	negc_M_1110_N_1001,
	neg_M_1110_N_1001,
	extu_b_M_1110_N_1001,
	extu_w_M_1110_N_1001,
	exts_b_M_1110_N_1001,
	exts_w_M_1110_N_1001,
	load_rm_rn_b_M_1111_N_1001,
	load_rm_rn_w_M_1111_N_1001,
	load_rm_rn_l_M_1111_N_1001,
	mov_rm_rn_M_1111_N_1001,
	load_postinc_rm_rn_b_M_1111_N_1001,
	load_postinc_rm_rn_w_M_1111_N_1001,
	load_postinc_rm_rn_l_M_1111_N_1001,
	not_M_1111_N_1001,
	swap_b_M_1111_N_1001,
	swap_w_M_1111_N_1001,
	negc_M_1111_N_1001,
	neg_M_1111_N_1001,
	extu_b_M_1111_N_1001,
	extu_w_M_1111_N_1001,
	exts_b_M_1111_N_1001,
	exts_w_M_1111_N_1001,
	load_rm_rn_b_M_0000_N_1010,
	load_rm_rn_w_M_0000_N_1010,
	load_rm_rn_l_M_0000_N_1010,
	mov_rm_rn_M_0000_N_1010,
	load_postinc_rm_rn_b_M_0000_N_1010,
	load_postinc_rm_rn_w_M_0000_N_1010,
	load_postinc_rm_rn_l_M_0000_N_1010,
	not_M_0000_N_1010,
	swap_b_M_0000_N_1010,
	swap_w_M_0000_N_1010,
	negc_M_0000_N_1010,
	neg_M_0000_N_1010,
	extu_b_M_0000_N_1010,
	extu_w_M_0000_N_1010,
	exts_b_M_0000_N_1010,
	exts_w_M_0000_N_1010,
	load_rm_rn_b_M_0001_N_1010,
	load_rm_rn_w_M_0001_N_1010,
	load_rm_rn_l_M_0001_N_1010,
	mov_rm_rn_M_0001_N_1010,
	load_postinc_rm_rn_b_M_0001_N_1010,
	load_postinc_rm_rn_w_M_0001_N_1010,
	load_postinc_rm_rn_l_M_0001_N_1010,
	not_M_0001_N_1010,
	swap_b_M_0001_N_1010,
	swap_w_M_0001_N_1010,
	negc_M_0001_N_1010,
	neg_M_0001_N_1010,
	extu_b_M_0001_N_1010,
	extu_w_M_0001_N_1010,
	exts_b_M_0001_N_1010,
	exts_w_M_0001_N_1010,
	load_rm_rn_b_M_0010_N_1010,
	load_rm_rn_w_M_0010_N_1010,
	load_rm_rn_l_M_0010_N_1010,
	mov_rm_rn_M_0010_N_1010,
	load_postinc_rm_rn_b_M_0010_N_1010,
	load_postinc_rm_rn_w_M_0010_N_1010,
	load_postinc_rm_rn_l_M_0010_N_1010,
	not_M_0010_N_1010,
	swap_b_M_0010_N_1010,
	swap_w_M_0010_N_1010,
	negc_M_0010_N_1010,
	neg_M_0010_N_1010,
	extu_b_M_0010_N_1010,
	extu_w_M_0010_N_1010,
	exts_b_M_0010_N_1010,
	exts_w_M_0010_N_1010,
	load_rm_rn_b_M_0011_N_1010,
	load_rm_rn_w_M_0011_N_1010,
	load_rm_rn_l_M_0011_N_1010,
	mov_rm_rn_M_0011_N_1010,
	load_postinc_rm_rn_b_M_0011_N_1010,
	load_postinc_rm_rn_w_M_0011_N_1010,
	load_postinc_rm_rn_l_M_0011_N_1010,
	not_M_0011_N_1010,
	swap_b_M_0011_N_1010,
	swap_w_M_0011_N_1010,
	negc_M_0011_N_1010,
	neg_M_0011_N_1010,
	extu_b_M_0011_N_1010,
	extu_w_M_0011_N_1010,
	exts_b_M_0011_N_1010,
	exts_w_M_0011_N_1010,
	load_rm_rn_b_M_0100_N_1010,
	load_rm_rn_w_M_0100_N_1010,
	load_rm_rn_l_M_0100_N_1010,
	mov_rm_rn_M_0100_N_1010,
	load_postinc_rm_rn_b_M_0100_N_1010,
	load_postinc_rm_rn_w_M_0100_N_1010,
	load_postinc_rm_rn_l_M_0100_N_1010,
	not_M_0100_N_1010,
	swap_b_M_0100_N_1010,
	swap_w_M_0100_N_1010,
	negc_M_0100_N_1010,
	neg_M_0100_N_1010,
	extu_b_M_0100_N_1010,
	extu_w_M_0100_N_1010,
	exts_b_M_0100_N_1010,
	exts_w_M_0100_N_1010,
	load_rm_rn_b_M_0101_N_1010,
	load_rm_rn_w_M_0101_N_1010,
	load_rm_rn_l_M_0101_N_1010,
	mov_rm_rn_M_0101_N_1010,
	load_postinc_rm_rn_b_M_0101_N_1010,
	load_postinc_rm_rn_w_M_0101_N_1010,
	load_postinc_rm_rn_l_M_0101_N_1010,
	not_M_0101_N_1010,
	swap_b_M_0101_N_1010,
	swap_w_M_0101_N_1010,
	negc_M_0101_N_1010,
	neg_M_0101_N_1010,
	extu_b_M_0101_N_1010,
	extu_w_M_0101_N_1010,
	exts_b_M_0101_N_1010,
	exts_w_M_0101_N_1010,
	load_rm_rn_b_M_0110_N_1010,
	load_rm_rn_w_M_0110_N_1010,
	load_rm_rn_l_M_0110_N_1010,
	mov_rm_rn_M_0110_N_1010,
	load_postinc_rm_rn_b_M_0110_N_1010,
	load_postinc_rm_rn_w_M_0110_N_1010,
	load_postinc_rm_rn_l_M_0110_N_1010,
	not_M_0110_N_1010,
	swap_b_M_0110_N_1010,
	swap_w_M_0110_N_1010,
	negc_M_0110_N_1010,
	neg_M_0110_N_1010,
	extu_b_M_0110_N_1010,
	extu_w_M_0110_N_1010,
	exts_b_M_0110_N_1010,
	exts_w_M_0110_N_1010,
	load_rm_rn_b_M_0111_N_1010,
	load_rm_rn_w_M_0111_N_1010,
	load_rm_rn_l_M_0111_N_1010,
	mov_rm_rn_M_0111_N_1010,
	load_postinc_rm_rn_b_M_0111_N_1010,
	load_postinc_rm_rn_w_M_0111_N_1010,
	load_postinc_rm_rn_l_M_0111_N_1010,
	not_M_0111_N_1010,
	swap_b_M_0111_N_1010,
	swap_w_M_0111_N_1010,
	negc_M_0111_N_1010,
	neg_M_0111_N_1010,
	extu_b_M_0111_N_1010,
	extu_w_M_0111_N_1010,
	exts_b_M_0111_N_1010,
	exts_w_M_0111_N_1010,
	load_rm_rn_b_M_1000_N_1010,
	load_rm_rn_w_M_1000_N_1010,
	load_rm_rn_l_M_1000_N_1010,
	mov_rm_rn_M_1000_N_1010,
	load_postinc_rm_rn_b_M_1000_N_1010,
	load_postinc_rm_rn_w_M_1000_N_1010,
	load_postinc_rm_rn_l_M_1000_N_1010,
	not_M_1000_N_1010,
	swap_b_M_1000_N_1010,
	swap_w_M_1000_N_1010,
	negc_M_1000_N_1010,
	neg_M_1000_N_1010,
	extu_b_M_1000_N_1010,
	extu_w_M_1000_N_1010,
	exts_b_M_1000_N_1010,
	exts_w_M_1000_N_1010,
	load_rm_rn_b_M_1001_N_1010,
	load_rm_rn_w_M_1001_N_1010,
	load_rm_rn_l_M_1001_N_1010,
	mov_rm_rn_M_1001_N_1010,
	load_postinc_rm_rn_b_M_1001_N_1010,
	load_postinc_rm_rn_w_M_1001_N_1010,
	load_postinc_rm_rn_l_M_1001_N_1010,
	not_M_1001_N_1010,
	swap_b_M_1001_N_1010,
	swap_w_M_1001_N_1010,
	negc_M_1001_N_1010,
	neg_M_1001_N_1010,
	extu_b_M_1001_N_1010,
	extu_w_M_1001_N_1010,
	exts_b_M_1001_N_1010,
	exts_w_M_1001_N_1010,
	load_rm_rn_b_M_1010_N_1010,
	load_rm_rn_w_M_1010_N_1010,
	load_rm_rn_l_M_1010_N_1010,
	mov_rm_rn_M_1010_N_1010,
	load_postinc_rm_rn_b_M_1010_N_1010,
	load_postinc_rm_rn_w_M_1010_N_1010,
	load_postinc_rm_rn_l_M_1010_N_1010,
	not_M_1010_N_1010,
	swap_b_M_1010_N_1010,
	swap_w_M_1010_N_1010,
	negc_M_1010_N_1010,
	neg_M_1010_N_1010,
	extu_b_M_1010_N_1010,
	extu_w_M_1010_N_1010,
	exts_b_M_1010_N_1010,
	exts_w_M_1010_N_1010,
	load_rm_rn_b_M_1011_N_1010,
	load_rm_rn_w_M_1011_N_1010,
	load_rm_rn_l_M_1011_N_1010,
	mov_rm_rn_M_1011_N_1010,
	load_postinc_rm_rn_b_M_1011_N_1010,
	load_postinc_rm_rn_w_M_1011_N_1010,
	load_postinc_rm_rn_l_M_1011_N_1010,
	not_M_1011_N_1010,
	swap_b_M_1011_N_1010,
	swap_w_M_1011_N_1010,
	negc_M_1011_N_1010,
	neg_M_1011_N_1010,
	extu_b_M_1011_N_1010,
	extu_w_M_1011_N_1010,
	exts_b_M_1011_N_1010,
	exts_w_M_1011_N_1010,
	load_rm_rn_b_M_1100_N_1010,
	load_rm_rn_w_M_1100_N_1010,
	load_rm_rn_l_M_1100_N_1010,
	mov_rm_rn_M_1100_N_1010,
	load_postinc_rm_rn_b_M_1100_N_1010,
	load_postinc_rm_rn_w_M_1100_N_1010,
	load_postinc_rm_rn_l_M_1100_N_1010,
	not_M_1100_N_1010,
	swap_b_M_1100_N_1010,
	swap_w_M_1100_N_1010,
	negc_M_1100_N_1010,
	neg_M_1100_N_1010,
	extu_b_M_1100_N_1010,
	extu_w_M_1100_N_1010,
	exts_b_M_1100_N_1010,
	exts_w_M_1100_N_1010,
	load_rm_rn_b_M_1101_N_1010,
	load_rm_rn_w_M_1101_N_1010,
	load_rm_rn_l_M_1101_N_1010,
	mov_rm_rn_M_1101_N_1010,
	load_postinc_rm_rn_b_M_1101_N_1010,
	load_postinc_rm_rn_w_M_1101_N_1010,
	load_postinc_rm_rn_l_M_1101_N_1010,
	not_M_1101_N_1010,
	swap_b_M_1101_N_1010,
	swap_w_M_1101_N_1010,
	negc_M_1101_N_1010,
	neg_M_1101_N_1010,
	extu_b_M_1101_N_1010,
	extu_w_M_1101_N_1010,
	exts_b_M_1101_N_1010,
	exts_w_M_1101_N_1010,
	load_rm_rn_b_M_1110_N_1010,
	load_rm_rn_w_M_1110_N_1010,
	load_rm_rn_l_M_1110_N_1010,
	mov_rm_rn_M_1110_N_1010,
	load_postinc_rm_rn_b_M_1110_N_1010,
	load_postinc_rm_rn_w_M_1110_N_1010,
	load_postinc_rm_rn_l_M_1110_N_1010,
	not_M_1110_N_1010,
	swap_b_M_1110_N_1010,
	swap_w_M_1110_N_1010,
	negc_M_1110_N_1010,
	neg_M_1110_N_1010,
	extu_b_M_1110_N_1010,
	extu_w_M_1110_N_1010,
	exts_b_M_1110_N_1010,
	exts_w_M_1110_N_1010,
	load_rm_rn_b_M_1111_N_1010,
	load_rm_rn_w_M_1111_N_1010,
	load_rm_rn_l_M_1111_N_1010,
	mov_rm_rn_M_1111_N_1010,
	load_postinc_rm_rn_b_M_1111_N_1010,
	load_postinc_rm_rn_w_M_1111_N_1010,
	load_postinc_rm_rn_l_M_1111_N_1010,
	not_M_1111_N_1010,
	swap_b_M_1111_N_1010,
	swap_w_M_1111_N_1010,
	negc_M_1111_N_1010,
	neg_M_1111_N_1010,
	extu_b_M_1111_N_1010,
	extu_w_M_1111_N_1010,
	exts_b_M_1111_N_1010,
	exts_w_M_1111_N_1010,
	load_rm_rn_b_M_0000_N_1011,
	load_rm_rn_w_M_0000_N_1011,
	load_rm_rn_l_M_0000_N_1011,
	mov_rm_rn_M_0000_N_1011,
	load_postinc_rm_rn_b_M_0000_N_1011,
	load_postinc_rm_rn_w_M_0000_N_1011,
	load_postinc_rm_rn_l_M_0000_N_1011,
	not_M_0000_N_1011,
	swap_b_M_0000_N_1011,
	swap_w_M_0000_N_1011,
	negc_M_0000_N_1011,
	neg_M_0000_N_1011,
	extu_b_M_0000_N_1011,
	extu_w_M_0000_N_1011,
	exts_b_M_0000_N_1011,
	exts_w_M_0000_N_1011,
	load_rm_rn_b_M_0001_N_1011,
	load_rm_rn_w_M_0001_N_1011,
	load_rm_rn_l_M_0001_N_1011,
	mov_rm_rn_M_0001_N_1011,
	load_postinc_rm_rn_b_M_0001_N_1011,
	load_postinc_rm_rn_w_M_0001_N_1011,
	load_postinc_rm_rn_l_M_0001_N_1011,
	not_M_0001_N_1011,
	swap_b_M_0001_N_1011,
	swap_w_M_0001_N_1011,
	negc_M_0001_N_1011,
	neg_M_0001_N_1011,
	extu_b_M_0001_N_1011,
	extu_w_M_0001_N_1011,
	exts_b_M_0001_N_1011,
	exts_w_M_0001_N_1011,
	load_rm_rn_b_M_0010_N_1011,
	load_rm_rn_w_M_0010_N_1011,
	load_rm_rn_l_M_0010_N_1011,
	mov_rm_rn_M_0010_N_1011,
	load_postinc_rm_rn_b_M_0010_N_1011,
	load_postinc_rm_rn_w_M_0010_N_1011,
	load_postinc_rm_rn_l_M_0010_N_1011,
	not_M_0010_N_1011,
	swap_b_M_0010_N_1011,
	swap_w_M_0010_N_1011,
	negc_M_0010_N_1011,
	neg_M_0010_N_1011,
	extu_b_M_0010_N_1011,
	extu_w_M_0010_N_1011,
	exts_b_M_0010_N_1011,
	exts_w_M_0010_N_1011,
	load_rm_rn_b_M_0011_N_1011,
	load_rm_rn_w_M_0011_N_1011,
	load_rm_rn_l_M_0011_N_1011,
	mov_rm_rn_M_0011_N_1011,
	load_postinc_rm_rn_b_M_0011_N_1011,
	load_postinc_rm_rn_w_M_0011_N_1011,
	load_postinc_rm_rn_l_M_0011_N_1011,
	not_M_0011_N_1011,
	swap_b_M_0011_N_1011,
	swap_w_M_0011_N_1011,
	negc_M_0011_N_1011,
	neg_M_0011_N_1011,
	extu_b_M_0011_N_1011,
	extu_w_M_0011_N_1011,
	exts_b_M_0011_N_1011,
	exts_w_M_0011_N_1011,
	load_rm_rn_b_M_0100_N_1011,
	load_rm_rn_w_M_0100_N_1011,
	load_rm_rn_l_M_0100_N_1011,
	mov_rm_rn_M_0100_N_1011,
	load_postinc_rm_rn_b_M_0100_N_1011,
	load_postinc_rm_rn_w_M_0100_N_1011,
	load_postinc_rm_rn_l_M_0100_N_1011,
	not_M_0100_N_1011,
	swap_b_M_0100_N_1011,
	swap_w_M_0100_N_1011,
	negc_M_0100_N_1011,
	neg_M_0100_N_1011,
	extu_b_M_0100_N_1011,
	extu_w_M_0100_N_1011,
	exts_b_M_0100_N_1011,
	exts_w_M_0100_N_1011,
	load_rm_rn_b_M_0101_N_1011,
	load_rm_rn_w_M_0101_N_1011,
	load_rm_rn_l_M_0101_N_1011,
	mov_rm_rn_M_0101_N_1011,
	load_postinc_rm_rn_b_M_0101_N_1011,
	load_postinc_rm_rn_w_M_0101_N_1011,
	load_postinc_rm_rn_l_M_0101_N_1011,
	not_M_0101_N_1011,
	swap_b_M_0101_N_1011,
	swap_w_M_0101_N_1011,
	negc_M_0101_N_1011,
	neg_M_0101_N_1011,
	extu_b_M_0101_N_1011,
	extu_w_M_0101_N_1011,
	exts_b_M_0101_N_1011,
	exts_w_M_0101_N_1011,
	load_rm_rn_b_M_0110_N_1011,
	load_rm_rn_w_M_0110_N_1011,
	load_rm_rn_l_M_0110_N_1011,
	mov_rm_rn_M_0110_N_1011,
	load_postinc_rm_rn_b_M_0110_N_1011,
	load_postinc_rm_rn_w_M_0110_N_1011,
	load_postinc_rm_rn_l_M_0110_N_1011,
	not_M_0110_N_1011,
	swap_b_M_0110_N_1011,
	swap_w_M_0110_N_1011,
	negc_M_0110_N_1011,
	neg_M_0110_N_1011,
	extu_b_M_0110_N_1011,
	extu_w_M_0110_N_1011,
	exts_b_M_0110_N_1011,
	exts_w_M_0110_N_1011,
	load_rm_rn_b_M_0111_N_1011,
	load_rm_rn_w_M_0111_N_1011,
	load_rm_rn_l_M_0111_N_1011,
	mov_rm_rn_M_0111_N_1011,
	load_postinc_rm_rn_b_M_0111_N_1011,
	load_postinc_rm_rn_w_M_0111_N_1011,
	load_postinc_rm_rn_l_M_0111_N_1011,
	not_M_0111_N_1011,
	swap_b_M_0111_N_1011,
	swap_w_M_0111_N_1011,
	negc_M_0111_N_1011,
	neg_M_0111_N_1011,
	extu_b_M_0111_N_1011,
	extu_w_M_0111_N_1011,
	exts_b_M_0111_N_1011,
	exts_w_M_0111_N_1011,
	load_rm_rn_b_M_1000_N_1011,
	load_rm_rn_w_M_1000_N_1011,
	load_rm_rn_l_M_1000_N_1011,
	mov_rm_rn_M_1000_N_1011,
	load_postinc_rm_rn_b_M_1000_N_1011,
	load_postinc_rm_rn_w_M_1000_N_1011,
	load_postinc_rm_rn_l_M_1000_N_1011,
	not_M_1000_N_1011,
	swap_b_M_1000_N_1011,
	swap_w_M_1000_N_1011,
	negc_M_1000_N_1011,
	neg_M_1000_N_1011,
	extu_b_M_1000_N_1011,
	extu_w_M_1000_N_1011,
	exts_b_M_1000_N_1011,
	exts_w_M_1000_N_1011,
	load_rm_rn_b_M_1001_N_1011,
	load_rm_rn_w_M_1001_N_1011,
	load_rm_rn_l_M_1001_N_1011,
	mov_rm_rn_M_1001_N_1011,
	load_postinc_rm_rn_b_M_1001_N_1011,
	load_postinc_rm_rn_w_M_1001_N_1011,
	load_postinc_rm_rn_l_M_1001_N_1011,
	not_M_1001_N_1011,
	swap_b_M_1001_N_1011,
	swap_w_M_1001_N_1011,
	negc_M_1001_N_1011,
	neg_M_1001_N_1011,
	extu_b_M_1001_N_1011,
	extu_w_M_1001_N_1011,
	exts_b_M_1001_N_1011,
	exts_w_M_1001_N_1011,
	load_rm_rn_b_M_1010_N_1011,
	load_rm_rn_w_M_1010_N_1011,
	load_rm_rn_l_M_1010_N_1011,
	mov_rm_rn_M_1010_N_1011,
	load_postinc_rm_rn_b_M_1010_N_1011,
	load_postinc_rm_rn_w_M_1010_N_1011,
	load_postinc_rm_rn_l_M_1010_N_1011,
	not_M_1010_N_1011,
	swap_b_M_1010_N_1011,
	swap_w_M_1010_N_1011,
	negc_M_1010_N_1011,
	neg_M_1010_N_1011,
	extu_b_M_1010_N_1011,
	extu_w_M_1010_N_1011,
	exts_b_M_1010_N_1011,
	exts_w_M_1010_N_1011,
	load_rm_rn_b_M_1011_N_1011,
	load_rm_rn_w_M_1011_N_1011,
	load_rm_rn_l_M_1011_N_1011,
	mov_rm_rn_M_1011_N_1011,
	load_postinc_rm_rn_b_M_1011_N_1011,
	load_postinc_rm_rn_w_M_1011_N_1011,
	load_postinc_rm_rn_l_M_1011_N_1011,
	not_M_1011_N_1011,
	swap_b_M_1011_N_1011,
	swap_w_M_1011_N_1011,
	negc_M_1011_N_1011,
	neg_M_1011_N_1011,
	extu_b_M_1011_N_1011,
	extu_w_M_1011_N_1011,
	exts_b_M_1011_N_1011,
	exts_w_M_1011_N_1011,
	load_rm_rn_b_M_1100_N_1011,
	load_rm_rn_w_M_1100_N_1011,
	load_rm_rn_l_M_1100_N_1011,
	mov_rm_rn_M_1100_N_1011,
	load_postinc_rm_rn_b_M_1100_N_1011,
	load_postinc_rm_rn_w_M_1100_N_1011,
	load_postinc_rm_rn_l_M_1100_N_1011,
	not_M_1100_N_1011,
	swap_b_M_1100_N_1011,
	swap_w_M_1100_N_1011,
	negc_M_1100_N_1011,
	neg_M_1100_N_1011,
	extu_b_M_1100_N_1011,
	extu_w_M_1100_N_1011,
	exts_b_M_1100_N_1011,
	exts_w_M_1100_N_1011,
	load_rm_rn_b_M_1101_N_1011,
	load_rm_rn_w_M_1101_N_1011,
	load_rm_rn_l_M_1101_N_1011,
	mov_rm_rn_M_1101_N_1011,
	load_postinc_rm_rn_b_M_1101_N_1011,
	load_postinc_rm_rn_w_M_1101_N_1011,
	load_postinc_rm_rn_l_M_1101_N_1011,
	not_M_1101_N_1011,
	swap_b_M_1101_N_1011,
	swap_w_M_1101_N_1011,
	negc_M_1101_N_1011,
	neg_M_1101_N_1011,
	extu_b_M_1101_N_1011,
	extu_w_M_1101_N_1011,
	exts_b_M_1101_N_1011,
	exts_w_M_1101_N_1011,
	load_rm_rn_b_M_1110_N_1011,
	load_rm_rn_w_M_1110_N_1011,
	load_rm_rn_l_M_1110_N_1011,
	mov_rm_rn_M_1110_N_1011,
	load_postinc_rm_rn_b_M_1110_N_1011,
	load_postinc_rm_rn_w_M_1110_N_1011,
	load_postinc_rm_rn_l_M_1110_N_1011,
	not_M_1110_N_1011,
	swap_b_M_1110_N_1011,
	swap_w_M_1110_N_1011,
	negc_M_1110_N_1011,
	neg_M_1110_N_1011,
	extu_b_M_1110_N_1011,
	extu_w_M_1110_N_1011,
	exts_b_M_1110_N_1011,
	exts_w_M_1110_N_1011,
	load_rm_rn_b_M_1111_N_1011,
	load_rm_rn_w_M_1111_N_1011,
	load_rm_rn_l_M_1111_N_1011,
	mov_rm_rn_M_1111_N_1011,
	load_postinc_rm_rn_b_M_1111_N_1011,
	load_postinc_rm_rn_w_M_1111_N_1011,
	load_postinc_rm_rn_l_M_1111_N_1011,
	not_M_1111_N_1011,
	swap_b_M_1111_N_1011,
	swap_w_M_1111_N_1011,
	negc_M_1111_N_1011,
	neg_M_1111_N_1011,
	extu_b_M_1111_N_1011,
	extu_w_M_1111_N_1011,
	exts_b_M_1111_N_1011,
	exts_w_M_1111_N_1011,
	load_rm_rn_b_M_0000_N_1100,
	load_rm_rn_w_M_0000_N_1100,
	load_rm_rn_l_M_0000_N_1100,
	mov_rm_rn_M_0000_N_1100,
	load_postinc_rm_rn_b_M_0000_N_1100,
	load_postinc_rm_rn_w_M_0000_N_1100,
	load_postinc_rm_rn_l_M_0000_N_1100,
	not_M_0000_N_1100,
	swap_b_M_0000_N_1100,
	swap_w_M_0000_N_1100,
	negc_M_0000_N_1100,
	neg_M_0000_N_1100,
	extu_b_M_0000_N_1100,
	extu_w_M_0000_N_1100,
	exts_b_M_0000_N_1100,
	exts_w_M_0000_N_1100,
	load_rm_rn_b_M_0001_N_1100,
	load_rm_rn_w_M_0001_N_1100,
	load_rm_rn_l_M_0001_N_1100,
	mov_rm_rn_M_0001_N_1100,
	load_postinc_rm_rn_b_M_0001_N_1100,
	load_postinc_rm_rn_w_M_0001_N_1100,
	load_postinc_rm_rn_l_M_0001_N_1100,
	not_M_0001_N_1100,
	swap_b_M_0001_N_1100,
	swap_w_M_0001_N_1100,
	negc_M_0001_N_1100,
	neg_M_0001_N_1100,
	extu_b_M_0001_N_1100,
	extu_w_M_0001_N_1100,
	exts_b_M_0001_N_1100,
	exts_w_M_0001_N_1100,
	load_rm_rn_b_M_0010_N_1100,
	load_rm_rn_w_M_0010_N_1100,
	load_rm_rn_l_M_0010_N_1100,
	mov_rm_rn_M_0010_N_1100,
	load_postinc_rm_rn_b_M_0010_N_1100,
	load_postinc_rm_rn_w_M_0010_N_1100,
	load_postinc_rm_rn_l_M_0010_N_1100,
	not_M_0010_N_1100,
	swap_b_M_0010_N_1100,
	swap_w_M_0010_N_1100,
	negc_M_0010_N_1100,
	neg_M_0010_N_1100,
	extu_b_M_0010_N_1100,
	extu_w_M_0010_N_1100,
	exts_b_M_0010_N_1100,
	exts_w_M_0010_N_1100,
	load_rm_rn_b_M_0011_N_1100,
	load_rm_rn_w_M_0011_N_1100,
	load_rm_rn_l_M_0011_N_1100,
	mov_rm_rn_M_0011_N_1100,
	load_postinc_rm_rn_b_M_0011_N_1100,
	load_postinc_rm_rn_w_M_0011_N_1100,
	load_postinc_rm_rn_l_M_0011_N_1100,
	not_M_0011_N_1100,
	swap_b_M_0011_N_1100,
	swap_w_M_0011_N_1100,
	negc_M_0011_N_1100,
	neg_M_0011_N_1100,
	extu_b_M_0011_N_1100,
	extu_w_M_0011_N_1100,
	exts_b_M_0011_N_1100,
	exts_w_M_0011_N_1100,
	load_rm_rn_b_M_0100_N_1100,
	load_rm_rn_w_M_0100_N_1100,
	load_rm_rn_l_M_0100_N_1100,
	mov_rm_rn_M_0100_N_1100,
	load_postinc_rm_rn_b_M_0100_N_1100,
	load_postinc_rm_rn_w_M_0100_N_1100,
	load_postinc_rm_rn_l_M_0100_N_1100,
	not_M_0100_N_1100,
	swap_b_M_0100_N_1100,
	swap_w_M_0100_N_1100,
	negc_M_0100_N_1100,
	neg_M_0100_N_1100,
	extu_b_M_0100_N_1100,
	extu_w_M_0100_N_1100,
	exts_b_M_0100_N_1100,
	exts_w_M_0100_N_1100,
	load_rm_rn_b_M_0101_N_1100,
	load_rm_rn_w_M_0101_N_1100,
	load_rm_rn_l_M_0101_N_1100,
	mov_rm_rn_M_0101_N_1100,
	load_postinc_rm_rn_b_M_0101_N_1100,
	load_postinc_rm_rn_w_M_0101_N_1100,
	load_postinc_rm_rn_l_M_0101_N_1100,
	not_M_0101_N_1100,
	swap_b_M_0101_N_1100,
	swap_w_M_0101_N_1100,
	negc_M_0101_N_1100,
	neg_M_0101_N_1100,
	extu_b_M_0101_N_1100,
	extu_w_M_0101_N_1100,
	exts_b_M_0101_N_1100,
	exts_w_M_0101_N_1100,
	load_rm_rn_b_M_0110_N_1100,
	load_rm_rn_w_M_0110_N_1100,
	load_rm_rn_l_M_0110_N_1100,
	mov_rm_rn_M_0110_N_1100,
	load_postinc_rm_rn_b_M_0110_N_1100,
	load_postinc_rm_rn_w_M_0110_N_1100,
	load_postinc_rm_rn_l_M_0110_N_1100,
	not_M_0110_N_1100,
	swap_b_M_0110_N_1100,
	swap_w_M_0110_N_1100,
	negc_M_0110_N_1100,
	neg_M_0110_N_1100,
	extu_b_M_0110_N_1100,
	extu_w_M_0110_N_1100,
	exts_b_M_0110_N_1100,
	exts_w_M_0110_N_1100,
	load_rm_rn_b_M_0111_N_1100,
	load_rm_rn_w_M_0111_N_1100,
	load_rm_rn_l_M_0111_N_1100,
	mov_rm_rn_M_0111_N_1100,
	load_postinc_rm_rn_b_M_0111_N_1100,
	load_postinc_rm_rn_w_M_0111_N_1100,
	load_postinc_rm_rn_l_M_0111_N_1100,
	not_M_0111_N_1100,
	swap_b_M_0111_N_1100,
	swap_w_M_0111_N_1100,
	negc_M_0111_N_1100,
	neg_M_0111_N_1100,
	extu_b_M_0111_N_1100,
	extu_w_M_0111_N_1100,
	exts_b_M_0111_N_1100,
	exts_w_M_0111_N_1100,
	load_rm_rn_b_M_1000_N_1100,
	load_rm_rn_w_M_1000_N_1100,
	load_rm_rn_l_M_1000_N_1100,
	mov_rm_rn_M_1000_N_1100,
	load_postinc_rm_rn_b_M_1000_N_1100,
	load_postinc_rm_rn_w_M_1000_N_1100,
	load_postinc_rm_rn_l_M_1000_N_1100,
	not_M_1000_N_1100,
	swap_b_M_1000_N_1100,
	swap_w_M_1000_N_1100,
	negc_M_1000_N_1100,
	neg_M_1000_N_1100,
	extu_b_M_1000_N_1100,
	extu_w_M_1000_N_1100,
	exts_b_M_1000_N_1100,
	exts_w_M_1000_N_1100,
	load_rm_rn_b_M_1001_N_1100,
	load_rm_rn_w_M_1001_N_1100,
	load_rm_rn_l_M_1001_N_1100,
	mov_rm_rn_M_1001_N_1100,
	load_postinc_rm_rn_b_M_1001_N_1100,
	load_postinc_rm_rn_w_M_1001_N_1100,
	load_postinc_rm_rn_l_M_1001_N_1100,
	not_M_1001_N_1100,
	swap_b_M_1001_N_1100,
	swap_w_M_1001_N_1100,
	negc_M_1001_N_1100,
	neg_M_1001_N_1100,
	extu_b_M_1001_N_1100,
	extu_w_M_1001_N_1100,
	exts_b_M_1001_N_1100,
	exts_w_M_1001_N_1100,
	load_rm_rn_b_M_1010_N_1100,
	load_rm_rn_w_M_1010_N_1100,
	load_rm_rn_l_M_1010_N_1100,
	mov_rm_rn_M_1010_N_1100,
	load_postinc_rm_rn_b_M_1010_N_1100,
	load_postinc_rm_rn_w_M_1010_N_1100,
	load_postinc_rm_rn_l_M_1010_N_1100,
	not_M_1010_N_1100,
	swap_b_M_1010_N_1100,
	swap_w_M_1010_N_1100,
	negc_M_1010_N_1100,
	neg_M_1010_N_1100,
	extu_b_M_1010_N_1100,
	extu_w_M_1010_N_1100,
	exts_b_M_1010_N_1100,
	exts_w_M_1010_N_1100,
	load_rm_rn_b_M_1011_N_1100,
	load_rm_rn_w_M_1011_N_1100,
	load_rm_rn_l_M_1011_N_1100,
	mov_rm_rn_M_1011_N_1100,
	load_postinc_rm_rn_b_M_1011_N_1100,
	load_postinc_rm_rn_w_M_1011_N_1100,
	load_postinc_rm_rn_l_M_1011_N_1100,
	not_M_1011_N_1100,
	swap_b_M_1011_N_1100,
	swap_w_M_1011_N_1100,
	negc_M_1011_N_1100,
	neg_M_1011_N_1100,
	extu_b_M_1011_N_1100,
	extu_w_M_1011_N_1100,
	exts_b_M_1011_N_1100,
	exts_w_M_1011_N_1100,
	load_rm_rn_b_M_1100_N_1100,
	load_rm_rn_w_M_1100_N_1100,
	load_rm_rn_l_M_1100_N_1100,
	mov_rm_rn_M_1100_N_1100,
	load_postinc_rm_rn_b_M_1100_N_1100,
	load_postinc_rm_rn_w_M_1100_N_1100,
	load_postinc_rm_rn_l_M_1100_N_1100,
	not_M_1100_N_1100,
	swap_b_M_1100_N_1100,
	swap_w_M_1100_N_1100,
	negc_M_1100_N_1100,
	neg_M_1100_N_1100,
	extu_b_M_1100_N_1100,
	extu_w_M_1100_N_1100,
	exts_b_M_1100_N_1100,
	exts_w_M_1100_N_1100,
	load_rm_rn_b_M_1101_N_1100,
	load_rm_rn_w_M_1101_N_1100,
	load_rm_rn_l_M_1101_N_1100,
	mov_rm_rn_M_1101_N_1100,
	load_postinc_rm_rn_b_M_1101_N_1100,
	load_postinc_rm_rn_w_M_1101_N_1100,
	load_postinc_rm_rn_l_M_1101_N_1100,
	not_M_1101_N_1100,
	swap_b_M_1101_N_1100,
	swap_w_M_1101_N_1100,
	negc_M_1101_N_1100,
	neg_M_1101_N_1100,
	extu_b_M_1101_N_1100,
	extu_w_M_1101_N_1100,
	exts_b_M_1101_N_1100,
	exts_w_M_1101_N_1100,
	load_rm_rn_b_M_1110_N_1100,
	load_rm_rn_w_M_1110_N_1100,
	load_rm_rn_l_M_1110_N_1100,
	mov_rm_rn_M_1110_N_1100,
	load_postinc_rm_rn_b_M_1110_N_1100,
	load_postinc_rm_rn_w_M_1110_N_1100,
	load_postinc_rm_rn_l_M_1110_N_1100,
	not_M_1110_N_1100,
	swap_b_M_1110_N_1100,
	swap_w_M_1110_N_1100,
	negc_M_1110_N_1100,
	neg_M_1110_N_1100,
	extu_b_M_1110_N_1100,
	extu_w_M_1110_N_1100,
	exts_b_M_1110_N_1100,
	exts_w_M_1110_N_1100,
	load_rm_rn_b_M_1111_N_1100,
	load_rm_rn_w_M_1111_N_1100,
	load_rm_rn_l_M_1111_N_1100,
	mov_rm_rn_M_1111_N_1100,
	load_postinc_rm_rn_b_M_1111_N_1100,
	load_postinc_rm_rn_w_M_1111_N_1100,
	load_postinc_rm_rn_l_M_1111_N_1100,
	not_M_1111_N_1100,
	swap_b_M_1111_N_1100,
	swap_w_M_1111_N_1100,
	negc_M_1111_N_1100,
	neg_M_1111_N_1100,
	extu_b_M_1111_N_1100,
	extu_w_M_1111_N_1100,
	exts_b_M_1111_N_1100,
	exts_w_M_1111_N_1100,
	load_rm_rn_b_M_0000_N_1101,
	load_rm_rn_w_M_0000_N_1101,
	load_rm_rn_l_M_0000_N_1101,
	mov_rm_rn_M_0000_N_1101,
	load_postinc_rm_rn_b_M_0000_N_1101,
	load_postinc_rm_rn_w_M_0000_N_1101,
	load_postinc_rm_rn_l_M_0000_N_1101,
	not_M_0000_N_1101,
	swap_b_M_0000_N_1101,
	swap_w_M_0000_N_1101,
	negc_M_0000_N_1101,
	neg_M_0000_N_1101,
	extu_b_M_0000_N_1101,
	extu_w_M_0000_N_1101,
	exts_b_M_0000_N_1101,
	exts_w_M_0000_N_1101,
	load_rm_rn_b_M_0001_N_1101,
	load_rm_rn_w_M_0001_N_1101,
	load_rm_rn_l_M_0001_N_1101,
	mov_rm_rn_M_0001_N_1101,
	load_postinc_rm_rn_b_M_0001_N_1101,
	load_postinc_rm_rn_w_M_0001_N_1101,
	load_postinc_rm_rn_l_M_0001_N_1101,
	not_M_0001_N_1101,
	swap_b_M_0001_N_1101,
	swap_w_M_0001_N_1101,
	negc_M_0001_N_1101,
	neg_M_0001_N_1101,
	extu_b_M_0001_N_1101,
	extu_w_M_0001_N_1101,
	exts_b_M_0001_N_1101,
	exts_w_M_0001_N_1101,
	load_rm_rn_b_M_0010_N_1101,
	load_rm_rn_w_M_0010_N_1101,
	load_rm_rn_l_M_0010_N_1101,
	mov_rm_rn_M_0010_N_1101,
	load_postinc_rm_rn_b_M_0010_N_1101,
	load_postinc_rm_rn_w_M_0010_N_1101,
	load_postinc_rm_rn_l_M_0010_N_1101,
	not_M_0010_N_1101,
	swap_b_M_0010_N_1101,
	swap_w_M_0010_N_1101,
	negc_M_0010_N_1101,
	neg_M_0010_N_1101,
	extu_b_M_0010_N_1101,
	extu_w_M_0010_N_1101,
	exts_b_M_0010_N_1101,
	exts_w_M_0010_N_1101,
	load_rm_rn_b_M_0011_N_1101,
	load_rm_rn_w_M_0011_N_1101,
	load_rm_rn_l_M_0011_N_1101,
	mov_rm_rn_M_0011_N_1101,
	load_postinc_rm_rn_b_M_0011_N_1101,
	load_postinc_rm_rn_w_M_0011_N_1101,
	load_postinc_rm_rn_l_M_0011_N_1101,
	not_M_0011_N_1101,
	swap_b_M_0011_N_1101,
	swap_w_M_0011_N_1101,
	negc_M_0011_N_1101,
	neg_M_0011_N_1101,
	extu_b_M_0011_N_1101,
	extu_w_M_0011_N_1101,
	exts_b_M_0011_N_1101,
	exts_w_M_0011_N_1101,
	load_rm_rn_b_M_0100_N_1101,
	load_rm_rn_w_M_0100_N_1101,
	load_rm_rn_l_M_0100_N_1101,
	mov_rm_rn_M_0100_N_1101,
	load_postinc_rm_rn_b_M_0100_N_1101,
	load_postinc_rm_rn_w_M_0100_N_1101,
	load_postinc_rm_rn_l_M_0100_N_1101,
	not_M_0100_N_1101,
	swap_b_M_0100_N_1101,
	swap_w_M_0100_N_1101,
	negc_M_0100_N_1101,
	neg_M_0100_N_1101,
	extu_b_M_0100_N_1101,
	extu_w_M_0100_N_1101,
	exts_b_M_0100_N_1101,
	exts_w_M_0100_N_1101,
	load_rm_rn_b_M_0101_N_1101,
	load_rm_rn_w_M_0101_N_1101,
	load_rm_rn_l_M_0101_N_1101,
	mov_rm_rn_M_0101_N_1101,
	load_postinc_rm_rn_b_M_0101_N_1101,
	load_postinc_rm_rn_w_M_0101_N_1101,
	load_postinc_rm_rn_l_M_0101_N_1101,
	not_M_0101_N_1101,
	swap_b_M_0101_N_1101,
	swap_w_M_0101_N_1101,
	negc_M_0101_N_1101,
	neg_M_0101_N_1101,
	extu_b_M_0101_N_1101,
	extu_w_M_0101_N_1101,
	exts_b_M_0101_N_1101,
	exts_w_M_0101_N_1101,
	load_rm_rn_b_M_0110_N_1101,
	load_rm_rn_w_M_0110_N_1101,
	load_rm_rn_l_M_0110_N_1101,
	mov_rm_rn_M_0110_N_1101,
	load_postinc_rm_rn_b_M_0110_N_1101,
	load_postinc_rm_rn_w_M_0110_N_1101,
	load_postinc_rm_rn_l_M_0110_N_1101,
	not_M_0110_N_1101,
	swap_b_M_0110_N_1101,
	swap_w_M_0110_N_1101,
	negc_M_0110_N_1101,
	neg_M_0110_N_1101,
	extu_b_M_0110_N_1101,
	extu_w_M_0110_N_1101,
	exts_b_M_0110_N_1101,
	exts_w_M_0110_N_1101,
	load_rm_rn_b_M_0111_N_1101,
	load_rm_rn_w_M_0111_N_1101,
	load_rm_rn_l_M_0111_N_1101,
	mov_rm_rn_M_0111_N_1101,
	load_postinc_rm_rn_b_M_0111_N_1101,
	load_postinc_rm_rn_w_M_0111_N_1101,
	load_postinc_rm_rn_l_M_0111_N_1101,
	not_M_0111_N_1101,
	swap_b_M_0111_N_1101,
	swap_w_M_0111_N_1101,
	negc_M_0111_N_1101,
	neg_M_0111_N_1101,
	extu_b_M_0111_N_1101,
	extu_w_M_0111_N_1101,
	exts_b_M_0111_N_1101,
	exts_w_M_0111_N_1101,
	load_rm_rn_b_M_1000_N_1101,
	load_rm_rn_w_M_1000_N_1101,
	load_rm_rn_l_M_1000_N_1101,
	mov_rm_rn_M_1000_N_1101,
	load_postinc_rm_rn_b_M_1000_N_1101,
	load_postinc_rm_rn_w_M_1000_N_1101,
	load_postinc_rm_rn_l_M_1000_N_1101,
	not_M_1000_N_1101,
	swap_b_M_1000_N_1101,
	swap_w_M_1000_N_1101,
	negc_M_1000_N_1101,
	neg_M_1000_N_1101,
	extu_b_M_1000_N_1101,
	extu_w_M_1000_N_1101,
	exts_b_M_1000_N_1101,
	exts_w_M_1000_N_1101,
	load_rm_rn_b_M_1001_N_1101,
	load_rm_rn_w_M_1001_N_1101,
	load_rm_rn_l_M_1001_N_1101,
	mov_rm_rn_M_1001_N_1101,
	load_postinc_rm_rn_b_M_1001_N_1101,
	load_postinc_rm_rn_w_M_1001_N_1101,
	load_postinc_rm_rn_l_M_1001_N_1101,
	not_M_1001_N_1101,
	swap_b_M_1001_N_1101,
	swap_w_M_1001_N_1101,
	negc_M_1001_N_1101,
	neg_M_1001_N_1101,
	extu_b_M_1001_N_1101,
	extu_w_M_1001_N_1101,
	exts_b_M_1001_N_1101,
	exts_w_M_1001_N_1101,
	load_rm_rn_b_M_1010_N_1101,
	load_rm_rn_w_M_1010_N_1101,
	load_rm_rn_l_M_1010_N_1101,
	mov_rm_rn_M_1010_N_1101,
	load_postinc_rm_rn_b_M_1010_N_1101,
	load_postinc_rm_rn_w_M_1010_N_1101,
	load_postinc_rm_rn_l_M_1010_N_1101,
	not_M_1010_N_1101,
	swap_b_M_1010_N_1101,
	swap_w_M_1010_N_1101,
	negc_M_1010_N_1101,
	neg_M_1010_N_1101,
	extu_b_M_1010_N_1101,
	extu_w_M_1010_N_1101,
	exts_b_M_1010_N_1101,
	exts_w_M_1010_N_1101,
	load_rm_rn_b_M_1011_N_1101,
	load_rm_rn_w_M_1011_N_1101,
	load_rm_rn_l_M_1011_N_1101,
	mov_rm_rn_M_1011_N_1101,
	load_postinc_rm_rn_b_M_1011_N_1101,
	load_postinc_rm_rn_w_M_1011_N_1101,
	load_postinc_rm_rn_l_M_1011_N_1101,
	not_M_1011_N_1101,
	swap_b_M_1011_N_1101,
	swap_w_M_1011_N_1101,
	negc_M_1011_N_1101,
	neg_M_1011_N_1101,
	extu_b_M_1011_N_1101,
	extu_w_M_1011_N_1101,
	exts_b_M_1011_N_1101,
	exts_w_M_1011_N_1101,
	load_rm_rn_b_M_1100_N_1101,
	load_rm_rn_w_M_1100_N_1101,
	load_rm_rn_l_M_1100_N_1101,
	mov_rm_rn_M_1100_N_1101,
	load_postinc_rm_rn_b_M_1100_N_1101,
	load_postinc_rm_rn_w_M_1100_N_1101,
	load_postinc_rm_rn_l_M_1100_N_1101,
	not_M_1100_N_1101,
	swap_b_M_1100_N_1101,
	swap_w_M_1100_N_1101,
	negc_M_1100_N_1101,
	neg_M_1100_N_1101,
	extu_b_M_1100_N_1101,
	extu_w_M_1100_N_1101,
	exts_b_M_1100_N_1101,
	exts_w_M_1100_N_1101,
	load_rm_rn_b_M_1101_N_1101,
	load_rm_rn_w_M_1101_N_1101,
	load_rm_rn_l_M_1101_N_1101,
	mov_rm_rn_M_1101_N_1101,
	load_postinc_rm_rn_b_M_1101_N_1101,
	load_postinc_rm_rn_w_M_1101_N_1101,
	load_postinc_rm_rn_l_M_1101_N_1101,
	not_M_1101_N_1101,
	swap_b_M_1101_N_1101,
	swap_w_M_1101_N_1101,
	negc_M_1101_N_1101,
	neg_M_1101_N_1101,
	extu_b_M_1101_N_1101,
	extu_w_M_1101_N_1101,
	exts_b_M_1101_N_1101,
	exts_w_M_1101_N_1101,
	load_rm_rn_b_M_1110_N_1101,
	load_rm_rn_w_M_1110_N_1101,
	load_rm_rn_l_M_1110_N_1101,
	mov_rm_rn_M_1110_N_1101,
	load_postinc_rm_rn_b_M_1110_N_1101,
	load_postinc_rm_rn_w_M_1110_N_1101,
	load_postinc_rm_rn_l_M_1110_N_1101,
	not_M_1110_N_1101,
	swap_b_M_1110_N_1101,
	swap_w_M_1110_N_1101,
	negc_M_1110_N_1101,
	neg_M_1110_N_1101,
	extu_b_M_1110_N_1101,
	extu_w_M_1110_N_1101,
	exts_b_M_1110_N_1101,
	exts_w_M_1110_N_1101,
	load_rm_rn_b_M_1111_N_1101,
	load_rm_rn_w_M_1111_N_1101,
	load_rm_rn_l_M_1111_N_1101,
	mov_rm_rn_M_1111_N_1101,
	load_postinc_rm_rn_b_M_1111_N_1101,
	load_postinc_rm_rn_w_M_1111_N_1101,
	load_postinc_rm_rn_l_M_1111_N_1101,
	not_M_1111_N_1101,
	swap_b_M_1111_N_1101,
	swap_w_M_1111_N_1101,
	negc_M_1111_N_1101,
	neg_M_1111_N_1101,
	extu_b_M_1111_N_1101,
	extu_w_M_1111_N_1101,
	exts_b_M_1111_N_1101,
	exts_w_M_1111_N_1101,
	load_rm_rn_b_M_0000_N_1110,
	load_rm_rn_w_M_0000_N_1110,
	load_rm_rn_l_M_0000_N_1110,
	mov_rm_rn_M_0000_N_1110,
	load_postinc_rm_rn_b_M_0000_N_1110,
	load_postinc_rm_rn_w_M_0000_N_1110,
	load_postinc_rm_rn_l_M_0000_N_1110,
	not_M_0000_N_1110,
	swap_b_M_0000_N_1110,
	swap_w_M_0000_N_1110,
	negc_M_0000_N_1110,
	neg_M_0000_N_1110,
	extu_b_M_0000_N_1110,
	extu_w_M_0000_N_1110,
	exts_b_M_0000_N_1110,
	exts_w_M_0000_N_1110,
	load_rm_rn_b_M_0001_N_1110,
	load_rm_rn_w_M_0001_N_1110,
	load_rm_rn_l_M_0001_N_1110,
	mov_rm_rn_M_0001_N_1110,
	load_postinc_rm_rn_b_M_0001_N_1110,
	load_postinc_rm_rn_w_M_0001_N_1110,
	load_postinc_rm_rn_l_M_0001_N_1110,
	not_M_0001_N_1110,
	swap_b_M_0001_N_1110,
	swap_w_M_0001_N_1110,
	negc_M_0001_N_1110,
	neg_M_0001_N_1110,
	extu_b_M_0001_N_1110,
	extu_w_M_0001_N_1110,
	exts_b_M_0001_N_1110,
	exts_w_M_0001_N_1110,
	load_rm_rn_b_M_0010_N_1110,
	load_rm_rn_w_M_0010_N_1110,
	load_rm_rn_l_M_0010_N_1110,
	mov_rm_rn_M_0010_N_1110,
	load_postinc_rm_rn_b_M_0010_N_1110,
	load_postinc_rm_rn_w_M_0010_N_1110,
	load_postinc_rm_rn_l_M_0010_N_1110,
	not_M_0010_N_1110,
	swap_b_M_0010_N_1110,
	swap_w_M_0010_N_1110,
	negc_M_0010_N_1110,
	neg_M_0010_N_1110,
	extu_b_M_0010_N_1110,
	extu_w_M_0010_N_1110,
	exts_b_M_0010_N_1110,
	exts_w_M_0010_N_1110,
	load_rm_rn_b_M_0011_N_1110,
	load_rm_rn_w_M_0011_N_1110,
	load_rm_rn_l_M_0011_N_1110,
	mov_rm_rn_M_0011_N_1110,
	load_postinc_rm_rn_b_M_0011_N_1110,
	load_postinc_rm_rn_w_M_0011_N_1110,
	load_postinc_rm_rn_l_M_0011_N_1110,
	not_M_0011_N_1110,
	swap_b_M_0011_N_1110,
	swap_w_M_0011_N_1110,
	negc_M_0011_N_1110,
	neg_M_0011_N_1110,
	extu_b_M_0011_N_1110,
	extu_w_M_0011_N_1110,
	exts_b_M_0011_N_1110,
	exts_w_M_0011_N_1110,
	load_rm_rn_b_M_0100_N_1110,
	load_rm_rn_w_M_0100_N_1110,
	load_rm_rn_l_M_0100_N_1110,
	mov_rm_rn_M_0100_N_1110,
	load_postinc_rm_rn_b_M_0100_N_1110,
	load_postinc_rm_rn_w_M_0100_N_1110,
	load_postinc_rm_rn_l_M_0100_N_1110,
	not_M_0100_N_1110,
	swap_b_M_0100_N_1110,
	swap_w_M_0100_N_1110,
	negc_M_0100_N_1110,
	neg_M_0100_N_1110,
	extu_b_M_0100_N_1110,
	extu_w_M_0100_N_1110,
	exts_b_M_0100_N_1110,
	exts_w_M_0100_N_1110,
	load_rm_rn_b_M_0101_N_1110,
	load_rm_rn_w_M_0101_N_1110,
	load_rm_rn_l_M_0101_N_1110,
	mov_rm_rn_M_0101_N_1110,
	load_postinc_rm_rn_b_M_0101_N_1110,
	load_postinc_rm_rn_w_M_0101_N_1110,
	load_postinc_rm_rn_l_M_0101_N_1110,
	not_M_0101_N_1110,
	swap_b_M_0101_N_1110,
	swap_w_M_0101_N_1110,
	negc_M_0101_N_1110,
	neg_M_0101_N_1110,
	extu_b_M_0101_N_1110,
	extu_w_M_0101_N_1110,
	exts_b_M_0101_N_1110,
	exts_w_M_0101_N_1110,
	load_rm_rn_b_M_0110_N_1110,
	load_rm_rn_w_M_0110_N_1110,
	load_rm_rn_l_M_0110_N_1110,
	mov_rm_rn_M_0110_N_1110,
	load_postinc_rm_rn_b_M_0110_N_1110,
	load_postinc_rm_rn_w_M_0110_N_1110,
	load_postinc_rm_rn_l_M_0110_N_1110,
	not_M_0110_N_1110,
	swap_b_M_0110_N_1110,
	swap_w_M_0110_N_1110,
	negc_M_0110_N_1110,
	neg_M_0110_N_1110,
	extu_b_M_0110_N_1110,
	extu_w_M_0110_N_1110,
	exts_b_M_0110_N_1110,
	exts_w_M_0110_N_1110,
	load_rm_rn_b_M_0111_N_1110,
	load_rm_rn_w_M_0111_N_1110,
	load_rm_rn_l_M_0111_N_1110,
	mov_rm_rn_M_0111_N_1110,
	load_postinc_rm_rn_b_M_0111_N_1110,
	load_postinc_rm_rn_w_M_0111_N_1110,
	load_postinc_rm_rn_l_M_0111_N_1110,
	not_M_0111_N_1110,
	swap_b_M_0111_N_1110,
	swap_w_M_0111_N_1110,
	negc_M_0111_N_1110,
	neg_M_0111_N_1110,
	extu_b_M_0111_N_1110,
	extu_w_M_0111_N_1110,
	exts_b_M_0111_N_1110,
	exts_w_M_0111_N_1110,
	load_rm_rn_b_M_1000_N_1110,
	load_rm_rn_w_M_1000_N_1110,
	load_rm_rn_l_M_1000_N_1110,
	mov_rm_rn_M_1000_N_1110,
	load_postinc_rm_rn_b_M_1000_N_1110,
	load_postinc_rm_rn_w_M_1000_N_1110,
	load_postinc_rm_rn_l_M_1000_N_1110,
	not_M_1000_N_1110,
	swap_b_M_1000_N_1110,
	swap_w_M_1000_N_1110,
	negc_M_1000_N_1110,
	neg_M_1000_N_1110,
	extu_b_M_1000_N_1110,
	extu_w_M_1000_N_1110,
	exts_b_M_1000_N_1110,
	exts_w_M_1000_N_1110,
	load_rm_rn_b_M_1001_N_1110,
	load_rm_rn_w_M_1001_N_1110,
	load_rm_rn_l_M_1001_N_1110,
	mov_rm_rn_M_1001_N_1110,
	load_postinc_rm_rn_b_M_1001_N_1110,
	load_postinc_rm_rn_w_M_1001_N_1110,
	load_postinc_rm_rn_l_M_1001_N_1110,
	not_M_1001_N_1110,
	swap_b_M_1001_N_1110,
	swap_w_M_1001_N_1110,
	negc_M_1001_N_1110,
	neg_M_1001_N_1110,
	extu_b_M_1001_N_1110,
	extu_w_M_1001_N_1110,
	exts_b_M_1001_N_1110,
	exts_w_M_1001_N_1110,
	load_rm_rn_b_M_1010_N_1110,
	load_rm_rn_w_M_1010_N_1110,
	load_rm_rn_l_M_1010_N_1110,
	mov_rm_rn_M_1010_N_1110,
	load_postinc_rm_rn_b_M_1010_N_1110,
	load_postinc_rm_rn_w_M_1010_N_1110,
	load_postinc_rm_rn_l_M_1010_N_1110,
	not_M_1010_N_1110,
	swap_b_M_1010_N_1110,
	swap_w_M_1010_N_1110,
	negc_M_1010_N_1110,
	neg_M_1010_N_1110,
	extu_b_M_1010_N_1110,
	extu_w_M_1010_N_1110,
	exts_b_M_1010_N_1110,
	exts_w_M_1010_N_1110,
	load_rm_rn_b_M_1011_N_1110,
	load_rm_rn_w_M_1011_N_1110,
	load_rm_rn_l_M_1011_N_1110,
	mov_rm_rn_M_1011_N_1110,
	load_postinc_rm_rn_b_M_1011_N_1110,
	load_postinc_rm_rn_w_M_1011_N_1110,
	load_postinc_rm_rn_l_M_1011_N_1110,
	not_M_1011_N_1110,
	swap_b_M_1011_N_1110,
	swap_w_M_1011_N_1110,
	negc_M_1011_N_1110,
	neg_M_1011_N_1110,
	extu_b_M_1011_N_1110,
	extu_w_M_1011_N_1110,
	exts_b_M_1011_N_1110,
	exts_w_M_1011_N_1110,
	load_rm_rn_b_M_1100_N_1110,
	load_rm_rn_w_M_1100_N_1110,
	load_rm_rn_l_M_1100_N_1110,
	mov_rm_rn_M_1100_N_1110,
	load_postinc_rm_rn_b_M_1100_N_1110,
	load_postinc_rm_rn_w_M_1100_N_1110,
	load_postinc_rm_rn_l_M_1100_N_1110,
	not_M_1100_N_1110,
	swap_b_M_1100_N_1110,
	swap_w_M_1100_N_1110,
	negc_M_1100_N_1110,
	neg_M_1100_N_1110,
	extu_b_M_1100_N_1110,
	extu_w_M_1100_N_1110,
	exts_b_M_1100_N_1110,
	exts_w_M_1100_N_1110,
	load_rm_rn_b_M_1101_N_1110,
	load_rm_rn_w_M_1101_N_1110,
	load_rm_rn_l_M_1101_N_1110,
	mov_rm_rn_M_1101_N_1110,
	load_postinc_rm_rn_b_M_1101_N_1110,
	load_postinc_rm_rn_w_M_1101_N_1110,
	load_postinc_rm_rn_l_M_1101_N_1110,
	not_M_1101_N_1110,
	swap_b_M_1101_N_1110,
	swap_w_M_1101_N_1110,
	negc_M_1101_N_1110,
	neg_M_1101_N_1110,
	extu_b_M_1101_N_1110,
	extu_w_M_1101_N_1110,
	exts_b_M_1101_N_1110,
	exts_w_M_1101_N_1110,
	load_rm_rn_b_M_1110_N_1110,
	load_rm_rn_w_M_1110_N_1110,
	load_rm_rn_l_M_1110_N_1110,
	mov_rm_rn_M_1110_N_1110,
	load_postinc_rm_rn_b_M_1110_N_1110,
	load_postinc_rm_rn_w_M_1110_N_1110,
	load_postinc_rm_rn_l_M_1110_N_1110,
	not_M_1110_N_1110,
	swap_b_M_1110_N_1110,
	swap_w_M_1110_N_1110,
	negc_M_1110_N_1110,
	neg_M_1110_N_1110,
	extu_b_M_1110_N_1110,
	extu_w_M_1110_N_1110,
	exts_b_M_1110_N_1110,
	exts_w_M_1110_N_1110,
	load_rm_rn_b_M_1111_N_1110,
	load_rm_rn_w_M_1111_N_1110,
	load_rm_rn_l_M_1111_N_1110,
	mov_rm_rn_M_1111_N_1110,
	load_postinc_rm_rn_b_M_1111_N_1110,
	load_postinc_rm_rn_w_M_1111_N_1110,
	load_postinc_rm_rn_l_M_1111_N_1110,
	not_M_1111_N_1110,
	swap_b_M_1111_N_1110,
	swap_w_M_1111_N_1110,
	negc_M_1111_N_1110,
	neg_M_1111_N_1110,
	extu_b_M_1111_N_1110,
	extu_w_M_1111_N_1110,
	exts_b_M_1111_N_1110,
	exts_w_M_1111_N_1110,
	load_rm_rn_b_M_0000_N_1111,
	load_rm_rn_w_M_0000_N_1111,
	load_rm_rn_l_M_0000_N_1111,
	mov_rm_rn_M_0000_N_1111,
	load_postinc_rm_rn_b_M_0000_N_1111,
	load_postinc_rm_rn_w_M_0000_N_1111,
	load_postinc_rm_rn_l_M_0000_N_1111,
	not_M_0000_N_1111,
	swap_b_M_0000_N_1111,
	swap_w_M_0000_N_1111,
	negc_M_0000_N_1111,
	neg_M_0000_N_1111,
	extu_b_M_0000_N_1111,
	extu_w_M_0000_N_1111,
	exts_b_M_0000_N_1111,
	exts_w_M_0000_N_1111,
	load_rm_rn_b_M_0001_N_1111,
	load_rm_rn_w_M_0001_N_1111,
	load_rm_rn_l_M_0001_N_1111,
	mov_rm_rn_M_0001_N_1111,
	load_postinc_rm_rn_b_M_0001_N_1111,
	load_postinc_rm_rn_w_M_0001_N_1111,
	load_postinc_rm_rn_l_M_0001_N_1111,
	not_M_0001_N_1111,
	swap_b_M_0001_N_1111,
	swap_w_M_0001_N_1111,
	negc_M_0001_N_1111,
	neg_M_0001_N_1111,
	extu_b_M_0001_N_1111,
	extu_w_M_0001_N_1111,
	exts_b_M_0001_N_1111,
	exts_w_M_0001_N_1111,
	load_rm_rn_b_M_0010_N_1111,
	load_rm_rn_w_M_0010_N_1111,
	load_rm_rn_l_M_0010_N_1111,
	mov_rm_rn_M_0010_N_1111,
	load_postinc_rm_rn_b_M_0010_N_1111,
	load_postinc_rm_rn_w_M_0010_N_1111,
	load_postinc_rm_rn_l_M_0010_N_1111,
	not_M_0010_N_1111,
	swap_b_M_0010_N_1111,
	swap_w_M_0010_N_1111,
	negc_M_0010_N_1111,
	neg_M_0010_N_1111,
	extu_b_M_0010_N_1111,
	extu_w_M_0010_N_1111,
	exts_b_M_0010_N_1111,
	exts_w_M_0010_N_1111,
	load_rm_rn_b_M_0011_N_1111,
	load_rm_rn_w_M_0011_N_1111,
	load_rm_rn_l_M_0011_N_1111,
	mov_rm_rn_M_0011_N_1111,
	load_postinc_rm_rn_b_M_0011_N_1111,
	load_postinc_rm_rn_w_M_0011_N_1111,
	load_postinc_rm_rn_l_M_0011_N_1111,
	not_M_0011_N_1111,
	swap_b_M_0011_N_1111,
	swap_w_M_0011_N_1111,
	negc_M_0011_N_1111,
	neg_M_0011_N_1111,
	extu_b_M_0011_N_1111,
	extu_w_M_0011_N_1111,
	exts_b_M_0011_N_1111,
	exts_w_M_0011_N_1111,
	load_rm_rn_b_M_0100_N_1111,
	load_rm_rn_w_M_0100_N_1111,
	load_rm_rn_l_M_0100_N_1111,
	mov_rm_rn_M_0100_N_1111,
	load_postinc_rm_rn_b_M_0100_N_1111,
	load_postinc_rm_rn_w_M_0100_N_1111,
	load_postinc_rm_rn_l_M_0100_N_1111,
	not_M_0100_N_1111,
	swap_b_M_0100_N_1111,
	swap_w_M_0100_N_1111,
	negc_M_0100_N_1111,
	neg_M_0100_N_1111,
	extu_b_M_0100_N_1111,
	extu_w_M_0100_N_1111,
	exts_b_M_0100_N_1111,
	exts_w_M_0100_N_1111,
	load_rm_rn_b_M_0101_N_1111,
	load_rm_rn_w_M_0101_N_1111,
	load_rm_rn_l_M_0101_N_1111,
	mov_rm_rn_M_0101_N_1111,
	load_postinc_rm_rn_b_M_0101_N_1111,
	load_postinc_rm_rn_w_M_0101_N_1111,
	load_postinc_rm_rn_l_M_0101_N_1111,
	not_M_0101_N_1111,
	swap_b_M_0101_N_1111,
	swap_w_M_0101_N_1111,
	negc_M_0101_N_1111,
	neg_M_0101_N_1111,
	extu_b_M_0101_N_1111,
	extu_w_M_0101_N_1111,
	exts_b_M_0101_N_1111,
	exts_w_M_0101_N_1111,
	load_rm_rn_b_M_0110_N_1111,
	load_rm_rn_w_M_0110_N_1111,
	load_rm_rn_l_M_0110_N_1111,
	mov_rm_rn_M_0110_N_1111,
	load_postinc_rm_rn_b_M_0110_N_1111,
	load_postinc_rm_rn_w_M_0110_N_1111,
	load_postinc_rm_rn_l_M_0110_N_1111,
	not_M_0110_N_1111,
	swap_b_M_0110_N_1111,
	swap_w_M_0110_N_1111,
	negc_M_0110_N_1111,
	neg_M_0110_N_1111,
	extu_b_M_0110_N_1111,
	extu_w_M_0110_N_1111,
	exts_b_M_0110_N_1111,
	exts_w_M_0110_N_1111,
	load_rm_rn_b_M_0111_N_1111,
	load_rm_rn_w_M_0111_N_1111,
	load_rm_rn_l_M_0111_N_1111,
	mov_rm_rn_M_0111_N_1111,
	load_postinc_rm_rn_b_M_0111_N_1111,
	load_postinc_rm_rn_w_M_0111_N_1111,
	load_postinc_rm_rn_l_M_0111_N_1111,
	not_M_0111_N_1111,
	swap_b_M_0111_N_1111,
	swap_w_M_0111_N_1111,
	negc_M_0111_N_1111,
	neg_M_0111_N_1111,
	extu_b_M_0111_N_1111,
	extu_w_M_0111_N_1111,
	exts_b_M_0111_N_1111,
	exts_w_M_0111_N_1111,
	load_rm_rn_b_M_1000_N_1111,
	load_rm_rn_w_M_1000_N_1111,
	load_rm_rn_l_M_1000_N_1111,
	mov_rm_rn_M_1000_N_1111,
	load_postinc_rm_rn_b_M_1000_N_1111,
	load_postinc_rm_rn_w_M_1000_N_1111,
	load_postinc_rm_rn_l_M_1000_N_1111,
	not_M_1000_N_1111,
	swap_b_M_1000_N_1111,
	swap_w_M_1000_N_1111,
	negc_M_1000_N_1111,
	neg_M_1000_N_1111,
	extu_b_M_1000_N_1111,
	extu_w_M_1000_N_1111,
	exts_b_M_1000_N_1111,
	exts_w_M_1000_N_1111,
	load_rm_rn_b_M_1001_N_1111,
	load_rm_rn_w_M_1001_N_1111,
	load_rm_rn_l_M_1001_N_1111,
	mov_rm_rn_M_1001_N_1111,
	load_postinc_rm_rn_b_M_1001_N_1111,
	load_postinc_rm_rn_w_M_1001_N_1111,
	load_postinc_rm_rn_l_M_1001_N_1111,
	not_M_1001_N_1111,
	swap_b_M_1001_N_1111,
	swap_w_M_1001_N_1111,
	negc_M_1001_N_1111,
	neg_M_1001_N_1111,
	extu_b_M_1001_N_1111,
	extu_w_M_1001_N_1111,
	exts_b_M_1001_N_1111,
	exts_w_M_1001_N_1111,
	load_rm_rn_b_M_1010_N_1111,
	load_rm_rn_w_M_1010_N_1111,
	load_rm_rn_l_M_1010_N_1111,
	mov_rm_rn_M_1010_N_1111,
	load_postinc_rm_rn_b_M_1010_N_1111,
	load_postinc_rm_rn_w_M_1010_N_1111,
	load_postinc_rm_rn_l_M_1010_N_1111,
	not_M_1010_N_1111,
	swap_b_M_1010_N_1111,
	swap_w_M_1010_N_1111,
	negc_M_1010_N_1111,
	neg_M_1010_N_1111,
	extu_b_M_1010_N_1111,
	extu_w_M_1010_N_1111,
	exts_b_M_1010_N_1111,
	exts_w_M_1010_N_1111,
	load_rm_rn_b_M_1011_N_1111,
	load_rm_rn_w_M_1011_N_1111,
	load_rm_rn_l_M_1011_N_1111,
	mov_rm_rn_M_1011_N_1111,
	load_postinc_rm_rn_b_M_1011_N_1111,
	load_postinc_rm_rn_w_M_1011_N_1111,
	load_postinc_rm_rn_l_M_1011_N_1111,
	not_M_1011_N_1111,
	swap_b_M_1011_N_1111,
	swap_w_M_1011_N_1111,
	negc_M_1011_N_1111,
	neg_M_1011_N_1111,
	extu_b_M_1011_N_1111,
	extu_w_M_1011_N_1111,
	exts_b_M_1011_N_1111,
	exts_w_M_1011_N_1111,
	load_rm_rn_b_M_1100_N_1111,
	load_rm_rn_w_M_1100_N_1111,
	load_rm_rn_l_M_1100_N_1111,
	mov_rm_rn_M_1100_N_1111,
	load_postinc_rm_rn_b_M_1100_N_1111,
	load_postinc_rm_rn_w_M_1100_N_1111,
	load_postinc_rm_rn_l_M_1100_N_1111,
	not_M_1100_N_1111,
	swap_b_M_1100_N_1111,
	swap_w_M_1100_N_1111,
	negc_M_1100_N_1111,
	neg_M_1100_N_1111,
	extu_b_M_1100_N_1111,
	extu_w_M_1100_N_1111,
	exts_b_M_1100_N_1111,
	exts_w_M_1100_N_1111,
	load_rm_rn_b_M_1101_N_1111,
	load_rm_rn_w_M_1101_N_1111,
	load_rm_rn_l_M_1101_N_1111,
	mov_rm_rn_M_1101_N_1111,
	load_postinc_rm_rn_b_M_1101_N_1111,
	load_postinc_rm_rn_w_M_1101_N_1111,
	load_postinc_rm_rn_l_M_1101_N_1111,
	not_M_1101_N_1111,
	swap_b_M_1101_N_1111,
	swap_w_M_1101_N_1111,
	negc_M_1101_N_1111,
	neg_M_1101_N_1111,
	extu_b_M_1101_N_1111,
	extu_w_M_1101_N_1111,
	exts_b_M_1101_N_1111,
	exts_w_M_1101_N_1111,
	load_rm_rn_b_M_1110_N_1111,
	load_rm_rn_w_M_1110_N_1111,
	load_rm_rn_l_M_1110_N_1111,
	mov_rm_rn_M_1110_N_1111,
	load_postinc_rm_rn_b_M_1110_N_1111,
	load_postinc_rm_rn_w_M_1110_N_1111,
	load_postinc_rm_rn_l_M_1110_N_1111,
	not_M_1110_N_1111,
	swap_b_M_1110_N_1111,
	swap_w_M_1110_N_1111,
	negc_M_1110_N_1111,
	neg_M_1110_N_1111,
	extu_b_M_1110_N_1111,
	extu_w_M_1110_N_1111,
	exts_b_M_1110_N_1111,
	exts_w_M_1110_N_1111,
	load_rm_rn_b_M_1111_N_1111,
	load_rm_rn_w_M_1111_N_1111,
	load_rm_rn_l_M_1111_N_1111,
	mov_rm_rn_M_1111_N_1111,
	load_postinc_rm_rn_b_M_1111_N_1111,
	load_postinc_rm_rn_w_M_1111_N_1111,
	load_postinc_rm_rn_l_M_1111_N_1111,
	not_M_1111_N_1111,
	swap_b_M_1111_N_1111,
	swap_w_M_1111_N_1111,
	negc_M_1111_N_1111,
	neg_M_1111_N_1111,
	extu_b_M_1111_N_1111,
	extu_w_M_1111_N_1111,
	exts_b_M_1111_N_1111,
	exts_w_M_1111_N_1111,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0000,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0001,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0010,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0011,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0100,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0101,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0110,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_0111,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1000,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1001,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1010,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1011,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1100,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1101,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1110,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	add_imm_rn_N_1111,
	store_r0_disp_rn_b_D_0000_N_0000,
	store_r0_disp_rn_b_D_0001_N_0000,
	store_r0_disp_rn_b_D_0010_N_0000,
	store_r0_disp_rn_b_D_0011_N_0000,
	store_r0_disp_rn_b_D_0100_N_0000,
	store_r0_disp_rn_b_D_0101_N_0000,
	store_r0_disp_rn_b_D_0110_N_0000,
	store_r0_disp_rn_b_D_0111_N_0000,
	store_r0_disp_rn_b_D_1000_N_0000,
	store_r0_disp_rn_b_D_1001_N_0000,
	store_r0_disp_rn_b_D_1010_N_0000,
	store_r0_disp_rn_b_D_1011_N_0000,
	store_r0_disp_rn_b_D_1100_N_0000,
	store_r0_disp_rn_b_D_1101_N_0000,
	store_r0_disp_rn_b_D_1110_N_0000,
	store_r0_disp_rn_b_D_1111_N_0000,
	store_r0_disp_rn_b_D_0000_N_0001,
	store_r0_disp_rn_b_D_0001_N_0001,
	store_r0_disp_rn_b_D_0010_N_0001,
	store_r0_disp_rn_b_D_0011_N_0001,
	store_r0_disp_rn_b_D_0100_N_0001,
	store_r0_disp_rn_b_D_0101_N_0001,
	store_r0_disp_rn_b_D_0110_N_0001,
	store_r0_disp_rn_b_D_0111_N_0001,
	store_r0_disp_rn_b_D_1000_N_0001,
	store_r0_disp_rn_b_D_1001_N_0001,
	store_r0_disp_rn_b_D_1010_N_0001,
	store_r0_disp_rn_b_D_1011_N_0001,
	store_r0_disp_rn_b_D_1100_N_0001,
	store_r0_disp_rn_b_D_1101_N_0001,
	store_r0_disp_rn_b_D_1110_N_0001,
	store_r0_disp_rn_b_D_1111_N_0001,
	store_r0_disp_rn_b_D_0000_N_0010,
	store_r0_disp_rn_b_D_0001_N_0010,
	store_r0_disp_rn_b_D_0010_N_0010,
	store_r0_disp_rn_b_D_0011_N_0010,
	store_r0_disp_rn_b_D_0100_N_0010,
	store_r0_disp_rn_b_D_0101_N_0010,
	store_r0_disp_rn_b_D_0110_N_0010,
	store_r0_disp_rn_b_D_0111_N_0010,
	store_r0_disp_rn_b_D_1000_N_0010,
	store_r0_disp_rn_b_D_1001_N_0010,
	store_r0_disp_rn_b_D_1010_N_0010,
	store_r0_disp_rn_b_D_1011_N_0010,
	store_r0_disp_rn_b_D_1100_N_0010,
	store_r0_disp_rn_b_D_1101_N_0010,
	store_r0_disp_rn_b_D_1110_N_0010,
	store_r0_disp_rn_b_D_1111_N_0010,
	store_r0_disp_rn_b_D_0000_N_0011,
	store_r0_disp_rn_b_D_0001_N_0011,
	store_r0_disp_rn_b_D_0010_N_0011,
	store_r0_disp_rn_b_D_0011_N_0011,
	store_r0_disp_rn_b_D_0100_N_0011,
	store_r0_disp_rn_b_D_0101_N_0011,
	store_r0_disp_rn_b_D_0110_N_0011,
	store_r0_disp_rn_b_D_0111_N_0011,
	store_r0_disp_rn_b_D_1000_N_0011,
	store_r0_disp_rn_b_D_1001_N_0011,
	store_r0_disp_rn_b_D_1010_N_0011,
	store_r0_disp_rn_b_D_1011_N_0011,
	store_r0_disp_rn_b_D_1100_N_0011,
	store_r0_disp_rn_b_D_1101_N_0011,
	store_r0_disp_rn_b_D_1110_N_0011,
	store_r0_disp_rn_b_D_1111_N_0011,
	store_r0_disp_rn_b_D_0000_N_0100,
	store_r0_disp_rn_b_D_0001_N_0100,
	store_r0_disp_rn_b_D_0010_N_0100,
	store_r0_disp_rn_b_D_0011_N_0100,
	store_r0_disp_rn_b_D_0100_N_0100,
	store_r0_disp_rn_b_D_0101_N_0100,
	store_r0_disp_rn_b_D_0110_N_0100,
	store_r0_disp_rn_b_D_0111_N_0100,
	store_r0_disp_rn_b_D_1000_N_0100,
	store_r0_disp_rn_b_D_1001_N_0100,
	store_r0_disp_rn_b_D_1010_N_0100,
	store_r0_disp_rn_b_D_1011_N_0100,
	store_r0_disp_rn_b_D_1100_N_0100,
	store_r0_disp_rn_b_D_1101_N_0100,
	store_r0_disp_rn_b_D_1110_N_0100,
	store_r0_disp_rn_b_D_1111_N_0100,
	store_r0_disp_rn_b_D_0000_N_0101,
	store_r0_disp_rn_b_D_0001_N_0101,
	store_r0_disp_rn_b_D_0010_N_0101,
	store_r0_disp_rn_b_D_0011_N_0101,
	store_r0_disp_rn_b_D_0100_N_0101,
	store_r0_disp_rn_b_D_0101_N_0101,
	store_r0_disp_rn_b_D_0110_N_0101,
	store_r0_disp_rn_b_D_0111_N_0101,
	store_r0_disp_rn_b_D_1000_N_0101,
	store_r0_disp_rn_b_D_1001_N_0101,
	store_r0_disp_rn_b_D_1010_N_0101,
	store_r0_disp_rn_b_D_1011_N_0101,
	store_r0_disp_rn_b_D_1100_N_0101,
	store_r0_disp_rn_b_D_1101_N_0101,
	store_r0_disp_rn_b_D_1110_N_0101,
	store_r0_disp_rn_b_D_1111_N_0101,
	store_r0_disp_rn_b_D_0000_N_0110,
	store_r0_disp_rn_b_D_0001_N_0110,
	store_r0_disp_rn_b_D_0010_N_0110,
	store_r0_disp_rn_b_D_0011_N_0110,
	store_r0_disp_rn_b_D_0100_N_0110,
	store_r0_disp_rn_b_D_0101_N_0110,
	store_r0_disp_rn_b_D_0110_N_0110,
	store_r0_disp_rn_b_D_0111_N_0110,
	store_r0_disp_rn_b_D_1000_N_0110,
	store_r0_disp_rn_b_D_1001_N_0110,
	store_r0_disp_rn_b_D_1010_N_0110,
	store_r0_disp_rn_b_D_1011_N_0110,
	store_r0_disp_rn_b_D_1100_N_0110,
	store_r0_disp_rn_b_D_1101_N_0110,
	store_r0_disp_rn_b_D_1110_N_0110,
	store_r0_disp_rn_b_D_1111_N_0110,
	store_r0_disp_rn_b_D_0000_N_0111,
	store_r0_disp_rn_b_D_0001_N_0111,
	store_r0_disp_rn_b_D_0010_N_0111,
	store_r0_disp_rn_b_D_0011_N_0111,
	store_r0_disp_rn_b_D_0100_N_0111,
	store_r0_disp_rn_b_D_0101_N_0111,
	store_r0_disp_rn_b_D_0110_N_0111,
	store_r0_disp_rn_b_D_0111_N_0111,
	store_r0_disp_rn_b_D_1000_N_0111,
	store_r0_disp_rn_b_D_1001_N_0111,
	store_r0_disp_rn_b_D_1010_N_0111,
	store_r0_disp_rn_b_D_1011_N_0111,
	store_r0_disp_rn_b_D_1100_N_0111,
	store_r0_disp_rn_b_D_1101_N_0111,
	store_r0_disp_rn_b_D_1110_N_0111,
	store_r0_disp_rn_b_D_1111_N_0111,
	store_r0_disp_rn_b_D_0000_N_1000,
	store_r0_disp_rn_b_D_0001_N_1000,
	store_r0_disp_rn_b_D_0010_N_1000,
	store_r0_disp_rn_b_D_0011_N_1000,
	store_r0_disp_rn_b_D_0100_N_1000,
	store_r0_disp_rn_b_D_0101_N_1000,
	store_r0_disp_rn_b_D_0110_N_1000,
	store_r0_disp_rn_b_D_0111_N_1000,
	store_r0_disp_rn_b_D_1000_N_1000,
	store_r0_disp_rn_b_D_1001_N_1000,
	store_r0_disp_rn_b_D_1010_N_1000,
	store_r0_disp_rn_b_D_1011_N_1000,
	store_r0_disp_rn_b_D_1100_N_1000,
	store_r0_disp_rn_b_D_1101_N_1000,
	store_r0_disp_rn_b_D_1110_N_1000,
	store_r0_disp_rn_b_D_1111_N_1000,
	store_r0_disp_rn_b_D_0000_N_1001,
	store_r0_disp_rn_b_D_0001_N_1001,
	store_r0_disp_rn_b_D_0010_N_1001,
	store_r0_disp_rn_b_D_0011_N_1001,
	store_r0_disp_rn_b_D_0100_N_1001,
	store_r0_disp_rn_b_D_0101_N_1001,
	store_r0_disp_rn_b_D_0110_N_1001,
	store_r0_disp_rn_b_D_0111_N_1001,
	store_r0_disp_rn_b_D_1000_N_1001,
	store_r0_disp_rn_b_D_1001_N_1001,
	store_r0_disp_rn_b_D_1010_N_1001,
	store_r0_disp_rn_b_D_1011_N_1001,
	store_r0_disp_rn_b_D_1100_N_1001,
	store_r0_disp_rn_b_D_1101_N_1001,
	store_r0_disp_rn_b_D_1110_N_1001,
	store_r0_disp_rn_b_D_1111_N_1001,
	store_r0_disp_rn_b_D_0000_N_1010,
	store_r0_disp_rn_b_D_0001_N_1010,
	store_r0_disp_rn_b_D_0010_N_1010,
	store_r0_disp_rn_b_D_0011_N_1010,
	store_r0_disp_rn_b_D_0100_N_1010,
	store_r0_disp_rn_b_D_0101_N_1010,
	store_r0_disp_rn_b_D_0110_N_1010,
	store_r0_disp_rn_b_D_0111_N_1010,
	store_r0_disp_rn_b_D_1000_N_1010,
	store_r0_disp_rn_b_D_1001_N_1010,
	store_r0_disp_rn_b_D_1010_N_1010,
	store_r0_disp_rn_b_D_1011_N_1010,
	store_r0_disp_rn_b_D_1100_N_1010,
	store_r0_disp_rn_b_D_1101_N_1010,
	store_r0_disp_rn_b_D_1110_N_1010,
	store_r0_disp_rn_b_D_1111_N_1010,
	store_r0_disp_rn_b_D_0000_N_1011,
	store_r0_disp_rn_b_D_0001_N_1011,
	store_r0_disp_rn_b_D_0010_N_1011,
	store_r0_disp_rn_b_D_0011_N_1011,
	store_r0_disp_rn_b_D_0100_N_1011,
	store_r0_disp_rn_b_D_0101_N_1011,
	store_r0_disp_rn_b_D_0110_N_1011,
	store_r0_disp_rn_b_D_0111_N_1011,
	store_r0_disp_rn_b_D_1000_N_1011,
	store_r0_disp_rn_b_D_1001_N_1011,
	store_r0_disp_rn_b_D_1010_N_1011,
	store_r0_disp_rn_b_D_1011_N_1011,
	store_r0_disp_rn_b_D_1100_N_1011,
	store_r0_disp_rn_b_D_1101_N_1011,
	store_r0_disp_rn_b_D_1110_N_1011,
	store_r0_disp_rn_b_D_1111_N_1011,
	store_r0_disp_rn_b_D_0000_N_1100,
	store_r0_disp_rn_b_D_0001_N_1100,
	store_r0_disp_rn_b_D_0010_N_1100,
	store_r0_disp_rn_b_D_0011_N_1100,
	store_r0_disp_rn_b_D_0100_N_1100,
	store_r0_disp_rn_b_D_0101_N_1100,
	store_r0_disp_rn_b_D_0110_N_1100,
	store_r0_disp_rn_b_D_0111_N_1100,
	store_r0_disp_rn_b_D_1000_N_1100,
	store_r0_disp_rn_b_D_1001_N_1100,
	store_r0_disp_rn_b_D_1010_N_1100,
	store_r0_disp_rn_b_D_1011_N_1100,
	store_r0_disp_rn_b_D_1100_N_1100,
	store_r0_disp_rn_b_D_1101_N_1100,
	store_r0_disp_rn_b_D_1110_N_1100,
	store_r0_disp_rn_b_D_1111_N_1100,
	store_r0_disp_rn_b_D_0000_N_1101,
	store_r0_disp_rn_b_D_0001_N_1101,
	store_r0_disp_rn_b_D_0010_N_1101,
	store_r0_disp_rn_b_D_0011_N_1101,
	store_r0_disp_rn_b_D_0100_N_1101,
	store_r0_disp_rn_b_D_0101_N_1101,
	store_r0_disp_rn_b_D_0110_N_1101,
	store_r0_disp_rn_b_D_0111_N_1101,
	store_r0_disp_rn_b_D_1000_N_1101,
	store_r0_disp_rn_b_D_1001_N_1101,
	store_r0_disp_rn_b_D_1010_N_1101,
	store_r0_disp_rn_b_D_1011_N_1101,
	store_r0_disp_rn_b_D_1100_N_1101,
	store_r0_disp_rn_b_D_1101_N_1101,
	store_r0_disp_rn_b_D_1110_N_1101,
	store_r0_disp_rn_b_D_1111_N_1101,
	store_r0_disp_rn_b_D_0000_N_1110,
	store_r0_disp_rn_b_D_0001_N_1110,
	store_r0_disp_rn_b_D_0010_N_1110,
	store_r0_disp_rn_b_D_0011_N_1110,
	store_r0_disp_rn_b_D_0100_N_1110,
	store_r0_disp_rn_b_D_0101_N_1110,
	store_r0_disp_rn_b_D_0110_N_1110,
	store_r0_disp_rn_b_D_0111_N_1110,
	store_r0_disp_rn_b_D_1000_N_1110,
	store_r0_disp_rn_b_D_1001_N_1110,
	store_r0_disp_rn_b_D_1010_N_1110,
	store_r0_disp_rn_b_D_1011_N_1110,
	store_r0_disp_rn_b_D_1100_N_1110,
	store_r0_disp_rn_b_D_1101_N_1110,
	store_r0_disp_rn_b_D_1110_N_1110,
	store_r0_disp_rn_b_D_1111_N_1110,
	store_r0_disp_rn_b_D_0000_N_1111,
	store_r0_disp_rn_b_D_0001_N_1111,
	store_r0_disp_rn_b_D_0010_N_1111,
	store_r0_disp_rn_b_D_0011_N_1111,
	store_r0_disp_rn_b_D_0100_N_1111,
	store_r0_disp_rn_b_D_0101_N_1111,
	store_r0_disp_rn_b_D_0110_N_1111,
	store_r0_disp_rn_b_D_0111_N_1111,
	store_r0_disp_rn_b_D_1000_N_1111,
	store_r0_disp_rn_b_D_1001_N_1111,
	store_r0_disp_rn_b_D_1010_N_1111,
	store_r0_disp_rn_b_D_1011_N_1111,
	store_r0_disp_rn_b_D_1100_N_1111,
	store_r0_disp_rn_b_D_1101_N_1111,
	store_r0_disp_rn_b_D_1110_N_1111,
	store_r0_disp_rn_b_D_1111_N_1111,
	store_r0_disp_rn_w_D_0000_N_0000,
	store_r0_disp_rn_w_D_0001_N_0000,
	store_r0_disp_rn_w_D_0010_N_0000,
	store_r0_disp_rn_w_D_0011_N_0000,
	store_r0_disp_rn_w_D_0100_N_0000,
	store_r0_disp_rn_w_D_0101_N_0000,
	store_r0_disp_rn_w_D_0110_N_0000,
	store_r0_disp_rn_w_D_0111_N_0000,
	store_r0_disp_rn_w_D_1000_N_0000,
	store_r0_disp_rn_w_D_1001_N_0000,
	store_r0_disp_rn_w_D_1010_N_0000,
	store_r0_disp_rn_w_D_1011_N_0000,
	store_r0_disp_rn_w_D_1100_N_0000,
	store_r0_disp_rn_w_D_1101_N_0000,
	store_r0_disp_rn_w_D_1110_N_0000,
	store_r0_disp_rn_w_D_1111_N_0000,
	store_r0_disp_rn_w_D_0000_N_0001,
	store_r0_disp_rn_w_D_0001_N_0001,
	store_r0_disp_rn_w_D_0010_N_0001,
	store_r0_disp_rn_w_D_0011_N_0001,
	store_r0_disp_rn_w_D_0100_N_0001,
	store_r0_disp_rn_w_D_0101_N_0001,
	store_r0_disp_rn_w_D_0110_N_0001,
	store_r0_disp_rn_w_D_0111_N_0001,
	store_r0_disp_rn_w_D_1000_N_0001,
	store_r0_disp_rn_w_D_1001_N_0001,
	store_r0_disp_rn_w_D_1010_N_0001,
	store_r0_disp_rn_w_D_1011_N_0001,
	store_r0_disp_rn_w_D_1100_N_0001,
	store_r0_disp_rn_w_D_1101_N_0001,
	store_r0_disp_rn_w_D_1110_N_0001,
	store_r0_disp_rn_w_D_1111_N_0001,
	store_r0_disp_rn_w_D_0000_N_0010,
	store_r0_disp_rn_w_D_0001_N_0010,
	store_r0_disp_rn_w_D_0010_N_0010,
	store_r0_disp_rn_w_D_0011_N_0010,
	store_r0_disp_rn_w_D_0100_N_0010,
	store_r0_disp_rn_w_D_0101_N_0010,
	store_r0_disp_rn_w_D_0110_N_0010,
	store_r0_disp_rn_w_D_0111_N_0010,
	store_r0_disp_rn_w_D_1000_N_0010,
	store_r0_disp_rn_w_D_1001_N_0010,
	store_r0_disp_rn_w_D_1010_N_0010,
	store_r0_disp_rn_w_D_1011_N_0010,
	store_r0_disp_rn_w_D_1100_N_0010,
	store_r0_disp_rn_w_D_1101_N_0010,
	store_r0_disp_rn_w_D_1110_N_0010,
	store_r0_disp_rn_w_D_1111_N_0010,
	store_r0_disp_rn_w_D_0000_N_0011,
	store_r0_disp_rn_w_D_0001_N_0011,
	store_r0_disp_rn_w_D_0010_N_0011,
	store_r0_disp_rn_w_D_0011_N_0011,
	store_r0_disp_rn_w_D_0100_N_0011,
	store_r0_disp_rn_w_D_0101_N_0011,
	store_r0_disp_rn_w_D_0110_N_0011,
	store_r0_disp_rn_w_D_0111_N_0011,
	store_r0_disp_rn_w_D_1000_N_0011,
	store_r0_disp_rn_w_D_1001_N_0011,
	store_r0_disp_rn_w_D_1010_N_0011,
	store_r0_disp_rn_w_D_1011_N_0011,
	store_r0_disp_rn_w_D_1100_N_0011,
	store_r0_disp_rn_w_D_1101_N_0011,
	store_r0_disp_rn_w_D_1110_N_0011,
	store_r0_disp_rn_w_D_1111_N_0011,
	store_r0_disp_rn_w_D_0000_N_0100,
	store_r0_disp_rn_w_D_0001_N_0100,
	store_r0_disp_rn_w_D_0010_N_0100,
	store_r0_disp_rn_w_D_0011_N_0100,
	store_r0_disp_rn_w_D_0100_N_0100,
	store_r0_disp_rn_w_D_0101_N_0100,
	store_r0_disp_rn_w_D_0110_N_0100,
	store_r0_disp_rn_w_D_0111_N_0100,
	store_r0_disp_rn_w_D_1000_N_0100,
	store_r0_disp_rn_w_D_1001_N_0100,
	store_r0_disp_rn_w_D_1010_N_0100,
	store_r0_disp_rn_w_D_1011_N_0100,
	store_r0_disp_rn_w_D_1100_N_0100,
	store_r0_disp_rn_w_D_1101_N_0100,
	store_r0_disp_rn_w_D_1110_N_0100,
	store_r0_disp_rn_w_D_1111_N_0100,
	store_r0_disp_rn_w_D_0000_N_0101,
	store_r0_disp_rn_w_D_0001_N_0101,
	store_r0_disp_rn_w_D_0010_N_0101,
	store_r0_disp_rn_w_D_0011_N_0101,
	store_r0_disp_rn_w_D_0100_N_0101,
	store_r0_disp_rn_w_D_0101_N_0101,
	store_r0_disp_rn_w_D_0110_N_0101,
	store_r0_disp_rn_w_D_0111_N_0101,
	store_r0_disp_rn_w_D_1000_N_0101,
	store_r0_disp_rn_w_D_1001_N_0101,
	store_r0_disp_rn_w_D_1010_N_0101,
	store_r0_disp_rn_w_D_1011_N_0101,
	store_r0_disp_rn_w_D_1100_N_0101,
	store_r0_disp_rn_w_D_1101_N_0101,
	store_r0_disp_rn_w_D_1110_N_0101,
	store_r0_disp_rn_w_D_1111_N_0101,
	store_r0_disp_rn_w_D_0000_N_0110,
	store_r0_disp_rn_w_D_0001_N_0110,
	store_r0_disp_rn_w_D_0010_N_0110,
	store_r0_disp_rn_w_D_0011_N_0110,
	store_r0_disp_rn_w_D_0100_N_0110,
	store_r0_disp_rn_w_D_0101_N_0110,
	store_r0_disp_rn_w_D_0110_N_0110,
	store_r0_disp_rn_w_D_0111_N_0110,
	store_r0_disp_rn_w_D_1000_N_0110,
	store_r0_disp_rn_w_D_1001_N_0110,
	store_r0_disp_rn_w_D_1010_N_0110,
	store_r0_disp_rn_w_D_1011_N_0110,
	store_r0_disp_rn_w_D_1100_N_0110,
	store_r0_disp_rn_w_D_1101_N_0110,
	store_r0_disp_rn_w_D_1110_N_0110,
	store_r0_disp_rn_w_D_1111_N_0110,
	store_r0_disp_rn_w_D_0000_N_0111,
	store_r0_disp_rn_w_D_0001_N_0111,
	store_r0_disp_rn_w_D_0010_N_0111,
	store_r0_disp_rn_w_D_0011_N_0111,
	store_r0_disp_rn_w_D_0100_N_0111,
	store_r0_disp_rn_w_D_0101_N_0111,
	store_r0_disp_rn_w_D_0110_N_0111,
	store_r0_disp_rn_w_D_0111_N_0111,
	store_r0_disp_rn_w_D_1000_N_0111,
	store_r0_disp_rn_w_D_1001_N_0111,
	store_r0_disp_rn_w_D_1010_N_0111,
	store_r0_disp_rn_w_D_1011_N_0111,
	store_r0_disp_rn_w_D_1100_N_0111,
	store_r0_disp_rn_w_D_1101_N_0111,
	store_r0_disp_rn_w_D_1110_N_0111,
	store_r0_disp_rn_w_D_1111_N_0111,
	store_r0_disp_rn_w_D_0000_N_1000,
	store_r0_disp_rn_w_D_0001_N_1000,
	store_r0_disp_rn_w_D_0010_N_1000,
	store_r0_disp_rn_w_D_0011_N_1000,
	store_r0_disp_rn_w_D_0100_N_1000,
	store_r0_disp_rn_w_D_0101_N_1000,
	store_r0_disp_rn_w_D_0110_N_1000,
	store_r0_disp_rn_w_D_0111_N_1000,
	store_r0_disp_rn_w_D_1000_N_1000,
	store_r0_disp_rn_w_D_1001_N_1000,
	store_r0_disp_rn_w_D_1010_N_1000,
	store_r0_disp_rn_w_D_1011_N_1000,
	store_r0_disp_rn_w_D_1100_N_1000,
	store_r0_disp_rn_w_D_1101_N_1000,
	store_r0_disp_rn_w_D_1110_N_1000,
	store_r0_disp_rn_w_D_1111_N_1000,
	store_r0_disp_rn_w_D_0000_N_1001,
	store_r0_disp_rn_w_D_0001_N_1001,
	store_r0_disp_rn_w_D_0010_N_1001,
	store_r0_disp_rn_w_D_0011_N_1001,
	store_r0_disp_rn_w_D_0100_N_1001,
	store_r0_disp_rn_w_D_0101_N_1001,
	store_r0_disp_rn_w_D_0110_N_1001,
	store_r0_disp_rn_w_D_0111_N_1001,
	store_r0_disp_rn_w_D_1000_N_1001,
	store_r0_disp_rn_w_D_1001_N_1001,
	store_r0_disp_rn_w_D_1010_N_1001,
	store_r0_disp_rn_w_D_1011_N_1001,
	store_r0_disp_rn_w_D_1100_N_1001,
	store_r0_disp_rn_w_D_1101_N_1001,
	store_r0_disp_rn_w_D_1110_N_1001,
	store_r0_disp_rn_w_D_1111_N_1001,
	store_r0_disp_rn_w_D_0000_N_1010,
	store_r0_disp_rn_w_D_0001_N_1010,
	store_r0_disp_rn_w_D_0010_N_1010,
	store_r0_disp_rn_w_D_0011_N_1010,
	store_r0_disp_rn_w_D_0100_N_1010,
	store_r0_disp_rn_w_D_0101_N_1010,
	store_r0_disp_rn_w_D_0110_N_1010,
	store_r0_disp_rn_w_D_0111_N_1010,
	store_r0_disp_rn_w_D_1000_N_1010,
	store_r0_disp_rn_w_D_1001_N_1010,
	store_r0_disp_rn_w_D_1010_N_1010,
	store_r0_disp_rn_w_D_1011_N_1010,
	store_r0_disp_rn_w_D_1100_N_1010,
	store_r0_disp_rn_w_D_1101_N_1010,
	store_r0_disp_rn_w_D_1110_N_1010,
	store_r0_disp_rn_w_D_1111_N_1010,
	store_r0_disp_rn_w_D_0000_N_1011,
	store_r0_disp_rn_w_D_0001_N_1011,
	store_r0_disp_rn_w_D_0010_N_1011,
	store_r0_disp_rn_w_D_0011_N_1011,
	store_r0_disp_rn_w_D_0100_N_1011,
	store_r0_disp_rn_w_D_0101_N_1011,
	store_r0_disp_rn_w_D_0110_N_1011,
	store_r0_disp_rn_w_D_0111_N_1011,
	store_r0_disp_rn_w_D_1000_N_1011,
	store_r0_disp_rn_w_D_1001_N_1011,
	store_r0_disp_rn_w_D_1010_N_1011,
	store_r0_disp_rn_w_D_1011_N_1011,
	store_r0_disp_rn_w_D_1100_N_1011,
	store_r0_disp_rn_w_D_1101_N_1011,
	store_r0_disp_rn_w_D_1110_N_1011,
	store_r0_disp_rn_w_D_1111_N_1011,
	store_r0_disp_rn_w_D_0000_N_1100,
	store_r0_disp_rn_w_D_0001_N_1100,
	store_r0_disp_rn_w_D_0010_N_1100,
	store_r0_disp_rn_w_D_0011_N_1100,
	store_r0_disp_rn_w_D_0100_N_1100,
	store_r0_disp_rn_w_D_0101_N_1100,
	store_r0_disp_rn_w_D_0110_N_1100,
	store_r0_disp_rn_w_D_0111_N_1100,
	store_r0_disp_rn_w_D_1000_N_1100,
	store_r0_disp_rn_w_D_1001_N_1100,
	store_r0_disp_rn_w_D_1010_N_1100,
	store_r0_disp_rn_w_D_1011_N_1100,
	store_r0_disp_rn_w_D_1100_N_1100,
	store_r0_disp_rn_w_D_1101_N_1100,
	store_r0_disp_rn_w_D_1110_N_1100,
	store_r0_disp_rn_w_D_1111_N_1100,
	store_r0_disp_rn_w_D_0000_N_1101,
	store_r0_disp_rn_w_D_0001_N_1101,
	store_r0_disp_rn_w_D_0010_N_1101,
	store_r0_disp_rn_w_D_0011_N_1101,
	store_r0_disp_rn_w_D_0100_N_1101,
	store_r0_disp_rn_w_D_0101_N_1101,
	store_r0_disp_rn_w_D_0110_N_1101,
	store_r0_disp_rn_w_D_0111_N_1101,
	store_r0_disp_rn_w_D_1000_N_1101,
	store_r0_disp_rn_w_D_1001_N_1101,
	store_r0_disp_rn_w_D_1010_N_1101,
	store_r0_disp_rn_w_D_1011_N_1101,
	store_r0_disp_rn_w_D_1100_N_1101,
	store_r0_disp_rn_w_D_1101_N_1101,
	store_r0_disp_rn_w_D_1110_N_1101,
	store_r0_disp_rn_w_D_1111_N_1101,
	store_r0_disp_rn_w_D_0000_N_1110,
	store_r0_disp_rn_w_D_0001_N_1110,
	store_r0_disp_rn_w_D_0010_N_1110,
	store_r0_disp_rn_w_D_0011_N_1110,
	store_r0_disp_rn_w_D_0100_N_1110,
	store_r0_disp_rn_w_D_0101_N_1110,
	store_r0_disp_rn_w_D_0110_N_1110,
	store_r0_disp_rn_w_D_0111_N_1110,
	store_r0_disp_rn_w_D_1000_N_1110,
	store_r0_disp_rn_w_D_1001_N_1110,
	store_r0_disp_rn_w_D_1010_N_1110,
	store_r0_disp_rn_w_D_1011_N_1110,
	store_r0_disp_rn_w_D_1100_N_1110,
	store_r0_disp_rn_w_D_1101_N_1110,
	store_r0_disp_rn_w_D_1110_N_1110,
	store_r0_disp_rn_w_D_1111_N_1110,
	store_r0_disp_rn_w_D_0000_N_1111,
	store_r0_disp_rn_w_D_0001_N_1111,
	store_r0_disp_rn_w_D_0010_N_1111,
	store_r0_disp_rn_w_D_0011_N_1111,
	store_r0_disp_rn_w_D_0100_N_1111,
	store_r0_disp_rn_w_D_0101_N_1111,
	store_r0_disp_rn_w_D_0110_N_1111,
	store_r0_disp_rn_w_D_0111_N_1111,
	store_r0_disp_rn_w_D_1000_N_1111,
	store_r0_disp_rn_w_D_1001_N_1111,
	store_r0_disp_rn_w_D_1010_N_1111,
	store_r0_disp_rn_w_D_1011_N_1111,
	store_r0_disp_rn_w_D_1100_N_1111,
	store_r0_disp_rn_w_D_1101_N_1111,
	store_r0_disp_rn_w_D_1110_N_1111,
	store_r0_disp_rn_w_D_1111_N_1111,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	load_disp_rm_r0_b_D_0000_M_0000,
	load_disp_rm_r0_b_D_0001_M_0000,
	load_disp_rm_r0_b_D_0010_M_0000,
	load_disp_rm_r0_b_D_0011_M_0000,
	load_disp_rm_r0_b_D_0100_M_0000,
	load_disp_rm_r0_b_D_0101_M_0000,
	load_disp_rm_r0_b_D_0110_M_0000,
	load_disp_rm_r0_b_D_0111_M_0000,
	load_disp_rm_r0_b_D_1000_M_0000,
	load_disp_rm_r0_b_D_1001_M_0000,
	load_disp_rm_r0_b_D_1010_M_0000,
	load_disp_rm_r0_b_D_1011_M_0000,
	load_disp_rm_r0_b_D_1100_M_0000,
	load_disp_rm_r0_b_D_1101_M_0000,
	load_disp_rm_r0_b_D_1110_M_0000,
	load_disp_rm_r0_b_D_1111_M_0000,
	load_disp_rm_r0_b_D_0000_M_0001,
	load_disp_rm_r0_b_D_0001_M_0001,
	load_disp_rm_r0_b_D_0010_M_0001,
	load_disp_rm_r0_b_D_0011_M_0001,
	load_disp_rm_r0_b_D_0100_M_0001,
	load_disp_rm_r0_b_D_0101_M_0001,
	load_disp_rm_r0_b_D_0110_M_0001,
	load_disp_rm_r0_b_D_0111_M_0001,
	load_disp_rm_r0_b_D_1000_M_0001,
	load_disp_rm_r0_b_D_1001_M_0001,
	load_disp_rm_r0_b_D_1010_M_0001,
	load_disp_rm_r0_b_D_1011_M_0001,
	load_disp_rm_r0_b_D_1100_M_0001,
	load_disp_rm_r0_b_D_1101_M_0001,
	load_disp_rm_r0_b_D_1110_M_0001,
	load_disp_rm_r0_b_D_1111_M_0001,
	load_disp_rm_r0_b_D_0000_M_0010,
	load_disp_rm_r0_b_D_0001_M_0010,
	load_disp_rm_r0_b_D_0010_M_0010,
	load_disp_rm_r0_b_D_0011_M_0010,
	load_disp_rm_r0_b_D_0100_M_0010,
	load_disp_rm_r0_b_D_0101_M_0010,
	load_disp_rm_r0_b_D_0110_M_0010,
	load_disp_rm_r0_b_D_0111_M_0010,
	load_disp_rm_r0_b_D_1000_M_0010,
	load_disp_rm_r0_b_D_1001_M_0010,
	load_disp_rm_r0_b_D_1010_M_0010,
	load_disp_rm_r0_b_D_1011_M_0010,
	load_disp_rm_r0_b_D_1100_M_0010,
	load_disp_rm_r0_b_D_1101_M_0010,
	load_disp_rm_r0_b_D_1110_M_0010,
	load_disp_rm_r0_b_D_1111_M_0010,
	load_disp_rm_r0_b_D_0000_M_0011,
	load_disp_rm_r0_b_D_0001_M_0011,
	load_disp_rm_r0_b_D_0010_M_0011,
	load_disp_rm_r0_b_D_0011_M_0011,
	load_disp_rm_r0_b_D_0100_M_0011,
	load_disp_rm_r0_b_D_0101_M_0011,
	load_disp_rm_r0_b_D_0110_M_0011,
	load_disp_rm_r0_b_D_0111_M_0011,
	load_disp_rm_r0_b_D_1000_M_0011,
	load_disp_rm_r0_b_D_1001_M_0011,
	load_disp_rm_r0_b_D_1010_M_0011,
	load_disp_rm_r0_b_D_1011_M_0011,
	load_disp_rm_r0_b_D_1100_M_0011,
	load_disp_rm_r0_b_D_1101_M_0011,
	load_disp_rm_r0_b_D_1110_M_0011,
	load_disp_rm_r0_b_D_1111_M_0011,
	load_disp_rm_r0_b_D_0000_M_0100,
	load_disp_rm_r0_b_D_0001_M_0100,
	load_disp_rm_r0_b_D_0010_M_0100,
	load_disp_rm_r0_b_D_0011_M_0100,
	load_disp_rm_r0_b_D_0100_M_0100,
	load_disp_rm_r0_b_D_0101_M_0100,
	load_disp_rm_r0_b_D_0110_M_0100,
	load_disp_rm_r0_b_D_0111_M_0100,
	load_disp_rm_r0_b_D_1000_M_0100,
	load_disp_rm_r0_b_D_1001_M_0100,
	load_disp_rm_r0_b_D_1010_M_0100,
	load_disp_rm_r0_b_D_1011_M_0100,
	load_disp_rm_r0_b_D_1100_M_0100,
	load_disp_rm_r0_b_D_1101_M_0100,
	load_disp_rm_r0_b_D_1110_M_0100,
	load_disp_rm_r0_b_D_1111_M_0100,
	load_disp_rm_r0_b_D_0000_M_0101,
	load_disp_rm_r0_b_D_0001_M_0101,
	load_disp_rm_r0_b_D_0010_M_0101,
	load_disp_rm_r0_b_D_0011_M_0101,
	load_disp_rm_r0_b_D_0100_M_0101,
	load_disp_rm_r0_b_D_0101_M_0101,
	load_disp_rm_r0_b_D_0110_M_0101,
	load_disp_rm_r0_b_D_0111_M_0101,
	load_disp_rm_r0_b_D_1000_M_0101,
	load_disp_rm_r0_b_D_1001_M_0101,
	load_disp_rm_r0_b_D_1010_M_0101,
	load_disp_rm_r0_b_D_1011_M_0101,
	load_disp_rm_r0_b_D_1100_M_0101,
	load_disp_rm_r0_b_D_1101_M_0101,
	load_disp_rm_r0_b_D_1110_M_0101,
	load_disp_rm_r0_b_D_1111_M_0101,
	load_disp_rm_r0_b_D_0000_M_0110,
	load_disp_rm_r0_b_D_0001_M_0110,
	load_disp_rm_r0_b_D_0010_M_0110,
	load_disp_rm_r0_b_D_0011_M_0110,
	load_disp_rm_r0_b_D_0100_M_0110,
	load_disp_rm_r0_b_D_0101_M_0110,
	load_disp_rm_r0_b_D_0110_M_0110,
	load_disp_rm_r0_b_D_0111_M_0110,
	load_disp_rm_r0_b_D_1000_M_0110,
	load_disp_rm_r0_b_D_1001_M_0110,
	load_disp_rm_r0_b_D_1010_M_0110,
	load_disp_rm_r0_b_D_1011_M_0110,
	load_disp_rm_r0_b_D_1100_M_0110,
	load_disp_rm_r0_b_D_1101_M_0110,
	load_disp_rm_r0_b_D_1110_M_0110,
	load_disp_rm_r0_b_D_1111_M_0110,
	load_disp_rm_r0_b_D_0000_M_0111,
	load_disp_rm_r0_b_D_0001_M_0111,
	load_disp_rm_r0_b_D_0010_M_0111,
	load_disp_rm_r0_b_D_0011_M_0111,
	load_disp_rm_r0_b_D_0100_M_0111,
	load_disp_rm_r0_b_D_0101_M_0111,
	load_disp_rm_r0_b_D_0110_M_0111,
	load_disp_rm_r0_b_D_0111_M_0111,
	load_disp_rm_r0_b_D_1000_M_0111,
	load_disp_rm_r0_b_D_1001_M_0111,
	load_disp_rm_r0_b_D_1010_M_0111,
	load_disp_rm_r0_b_D_1011_M_0111,
	load_disp_rm_r0_b_D_1100_M_0111,
	load_disp_rm_r0_b_D_1101_M_0111,
	load_disp_rm_r0_b_D_1110_M_0111,
	load_disp_rm_r0_b_D_1111_M_0111,
	load_disp_rm_r0_b_D_0000_M_1000,
	load_disp_rm_r0_b_D_0001_M_1000,
	load_disp_rm_r0_b_D_0010_M_1000,
	load_disp_rm_r0_b_D_0011_M_1000,
	load_disp_rm_r0_b_D_0100_M_1000,
	load_disp_rm_r0_b_D_0101_M_1000,
	load_disp_rm_r0_b_D_0110_M_1000,
	load_disp_rm_r0_b_D_0111_M_1000,
	load_disp_rm_r0_b_D_1000_M_1000,
	load_disp_rm_r0_b_D_1001_M_1000,
	load_disp_rm_r0_b_D_1010_M_1000,
	load_disp_rm_r0_b_D_1011_M_1000,
	load_disp_rm_r0_b_D_1100_M_1000,
	load_disp_rm_r0_b_D_1101_M_1000,
	load_disp_rm_r0_b_D_1110_M_1000,
	load_disp_rm_r0_b_D_1111_M_1000,
	load_disp_rm_r0_b_D_0000_M_1001,
	load_disp_rm_r0_b_D_0001_M_1001,
	load_disp_rm_r0_b_D_0010_M_1001,
	load_disp_rm_r0_b_D_0011_M_1001,
	load_disp_rm_r0_b_D_0100_M_1001,
	load_disp_rm_r0_b_D_0101_M_1001,
	load_disp_rm_r0_b_D_0110_M_1001,
	load_disp_rm_r0_b_D_0111_M_1001,
	load_disp_rm_r0_b_D_1000_M_1001,
	load_disp_rm_r0_b_D_1001_M_1001,
	load_disp_rm_r0_b_D_1010_M_1001,
	load_disp_rm_r0_b_D_1011_M_1001,
	load_disp_rm_r0_b_D_1100_M_1001,
	load_disp_rm_r0_b_D_1101_M_1001,
	load_disp_rm_r0_b_D_1110_M_1001,
	load_disp_rm_r0_b_D_1111_M_1001,
	load_disp_rm_r0_b_D_0000_M_1010,
	load_disp_rm_r0_b_D_0001_M_1010,
	load_disp_rm_r0_b_D_0010_M_1010,
	load_disp_rm_r0_b_D_0011_M_1010,
	load_disp_rm_r0_b_D_0100_M_1010,
	load_disp_rm_r0_b_D_0101_M_1010,
	load_disp_rm_r0_b_D_0110_M_1010,
	load_disp_rm_r0_b_D_0111_M_1010,
	load_disp_rm_r0_b_D_1000_M_1010,
	load_disp_rm_r0_b_D_1001_M_1010,
	load_disp_rm_r0_b_D_1010_M_1010,
	load_disp_rm_r0_b_D_1011_M_1010,
	load_disp_rm_r0_b_D_1100_M_1010,
	load_disp_rm_r0_b_D_1101_M_1010,
	load_disp_rm_r0_b_D_1110_M_1010,
	load_disp_rm_r0_b_D_1111_M_1010,
	load_disp_rm_r0_b_D_0000_M_1011,
	load_disp_rm_r0_b_D_0001_M_1011,
	load_disp_rm_r0_b_D_0010_M_1011,
	load_disp_rm_r0_b_D_0011_M_1011,
	load_disp_rm_r0_b_D_0100_M_1011,
	load_disp_rm_r0_b_D_0101_M_1011,
	load_disp_rm_r0_b_D_0110_M_1011,
	load_disp_rm_r0_b_D_0111_M_1011,
	load_disp_rm_r0_b_D_1000_M_1011,
	load_disp_rm_r0_b_D_1001_M_1011,
	load_disp_rm_r0_b_D_1010_M_1011,
	load_disp_rm_r0_b_D_1011_M_1011,
	load_disp_rm_r0_b_D_1100_M_1011,
	load_disp_rm_r0_b_D_1101_M_1011,
	load_disp_rm_r0_b_D_1110_M_1011,
	load_disp_rm_r0_b_D_1111_M_1011,
	load_disp_rm_r0_b_D_0000_M_1100,
	load_disp_rm_r0_b_D_0001_M_1100,
	load_disp_rm_r0_b_D_0010_M_1100,
	load_disp_rm_r0_b_D_0011_M_1100,
	load_disp_rm_r0_b_D_0100_M_1100,
	load_disp_rm_r0_b_D_0101_M_1100,
	load_disp_rm_r0_b_D_0110_M_1100,
	load_disp_rm_r0_b_D_0111_M_1100,
	load_disp_rm_r0_b_D_1000_M_1100,
	load_disp_rm_r0_b_D_1001_M_1100,
	load_disp_rm_r0_b_D_1010_M_1100,
	load_disp_rm_r0_b_D_1011_M_1100,
	load_disp_rm_r0_b_D_1100_M_1100,
	load_disp_rm_r0_b_D_1101_M_1100,
	load_disp_rm_r0_b_D_1110_M_1100,
	load_disp_rm_r0_b_D_1111_M_1100,
	load_disp_rm_r0_b_D_0000_M_1101,
	load_disp_rm_r0_b_D_0001_M_1101,
	load_disp_rm_r0_b_D_0010_M_1101,
	load_disp_rm_r0_b_D_0011_M_1101,
	load_disp_rm_r0_b_D_0100_M_1101,
	load_disp_rm_r0_b_D_0101_M_1101,
	load_disp_rm_r0_b_D_0110_M_1101,
	load_disp_rm_r0_b_D_0111_M_1101,
	load_disp_rm_r0_b_D_1000_M_1101,
	load_disp_rm_r0_b_D_1001_M_1101,
	load_disp_rm_r0_b_D_1010_M_1101,
	load_disp_rm_r0_b_D_1011_M_1101,
	load_disp_rm_r0_b_D_1100_M_1101,
	load_disp_rm_r0_b_D_1101_M_1101,
	load_disp_rm_r0_b_D_1110_M_1101,
	load_disp_rm_r0_b_D_1111_M_1101,
	load_disp_rm_r0_b_D_0000_M_1110,
	load_disp_rm_r0_b_D_0001_M_1110,
	load_disp_rm_r0_b_D_0010_M_1110,
	load_disp_rm_r0_b_D_0011_M_1110,
	load_disp_rm_r0_b_D_0100_M_1110,
	load_disp_rm_r0_b_D_0101_M_1110,
	load_disp_rm_r0_b_D_0110_M_1110,
	load_disp_rm_r0_b_D_0111_M_1110,
	load_disp_rm_r0_b_D_1000_M_1110,
	load_disp_rm_r0_b_D_1001_M_1110,
	load_disp_rm_r0_b_D_1010_M_1110,
	load_disp_rm_r0_b_D_1011_M_1110,
	load_disp_rm_r0_b_D_1100_M_1110,
	load_disp_rm_r0_b_D_1101_M_1110,
	load_disp_rm_r0_b_D_1110_M_1110,
	load_disp_rm_r0_b_D_1111_M_1110,
	load_disp_rm_r0_b_D_0000_M_1111,
	load_disp_rm_r0_b_D_0001_M_1111,
	load_disp_rm_r0_b_D_0010_M_1111,
	load_disp_rm_r0_b_D_0011_M_1111,
	load_disp_rm_r0_b_D_0100_M_1111,
	load_disp_rm_r0_b_D_0101_M_1111,
	load_disp_rm_r0_b_D_0110_M_1111,
	load_disp_rm_r0_b_D_0111_M_1111,
	load_disp_rm_r0_b_D_1000_M_1111,
	load_disp_rm_r0_b_D_1001_M_1111,
	load_disp_rm_r0_b_D_1010_M_1111,
	load_disp_rm_r0_b_D_1011_M_1111,
	load_disp_rm_r0_b_D_1100_M_1111,
	load_disp_rm_r0_b_D_1101_M_1111,
	load_disp_rm_r0_b_D_1110_M_1111,
	load_disp_rm_r0_b_D_1111_M_1111,
	load_disp_rm_r0_w_D_0000_M_0000,
	load_disp_rm_r0_w_D_0001_M_0000,
	load_disp_rm_r0_w_D_0010_M_0000,
	load_disp_rm_r0_w_D_0011_M_0000,
	load_disp_rm_r0_w_D_0100_M_0000,
	load_disp_rm_r0_w_D_0101_M_0000,
	load_disp_rm_r0_w_D_0110_M_0000,
	load_disp_rm_r0_w_D_0111_M_0000,
	load_disp_rm_r0_w_D_1000_M_0000,
	load_disp_rm_r0_w_D_1001_M_0000,
	load_disp_rm_r0_w_D_1010_M_0000,
	load_disp_rm_r0_w_D_1011_M_0000,
	load_disp_rm_r0_w_D_1100_M_0000,
	load_disp_rm_r0_w_D_1101_M_0000,
	load_disp_rm_r0_w_D_1110_M_0000,
	load_disp_rm_r0_w_D_1111_M_0000,
	load_disp_rm_r0_w_D_0000_M_0001,
	load_disp_rm_r0_w_D_0001_M_0001,
	load_disp_rm_r0_w_D_0010_M_0001,
	load_disp_rm_r0_w_D_0011_M_0001,
	load_disp_rm_r0_w_D_0100_M_0001,
	load_disp_rm_r0_w_D_0101_M_0001,
	load_disp_rm_r0_w_D_0110_M_0001,
	load_disp_rm_r0_w_D_0111_M_0001,
	load_disp_rm_r0_w_D_1000_M_0001,
	load_disp_rm_r0_w_D_1001_M_0001,
	load_disp_rm_r0_w_D_1010_M_0001,
	load_disp_rm_r0_w_D_1011_M_0001,
	load_disp_rm_r0_w_D_1100_M_0001,
	load_disp_rm_r0_w_D_1101_M_0001,
	load_disp_rm_r0_w_D_1110_M_0001,
	load_disp_rm_r0_w_D_1111_M_0001,
	load_disp_rm_r0_w_D_0000_M_0010,
	load_disp_rm_r0_w_D_0001_M_0010,
	load_disp_rm_r0_w_D_0010_M_0010,
	load_disp_rm_r0_w_D_0011_M_0010,
	load_disp_rm_r0_w_D_0100_M_0010,
	load_disp_rm_r0_w_D_0101_M_0010,
	load_disp_rm_r0_w_D_0110_M_0010,
	load_disp_rm_r0_w_D_0111_M_0010,
	load_disp_rm_r0_w_D_1000_M_0010,
	load_disp_rm_r0_w_D_1001_M_0010,
	load_disp_rm_r0_w_D_1010_M_0010,
	load_disp_rm_r0_w_D_1011_M_0010,
	load_disp_rm_r0_w_D_1100_M_0010,
	load_disp_rm_r0_w_D_1101_M_0010,
	load_disp_rm_r0_w_D_1110_M_0010,
	load_disp_rm_r0_w_D_1111_M_0010,
	load_disp_rm_r0_w_D_0000_M_0011,
	load_disp_rm_r0_w_D_0001_M_0011,
	load_disp_rm_r0_w_D_0010_M_0011,
	load_disp_rm_r0_w_D_0011_M_0011,
	load_disp_rm_r0_w_D_0100_M_0011,
	load_disp_rm_r0_w_D_0101_M_0011,
	load_disp_rm_r0_w_D_0110_M_0011,
	load_disp_rm_r0_w_D_0111_M_0011,
	load_disp_rm_r0_w_D_1000_M_0011,
	load_disp_rm_r0_w_D_1001_M_0011,
	load_disp_rm_r0_w_D_1010_M_0011,
	load_disp_rm_r0_w_D_1011_M_0011,
	load_disp_rm_r0_w_D_1100_M_0011,
	load_disp_rm_r0_w_D_1101_M_0011,
	load_disp_rm_r0_w_D_1110_M_0011,
	load_disp_rm_r0_w_D_1111_M_0011,
	load_disp_rm_r0_w_D_0000_M_0100,
	load_disp_rm_r0_w_D_0001_M_0100,
	load_disp_rm_r0_w_D_0010_M_0100,
	load_disp_rm_r0_w_D_0011_M_0100,
	load_disp_rm_r0_w_D_0100_M_0100,
	load_disp_rm_r0_w_D_0101_M_0100,
	load_disp_rm_r0_w_D_0110_M_0100,
	load_disp_rm_r0_w_D_0111_M_0100,
	load_disp_rm_r0_w_D_1000_M_0100,
	load_disp_rm_r0_w_D_1001_M_0100,
	load_disp_rm_r0_w_D_1010_M_0100,
	load_disp_rm_r0_w_D_1011_M_0100,
	load_disp_rm_r0_w_D_1100_M_0100,
	load_disp_rm_r0_w_D_1101_M_0100,
	load_disp_rm_r0_w_D_1110_M_0100,
	load_disp_rm_r0_w_D_1111_M_0100,
	load_disp_rm_r0_w_D_0000_M_0101,
	load_disp_rm_r0_w_D_0001_M_0101,
	load_disp_rm_r0_w_D_0010_M_0101,
	load_disp_rm_r0_w_D_0011_M_0101,
	load_disp_rm_r0_w_D_0100_M_0101,
	load_disp_rm_r0_w_D_0101_M_0101,
	load_disp_rm_r0_w_D_0110_M_0101,
	load_disp_rm_r0_w_D_0111_M_0101,
	load_disp_rm_r0_w_D_1000_M_0101,
	load_disp_rm_r0_w_D_1001_M_0101,
	load_disp_rm_r0_w_D_1010_M_0101,
	load_disp_rm_r0_w_D_1011_M_0101,
	load_disp_rm_r0_w_D_1100_M_0101,
	load_disp_rm_r0_w_D_1101_M_0101,
	load_disp_rm_r0_w_D_1110_M_0101,
	load_disp_rm_r0_w_D_1111_M_0101,
	load_disp_rm_r0_w_D_0000_M_0110,
	load_disp_rm_r0_w_D_0001_M_0110,
	load_disp_rm_r0_w_D_0010_M_0110,
	load_disp_rm_r0_w_D_0011_M_0110,
	load_disp_rm_r0_w_D_0100_M_0110,
	load_disp_rm_r0_w_D_0101_M_0110,
	load_disp_rm_r0_w_D_0110_M_0110,
	load_disp_rm_r0_w_D_0111_M_0110,
	load_disp_rm_r0_w_D_1000_M_0110,
	load_disp_rm_r0_w_D_1001_M_0110,
	load_disp_rm_r0_w_D_1010_M_0110,
	load_disp_rm_r0_w_D_1011_M_0110,
	load_disp_rm_r0_w_D_1100_M_0110,
	load_disp_rm_r0_w_D_1101_M_0110,
	load_disp_rm_r0_w_D_1110_M_0110,
	load_disp_rm_r0_w_D_1111_M_0110,
	load_disp_rm_r0_w_D_0000_M_0111,
	load_disp_rm_r0_w_D_0001_M_0111,
	load_disp_rm_r0_w_D_0010_M_0111,
	load_disp_rm_r0_w_D_0011_M_0111,
	load_disp_rm_r0_w_D_0100_M_0111,
	load_disp_rm_r0_w_D_0101_M_0111,
	load_disp_rm_r0_w_D_0110_M_0111,
	load_disp_rm_r0_w_D_0111_M_0111,
	load_disp_rm_r0_w_D_1000_M_0111,
	load_disp_rm_r0_w_D_1001_M_0111,
	load_disp_rm_r0_w_D_1010_M_0111,
	load_disp_rm_r0_w_D_1011_M_0111,
	load_disp_rm_r0_w_D_1100_M_0111,
	load_disp_rm_r0_w_D_1101_M_0111,
	load_disp_rm_r0_w_D_1110_M_0111,
	load_disp_rm_r0_w_D_1111_M_0111,
	load_disp_rm_r0_w_D_0000_M_1000,
	load_disp_rm_r0_w_D_0001_M_1000,
	load_disp_rm_r0_w_D_0010_M_1000,
	load_disp_rm_r0_w_D_0011_M_1000,
	load_disp_rm_r0_w_D_0100_M_1000,
	load_disp_rm_r0_w_D_0101_M_1000,
	load_disp_rm_r0_w_D_0110_M_1000,
	load_disp_rm_r0_w_D_0111_M_1000,
	load_disp_rm_r0_w_D_1000_M_1000,
	load_disp_rm_r0_w_D_1001_M_1000,
	load_disp_rm_r0_w_D_1010_M_1000,
	load_disp_rm_r0_w_D_1011_M_1000,
	load_disp_rm_r0_w_D_1100_M_1000,
	load_disp_rm_r0_w_D_1101_M_1000,
	load_disp_rm_r0_w_D_1110_M_1000,
	load_disp_rm_r0_w_D_1111_M_1000,
	load_disp_rm_r0_w_D_0000_M_1001,
	load_disp_rm_r0_w_D_0001_M_1001,
	load_disp_rm_r0_w_D_0010_M_1001,
	load_disp_rm_r0_w_D_0011_M_1001,
	load_disp_rm_r0_w_D_0100_M_1001,
	load_disp_rm_r0_w_D_0101_M_1001,
	load_disp_rm_r0_w_D_0110_M_1001,
	load_disp_rm_r0_w_D_0111_M_1001,
	load_disp_rm_r0_w_D_1000_M_1001,
	load_disp_rm_r0_w_D_1001_M_1001,
	load_disp_rm_r0_w_D_1010_M_1001,
	load_disp_rm_r0_w_D_1011_M_1001,
	load_disp_rm_r0_w_D_1100_M_1001,
	load_disp_rm_r0_w_D_1101_M_1001,
	load_disp_rm_r0_w_D_1110_M_1001,
	load_disp_rm_r0_w_D_1111_M_1001,
	load_disp_rm_r0_w_D_0000_M_1010,
	load_disp_rm_r0_w_D_0001_M_1010,
	load_disp_rm_r0_w_D_0010_M_1010,
	load_disp_rm_r0_w_D_0011_M_1010,
	load_disp_rm_r0_w_D_0100_M_1010,
	load_disp_rm_r0_w_D_0101_M_1010,
	load_disp_rm_r0_w_D_0110_M_1010,
	load_disp_rm_r0_w_D_0111_M_1010,
	load_disp_rm_r0_w_D_1000_M_1010,
	load_disp_rm_r0_w_D_1001_M_1010,
	load_disp_rm_r0_w_D_1010_M_1010,
	load_disp_rm_r0_w_D_1011_M_1010,
	load_disp_rm_r0_w_D_1100_M_1010,
	load_disp_rm_r0_w_D_1101_M_1010,
	load_disp_rm_r0_w_D_1110_M_1010,
	load_disp_rm_r0_w_D_1111_M_1010,
	load_disp_rm_r0_w_D_0000_M_1011,
	load_disp_rm_r0_w_D_0001_M_1011,
	load_disp_rm_r0_w_D_0010_M_1011,
	load_disp_rm_r0_w_D_0011_M_1011,
	load_disp_rm_r0_w_D_0100_M_1011,
	load_disp_rm_r0_w_D_0101_M_1011,
	load_disp_rm_r0_w_D_0110_M_1011,
	load_disp_rm_r0_w_D_0111_M_1011,
	load_disp_rm_r0_w_D_1000_M_1011,
	load_disp_rm_r0_w_D_1001_M_1011,
	load_disp_rm_r0_w_D_1010_M_1011,
	load_disp_rm_r0_w_D_1011_M_1011,
	load_disp_rm_r0_w_D_1100_M_1011,
	load_disp_rm_r0_w_D_1101_M_1011,
	load_disp_rm_r0_w_D_1110_M_1011,
	load_disp_rm_r0_w_D_1111_M_1011,
	load_disp_rm_r0_w_D_0000_M_1100,
	load_disp_rm_r0_w_D_0001_M_1100,
	load_disp_rm_r0_w_D_0010_M_1100,
	load_disp_rm_r0_w_D_0011_M_1100,
	load_disp_rm_r0_w_D_0100_M_1100,
	load_disp_rm_r0_w_D_0101_M_1100,
	load_disp_rm_r0_w_D_0110_M_1100,
	load_disp_rm_r0_w_D_0111_M_1100,
	load_disp_rm_r0_w_D_1000_M_1100,
	load_disp_rm_r0_w_D_1001_M_1100,
	load_disp_rm_r0_w_D_1010_M_1100,
	load_disp_rm_r0_w_D_1011_M_1100,
	load_disp_rm_r0_w_D_1100_M_1100,
	load_disp_rm_r0_w_D_1101_M_1100,
	load_disp_rm_r0_w_D_1110_M_1100,
	load_disp_rm_r0_w_D_1111_M_1100,
	load_disp_rm_r0_w_D_0000_M_1101,
	load_disp_rm_r0_w_D_0001_M_1101,
	load_disp_rm_r0_w_D_0010_M_1101,
	load_disp_rm_r0_w_D_0011_M_1101,
	load_disp_rm_r0_w_D_0100_M_1101,
	load_disp_rm_r0_w_D_0101_M_1101,
	load_disp_rm_r0_w_D_0110_M_1101,
	load_disp_rm_r0_w_D_0111_M_1101,
	load_disp_rm_r0_w_D_1000_M_1101,
	load_disp_rm_r0_w_D_1001_M_1101,
	load_disp_rm_r0_w_D_1010_M_1101,
	load_disp_rm_r0_w_D_1011_M_1101,
	load_disp_rm_r0_w_D_1100_M_1101,
	load_disp_rm_r0_w_D_1101_M_1101,
	load_disp_rm_r0_w_D_1110_M_1101,
	load_disp_rm_r0_w_D_1111_M_1101,
	load_disp_rm_r0_w_D_0000_M_1110,
	load_disp_rm_r0_w_D_0001_M_1110,
	load_disp_rm_r0_w_D_0010_M_1110,
	load_disp_rm_r0_w_D_0011_M_1110,
	load_disp_rm_r0_w_D_0100_M_1110,
	load_disp_rm_r0_w_D_0101_M_1110,
	load_disp_rm_r0_w_D_0110_M_1110,
	load_disp_rm_r0_w_D_0111_M_1110,
	load_disp_rm_r0_w_D_1000_M_1110,
	load_disp_rm_r0_w_D_1001_M_1110,
	load_disp_rm_r0_w_D_1010_M_1110,
	load_disp_rm_r0_w_D_1011_M_1110,
	load_disp_rm_r0_w_D_1100_M_1110,
	load_disp_rm_r0_w_D_1101_M_1110,
	load_disp_rm_r0_w_D_1110_M_1110,
	load_disp_rm_r0_w_D_1111_M_1110,
	load_disp_rm_r0_w_D_0000_M_1111,
	load_disp_rm_r0_w_D_0001_M_1111,
	load_disp_rm_r0_w_D_0010_M_1111,
	load_disp_rm_r0_w_D_0011_M_1111,
	load_disp_rm_r0_w_D_0100_M_1111,
	load_disp_rm_r0_w_D_0101_M_1111,
	load_disp_rm_r0_w_D_0110_M_1111,
	load_disp_rm_r0_w_D_0111_M_1111,
	load_disp_rm_r0_w_D_1000_M_1111,
	load_disp_rm_r0_w_D_1001_M_1111,
	load_disp_rm_r0_w_D_1010_M_1111,
	load_disp_rm_r0_w_D_1011_M_1111,
	load_disp_rm_r0_w_D_1100_M_1111,
	load_disp_rm_r0_w_D_1101_M_1111,
	load_disp_rm_r0_w_D_1110_M_1111,
	load_disp_rm_r0_w_D_1111_M_1111,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	cmpeq_imm_r0,
	bt_D_00000000,
	bt_D_00000001,
	bt_D_00000010,
	bt_D_00000011,
	bt_D_00000100,
	bt_D_00000101,
	bt_D_00000110,
	bt_D_00000111,
	bt_D_00001000,
	bt_D_00001001,
	bt_D_00001010,
	bt_D_00001011,
	bt_D_00001100,
	bt_D_00001101,
	bt_D_00001110,
	bt_D_00001111,
	bt_D_00010000,
	bt_D_00010001,
	bt_D_00010010,
	bt_D_00010011,
	bt_D_00010100,
	bt_D_00010101,
	bt_D_00010110,
	bt_D_00010111,
	bt_D_00011000,
	bt_D_00011001,
	bt_D_00011010,
	bt_D_00011011,
	bt_D_00011100,
	bt_D_00011101,
	bt_D_00011110,
	bt_D_00011111,
	bt_D_00100000,
	bt_D_00100001,
	bt_D_00100010,
	bt_D_00100011,
	bt_D_00100100,
	bt_D_00100101,
	bt_D_00100110,
	bt_D_00100111,
	bt_D_00101000,
	bt_D_00101001,
	bt_D_00101010,
	bt_D_00101011,
	bt_D_00101100,
	bt_D_00101101,
	bt_D_00101110,
	bt_D_00101111,
	bt_D_00110000,
	bt_D_00110001,
	bt_D_00110010,
	bt_D_00110011,
	bt_D_00110100,
	bt_D_00110101,
	bt_D_00110110,
	bt_D_00110111,
	bt_D_00111000,
	bt_D_00111001,
	bt_D_00111010,
	bt_D_00111011,
	bt_D_00111100,
	bt_D_00111101,
	bt_D_00111110,
	bt_D_00111111,
	bt_D_01000000,
	bt_D_01000001,
	bt_D_01000010,
	bt_D_01000011,
	bt_D_01000100,
	bt_D_01000101,
	bt_D_01000110,
	bt_D_01000111,
	bt_D_01001000,
	bt_D_01001001,
	bt_D_01001010,
	bt_D_01001011,
	bt_D_01001100,
	bt_D_01001101,
	bt_D_01001110,
	bt_D_01001111,
	bt_D_01010000,
	bt_D_01010001,
	bt_D_01010010,
	bt_D_01010011,
	bt_D_01010100,
	bt_D_01010101,
	bt_D_01010110,
	bt_D_01010111,
	bt_D_01011000,
	bt_D_01011001,
	bt_D_01011010,
	bt_D_01011011,
	bt_D_01011100,
	bt_D_01011101,
	bt_D_01011110,
	bt_D_01011111,
	bt_D_01100000,
	bt_D_01100001,
	bt_D_01100010,
	bt_D_01100011,
	bt_D_01100100,
	bt_D_01100101,
	bt_D_01100110,
	bt_D_01100111,
	bt_D_01101000,
	bt_D_01101001,
	bt_D_01101010,
	bt_D_01101011,
	bt_D_01101100,
	bt_D_01101101,
	bt_D_01101110,
	bt_D_01101111,
	bt_D_01110000,
	bt_D_01110001,
	bt_D_01110010,
	bt_D_01110011,
	bt_D_01110100,
	bt_D_01110101,
	bt_D_01110110,
	bt_D_01110111,
	bt_D_01111000,
	bt_D_01111001,
	bt_D_01111010,
	bt_D_01111011,
	bt_D_01111100,
	bt_D_01111101,
	bt_D_01111110,
	bt_D_01111111,
	bt_D_10000000,
	bt_D_10000001,
	bt_D_10000010,
	bt_D_10000011,
	bt_D_10000100,
	bt_D_10000101,
	bt_D_10000110,
	bt_D_10000111,
	bt_D_10001000,
	bt_D_10001001,
	bt_D_10001010,
	bt_D_10001011,
	bt_D_10001100,
	bt_D_10001101,
	bt_D_10001110,
	bt_D_10001111,
	bt_D_10010000,
	bt_D_10010001,
	bt_D_10010010,
	bt_D_10010011,
	bt_D_10010100,
	bt_D_10010101,
	bt_D_10010110,
	bt_D_10010111,
	bt_D_10011000,
	bt_D_10011001,
	bt_D_10011010,
	bt_D_10011011,
	bt_D_10011100,
	bt_D_10011101,
	bt_D_10011110,
	bt_D_10011111,
	bt_D_10100000,
	bt_D_10100001,
	bt_D_10100010,
	bt_D_10100011,
	bt_D_10100100,
	bt_D_10100101,
	bt_D_10100110,
	bt_D_10100111,
	bt_D_10101000,
	bt_D_10101001,
	bt_D_10101010,
	bt_D_10101011,
	bt_D_10101100,
	bt_D_10101101,
	bt_D_10101110,
	bt_D_10101111,
	bt_D_10110000,
	bt_D_10110001,
	bt_D_10110010,
	bt_D_10110011,
	bt_D_10110100,
	bt_D_10110101,
	bt_D_10110110,
	bt_D_10110111,
	bt_D_10111000,
	bt_D_10111001,
	bt_D_10111010,
	bt_D_10111011,
	bt_D_10111100,
	bt_D_10111101,
	bt_D_10111110,
	bt_D_10111111,
	bt_D_11000000,
	bt_D_11000001,
	bt_D_11000010,
	bt_D_11000011,
	bt_D_11000100,
	bt_D_11000101,
	bt_D_11000110,
	bt_D_11000111,
	bt_D_11001000,
	bt_D_11001001,
	bt_D_11001010,
	bt_D_11001011,
	bt_D_11001100,
	bt_D_11001101,
	bt_D_11001110,
	bt_D_11001111,
	bt_D_11010000,
	bt_D_11010001,
	bt_D_11010010,
	bt_D_11010011,
	bt_D_11010100,
	bt_D_11010101,
	bt_D_11010110,
	bt_D_11010111,
	bt_D_11011000,
	bt_D_11011001,
	bt_D_11011010,
	bt_D_11011011,
	bt_D_11011100,
	bt_D_11011101,
	bt_D_11011110,
	bt_D_11011111,
	bt_D_11100000,
	bt_D_11100001,
	bt_D_11100010,
	bt_D_11100011,
	bt_D_11100100,
	bt_D_11100101,
	bt_D_11100110,
	bt_D_11100111,
	bt_D_11101000,
	bt_D_11101001,
	bt_D_11101010,
	bt_D_11101011,
	bt_D_11101100,
	bt_D_11101101,
	bt_D_11101110,
	bt_D_11101111,
	bt_D_11110000,
	bt_D_11110001,
	bt_D_11110010,
	bt_D_11110011,
	bt_D_11110100,
	bt_D_11110101,
	bt_D_11110110,
	bt_D_11110111,
	bt_D_11111000,
	bt_D_11111001,
	bt_D_11111010,
	bt_D_11111011,
	bt_D_11111100,
	bt_D_11111101,
	bt_D_11111110,
	bt_D_11111111,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	bf_D_00000000,
	bf_D_00000001,
	bf_D_00000010,
	bf_D_00000011,
	bf_D_00000100,
	bf_D_00000101,
	bf_D_00000110,
	bf_D_00000111,
	bf_D_00001000,
	bf_D_00001001,
	bf_D_00001010,
	bf_D_00001011,
	bf_D_00001100,
	bf_D_00001101,
	bf_D_00001110,
	bf_D_00001111,
	bf_D_00010000,
	bf_D_00010001,
	bf_D_00010010,
	bf_D_00010011,
	bf_D_00010100,
	bf_D_00010101,
	bf_D_00010110,
	bf_D_00010111,
	bf_D_00011000,
	bf_D_00011001,
	bf_D_00011010,
	bf_D_00011011,
	bf_D_00011100,
	bf_D_00011101,
	bf_D_00011110,
	bf_D_00011111,
	bf_D_00100000,
	bf_D_00100001,
	bf_D_00100010,
	bf_D_00100011,
	bf_D_00100100,
	bf_D_00100101,
	bf_D_00100110,
	bf_D_00100111,
	bf_D_00101000,
	bf_D_00101001,
	bf_D_00101010,
	bf_D_00101011,
	bf_D_00101100,
	bf_D_00101101,
	bf_D_00101110,
	bf_D_00101111,
	bf_D_00110000,
	bf_D_00110001,
	bf_D_00110010,
	bf_D_00110011,
	bf_D_00110100,
	bf_D_00110101,
	bf_D_00110110,
	bf_D_00110111,
	bf_D_00111000,
	bf_D_00111001,
	bf_D_00111010,
	bf_D_00111011,
	bf_D_00111100,
	bf_D_00111101,
	bf_D_00111110,
	bf_D_00111111,
	bf_D_01000000,
	bf_D_01000001,
	bf_D_01000010,
	bf_D_01000011,
	bf_D_01000100,
	bf_D_01000101,
	bf_D_01000110,
	bf_D_01000111,
	bf_D_01001000,
	bf_D_01001001,
	bf_D_01001010,
	bf_D_01001011,
	bf_D_01001100,
	bf_D_01001101,
	bf_D_01001110,
	bf_D_01001111,
	bf_D_01010000,
	bf_D_01010001,
	bf_D_01010010,
	bf_D_01010011,
	bf_D_01010100,
	bf_D_01010101,
	bf_D_01010110,
	bf_D_01010111,
	bf_D_01011000,
	bf_D_01011001,
	bf_D_01011010,
	bf_D_01011011,
	bf_D_01011100,
	bf_D_01011101,
	bf_D_01011110,
	bf_D_01011111,
	bf_D_01100000,
	bf_D_01100001,
	bf_D_01100010,
	bf_D_01100011,
	bf_D_01100100,
	bf_D_01100101,
	bf_D_01100110,
	bf_D_01100111,
	bf_D_01101000,
	bf_D_01101001,
	bf_D_01101010,
	bf_D_01101011,
	bf_D_01101100,
	bf_D_01101101,
	bf_D_01101110,
	bf_D_01101111,
	bf_D_01110000,
	bf_D_01110001,
	bf_D_01110010,
	bf_D_01110011,
	bf_D_01110100,
	bf_D_01110101,
	bf_D_01110110,
	bf_D_01110111,
	bf_D_01111000,
	bf_D_01111001,
	bf_D_01111010,
	bf_D_01111011,
	bf_D_01111100,
	bf_D_01111101,
	bf_D_01111110,
	bf_D_01111111,
	bf_D_10000000,
	bf_D_10000001,
	bf_D_10000010,
	bf_D_10000011,
	bf_D_10000100,
	bf_D_10000101,
	bf_D_10000110,
	bf_D_10000111,
	bf_D_10001000,
	bf_D_10001001,
	bf_D_10001010,
	bf_D_10001011,
	bf_D_10001100,
	bf_D_10001101,
	bf_D_10001110,
	bf_D_10001111,
	bf_D_10010000,
	bf_D_10010001,
	bf_D_10010010,
	bf_D_10010011,
	bf_D_10010100,
	bf_D_10010101,
	bf_D_10010110,
	bf_D_10010111,
	bf_D_10011000,
	bf_D_10011001,
	bf_D_10011010,
	bf_D_10011011,
	bf_D_10011100,
	bf_D_10011101,
	bf_D_10011110,
	bf_D_10011111,
	bf_D_10100000,
	bf_D_10100001,
	bf_D_10100010,
	bf_D_10100011,
	bf_D_10100100,
	bf_D_10100101,
	bf_D_10100110,
	bf_D_10100111,
	bf_D_10101000,
	bf_D_10101001,
	bf_D_10101010,
	bf_D_10101011,
	bf_D_10101100,
	bf_D_10101101,
	bf_D_10101110,
	bf_D_10101111,
	bf_D_10110000,
	bf_D_10110001,
	bf_D_10110010,
	bf_D_10110011,
	bf_D_10110100,
	bf_D_10110101,
	bf_D_10110110,
	bf_D_10110111,
	bf_D_10111000,
	bf_D_10111001,
	bf_D_10111010,
	bf_D_10111011,
	bf_D_10111100,
	bf_D_10111101,
	bf_D_10111110,
	bf_D_10111111,
	bf_D_11000000,
	bf_D_11000001,
	bf_D_11000010,
	bf_D_11000011,
	bf_D_11000100,
	bf_D_11000101,
	bf_D_11000110,
	bf_D_11000111,
	bf_D_11001000,
	bf_D_11001001,
	bf_D_11001010,
	bf_D_11001011,
	bf_D_11001100,
	bf_D_11001101,
	bf_D_11001110,
	bf_D_11001111,
	bf_D_11010000,
	bf_D_11010001,
	bf_D_11010010,
	bf_D_11010011,
	bf_D_11010100,
	bf_D_11010101,
	bf_D_11010110,
	bf_D_11010111,
	bf_D_11011000,
	bf_D_11011001,
	bf_D_11011010,
	bf_D_11011011,
	bf_D_11011100,
	bf_D_11011101,
	bf_D_11011110,
	bf_D_11011111,
	bf_D_11100000,
	bf_D_11100001,
	bf_D_11100010,
	bf_D_11100011,
	bf_D_11100100,
	bf_D_11100101,
	bf_D_11100110,
	bf_D_11100111,
	bf_D_11101000,
	bf_D_11101001,
	bf_D_11101010,
	bf_D_11101011,
	bf_D_11101100,
	bf_D_11101101,
	bf_D_11101110,
	bf_D_11101111,
	bf_D_11110000,
	bf_D_11110001,
	bf_D_11110010,
	bf_D_11110011,
	bf_D_11110100,
	bf_D_11110101,
	bf_D_11110110,
	bf_D_11110111,
	bf_D_11111000,
	bf_D_11111001,
	bf_D_11111010,
	bf_D_11111011,
	bf_D_11111100,
	bf_D_11111101,
	bf_D_11111110,
	bf_D_11111111,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	bt_s_D_00000000,
	bt_s_D_00000001,
	bt_s_D_00000010,
	bt_s_D_00000011,
	bt_s_D_00000100,
	bt_s_D_00000101,
	bt_s_D_00000110,
	bt_s_D_00000111,
	bt_s_D_00001000,
	bt_s_D_00001001,
	bt_s_D_00001010,
	bt_s_D_00001011,
	bt_s_D_00001100,
	bt_s_D_00001101,
	bt_s_D_00001110,
	bt_s_D_00001111,
	bt_s_D_00010000,
	bt_s_D_00010001,
	bt_s_D_00010010,
	bt_s_D_00010011,
	bt_s_D_00010100,
	bt_s_D_00010101,
	bt_s_D_00010110,
	bt_s_D_00010111,
	bt_s_D_00011000,
	bt_s_D_00011001,
	bt_s_D_00011010,
	bt_s_D_00011011,
	bt_s_D_00011100,
	bt_s_D_00011101,
	bt_s_D_00011110,
	bt_s_D_00011111,
	bt_s_D_00100000,
	bt_s_D_00100001,
	bt_s_D_00100010,
	bt_s_D_00100011,
	bt_s_D_00100100,
	bt_s_D_00100101,
	bt_s_D_00100110,
	bt_s_D_00100111,
	bt_s_D_00101000,
	bt_s_D_00101001,
	bt_s_D_00101010,
	bt_s_D_00101011,
	bt_s_D_00101100,
	bt_s_D_00101101,
	bt_s_D_00101110,
	bt_s_D_00101111,
	bt_s_D_00110000,
	bt_s_D_00110001,
	bt_s_D_00110010,
	bt_s_D_00110011,
	bt_s_D_00110100,
	bt_s_D_00110101,
	bt_s_D_00110110,
	bt_s_D_00110111,
	bt_s_D_00111000,
	bt_s_D_00111001,
	bt_s_D_00111010,
	bt_s_D_00111011,
	bt_s_D_00111100,
	bt_s_D_00111101,
	bt_s_D_00111110,
	bt_s_D_00111111,
	bt_s_D_01000000,
	bt_s_D_01000001,
	bt_s_D_01000010,
	bt_s_D_01000011,
	bt_s_D_01000100,
	bt_s_D_01000101,
	bt_s_D_01000110,
	bt_s_D_01000111,
	bt_s_D_01001000,
	bt_s_D_01001001,
	bt_s_D_01001010,
	bt_s_D_01001011,
	bt_s_D_01001100,
	bt_s_D_01001101,
	bt_s_D_01001110,
	bt_s_D_01001111,
	bt_s_D_01010000,
	bt_s_D_01010001,
	bt_s_D_01010010,
	bt_s_D_01010011,
	bt_s_D_01010100,
	bt_s_D_01010101,
	bt_s_D_01010110,
	bt_s_D_01010111,
	bt_s_D_01011000,
	bt_s_D_01011001,
	bt_s_D_01011010,
	bt_s_D_01011011,
	bt_s_D_01011100,
	bt_s_D_01011101,
	bt_s_D_01011110,
	bt_s_D_01011111,
	bt_s_D_01100000,
	bt_s_D_01100001,
	bt_s_D_01100010,
	bt_s_D_01100011,
	bt_s_D_01100100,
	bt_s_D_01100101,
	bt_s_D_01100110,
	bt_s_D_01100111,
	bt_s_D_01101000,
	bt_s_D_01101001,
	bt_s_D_01101010,
	bt_s_D_01101011,
	bt_s_D_01101100,
	bt_s_D_01101101,
	bt_s_D_01101110,
	bt_s_D_01101111,
	bt_s_D_01110000,
	bt_s_D_01110001,
	bt_s_D_01110010,
	bt_s_D_01110011,
	bt_s_D_01110100,
	bt_s_D_01110101,
	bt_s_D_01110110,
	bt_s_D_01110111,
	bt_s_D_01111000,
	bt_s_D_01111001,
	bt_s_D_01111010,
	bt_s_D_01111011,
	bt_s_D_01111100,
	bt_s_D_01111101,
	bt_s_D_01111110,
	bt_s_D_01111111,
	bt_s_D_10000000,
	bt_s_D_10000001,
	bt_s_D_10000010,
	bt_s_D_10000011,
	bt_s_D_10000100,
	bt_s_D_10000101,
	bt_s_D_10000110,
	bt_s_D_10000111,
	bt_s_D_10001000,
	bt_s_D_10001001,
	bt_s_D_10001010,
	bt_s_D_10001011,
	bt_s_D_10001100,
	bt_s_D_10001101,
	bt_s_D_10001110,
	bt_s_D_10001111,
	bt_s_D_10010000,
	bt_s_D_10010001,
	bt_s_D_10010010,
	bt_s_D_10010011,
	bt_s_D_10010100,
	bt_s_D_10010101,
	bt_s_D_10010110,
	bt_s_D_10010111,
	bt_s_D_10011000,
	bt_s_D_10011001,
	bt_s_D_10011010,
	bt_s_D_10011011,
	bt_s_D_10011100,
	bt_s_D_10011101,
	bt_s_D_10011110,
	bt_s_D_10011111,
	bt_s_D_10100000,
	bt_s_D_10100001,
	bt_s_D_10100010,
	bt_s_D_10100011,
	bt_s_D_10100100,
	bt_s_D_10100101,
	bt_s_D_10100110,
	bt_s_D_10100111,
	bt_s_D_10101000,
	bt_s_D_10101001,
	bt_s_D_10101010,
	bt_s_D_10101011,
	bt_s_D_10101100,
	bt_s_D_10101101,
	bt_s_D_10101110,
	bt_s_D_10101111,
	bt_s_D_10110000,
	bt_s_D_10110001,
	bt_s_D_10110010,
	bt_s_D_10110011,
	bt_s_D_10110100,
	bt_s_D_10110101,
	bt_s_D_10110110,
	bt_s_D_10110111,
	bt_s_D_10111000,
	bt_s_D_10111001,
	bt_s_D_10111010,
	bt_s_D_10111011,
	bt_s_D_10111100,
	bt_s_D_10111101,
	bt_s_D_10111110,
	bt_s_D_10111111,
	bt_s_D_11000000,
	bt_s_D_11000001,
	bt_s_D_11000010,
	bt_s_D_11000011,
	bt_s_D_11000100,
	bt_s_D_11000101,
	bt_s_D_11000110,
	bt_s_D_11000111,
	bt_s_D_11001000,
	bt_s_D_11001001,
	bt_s_D_11001010,
	bt_s_D_11001011,
	bt_s_D_11001100,
	bt_s_D_11001101,
	bt_s_D_11001110,
	bt_s_D_11001111,
	bt_s_D_11010000,
	bt_s_D_11010001,
	bt_s_D_11010010,
	bt_s_D_11010011,
	bt_s_D_11010100,
	bt_s_D_11010101,
	bt_s_D_11010110,
	bt_s_D_11010111,
	bt_s_D_11011000,
	bt_s_D_11011001,
	bt_s_D_11011010,
	bt_s_D_11011011,
	bt_s_D_11011100,
	bt_s_D_11011101,
	bt_s_D_11011110,
	bt_s_D_11011111,
	bt_s_D_11100000,
	bt_s_D_11100001,
	bt_s_D_11100010,
	bt_s_D_11100011,
	bt_s_D_11100100,
	bt_s_D_11100101,
	bt_s_D_11100110,
	bt_s_D_11100111,
	bt_s_D_11101000,
	bt_s_D_11101001,
	bt_s_D_11101010,
	bt_s_D_11101011,
	bt_s_D_11101100,
	bt_s_D_11101101,
	bt_s_D_11101110,
	bt_s_D_11101111,
	bt_s_D_11110000,
	bt_s_D_11110001,
	bt_s_D_11110010,
	bt_s_D_11110011,
	bt_s_D_11110100,
	bt_s_D_11110101,
	bt_s_D_11110110,
	bt_s_D_11110111,
	bt_s_D_11111000,
	bt_s_D_11111001,
	bt_s_D_11111010,
	bt_s_D_11111011,
	bt_s_D_11111100,
	bt_s_D_11111101,
	bt_s_D_11111110,
	bt_s_D_11111111,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	bf_s_D_00000000,
	bf_s_D_00000001,
	bf_s_D_00000010,
	bf_s_D_00000011,
	bf_s_D_00000100,
	bf_s_D_00000101,
	bf_s_D_00000110,
	bf_s_D_00000111,
	bf_s_D_00001000,
	bf_s_D_00001001,
	bf_s_D_00001010,
	bf_s_D_00001011,
	bf_s_D_00001100,
	bf_s_D_00001101,
	bf_s_D_00001110,
	bf_s_D_00001111,
	bf_s_D_00010000,
	bf_s_D_00010001,
	bf_s_D_00010010,
	bf_s_D_00010011,
	bf_s_D_00010100,
	bf_s_D_00010101,
	bf_s_D_00010110,
	bf_s_D_00010111,
	bf_s_D_00011000,
	bf_s_D_00011001,
	bf_s_D_00011010,
	bf_s_D_00011011,
	bf_s_D_00011100,
	bf_s_D_00011101,
	bf_s_D_00011110,
	bf_s_D_00011111,
	bf_s_D_00100000,
	bf_s_D_00100001,
	bf_s_D_00100010,
	bf_s_D_00100011,
	bf_s_D_00100100,
	bf_s_D_00100101,
	bf_s_D_00100110,
	bf_s_D_00100111,
	bf_s_D_00101000,
	bf_s_D_00101001,
	bf_s_D_00101010,
	bf_s_D_00101011,
	bf_s_D_00101100,
	bf_s_D_00101101,
	bf_s_D_00101110,
	bf_s_D_00101111,
	bf_s_D_00110000,
	bf_s_D_00110001,
	bf_s_D_00110010,
	bf_s_D_00110011,
	bf_s_D_00110100,
	bf_s_D_00110101,
	bf_s_D_00110110,
	bf_s_D_00110111,
	bf_s_D_00111000,
	bf_s_D_00111001,
	bf_s_D_00111010,
	bf_s_D_00111011,
	bf_s_D_00111100,
	bf_s_D_00111101,
	bf_s_D_00111110,
	bf_s_D_00111111,
	bf_s_D_01000000,
	bf_s_D_01000001,
	bf_s_D_01000010,
	bf_s_D_01000011,
	bf_s_D_01000100,
	bf_s_D_01000101,
	bf_s_D_01000110,
	bf_s_D_01000111,
	bf_s_D_01001000,
	bf_s_D_01001001,
	bf_s_D_01001010,
	bf_s_D_01001011,
	bf_s_D_01001100,
	bf_s_D_01001101,
	bf_s_D_01001110,
	bf_s_D_01001111,
	bf_s_D_01010000,
	bf_s_D_01010001,
	bf_s_D_01010010,
	bf_s_D_01010011,
	bf_s_D_01010100,
	bf_s_D_01010101,
	bf_s_D_01010110,
	bf_s_D_01010111,
	bf_s_D_01011000,
	bf_s_D_01011001,
	bf_s_D_01011010,
	bf_s_D_01011011,
	bf_s_D_01011100,
	bf_s_D_01011101,
	bf_s_D_01011110,
	bf_s_D_01011111,
	bf_s_D_01100000,
	bf_s_D_01100001,
	bf_s_D_01100010,
	bf_s_D_01100011,
	bf_s_D_01100100,
	bf_s_D_01100101,
	bf_s_D_01100110,
	bf_s_D_01100111,
	bf_s_D_01101000,
	bf_s_D_01101001,
	bf_s_D_01101010,
	bf_s_D_01101011,
	bf_s_D_01101100,
	bf_s_D_01101101,
	bf_s_D_01101110,
	bf_s_D_01101111,
	bf_s_D_01110000,
	bf_s_D_01110001,
	bf_s_D_01110010,
	bf_s_D_01110011,
	bf_s_D_01110100,
	bf_s_D_01110101,
	bf_s_D_01110110,
	bf_s_D_01110111,
	bf_s_D_01111000,
	bf_s_D_01111001,
	bf_s_D_01111010,
	bf_s_D_01111011,
	bf_s_D_01111100,
	bf_s_D_01111101,
	bf_s_D_01111110,
	bf_s_D_01111111,
	bf_s_D_10000000,
	bf_s_D_10000001,
	bf_s_D_10000010,
	bf_s_D_10000011,
	bf_s_D_10000100,
	bf_s_D_10000101,
	bf_s_D_10000110,
	bf_s_D_10000111,
	bf_s_D_10001000,
	bf_s_D_10001001,
	bf_s_D_10001010,
	bf_s_D_10001011,
	bf_s_D_10001100,
	bf_s_D_10001101,
	bf_s_D_10001110,
	bf_s_D_10001111,
	bf_s_D_10010000,
	bf_s_D_10010001,
	bf_s_D_10010010,
	bf_s_D_10010011,
	bf_s_D_10010100,
	bf_s_D_10010101,
	bf_s_D_10010110,
	bf_s_D_10010111,
	bf_s_D_10011000,
	bf_s_D_10011001,
	bf_s_D_10011010,
	bf_s_D_10011011,
	bf_s_D_10011100,
	bf_s_D_10011101,
	bf_s_D_10011110,
	bf_s_D_10011111,
	bf_s_D_10100000,
	bf_s_D_10100001,
	bf_s_D_10100010,
	bf_s_D_10100011,
	bf_s_D_10100100,
	bf_s_D_10100101,
	bf_s_D_10100110,
	bf_s_D_10100111,
	bf_s_D_10101000,
	bf_s_D_10101001,
	bf_s_D_10101010,
	bf_s_D_10101011,
	bf_s_D_10101100,
	bf_s_D_10101101,
	bf_s_D_10101110,
	bf_s_D_10101111,
	bf_s_D_10110000,
	bf_s_D_10110001,
	bf_s_D_10110010,
	bf_s_D_10110011,
	bf_s_D_10110100,
	bf_s_D_10110101,
	bf_s_D_10110110,
	bf_s_D_10110111,
	bf_s_D_10111000,
	bf_s_D_10111001,
	bf_s_D_10111010,
	bf_s_D_10111011,
	bf_s_D_10111100,
	bf_s_D_10111101,
	bf_s_D_10111110,
	bf_s_D_10111111,
	bf_s_D_11000000,
	bf_s_D_11000001,
	bf_s_D_11000010,
	bf_s_D_11000011,
	bf_s_D_11000100,
	bf_s_D_11000101,
	bf_s_D_11000110,
	bf_s_D_11000111,
	bf_s_D_11001000,
	bf_s_D_11001001,
	bf_s_D_11001010,
	bf_s_D_11001011,
	bf_s_D_11001100,
	bf_s_D_11001101,
	bf_s_D_11001110,
	bf_s_D_11001111,
	bf_s_D_11010000,
	bf_s_D_11010001,
	bf_s_D_11010010,
	bf_s_D_11010011,
	bf_s_D_11010100,
	bf_s_D_11010101,
	bf_s_D_11010110,
	bf_s_D_11010111,
	bf_s_D_11011000,
	bf_s_D_11011001,
	bf_s_D_11011010,
	bf_s_D_11011011,
	bf_s_D_11011100,
	bf_s_D_11011101,
	bf_s_D_11011110,
	bf_s_D_11011111,
	bf_s_D_11100000,
	bf_s_D_11100001,
	bf_s_D_11100010,
	bf_s_D_11100011,
	bf_s_D_11100100,
	bf_s_D_11100101,
	bf_s_D_11100110,
	bf_s_D_11100111,
	bf_s_D_11101000,
	bf_s_D_11101001,
	bf_s_D_11101010,
	bf_s_D_11101011,
	bf_s_D_11101100,
	bf_s_D_11101101,
	bf_s_D_11101110,
	bf_s_D_11101111,
	bf_s_D_11110000,
	bf_s_D_11110001,
	bf_s_D_11110010,
	bf_s_D_11110011,
	bf_s_D_11110100,
	bf_s_D_11110101,
	bf_s_D_11110110,
	bf_s_D_11110111,
	bf_s_D_11111000,
	bf_s_D_11111001,
	bf_s_D_11111010,
	bf_s_D_11111011,
	bf_s_D_11111100,
	bf_s_D_11111101,
	bf_s_D_11111110,
	bf_s_D_11111111,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0000,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0001,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0010,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0011,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0100,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0101,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0110,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_0111,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1000,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1001,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1010,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1011,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1100,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1101,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1110,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	mov_disp_w_pc_N_1111,
	bra,
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	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	bsr,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_b,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_w,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	store_r0_disp_gpr_l,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	trapa,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_b,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_w,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	load_disp_gbr_r0_l,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	mova,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	tst_imm_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	andi_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	xor_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	or_imm_r0,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	tst_imm_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	andi_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	xor_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	or_imm_r0_gbr,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0000,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0001,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0010,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0011,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0100,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0101,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0110,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_0111,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1000,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1001,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1010,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1011,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1100,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1101,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1110,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_disp_l_pc_N_1111,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0000,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0001,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0010,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0011,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0100,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0101,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0110,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_0111,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1000,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1001,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1010,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1011,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1100,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1101,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1110,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	mov_imm_N_1111,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
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void sh2_execute(sh2_context *context, uint32_t target_cycle)
{
	uint32_t sh2_write32_tmp;
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	uint32_t sh2_interrupt_cmp_tmp32__;
	sh2_sync_cycle(context, target_cycle);
	if (context->breakpoints) {
		while (context->cycles < target_cycle)
		{
			if (context->cycles >= context->sync_cycle) {
				sh2_sync_cycle(context, target_cycle);
			}
	if (context->delay_slot) {
	} else {
	if (context->cycles >= context->int_cycle) {
	if (context->int_ack) {
	context->int_ack(context);
	}
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[15] = context->gpr[15] - 4;
	context->sr = 240 & context->sr;
	if (context->t) {
	context->sr = 1 | context->sr;
	}
	if (context->s) {
	context->sr = 2 | context->sr;
	}
	if (context->q) {
	context->sr = 256 | context->sr;
	}
	if (context->m) {
	context->sr = 512 | context->sr;
	}
	sh2_write32_tmp = context->gpr[15] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[15], context, context->sr);
	context->did_mem = 1;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[15] = context->gpr[15] - 4;
	sh2_write32_tmp = context->gpr[15] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[15], context, context->pc);
	context->did_mem = 1;
	context->scratch1 = context->int_vector << 2;
	context->scratch1 = context->vbr + context->scratch1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->pc = context->scratch1 - 2;
	context->sr = context->int_priority << 4;
	context->prefetch_full = 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	sh2_sync_cycle(context, target_cycle);
	}
	}
			char key_buf[6];
			debug_handler handler = tern_find_ptr(context->breakpoints, tern_int_key(context->pc, key_buf));
			if (handler) {
				handler(context, context->pc);
			}
	impl_main[context->prefetch_cur](context, target_cycle);
	}
	} else {
	while (context->cycles < target_cycle)
	{
		if (context->cycles >= context->sync_cycle) {
			sh2_sync_cycle(context, target_cycle);
		}
	if (context->delay_slot) {
	} else {
	if (context->cycles >= context->int_cycle) {
	if (context->int_ack) {
	context->int_ack(context);
	}
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[15] = context->gpr[15] - 4;
	context->sr = 240 & context->sr;
	if (context->t) {
	context->sr = 1 | context->sr;
	}
	if (context->s) {
	context->sr = 2 | context->sr;
	}
	if (context->q) {
	context->sr = 256 | context->sr;
	}
	if (context->m) {
	context->sr = 512 | context->sr;
	}
	sh2_write32_tmp = context->gpr[15] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[15], context, context->sr);
	context->did_mem = 1;
	context->cycles += context->opts->gen.clock_divider * 1;
	context->gpr[15] = context->gpr[15] - 4;
	sh2_write32_tmp = context->gpr[15] >> 29;
	context->write32[sh2_write32_tmp](context->gpr[15], context, context->pc);
	context->did_mem = 1;
	context->scratch1 = context->int_vector << 2;
	context->scratch1 = context->vbr + context->scratch1;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->pc = context->scratch1 - 2;
	context->sr = context->int_priority << 4;
	context->prefetch_full = 0;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
	sh2_sync_cycle(context, target_cycle);
	}
	}
	impl_main[context->prefetch_cur](context, target_cycle);
	}
	}
}
void sh2_reset(sh2_context *context)
{
	uint32_t sh2_read32_tmp;
	uint32_t sh2_read16_tmp;
	context->sr = 240;
	context->int_cycle = 4294967295;
	context->sr = 240;
	context->t = 0;
	context->s = 120;
	context->s = 0;
	context->q = 0;
	context->q = 0;
	context->m = 0;
	context->m = 0;
	context->vbr = 0;
	context->sleeping = 0;
	context->periph_reset(context);
	context->scratch1 = 0;
	context->scratch1 = context->vbr + 0;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->pc = context->scratch1 - 2;
	context->scratch1 = 4;
	context->scratch1 = context->vbr + 4;
	sh2_read32_tmp = context->scratch1 >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->scratch1, context);
	context->gpr[15] = context->scratch1;
	context->pc = 2 + context->pc;
	if (context->prefetch_full) {
	context->prefetch_cur = context->prefetch_next;
	context->prefetch_full = 0;
	} else {
	if (context->did_mem) {
	context->cycles += context->opts->gen.clock_divider * 1;
	}
	context->scratch1 = context->pc & 2;
	if (context->scratch1) {
	sh2_read16_tmp = context->pc >> 29;
	context->scratch1 = context->read16[sh2_read16_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1;
	} else {
	sh2_read32_tmp = context->pc >> 29;
	context->scratch1 = context->read32[sh2_read32_tmp](context->pc, context);
	context->prefetch_cur = context->scratch1 >> 16;
	context->prefetch_next = context->scratch1;
	context->prefetch_full = 1;
	}
	}
	context->delay_slot = 0;
	context->did_mem = 0;
}

void sh2_disperse_sr(sh2_context *context)
{
	context->sr = 1011 & context->sr;
	context->t = context->sr & 1;
	context->s = context->sr >> 1;
	context->s = 1 & context->s;
	context->q = context->sr >> 8;
	context->q = 1 & context->q;
	context->m = context->sr >> 9;
	context->m = 1 & context->m;
}

void sh2_collect_sr(sh2_context *context)
{
	context->sr = 240 & context->sr;
	if (context->t) {
	context->sr = 1 | context->sr;
	}
	if (context->s) {
	context->sr = 2 | context->sr;
	}
	if (context->q) {
	context->sr = 256 | context->sr;
	}
	if (context->m) {
	context->sr = 512 | context->sr;
	}
}

